drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 225 {
 226         u32 reg;
 227         int i, count;
 228
 229         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 230         if (rt2x00_get_field32(reg, WLAN_EN))
 231                 return 0;
 232
 233         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 234         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 235         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 236         rt2x00_set_field32(&reg, WLAN_EN, 1);
 237         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 238
 239         udelay(REGISTER_BUSY_DELAY);
 240
 241         count = 0;
 242         do {
 243                 /*
 244                  * Check PLL_LD & XTAL_RDY.
 245                  */
 246                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 247                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 248                         if (rt2x00_get_field32(reg, PLL_LD) &&
 249                             rt2x00_get_field32(reg, XTAL_RDY))
 250                                 break;
 251                         udelay(REGISTER_BUSY_DELAY);
 252                 }
 253
 254                 if (i >= REGISTER_BUSY_COUNT) {
 255
 256                         if (count >= 10)
 257                                 return -EIO;
 258
 259                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 260                         udelay(REGISTER_BUSY_DELAY);
 261                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 262                         udelay(REGISTER_BUSY_DELAY);
 263                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 264                         udelay(REGISTER_BUSY_DELAY);
 265                         count++;
 266                 } else {
 267                         count = 0;
 268                 }
 269
 270                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 271                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 272                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 273                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 274                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 275                 udelay(10);
 276                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 277                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 278                 udelay(10);
 279                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 280         } while (count != 0);
 281
 282         return 0;
 283 }
 284
 285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 286                         const u8 command, const u8 token,
 287                         const u8 arg0, const u8 arg1)
 288 {
 289         u32 reg;
 290
 291         /*
 292          * SOC devices don't support MCU requests.
 293          */
 294         if (rt2x00_is_soc(rt2x00dev))
 295                 return;
 296
 297         mutex_lock(&rt2x00dev->csr_mutex);
 298
 299         /*
 300          * Wait until the MCU becomes available, afterwards we
 301          * can safely write the new data into the register.
 302          */
 303         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 304                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 305                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 306                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 307                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 308                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 309
 310                 reg = 0;
 311                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 312                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 313         }
 314
 315         mutex_unlock(&rt2x00dev->csr_mutex);
 316 }
 317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 318
 319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 320 {
 321         unsigned int i = 0;
 322         u32 reg;
 323
 324         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 325                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 326                 if (reg && reg != ~0)
 327                         return 0;
 328                 msleep(1);
 329         }
 330
 331         ERROR(rt2x00dev, "Unstable hardware.\n");
 332         return -EBUSY;
 333 }
 334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 335
 336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 337 {
 338         unsigned int i;
 339         u32 reg;
 340
 341         /*
 342          * Some devices are really slow to respond here. Wait a whole second
 343          * before timing out.
 344          */
 345         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 346                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 347                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 348                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 349                         return 0;
 350
 351                 msleep(10);
 352         }
 353
 354         ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
 355         return -EACCES;
 356 }
 357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 358
 359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 360 {
 361         u32 reg;
 362
 363         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 364         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 365         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 366         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 367         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 368         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 369         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 370 }
 371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 372
 373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 374 {
 375         u16 fw_crc;
 376         u16 crc;
 377
 378         /*
 379          * The last 2 bytes in the firmware array are the crc checksum itself,
 380          * this means that we should never pass those 2 bytes to the crc
 381          * algorithm.
 382          */
 383         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 384
 385         /*
 386          * Use the crc ccitt algorithm.
 387          * This will return the same value as the legacy driver which
 388          * used bit ordering reversion on the both the firmware bytes
 389          * before input input as well as on the final output.
 390          * Obviously using crc ccitt directly is much more efficient.
 391          */
 392         crc = crc_ccitt(~0, data, len - 2);
 393
 394         /*
 395          * There is a small difference between the crc-itu-t + bitrev and
 396          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 397          * will be swapped, use swab16 to convert the crc to the correct
 398          * value.
 399          */
 400         crc = swab16(crc);
 401
 402         return fw_crc == crc;
 403 }
 404
 405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 406                           const u8 *data, const size_t len)
 407 {
 408         size_t offset = 0;
 409         size_t fw_len;
 410         bool multiple;
 411
 412         /*
 413          * PCI(e) & SOC devices require firmware with a length
 414          * of 8kb. USB devices require firmware files with a length
 415          * of 4kb. Certain USB chipsets however require different firmware,
 416          * which Ralink only provides attached to the original firmware
 417          * file. Thus for USB devices, firmware files have a length
 418          * which is a multiple of 4kb. The firmware for rt3290 chip also
 419          * have a length which is a multiple of 4kb.
 420          */
 421         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 422                 fw_len = 4096;
 423         else
 424                 fw_len = 8192;
 425
 426         multiple = true;
 427         /*
 428          * Validate the firmware length
 429          */
 430         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 431                 return FW_BAD_LENGTH;
 432
 433         /*
 434          * Check if the chipset requires one of the upper parts
 435          * of the firmware.
 436          */
 437         if (rt2x00_is_usb(rt2x00dev) &&
 438             !rt2x00_rt(rt2x00dev, RT2860) &&
 439             !rt2x00_rt(rt2x00dev, RT2872) &&
 440             !rt2x00_rt(rt2x00dev, RT3070) &&
 441             ((len / fw_len) == 1))
 442                 return FW_BAD_VERSION;
 443
 444         /*
 445          * 8kb firmware files must be checked as if it were
 446          * 2 separate firmware files.
 447          */
 448         while (offset < len) {
 449                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 450                         return FW_BAD_CRC;
 451
 452                 offset += fw_len;
 453         }
 454
 455         return FW_OK;
 456 }
 457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 458
 459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 460                          const u8 *data, const size_t len)
 461 {
 462         unsigned int i;
 463         u32 reg;
 464         int retval;
 465
 466         if (rt2x00_rt(rt2x00dev, RT3290)) {
 467                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 468                 if (retval)
 469                         return -EBUSY;
 470         }
 471
 472         /*
 473          * If driver doesn't wake up firmware here,
 474          * rt2800_load_firmware will hang forever when interface is up again.
 475          */
 476         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 477
 478         /*
 479          * Wait for stable hardware.
 480          */
 481         if (rt2800_wait_csr_ready(rt2x00dev))
 482                 return -EBUSY;
 483
 484         if (rt2x00_is_pci(rt2x00dev)) {
 485                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 486                     rt2x00_rt(rt2x00dev, RT3572) ||
 487                     rt2x00_rt(rt2x00dev, RT5390) ||
 488                     rt2x00_rt(rt2x00dev, RT5392)) {
 489                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 490                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 491                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 492                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 493                 }
 494                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 495         }
 496
 497         rt2800_disable_wpdma(rt2x00dev);
 498
 499         /*
 500          * Write firmware to the device.
 501          */
 502         rt2800_drv_write_firmware(rt2x00dev, data, len);
 503
 504         /*
 505          * Wait for device to stabilize.
 506          */
 507         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 508                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 509                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 510                         break;
 511                 msleep(1);
 512         }
 513
 514         if (i == REGISTER_BUSY_COUNT) {
 515                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 516                 return -EBUSY;
 517         }
 518
 519         /*
 520          * Disable DMA, will be reenabled later when enabling
 521          * the radio.
 522          */
 523         rt2800_disable_wpdma(rt2x00dev);
 524
 525         /*
 526          * Initialize firmware.
 527          */
 528         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 529         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 530         if (rt2x00_is_usb(rt2x00dev)) {
 531                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 532                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 533         }
 534         msleep(1);
 535
 536         return 0;
 537 }
 538 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 539
 540 void rt2800_write_tx_data(struct queue_entry *entry,
 541                           struct txentry_desc *txdesc)
 542 {
 543         __le32 *txwi = rt2800_drv_get_txwi(entry);
 544         u32 word;
 545
 546         /*
 547          * Initialize TX Info descriptor
 548          */
 549         rt2x00_desc_read(txwi, 0, &word);
 550         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 551                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 552         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 553                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 554         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 555         rt2x00_set_field32(&word, TXWI_W0_TS,
 556                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 557         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 558                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 559         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 560                            txdesc->u.ht.mpdu_density);
 561         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 562         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 563         rt2x00_set_field32(&word, TXWI_W0_BW,
 564                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 565         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 566                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 567         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 568         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 569         rt2x00_desc_write(txwi, 0, word);
 570
 571         rt2x00_desc_read(txwi, 1, &word);
 572         rt2x00_set_field32(&word, TXWI_W1_ACK,
 573                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 574         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 575                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 576         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 577         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 578                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 579                            txdesc->key_idx : txdesc->u.ht.wcid);
 580         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 581                            txdesc->length);
 582         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 583         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 584         rt2x00_desc_write(txwi, 1, word);
 585
 586         /*
 587          * Always write 0 to IV/EIV fields, hardware will insert the IV
 588          * from the IVEIV register when TXD_W3_WIV is set to 0.
 589          * When TXD_W3_WIV is set to 1 it will use the IV data
 590          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 591          * crypto entry in the registers should be used to encrypt the frame.
 592          */
 593         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 594         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 595 }
 596 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 597
 598 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 599 {
 600         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 601         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 602         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 603         u16 eeprom;
 604         u8 offset0;
 605         u8 offset1;
 606         u8 offset2;
 607
 608         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 609                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 610                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 611                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 612                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 613                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 614         } else {
 615                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 616                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 617                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 618                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 619                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 620         }
 621
 622         /*
 623          * Convert the value from the descriptor into the RSSI value
 624          * If the value in the descriptor is 0, it is considered invalid
 625          * and the default (extremely low) rssi value is assumed
 626          */
 627         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 628         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 629         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 630
 631         /*
 632          * mac80211 only accepts a single RSSI value. Calculating the
 633          * average doesn't deliver a fair answer either since -60:-60 would
 634          * be considered equally good as -50:-70 while the second is the one
 635          * which gives less energy...
 636          */
 637         rssi0 = max(rssi0, rssi1);
 638         return (int)max(rssi0, rssi2);
 639 }
 640
 641 void rt2800_process_rxwi(struct queue_entry *entry,
 642                          struct rxdone_entry_desc *rxdesc)
 643 {
 644         __le32 *rxwi = (__le32 *) entry->skb->data;
 645         u32 word;
 646
 647         rt2x00_desc_read(rxwi, 0, &word);
 648
 649         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 650         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 651
 652         rt2x00_desc_read(rxwi, 1, &word);
 653
 654         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 655                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 656
 657         if (rt2x00_get_field32(word, RXWI_W1_BW))
 658                 rxdesc->flags |= RX_FLAG_40MHZ;
 659
 660         /*
 661          * Detect RX rate, always use MCS as signal type.
 662          */
 663         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 664         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 665         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 666
 667         /*
 668          * Mask of 0x8 bit to remove the short preamble flag.
 669          */
 670         if (rxdesc->rate_mode == RATE_MODE_CCK)
 671                 rxdesc->signal &= ~0x8;
 672
 673         rt2x00_desc_read(rxwi, 2, &word);
 674
 675         /*
 676          * Convert descriptor AGC value to RSSI value.
 677          */
 678         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 679
 680         /*
 681          * Remove RXWI descriptor from start of buffer.
 682          */
 683         skb_pull(entry->skb, RXWI_DESC_SIZE);
 684 }
 685 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 686
 687 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 688 {
 689         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 690         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 691         struct txdone_entry_desc txdesc;
 692         u32 word;
 693         u16 mcs, real_mcs;
 694         int aggr, ampdu;
 695
 696         /*
 697          * Obtain the status about this packet.
 698          */
 699         txdesc.flags = 0;
 700         rt2x00_desc_read(txwi, 0, &word);
 701
 702         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 703         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 704
 705         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 706         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 707
 708         /*
 709          * If a frame was meant to be sent as a single non-aggregated MPDU
 710          * but ended up in an aggregate the used tx rate doesn't correlate
 711          * with the one specified in the TXWI as the whole aggregate is sent
 712          * with the same rate.
 713          *
 714          * For example: two frames are sent to rt2x00, the first one sets
 715          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 716          * and requests MCS15. If the hw aggregates both frames into one
 717          * AMDPU the tx status for both frames will contain MCS7 although
 718          * the frame was sent successfully.
 719          *
 720          * Hence, replace the requested rate with the real tx rate to not
 721          * confuse the rate control algortihm by providing clearly wrong
 722          * data.
 723          */
 724         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 725                 skbdesc->tx_rate_idx = real_mcs;
 726                 mcs = real_mcs;
 727         }
 728
 729         if (aggr == 1 || ampdu == 1)
 730                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 731
 732         /*
 733          * Ralink has a retry mechanism using a global fallback
 734          * table. We setup this fallback table to try the immediate
 735          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 736          * always contains the MCS used for the last transmission, be
 737          * it successful or not.
 738          */
 739         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 740                 /*
 741                  * Transmission succeeded. The number of retries is
 742                  * mcs - real_mcs
 743                  */
 744                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 745                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 746         } else {
 747                 /*
 748                  * Transmission failed. The number of retries is
 749                  * always 7 in this case (for a total number of 8
 750                  * frames sent).
 751                  */
 752                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 753                 txdesc.retry = rt2x00dev->long_retry;
 754         }
 755
 756         /*
 757          * the frame was retried at least once
 758          * -> hw used fallback rates
 759          */
 760         if (txdesc.retry)
 761                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 762
 763         rt2x00lib_txdone(entry, &txdesc);
 764 }
 765 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 766
 767 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 768 {
 769         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 770         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 771         unsigned int beacon_base;
 772         unsigned int padding_len;
 773         u32 orig_reg, reg;
 774
 775         /*
 776          * Disable beaconing while we are reloading the beacon data,
 777          * otherwise we might be sending out invalid data.
 778          */
 779         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 780         orig_reg = reg;
 781         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 782         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 783
 784         /*
 785          * Add space for the TXWI in front of the skb.
 786          */
 787         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 788
 789         /*
 790          * Register descriptor details in skb frame descriptor.
 791          */
 792         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 793         skbdesc->desc = entry->skb->data;
 794         skbdesc->desc_len = TXWI_DESC_SIZE;
 795
 796         /*
 797          * Add the TXWI for the beacon to the skb.
 798          */
 799         rt2800_write_tx_data(entry, txdesc);
 800
 801         /*
 802          * Dump beacon to userspace through debugfs.
 803          */
 804         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 805
 806         /*
 807          * Write entire beacon with TXWI and padding to register.
 808          */
 809         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 810         if (padding_len && skb_pad(entry->skb, padding_len)) {
 811                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 812                 /* skb freed by skb_pad() on failure */
 813                 entry->skb = NULL;
 814                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 815                 return;
 816         }
 817
 818         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 819         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 820                                    entry->skb->len + padding_len);
 821
 822         /*
 823          * Enable beaconing again.
 824          */
 825         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 826         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 827
 828         /*
 829          * Clean up beacon skb.
 830          */
 831         dev_kfree_skb_any(entry->skb);
 832         entry->skb = NULL;
 833 }
 834 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 835
 836 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 837                                                 unsigned int beacon_base)
 838 {
 839         int i;
 840
 841         /*
 842          * For the Beacon base registers we only need to clear
 843          * the whole TXWI which (when set to 0) will invalidate
 844          * the entire beacon.
 845          */
 846         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 847                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 848 }
 849
 850 void rt2800_clear_beacon(struct queue_entry *entry)
 851 {
 852         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 853         u32 reg;
 854
 855         /*
 856          * Disable beaconing while we are reloading the beacon data,
 857          * otherwise we might be sending out invalid data.
 858          */
 859         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 860         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 861         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 862
 863         /*
 864          * Clear beacon.
 865          */
 866         rt2800_clear_beacon_register(rt2x00dev,
 867                                      HW_BEACON_OFFSET(entry->entry_idx));
 868
 869         /*
 870          * Enabled beaconing again.
 871          */
 872         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 873         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 874 }
 875 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 876
 877 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 878 const struct rt2x00debug rt2800_rt2x00debug = {
 879         .owner  = THIS_MODULE,
 880         .csr    = {
 881                 .read           = rt2800_register_read,
 882                 .write          = rt2800_register_write,
 883                 .flags          = RT2X00DEBUGFS_OFFSET,
 884                 .word_base      = CSR_REG_BASE,
 885                 .word_size      = sizeof(u32),
 886                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 887         },
 888         .eeprom = {
 889                 .read           = rt2x00_eeprom_read,
 890                 .write          = rt2x00_eeprom_write,
 891                 .word_base      = EEPROM_BASE,
 892                 .word_size      = sizeof(u16),
 893                 .word_count     = EEPROM_SIZE / sizeof(u16),
 894         },
 895         .bbp    = {
 896                 .read           = rt2800_bbp_read,
 897                 .write          = rt2800_bbp_write,
 898                 .word_base      = BBP_BASE,
 899                 .word_size      = sizeof(u8),
 900                 .word_count     = BBP_SIZE / sizeof(u8),
 901         },
 902         .rf     = {
 903                 .read           = rt2x00_rf_read,
 904                 .write          = rt2800_rf_write,
 905                 .word_base      = RF_BASE,
 906                 .word_size      = sizeof(u32),
 907                 .word_count     = RF_SIZE / sizeof(u32),
 908         },
 909         .rfcsr  = {
 910                 .read           = rt2800_rfcsr_read,
 911                 .write          = rt2800_rfcsr_write,
 912                 .word_base      = RFCSR_BASE,
 913                 .word_size      = sizeof(u8),
 914                 .word_count     = RFCSR_SIZE / sizeof(u8),
 915         },
 916 };
 917 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 918 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 919
 920 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 921 {
 922         u32 reg;
 923
 924         if (rt2x00_rt(rt2x00dev, RT3290)) {
 925                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 926                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
 927         } else {
 928                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
 929                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
 930         }
 931 }
 932 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 933
 934 #ifdef CONFIG_RT2X00_LIB_LEDS
 935 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 936                                   enum led_brightness brightness)
 937 {
 938         struct rt2x00_led *led =
 939             container_of(led_cdev, struct rt2x00_led, led_dev);
 940         unsigned int enabled = brightness != LED_OFF;
 941         unsigned int bg_mode =
 942             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 943         unsigned int polarity =
 944                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 945                                    EEPROM_FREQ_LED_POLARITY);
 946         unsigned int ledmode =
 947                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 948                                    EEPROM_FREQ_LED_MODE);
 949         u32 reg;
 950
 951         /* Check for SoC (SOC devices don't support MCU requests) */
 952         if (rt2x00_is_soc(led->rt2x00dev)) {
 953                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 954
 955                 /* Set LED Polarity */
 956                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 957
 958                 /* Set LED Mode */
 959                 if (led->type == LED_TYPE_RADIO) {
 960                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 961                                            enabled ? 3 : 0);
 962                 } else if (led->type == LED_TYPE_ASSOC) {
 963                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 964                                            enabled ? 3 : 0);
 965                 } else if (led->type == LED_TYPE_QUALITY) {
 966                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 967                                            enabled ? 3 : 0);
 968                 }
 969
 970                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 971
 972         } else {
 973                 if (led->type == LED_TYPE_RADIO) {
 974                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 975                                               enabled ? 0x20 : 0);
 976                 } else if (led->type == LED_TYPE_ASSOC) {
 977                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 978                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 979                 } else if (led->type == LED_TYPE_QUALITY) {
 980                         /*
 981                          * The brightness is divided into 6 levels (0 - 5),
 982                          * The specs tell us the following levels:
 983                          *      0, 1 ,3, 7, 15, 31
 984                          * to determine the level in a simple way we can simply
 985                          * work with bitshifting:
 986                          *      (1 << level) - 1
 987                          */
 988                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 989                                               (1 << brightness / (LED_FULL / 6)) - 1,
 990                                               polarity);
 991                 }
 992         }
 993 }
 994
 995 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 996                      struct rt2x00_led *led, enum led_type type)
 997 {
 998         led->rt2x00dev = rt2x00dev;
 999         led->type = type;
1000         led->led_dev.brightness_set = rt2800_brightness_set;
1001         led->flags = LED_INITIALIZED;
1002 }
1003 #endif /* CONFIG_RT2X00_LIB_LEDS */
1004
1005 /*
1006  * Configuration handlers.
1007  */
1008 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1009                                const u8 *address,
1010                                int wcid)
1011 {
1012         struct mac_wcid_entry wcid_entry;
1013         u32 offset;
1014
1015         offset = MAC_WCID_ENTRY(wcid);
1016
1017         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1018         if (address)
1019                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1020
1021         rt2800_register_multiwrite(rt2x00dev, offset,
1022                                       &wcid_entry, sizeof(wcid_entry));
1023 }
1024
1025 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1026 {
1027         u32 offset;
1028         offset = MAC_WCID_ATTR_ENTRY(wcid);
1029         rt2800_register_write(rt2x00dev, offset, 0);
1030 }
1031
1032 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1033                                            int wcid, u32 bssidx)
1034 {
1035         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1036         u32 reg;
1037
1038         /*
1039          * The BSS Idx numbers is split in a main value of 3 bits,
1040          * and a extended field for adding one additional bit to the value.
1041          */
1042         rt2800_register_read(rt2x00dev, offset, &reg);
1043         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1044         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1045                            (bssidx & 0x8) >> 3);
1046         rt2800_register_write(rt2x00dev, offset, reg);
1047 }
1048
1049 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1050                                            struct rt2x00lib_crypto *crypto,
1051                                            struct ieee80211_key_conf *key)
1052 {
1053         struct mac_iveiv_entry iveiv_entry;
1054         u32 offset;
1055         u32 reg;
1056
1057         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1058
1059         if (crypto->cmd == SET_KEY) {
1060                 rt2800_register_read(rt2x00dev, offset, &reg);
1061                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1062                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1063                 /*
1064                  * Both the cipher as the BSS Idx numbers are split in a main
1065                  * value of 3 bits, and a extended field for adding one additional
1066                  * bit to the value.
1067                  */
1068                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1069                                    (crypto->cipher & 0x7));
1070                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1071                                    (crypto->cipher & 0x8) >> 3);
1072                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1073                 rt2800_register_write(rt2x00dev, offset, reg);
1074         } else {
1075                 /* Delete the cipher without touching the bssidx */
1076                 rt2800_register_read(rt2x00dev, offset, &reg);
1077                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1078                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1079                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1080                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1081                 rt2800_register_write(rt2x00dev, offset, reg);
1082         }
1083
1084         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1085
1086         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1087         if ((crypto->cipher == CIPHER_TKIP) ||
1088             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1089             (crypto->cipher == CIPHER_AES))
1090                 iveiv_entry.iv[3] |= 0x20;
1091         iveiv_entry.iv[3] |= key->keyidx << 6;
1092         rt2800_register_multiwrite(rt2x00dev, offset,
1093                                       &iveiv_entry, sizeof(iveiv_entry));
1094 }
1095
1096 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1097                              struct rt2x00lib_crypto *crypto,
1098                              struct ieee80211_key_conf *key)
1099 {
1100         struct hw_key_entry key_entry;
1101         struct rt2x00_field32 field;
1102         u32 offset;
1103         u32 reg;
1104
1105         if (crypto->cmd == SET_KEY) {
1106                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1107
1108                 memcpy(key_entry.key, crypto->key,
1109                        sizeof(key_entry.key));
1110                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1111                        sizeof(key_entry.tx_mic));
1112                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1113                        sizeof(key_entry.rx_mic));
1114
1115                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1116                 rt2800_register_multiwrite(rt2x00dev, offset,
1117                                               &key_entry, sizeof(key_entry));
1118         }
1119
1120         /*
1121          * The cipher types are stored over multiple registers
1122          * starting with SHARED_KEY_MODE_BASE each word will have
1123          * 32 bits and contains the cipher types for 2 bssidx each.
1124          * Using the correct defines correctly will cause overhead,
1125          * so just calculate the correct offset.
1126          */
1127         field.bit_offset = 4 * (key->hw_key_idx % 8);
1128         field.bit_mask = 0x7 << field.bit_offset;
1129
1130         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1131
1132         rt2800_register_read(rt2x00dev, offset, &reg);
1133         rt2x00_set_field32(&reg, field,
1134                            (crypto->cmd == SET_KEY) * crypto->cipher);
1135         rt2800_register_write(rt2x00dev, offset, reg);
1136
1137         /*
1138          * Update WCID information
1139          */
1140         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1141         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1142                                        crypto->bssidx);
1143         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1144
1145         return 0;
1146 }
1147 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1148
1149 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1150 {
1151         struct mac_wcid_entry wcid_entry;
1152         int idx;
1153         u32 offset;
1154
1155         /*
1156          * Search for the first free WCID entry and return the corresponding
1157          * index.
1158          *
1159          * Make sure the WCID starts _after_ the last possible shared key
1160          * entry (>32).
1161          *
1162          * Since parts of the pairwise key table might be shared with
1163          * the beacon frame buffers 6 & 7 we should only write into the
1164          * first 222 entries.
1165          */
1166         for (idx = 33; idx <= 222; idx++) {
1167                 offset = MAC_WCID_ENTRY(idx);
1168                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1169                                           sizeof(wcid_entry));
1170                 if (is_broadcast_ether_addr(wcid_entry.mac))
1171                         return idx;
1172         }
1173
1174         /*
1175          * Use -1 to indicate that we don't have any more space in the WCID
1176          * table.
1177          */
1178         return -1;
1179 }
1180
1181 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1182                                struct rt2x00lib_crypto *crypto,
1183                                struct ieee80211_key_conf *key)
1184 {
1185         struct hw_key_entry key_entry;
1186         u32 offset;
1187
1188         if (crypto->cmd == SET_KEY) {
1189                 /*
1190                  * Allow key configuration only for STAs that are
1191                  * known by the hw.
1192                  */
1193                 if (crypto->wcid < 0)
1194                         return -ENOSPC;
1195                 key->hw_key_idx = crypto->wcid;
1196
1197                 memcpy(key_entry.key, crypto->key,
1198                        sizeof(key_entry.key));
1199                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1200                        sizeof(key_entry.tx_mic));
1201                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1202                        sizeof(key_entry.rx_mic));
1203
1204                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1205                 rt2800_register_multiwrite(rt2x00dev, offset,
1206                                               &key_entry, sizeof(key_entry));
1207         }
1208
1209         /*
1210          * Update WCID information
1211          */
1212         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1213
1214         return 0;
1215 }
1216 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1217
1218 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1219                    struct ieee80211_sta *sta)
1220 {
1221         int wcid;
1222         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1223
1224         /*
1225          * Find next free WCID.
1226          */
1227         wcid = rt2800_find_wcid(rt2x00dev);
1228
1229         /*
1230          * Store selected wcid even if it is invalid so that we can
1231          * later decide if the STA is uploaded into the hw.
1232          */
1233         sta_priv->wcid = wcid;
1234
1235         /*
1236          * No space left in the device, however, we can still communicate
1237          * with the STA -> No error.
1238          */
1239         if (wcid < 0)
1240                 return 0;
1241
1242         /*
1243          * Clean up WCID attributes and write STA address to the device.
1244          */
1245         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1246         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1247         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1248                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1249         return 0;
1250 }
1251 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1252
1253 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1254 {
1255         /*
1256          * Remove WCID entry, no need to clean the attributes as they will
1257          * get renewed when the WCID is reused.
1258          */
1259         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1260
1261         return 0;
1262 }
1263 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1264
1265 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1266                           const unsigned int filter_flags)
1267 {
1268         u32 reg;
1269
1270         /*
1271          * Start configuration steps.
1272          * Note that the version error will always be dropped
1273          * and broadcast frames will always be accepted since
1274          * there is no filter for it at this time.
1275          */
1276         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1277         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1278                            !(filter_flags & FIF_FCSFAIL));
1279         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1280                            !(filter_flags & FIF_PLCPFAIL));
1281         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1282                            !(filter_flags & FIF_PROMISC_IN_BSS));
1283         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1284         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1285         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1286                            !(filter_flags & FIF_ALLMULTI));
1287         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1288         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1289         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1290                            !(filter_flags & FIF_CONTROL));
1291         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1292                            !(filter_flags & FIF_CONTROL));
1293         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1294                            !(filter_flags & FIF_CONTROL));
1295         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1296                            !(filter_flags & FIF_CONTROL));
1297         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1298                            !(filter_flags & FIF_CONTROL));
1299         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1300                            !(filter_flags & FIF_PSPOLL));
1301         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1302         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1303                            !(filter_flags & FIF_CONTROL));
1304         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1305                            !(filter_flags & FIF_CONTROL));
1306         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1307 }
1308 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1309
1310 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1311                         struct rt2x00intf_conf *conf, const unsigned int flags)
1312 {
1313         u32 reg;
1314         bool update_bssid = false;
1315
1316         if (flags & CONFIG_UPDATE_TYPE) {
1317                 /*
1318                  * Enable synchronisation.
1319                  */
1320                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1321                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1322                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1323
1324                 if (conf->sync == TSF_SYNC_AP_NONE) {
1325                         /*
1326                          * Tune beacon queue transmit parameters for AP mode
1327                          */
1328                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1329                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1330                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1331                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1332                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1333                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1334                 } else {
1335                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1336                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1337                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1338                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1339                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1340                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1341                 }
1342         }
1343
1344         if (flags & CONFIG_UPDATE_MAC) {
1345                 if (flags & CONFIG_UPDATE_TYPE &&
1346                     conf->sync == TSF_SYNC_AP_NONE) {
1347                         /*
1348                          * The BSSID register has to be set to our own mac
1349                          * address in AP mode.
1350                          */
1351                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1352                         update_bssid = true;
1353                 }
1354
1355                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1356                         reg = le32_to_cpu(conf->mac[1]);
1357                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1358                         conf->mac[1] = cpu_to_le32(reg);
1359                 }
1360
1361                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1362                                               conf->mac, sizeof(conf->mac));
1363         }
1364
1365         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1366                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1367                         reg = le32_to_cpu(conf->bssid[1]);
1368                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1369                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1370                         conf->bssid[1] = cpu_to_le32(reg);
1371                 }
1372
1373                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1374                                               conf->bssid, sizeof(conf->bssid));
1375         }
1376 }
1377 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1378
1379 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1380                                     struct rt2x00lib_erp *erp)
1381 {
1382         bool any_sta_nongf = !!(erp->ht_opmode &
1383                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1384         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1385         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1386         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1387         u32 reg;
1388
1389         /* default protection rate for HT20: OFDM 24M */
1390         mm20_rate = gf20_rate = 0x4004;
1391
1392         /* default protection rate for HT40: duplicate OFDM 24M */
1393         mm40_rate = gf40_rate = 0x4084;
1394
1395         switch (protection) {
1396         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1397                 /*
1398                  * All STAs in this BSS are HT20/40 but there might be
1399                  * STAs not supporting greenfield mode.
1400                  * => Disable protection for HT transmissions.
1401                  */
1402                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1403
1404                 break;
1405         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1406                 /*
1407                  * All STAs in this BSS are HT20 or HT20/40 but there
1408                  * might be STAs not supporting greenfield mode.
1409                  * => Protect all HT40 transmissions.
1410                  */
1411                 mm20_mode = gf20_mode = 0;
1412                 mm40_mode = gf40_mode = 2;
1413
1414                 break;
1415         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1416                 /*
1417                  * Nonmember protection:
1418                  * According to 802.11n we _should_ protect all
1419                  * HT transmissions (but we don't have to).
1420                  *
1421                  * But if cts_protection is enabled we _shall_ protect
1422                  * all HT transmissions using a CCK rate.
1423                  *
1424                  * And if any station is non GF we _shall_ protect
1425                  * GF transmissions.
1426                  *
1427                  * We decide to protect everything
1428                  * -> fall through to mixed mode.
1429                  */
1430         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1431                 /*
1432                  * Legacy STAs are present
1433                  * => Protect all HT transmissions.
1434                  */
1435                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1436
1437                 /*
1438                  * If erp protection is needed we have to protect HT
1439                  * transmissions with CCK 11M long preamble.
1440                  */
1441                 if (erp->cts_protection) {
1442                         /* don't duplicate RTS/CTS in CCK mode */
1443                         mm20_rate = mm40_rate = 0x0003;
1444                         gf20_rate = gf40_rate = 0x0003;
1445                 }
1446                 break;
1447         }
1448
1449         /* check for STAs not supporting greenfield mode */
1450         if (any_sta_nongf)
1451                 gf20_mode = gf40_mode = 2;
1452
1453         /* Update HT protection config */
1454         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1455         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1456         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1457         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1458
1459         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1460         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1461         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1462         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1463
1464         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1465         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1466         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1467         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1468
1469         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1470         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1471         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1472         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1473 }
1474
1475 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1476                        u32 changed)
1477 {
1478         u32 reg;
1479
1480         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1481                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1482                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1483                                    !!erp->short_preamble);
1484                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1485                                    !!erp->short_preamble);
1486                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1487         }
1488
1489         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1490                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1491                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1492                                    erp->cts_protection ? 2 : 0);
1493                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1494         }
1495
1496         if (changed & BSS_CHANGED_BASIC_RATES) {
1497                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1498                                          erp->basic_rates);
1499                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1500         }
1501
1502         if (changed & BSS_CHANGED_ERP_SLOT) {
1503                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1504                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1505                                    erp->slot_time);
1506                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1507
1508                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1509                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1510                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1511         }
1512
1513         if (changed & BSS_CHANGED_BEACON_INT) {
1514                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1515                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1516                                    erp->beacon_int * 16);
1517                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1518         }
1519
1520         if (changed & BSS_CHANGED_HT)
1521                 rt2800_config_ht_opmode(rt2x00dev, erp);
1522 }
1523 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1524
1525 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1526 {
1527         u32 reg;
1528         u16 eeprom;
1529         u8 led_ctrl, led_g_mode, led_r_mode;
1530
1531         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1532         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1533                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1534                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1535         } else {
1536                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1537                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1538         }
1539         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1540
1541         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1542         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1543         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1544         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1545             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1546                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1547                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1548                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1549                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1550                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1551                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1552                 } else {
1553                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1554                                            (led_g_mode << 2) | led_r_mode, 1);
1555                 }
1556         }
1557 }
1558
1559 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1560                                      enum antenna ant)
1561 {
1562         u32 reg;
1563         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1564         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1565
1566         if (rt2x00_is_pci(rt2x00dev)) {
1567                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1568                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1569                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1570         } else if (rt2x00_is_usb(rt2x00dev))
1571                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1572                                    eesk_pin, 0);
1573
1574         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1575         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1576         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1577         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1578 }
1579
1580 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1581 {
1582         u8 r1;
1583         u8 r3;
1584         u16 eeprom;
1585
1586         rt2800_bbp_read(rt2x00dev, 1, &r1);
1587         rt2800_bbp_read(rt2x00dev, 3, &r3);
1588
1589         if (rt2x00_rt(rt2x00dev, RT3572) &&
1590             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1591                 rt2800_config_3572bt_ant(rt2x00dev);
1592
1593         /*
1594          * Configure the TX antenna.
1595          */
1596         switch (ant->tx_chain_num) {
1597         case 1:
1598                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1599                 break;
1600         case 2:
1601                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1602                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1603                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1604                 else
1605                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1606                 break;
1607         case 3:
1608                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1609                 break;
1610         }
1611
1612         /*
1613          * Configure the RX antenna.
1614          */
1615         switch (ant->rx_chain_num) {
1616         case 1:
1617                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1618                     rt2x00_rt(rt2x00dev, RT3090) ||
1619                     rt2x00_rt(rt2x00dev, RT3352) ||
1620                     rt2x00_rt(rt2x00dev, RT3390)) {
1621                         rt2x00_eeprom_read(rt2x00dev,
1622                                            EEPROM_NIC_CONF1, &eeprom);
1623                         if (rt2x00_get_field16(eeprom,
1624                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1625                                 rt2800_set_ant_diversity(rt2x00dev,
1626                                                 rt2x00dev->default_ant.rx);
1627                 }
1628                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1629                 break;
1630         case 2:
1631                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1632                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1633                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1634                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1635                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1636                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1637                 } else {
1638                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1639                 }
1640                 break;
1641         case 3:
1642                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1643                 break;
1644         }
1645
1646         rt2800_bbp_write(rt2x00dev, 3, r3);
1647         rt2800_bbp_write(rt2x00dev, 1, r1);
1648 }
1649 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1650
1651 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1652                                    struct rt2x00lib_conf *libconf)
1653 {
1654         u16 eeprom;
1655         short lna_gain;
1656
1657         if (libconf->rf.channel <= 14) {
1658                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1659                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1660         } else if (libconf->rf.channel <= 64) {
1661                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1662                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1663         } else if (libconf->rf.channel <= 128) {
1664                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1665                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1666         } else {
1667                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1668                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1669         }
1670
1671         rt2x00dev->lna_gain = lna_gain;
1672 }
1673
1674 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1675                                          struct ieee80211_conf *conf,
1676                                          struct rf_channel *rf,
1677                                          struct channel_info *info)
1678 {
1679         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1680
1681         if (rt2x00dev->default_ant.tx_chain_num == 1)
1682                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1683
1684         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1685                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1686                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1687         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1688                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1689
1690         if (rf->channel > 14) {
1691                 /*
1692                  * When TX power is below 0, we should increase it by 7 to
1693                  * make it a positive value (Minimum value is -7).
1694                  * However this means that values between 0 and 7 have
1695                  * double meaning, and we should set a 7DBm boost flag.
1696                  */
1697                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1698                                    (info->default_power1 >= 0));
1699
1700                 if (info->default_power1 < 0)
1701                         info->default_power1 += 7;
1702
1703                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1704
1705                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1706                                    (info->default_power2 >= 0));
1707
1708                 if (info->default_power2 < 0)
1709                         info->default_power2 += 7;
1710
1711                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1712         } else {
1713                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1714                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1715         }
1716
1717         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1718
1719         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1720         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1721         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1722         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1723
1724         udelay(200);
1725
1726         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1727         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1728         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1729         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1730
1731         udelay(200);
1732
1733         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1734         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1735         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1736         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1737 }
1738
1739 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1740                                          struct ieee80211_conf *conf,
1741                                          struct rf_channel *rf,
1742                                          struct channel_info *info)
1743 {
1744         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1745         u8 rfcsr, calib_tx, calib_rx;
1746
1747         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1748
1749         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1750         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1751         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1752
1753         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1754         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1755         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1756
1757         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1758         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1759         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1760
1761         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1762         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1763         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1764
1765         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1766         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1767         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1768                           rt2x00dev->default_ant.rx_chain_num <= 1);
1769         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1770                           rt2x00dev->default_ant.rx_chain_num <= 2);
1771         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1772         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1773                           rt2x00dev->default_ant.tx_chain_num <= 1);
1774         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1775                           rt2x00dev->default_ant.tx_chain_num <= 2);
1776         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1777
1778         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1779         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1780         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1781         msleep(1);
1782         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1783         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1784
1785         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1786         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1787         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1788
1789         if (rt2x00_rt(rt2x00dev, RT3390)) {
1790                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1791                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1792         } else {
1793                 if (conf_is_ht40(conf)) {
1794                         calib_tx = drv_data->calibration_bw40;
1795                         calib_rx = drv_data->calibration_bw40;
1796                 } else {
1797                         calib_tx = drv_data->calibration_bw20;
1798                         calib_rx = drv_data->calibration_bw20;
1799                 }
1800         }
1801
1802         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1803         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1804         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1805
1806         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1807         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1808         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1809
1810         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1811         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1812         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1813
1814         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1815         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1816         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1817         msleep(1);
1818         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1819         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1820 }
1821
1822 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1823                                          struct ieee80211_conf *conf,
1824                                          struct rf_channel *rf,
1825                                          struct channel_info *info)
1826 {
1827         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1828         u8 rfcsr;
1829         u32 reg;
1830
1831         if (rf->channel <= 14) {
1832                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1833                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1834         } else {
1835                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1836                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1837         }
1838
1839         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1840         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1841
1842         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1843         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1844         if (rf->channel <= 14)
1845                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1846         else
1847                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1848         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1849
1850         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1851         if (rf->channel <= 14)
1852                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1853         else
1854                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1855         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1856
1857         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1858         if (rf->channel <= 14) {
1859                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1860                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1861                                   info->default_power1);
1862         } else {
1863                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1864                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1865                                 (info->default_power1 & 0x3) |
1866                                 ((info->default_power1 & 0xC) << 1));
1867         }
1868         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1869
1870         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1871         if (rf->channel <= 14) {
1872                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1873                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1874                                   info->default_power2);
1875         } else {
1876                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1877                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1878                                 (info->default_power2 & 0x3) |
1879                                 ((info->default_power2 & 0xC) << 1));
1880         }
1881         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1882
1883         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1884         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1885         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1886         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1887         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1888         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1889         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1890         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1891                 if (rf->channel <= 14) {
1892                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1893                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1894                 }
1895                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1896                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1897         } else {
1898                 switch (rt2x00dev->default_ant.tx_chain_num) {
1899                 case 1:
1900                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1901                 case 2:
1902                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1903                         break;
1904                 }
1905
1906                 switch (rt2x00dev->default_ant.rx_chain_num) {
1907                 case 1:
1908                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1909                 case 2:
1910                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1911                         break;
1912                 }
1913         }
1914         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1915
1916         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1917         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1918         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1919
1920         if (conf_is_ht40(conf)) {
1921                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1922                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1923         } else {
1924                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1925                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1926         }
1927
1928         if (rf->channel <= 14) {
1929                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1930                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1931                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1932                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1933                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1934                 rfcsr = 0x4c;
1935                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1936                                   drv_data->txmixer_gain_24g);
1937                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1938                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1939                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1940                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1941                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1942                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1943                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1944                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1945         } else {
1946                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1947                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1948                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1949                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1950                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1951                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1952                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1953                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1954                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1955                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1956                 rfcsr = 0x7a;
1957                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1958                                   drv_data->txmixer_gain_5g);
1959                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1960                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1961                 if (rf->channel <= 64) {
1962                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1963                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1964                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1965                 } else if (rf->channel <= 128) {
1966                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1967                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1968                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1969                 } else {
1970                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1971                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1972                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1973                 }
1974                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1975                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1976                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1977         }
1978
1979         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1980         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1981         if (rf->channel <= 14)
1982                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1983         else
1984                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1985         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1986
1987         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1988         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1989         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1990 }
1991
1992 #define POWER_BOUND             0x27
1993 #define POWER_BOUND_5G          0x2b
1994 #define FREQ_OFFSET_BOUND       0x5f
1995
1996 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1997 {
1998         u8 rfcsr;
1999
2000         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2001         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2002                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2003         else
2004                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2005         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2006 }
2007
2008 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2009                                          struct ieee80211_conf *conf,
2010                                          struct rf_channel *rf,
2011                                          struct channel_info *info)
2012 {
2013         u8 rfcsr;
2014
2015         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2016         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2017         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2018         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2019         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2020
2021         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2022         if (info->default_power1 > POWER_BOUND)
2023                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2024         else
2025                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2026         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2027
2028         rt2800_adjust_freq_offset(rt2x00dev);
2029
2030         if (rf->channel <= 14) {
2031                 if (rf->channel == 6)
2032                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2033                 else
2034                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2035
2036                 if (rf->channel >= 1 && rf->channel <= 6)
2037                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2038                 else if (rf->channel >= 7 && rf->channel <= 11)
2039                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2040                 else if (rf->channel >= 12 && rf->channel <= 14)
2041                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2042         }
2043 }
2044
2045 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2046                                          struct ieee80211_conf *conf,
2047                                          struct rf_channel *rf,
2048                                          struct channel_info *info)
2049 {
2050         u8 rfcsr;
2051
2052         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2053         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2054
2055         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2056         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2057         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2058
2059         if (info->default_power1 > POWER_BOUND)
2060                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2061         else
2062                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2063
2064         if (info->default_power2 > POWER_BOUND)
2065                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2066         else
2067                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2068
2069         rt2800_adjust_freq_offset(rt2x00dev);
2070
2071         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2072         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2073         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2074
2075         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2076                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2077         else
2078                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2079
2080         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2081                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2082         else
2083                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2084
2085         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2086         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2087
2088         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2089
2090         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2091 }
2092
2093 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2094                                          struct ieee80211_conf *conf,
2095                                          struct rf_channel *rf,
2096                                          struct channel_info *info)
2097 {
2098         u8 rfcsr;
2099
2100         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2101         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2102         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2103         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2104         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2105
2106         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2107         if (info->default_power1 > POWER_BOUND)
2108                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2109         else
2110                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2111         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2112
2113         if (rt2x00_rt(rt2x00dev, RT5392)) {
2114                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2115                 if (info->default_power1 > POWER_BOUND)
2116                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2117                 else
2118                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2119                                           info->default_power2);
2120                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2121         }
2122
2123         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2124         if (rt2x00_rt(rt2x00dev, RT5392)) {
2125                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2126                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2127         }
2128         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2129         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2130         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2131         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2132         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2133
2134         rt2800_adjust_freq_offset(rt2x00dev);
2135
2136         if (rf->channel <= 14) {
2137                 int idx = rf->channel-1;
2138
2139                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2140                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2141                                 /* r55/r59 value array of channel 1~14 */
2142                                 static const char r55_bt_rev[] = {0x83, 0x83,
2143                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2144                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2145                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2146                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2147                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2148
2149                                 rt2800_rfcsr_write(rt2x00dev, 55,
2150                                                    r55_bt_rev[idx]);
2151                                 rt2800_rfcsr_write(rt2x00dev, 59,
2152                                                    r59_bt_rev[idx]);
2153                         } else {
2154                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2155                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2156                                         0x88, 0x88, 0x86, 0x85, 0x84};
2157
2158                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2159                         }
2160                 } else {
2161                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2162                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2163                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2164                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2165                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2166                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2167                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2168
2169                                 rt2800_rfcsr_write(rt2x00dev, 55,
2170                                                    r55_nonbt_rev[idx]);
2171                                 rt2800_rfcsr_write(rt2x00dev, 59,
2172                                                    r59_nonbt_rev[idx]);
2173                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2174                                    rt2x00_rt(rt2x00dev, RT5392)) {
2175                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2176                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2177                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2178
2179                                 rt2800_rfcsr_write(rt2x00dev, 59,
2180                                                    r59_non_bt[idx]);
2181                         }
2182                 }
2183         }
2184 }
2185
2186 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2187                                          struct ieee80211_conf *conf,
2188                                          struct rf_channel *rf,
2189                                          struct channel_info *info)
2190 {
2191         u8 rfcsr, ep_reg;
2192         u32 reg;
2193         int power_bound;
2194
2195         /* TODO */
2196         const bool is_11b = false;
2197         const bool is_type_ep = false;
2198
2199         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2200         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2201                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2202         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2203
2204         /* Order of values on rf_channel entry: N, K, mod, R */
2205         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2206
2207         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2208         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2209         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2210         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2211         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2212
2213         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2214         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2215         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2216         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2217
2218         if (rf->channel <= 14) {
2219                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2220                 /* FIXME: RF11 owerwrite ? */
2221                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2222                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2223                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2224                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2225                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2226                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2227                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2228                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2229                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2230                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2231                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2232                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2233                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2234                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2235                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2236                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2237                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2238                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2239                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2240                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2241                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2242                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2243                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2244                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2245                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2246                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2247                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2248                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2249
2250                 /* TODO RF27 <- tssi */
2251
2252                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2253                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2254                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2255
2256                 if (is_11b) {
2257                         /* CCK */
2258                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2259                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2260                         if (is_type_ep)
2261                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2262                         else
2263                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2264                 } else {
2265                         /* OFDM */
2266                         if (is_type_ep)
2267                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2268                         else
2269                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2270                 }
2271
2272                 power_bound = POWER_BOUND;
2273                 ep_reg = 0x2;
2274         } else {
2275                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2276                 /* FIMXE: RF11 overwrite */
2277                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2278                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2279                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2280                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2281                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2282                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2283                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2284                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2285                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2286                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2287                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2288                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2289                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2290                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2291
2292                 /* TODO RF27 <- tssi */
2293
2294                 if (rf->channel >= 36 && rf->channel <= 64) {
2295
2296                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2297                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2298                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2299                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2300                         if (rf->channel <= 50)
2301                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2302                         else if (rf->channel >= 52)
2303                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2304                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2305                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2306                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2307                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2308                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2309                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2310                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2311                         if (rf->channel <= 50) {
2312                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2313                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2314                         } else if (rf->channel >= 52) {
2315                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2316                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2317                         }
2318
2319                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2320                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2321                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2322
2323                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2324
2325                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2326                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2327                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2328                         if (rf->channel <= 153) {
2329                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2330                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2331                         } else if (rf->channel >= 155) {
2332                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2333                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2334                         }
2335                         if (rf->channel <= 138) {
2336                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2337                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2338                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2339                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2340                         } else if (rf->channel >= 140) {
2341                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2342                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2343                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2344                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2345                         }
2346                         if (rf->channel <= 124)
2347                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2348                         else if (rf->channel >= 126)
2349                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2350                         if (rf->channel <= 138)
2351                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2352                         else if (rf->channel >= 140)
2353                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2354                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2355                         if (rf->channel <= 138)
2356                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2357                         else if (rf->channel >= 140)
2358                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2359                         if (rf->channel <= 128)
2360                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2361                         else if (rf->channel >= 130)
2362                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2363                         if (rf->channel <= 116)
2364                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2365                         else if (rf->channel >= 118)
2366                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2367                         if (rf->channel <= 138)
2368                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2369                         else if (rf->channel >= 140)
2370                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2371                         if (rf->channel <= 116)
2372                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2373                         else if (rf->channel >= 118)
2374                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2375                 }
2376
2377                 power_bound = POWER_BOUND_5G;
2378                 ep_reg = 0x3;
2379         }
2380
2381         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2382         if (info->default_power1 > power_bound)
2383                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2384         else
2385                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2386         if (is_type_ep)
2387                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2388         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2389
2390         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2391         if (info->default_power1 > power_bound)
2392                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2393         else
2394                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2395         if (is_type_ep)
2396                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2397         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2398
2399         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2400         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2401         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2402
2403         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2404                           rt2x00dev->default_ant.tx_chain_num >= 1);
2405         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2406                           rt2x00dev->default_ant.tx_chain_num == 2);
2407         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2408
2409         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2410                           rt2x00dev->default_ant.rx_chain_num >= 1);
2411         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2412                           rt2x00dev->default_ant.rx_chain_num == 2);
2413         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2414
2415         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2416         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2417
2418         if (conf_is_ht40(conf))
2419                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2420         else
2421                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2422
2423         if (!is_11b) {
2424                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2425                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2426         }
2427
2428         /* TODO proper frequency adjustment */
2429         rt2800_adjust_freq_offset(rt2x00dev);
2430
2431         /* TODO merge with others */
2432         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2433         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2434         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2435
2436         /* BBP settings */
2437         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2438         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2439         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2440
2441         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2442         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2443         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2444         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2445
2446         /* GLRT band configuration */
2447         rt2800_bbp_write(rt2x00dev, 195, 128);
2448         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2449         rt2800_bbp_write(rt2x00dev, 195, 129);
2450         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2451         rt2800_bbp_write(rt2x00dev, 195, 130);
2452         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2453         rt2800_bbp_write(rt2x00dev, 195, 131);
2454         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2455         rt2800_bbp_write(rt2x00dev, 195, 133);
2456         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2457         rt2800_bbp_write(rt2x00dev, 195, 124);
2458         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2459 }
2460
2461 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2462 {
2463         u8 cal;
2464
2465         /* TODO */
2466         if (WARN_ON_ONCE(channel > 14))
2467                 return;
2468
2469         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2470         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2471         rt2800_bbp_write(rt2x00dev, 159, cal);
2472
2473         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2474         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2475         rt2800_bbp_write(rt2x00dev, 159, cal);
2476
2477         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2478         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2479         rt2800_bbp_write(rt2x00dev, 159, cal);
2480
2481         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2482         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2483         rt2800_bbp_write(rt2x00dev, 159, cal);
2484
2485         /* RF IQ compensation control */
2486         rt2800_bbp_write(rt2x00dev, 158, 0x04);
2487         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2488         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2489
2490         /* RF IQ imbalance compensation control */
2491         rt2800_bbp_write(rt2x00dev, 158, 0x03);
2492         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2493         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2494 }
2495
2496 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2497                                   struct ieee80211_conf *conf,
2498                                   struct rf_channel *rf,
2499                                   struct channel_info *info)
2500 {
2501         u32 reg;
2502         unsigned int tx_pin;
2503         u8 bbp, rfcsr;
2504
2505         if (rf->channel <= 14) {
2506                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2507                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2508         } else {
2509                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2510                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2511         }
2512
2513         switch (rt2x00dev->chip.rf) {
2514         case RF2020:
2515         case RF3020:
2516         case RF3021:
2517         case RF3022:
2518         case RF3320:
2519                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2520                 break;
2521         case RF3052:
2522                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2523                 break;
2524         case RF3290:
2525                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2526                 break;
2527         case RF3322:
2528                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2529                 break;
2530         case RF5360:
2531         case RF5370:
2532         case RF5372:
2533         case RF5390:
2534         case RF5392:
2535                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2536                 break;
2537         case RF5592:
2538                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2539                 break;
2540         default:
2541                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2542         }
2543
2544         if (rt2x00_rf(rt2x00dev, RF3290) ||
2545             rt2x00_rf(rt2x00dev, RF3322) ||
2546             rt2x00_rf(rt2x00dev, RF5360) ||
2547             rt2x00_rf(rt2x00dev, RF5370) ||
2548             rt2x00_rf(rt2x00dev, RF5372) ||
2549             rt2x00_rf(rt2x00dev, RF5390) ||
2550             rt2x00_rf(rt2x00dev, RF5392)) {
2551                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2552                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2553                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2554                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2555
2556                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2557                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2558                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2559         }
2560
2561         /*
2562          * Change BBP settings
2563          */
2564         if (rt2x00_rt(rt2x00dev, RT3352)) {
2565                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2566                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2567                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2568                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2569         } else {
2570                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2571                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2572                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2573                 rt2800_bbp_write(rt2x00dev, 86, 0);
2574         }
2575
2576         if (rf->channel <= 14) {
2577                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2578                     !rt2x00_rt(rt2x00dev, RT5392)) {
2579                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2580                                      &rt2x00dev->cap_flags)) {
2581                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2582                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2583                         } else {
2584                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2585                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2586                         }
2587                 }
2588         } else {
2589                 if (rt2x00_rt(rt2x00dev, RT3572))
2590                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2591                 else
2592                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2593
2594                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2595                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2596                 else
2597                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2598         }
2599
2600         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2601         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2602         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2603         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2604         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2605
2606         if (rt2x00_rt(rt2x00dev, RT3572))
2607                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2608
2609         tx_pin = 0;
2610
2611         /* Turn on unused PA or LNA when not using 1T or 1R */
2612         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2613                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2614                                    rf->channel > 14);
2615                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2616                                    rf->channel <= 14);
2617         }
2618
2619         /* Turn on unused PA or LNA when not using 1T or 1R */
2620         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2621                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2622                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2623         }
2624
2625         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2626         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2627         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2628         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2629         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2630                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2631         else
2632                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2633                                    rf->channel <= 14);
2634         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2635
2636         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2637
2638         if (rt2x00_rt(rt2x00dev, RT3572))
2639                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2640
2641         if (rt2x00_rt(rt2x00dev, RT5592)) {
2642                 rt2800_bbp_write(rt2x00dev, 195, 141);
2643                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2644
2645                 /* TODO AGC adjust */
2646                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2647         }
2648
2649         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2650         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2651         rt2800_bbp_write(rt2x00dev, 4, bbp);
2652
2653         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2654         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2655         rt2800_bbp_write(rt2x00dev, 3, bbp);
2656
2657         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2658                 if (conf_is_ht40(conf)) {
2659                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2660                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2661                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2662                 } else {
2663                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2664                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2665                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2666                 }
2667         }
2668
2669         msleep(1);
2670
2671         /*
2672          * Clear channel statistic counters
2673          */
2674         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2675         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2676         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2677
2678         /*
2679          * Clear update flag
2680          */
2681         if (rt2x00_rt(rt2x00dev, RT3352)) {
2682                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2683                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2684                 rt2800_bbp_write(rt2x00dev, 49, bbp);
2685         }
2686 }
2687
2688 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2689 {
2690         u8 tssi_bounds[9];
2691         u8 current_tssi;
2692         u16 eeprom;
2693         u8 step;
2694         int i;
2695
2696         /*
2697          * Read TSSI boundaries for temperature compensation from
2698          * the EEPROM.
2699          *
2700          * Array idx               0    1    2    3    4    5    6    7    8
2701          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2702          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2703          */
2704         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2705                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2706                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2707                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2708                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2709                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2710
2711                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2712                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2713                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2714                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2715                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2716
2717                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2718                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2719                                         EEPROM_TSSI_BOUND_BG3_REF);
2720                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2721                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2722
2723                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2724                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2725                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2726                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2727                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2728
2729                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2730                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2731                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2732
2733                 step = rt2x00_get_field16(eeprom,
2734                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2735         } else {
2736                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2737                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2738                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2739                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2740                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2741
2742                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2743                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2744                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2745                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2746                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2747
2748                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2749                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2750                                         EEPROM_TSSI_BOUND_A3_REF);
2751                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2752                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2753
2754                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2755                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2756                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2757                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2758                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2759
2760                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2761                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2762                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2763
2764                 step = rt2x00_get_field16(eeprom,
2765                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2766         }
2767
2768         /*
2769          * Check if temperature compensation is supported.
2770          */
2771         if (tssi_bounds[4] == 0xff || step == 0xff)
2772                 return 0;
2773
2774         /*
2775          * Read current TSSI (BBP 49).
2776          */
2777         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2778
2779         /*
2780          * Compare TSSI value (BBP49) with the compensation boundaries
2781          * from the EEPROM and increase or decrease tx power.
2782          */
2783         for (i = 0; i <= 3; i++) {
2784                 if (current_tssi > tssi_bounds[i])
2785                         break;
2786         }
2787
2788         if (i == 4) {
2789                 for (i = 8; i >= 5; i--) {
2790                         if (current_tssi < tssi_bounds[i])
2791                                 break;
2792                 }
2793         }
2794
2795         return (i - 4) * step;
2796 }
2797
2798 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2799                                       enum ieee80211_band band)
2800 {
2801         u16 eeprom;
2802         u8 comp_en;
2803         u8 comp_type;
2804         int comp_value = 0;
2805
2806         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2807
2808         /*
2809          * HT40 compensation not required.
2810          */
2811         if (eeprom == 0xffff ||
2812             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2813                 return 0;
2814
2815         if (band == IEEE80211_BAND_2GHZ) {
2816                 comp_en = rt2x00_get_field16(eeprom,
2817                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2818                 if (comp_en) {
2819                         comp_type = rt2x00_get_field16(eeprom,
2820                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2821                         comp_value = rt2x00_get_field16(eeprom,
2822                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2823                         if (!comp_type)
2824                                 comp_value = -comp_value;
2825                 }
2826         } else {
2827                 comp_en = rt2x00_get_field16(eeprom,
2828                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2829                 if (comp_en) {
2830                         comp_type = rt2x00_get_field16(eeprom,
2831                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2832                         comp_value = rt2x00_get_field16(eeprom,
2833                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2834                         if (!comp_type)
2835                                 comp_value = -comp_value;
2836                 }
2837         }
2838
2839         return comp_value;
2840 }
2841
2842 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2843                                         int power_level, int max_power)
2844 {
2845         int delta;
2846
2847         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2848                 return 0;
2849
2850         /*
2851          * XXX: We don't know the maximum transmit power of our hardware since
2852          * the EEPROM doesn't expose it. We only know that we are calibrated
2853          * to 100% tx power.
2854          *
2855          * Hence, we assume the regulatory limit that cfg80211 calulated for
2856          * the current channel is our maximum and if we are requested to lower
2857          * the value we just reduce our tx power accordingly.
2858          */
2859         delta = power_level - max_power;
2860         return min(delta, 0);
2861 }
2862
2863 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2864                                    enum ieee80211_band band, int power_level,
2865                                    u8 txpower, int delta)
2866 {
2867         u16 eeprom;
2868         u8 criterion;
2869         u8 eirp_txpower;
2870         u8 eirp_txpower_criterion;
2871         u8 reg_limit;
2872
2873         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2874                 /*
2875                  * Check if eirp txpower exceed txpower_limit.
2876                  * We use OFDM 6M as criterion and its eirp txpower
2877                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2878                  * .11b data rate need add additional 4dbm
2879                  * when calculating eirp txpower.
2880                  */
2881                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2882                                    &eeprom);
2883                 criterion = rt2x00_get_field16(eeprom,
2884                                                EEPROM_TXPOWER_BYRATE_RATE0);
2885
2886                 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2887                                    &eeprom);
2888
2889                 if (band == IEEE80211_BAND_2GHZ)
2890                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2891                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2892                 else
2893                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2894                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2895
2896                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2897                                (is_rate_b ? 4 : 0) + delta;
2898
2899                 reg_limit = (eirp_txpower > power_level) ?
2900                                         (eirp_txpower - power_level) : 0;
2901         } else
2902                 reg_limit = 0;
2903
2904         txpower = max(0, txpower + delta - reg_limit);
2905         return min_t(u8, txpower, 0xc);
2906 }
2907
2908 /*
2909  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2910  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2911  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2912  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2913  * Reference per rate transmit power values are located in the EEPROM at
2914  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2915  * current conditions (i.e. band, bandwidth, temperature, user settings).
2916  */
2917 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2918                                   struct ieee80211_channel *chan,
2919                                   int power_level)
2920 {
2921         u8 txpower, r1;
2922         u16 eeprom;
2923         u32 reg, offset;
2924         int i, is_rate_b, delta, power_ctrl;
2925         enum ieee80211_band band = chan->band;
2926
2927         /*
2928          * Calculate HT40 compensation. For 40MHz we need to add or subtract
2929          * value read from EEPROM (different for 2GHz and for 5GHz).
2930          */
2931         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2932
2933         /*
2934          * Calculate temperature compensation. Depends on measurement of current
2935          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
2936          * to temperature or maybe other factors) is smaller or bigger than
2937          * expected. We adjust it, based on TSSI reference and boundaries values
2938          * provided in EEPROM.
2939          */
2940         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2941
2942         /*
2943          * Decrease power according to user settings, on devices with unknown
2944          * maximum tx power. For other devices we take user power_level into
2945          * consideration on rt2800_compensate_txpower().
2946          */
2947         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
2948                                               chan->max_power);
2949
2950         /*
2951          * BBP_R1 controls TX power for all rates, it allow to set the following
2952          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2953          *
2954          * TODO: we do not use +6 dBm option to do not increase power beyond
2955          * regulatory limit, however this could be utilized for devices with
2956          * CAPABILITY_POWER_LIMIT.
2957          */
2958         rt2800_bbp_read(rt2x00dev, 1, &r1);
2959         if (delta <= -12) {
2960                 power_ctrl = 2;
2961                 delta += 12;
2962         } else if (delta <= -6) {
2963                 power_ctrl = 1;
2964                 delta += 6;
2965         } else {
2966                 power_ctrl = 0;
2967         }
2968         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
2969         rt2800_bbp_write(rt2x00dev, 1, r1);
2970         offset = TX_PWR_CFG_0;
2971
2972         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2973                 /* just to be safe */
2974                 if (offset > TX_PWR_CFG_4)
2975                         break;
2976
2977                 rt2800_register_read(rt2x00dev, offset, &reg);
2978
2979                 /* read the next four txpower values */
2980                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2981                                    &eeprom);
2982
2983                 is_rate_b = i ? 0 : 1;
2984                 /*
2985                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2986                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2987                  * TX_PWR_CFG_4: unknown
2988                  */
2989                 txpower = rt2x00_get_field16(eeprom,
2990                                              EEPROM_TXPOWER_BYRATE_RATE0);
2991                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2992                                              power_level, txpower, delta);
2993                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2994
2995                 /*
2996                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2997                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2998                  * TX_PWR_CFG_4: unknown
2999                  */
3000                 txpower = rt2x00_get_field16(eeprom,
3001                                              EEPROM_TXPOWER_BYRATE_RATE1);
3002                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3003                                              power_level, txpower, delta);
3004                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
3005
3006                 /*
3007                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3008                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
3009                  * TX_PWR_CFG_4: unknown
3010                  */
3011                 txpower = rt2x00_get_field16(eeprom,
3012                                              EEPROM_TXPOWER_BYRATE_RATE2);
3013                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3014                                              power_level, txpower, delta);
3015                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
3016
3017                 /*
3018                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3019                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
3020                  * TX_PWR_CFG_4: unknown
3021                  */
3022                 txpower = rt2x00_get_field16(eeprom,
3023                                              EEPROM_TXPOWER_BYRATE_RATE3);
3024                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3025                                              power_level, txpower, delta);
3026                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
3027
3028                 /* read the next four txpower values */
3029                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
3030                                    &eeprom);
3031
3032                 is_rate_b = 0;
3033                 /*
3034                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3035                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3036                  * TX_PWR_CFG_4: unknown
3037                  */
3038                 txpower = rt2x00_get_field16(eeprom,
3039                                              EEPROM_TXPOWER_BYRATE_RATE0);
3040                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3041                                              power_level, txpower, delta);
3042                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3043
3044                 /*
3045                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3046                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3047                  * TX_PWR_CFG_4: unknown
3048                  */
3049                 txpower = rt2x00_get_field16(eeprom,
3050                                              EEPROM_TXPOWER_BYRATE_RATE1);
3051                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3052                                              power_level, txpower, delta);
3053                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3054
3055                 /*
3056                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3057                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3058                  * TX_PWR_CFG_4: unknown
3059                  */
3060                 txpower = rt2x00_get_field16(eeprom,
3061                                              EEPROM_TXPOWER_BYRATE_RATE2);
3062                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3063                                              power_level, txpower, delta);
3064                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3065
3066                 /*
3067                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3068                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3069                  * TX_PWR_CFG_4: unknown
3070                  */
3071                 txpower = rt2x00_get_field16(eeprom,
3072                                              EEPROM_TXPOWER_BYRATE_RATE3);
3073                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3074                                              power_level, txpower, delta);
3075                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3076
3077                 rt2800_register_write(rt2x00dev, offset, reg);
3078
3079                 /* next TX_PWR_CFG register */
3080                 offset += 4;
3081         }
3082 }
3083
3084 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3085 {
3086         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
3087                               rt2x00dev->tx_power);
3088 }
3089 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3090
3091 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3092 {
3093         u32     tx_pin;
3094         u8      rfcsr;
3095
3096         /*
3097          * A voltage-controlled oscillator(VCO) is an electronic oscillator
3098          * designed to be controlled in oscillation frequency by a voltage
3099          * input. Maybe the temperature will affect the frequency of
3100          * oscillation to be shifted. The VCO calibration will be called
3101          * periodically to adjust the frequency to be precision.
3102         */
3103
3104         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3105         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3106         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3107
3108         switch (rt2x00dev->chip.rf) {
3109         case RF2020:
3110         case RF3020:
3111         case RF3021:
3112         case RF3022:
3113         case RF3320:
3114         case RF3052:
3115                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3116                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3117                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3118                 break;
3119         case RF3290:
3120         case RF5360:
3121         case RF5370:
3122         case RF5372:
3123         case RF5390:
3124         case RF5392:
3125                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3126                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3127                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3128                 break;
3129         default:
3130                 return;
3131         }
3132
3133         mdelay(1);
3134
3135         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3136         if (rt2x00dev->rf_channel <= 14) {
3137                 switch (rt2x00dev->default_ant.tx_chain_num) {
3138                 case 3:
3139                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3140                         /* fall through */
3141                 case 2:
3142                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3143                         /* fall through */
3144                 case 1:
3145                 default:
3146                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3147                         break;
3148                 }
3149         } else {
3150                 switch (rt2x00dev->default_ant.tx_chain_num) {
3151                 case 3:
3152                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3153                         /* fall through */
3154                 case 2:
3155                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3156                         /* fall through */
3157                 case 1:
3158                 default:
3159                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3160                         break;
3161                 }
3162         }
3163         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3164
3165 }
3166 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3167
3168 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3169                                       struct rt2x00lib_conf *libconf)
3170 {
3171         u32 reg;
3172
3173         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3174         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3175                            libconf->conf->short_frame_max_tx_count);
3176         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3177                            libconf->conf->long_frame_max_tx_count);
3178         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3179 }
3180
3181 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3182                              struct rt2x00lib_conf *libconf)
3183 {
3184         enum dev_state state =
3185             (libconf->conf->flags & IEEE80211_CONF_PS) ?
3186                 STATE_SLEEP : STATE_AWAKE;
3187         u32 reg;
3188
3189         if (state == STATE_SLEEP) {
3190                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3191
3192                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3193                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3194                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3195                                    libconf->conf->listen_interval - 1);
3196                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3197                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3198
3199                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3200         } else {
3201                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3202                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3203                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3204                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3205                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3206
3207                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3208         }
3209 }
3210
3211 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3212                    struct rt2x00lib_conf *libconf,
3213                    const unsigned int flags)
3214 {
3215         /* Always recalculate LNA gain before changing configuration */
3216         rt2800_config_lna_gain(rt2x00dev, libconf);
3217
3218         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3219                 rt2800_config_channel(rt2x00dev, libconf->conf,
3220                                       &libconf->rf, &libconf->channel);
3221                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3222                                       libconf->conf->power_level);
3223         }
3224         if (flags & IEEE80211_CONF_CHANGE_POWER)
3225                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3226                                       libconf->conf->power_level);
3227         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3228                 rt2800_config_retry_limit(rt2x00dev, libconf);
3229         if (flags & IEEE80211_CONF_CHANGE_PS)
3230                 rt2800_config_ps(rt2x00dev, libconf);
3231 }
3232 EXPORT_SYMBOL_GPL(rt2800_config);
3233
3234 /*
3235  * Link tuning
3236  */
3237 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3238 {
3239         u32 reg;
3240
3241         /*
3242          * Update FCS error count from register.
3243          */
3244         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3245         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3246 }
3247 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3248
3249 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3250 {
3251         u8 vgc;
3252
3253         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3254                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3255                     rt2x00_rt(rt2x00dev, RT3071) ||
3256                     rt2x00_rt(rt2x00dev, RT3090) ||
3257                     rt2x00_rt(rt2x00dev, RT3290) ||
3258                     rt2x00_rt(rt2x00dev, RT3390) ||
3259                     rt2x00_rt(rt2x00dev, RT3572) ||
3260                     rt2x00_rt(rt2x00dev, RT5390) ||
3261                     rt2x00_rt(rt2x00dev, RT5392))
3262                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3263                 else
3264                         vgc = 0x2e + rt2x00dev->lna_gain;
3265         } else { /* 5GHZ band */
3266                 if (rt2x00_rt(rt2x00dev, RT3572))
3267                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3268                 else {
3269                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3270                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3271                         else
3272                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3273                 }
3274         }
3275
3276         return vgc;
3277 }
3278
3279 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3280                                   struct link_qual *qual, u8 vgc_level)
3281 {
3282         if (qual->vgc_level != vgc_level) {
3283                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3284                 qual->vgc_level = vgc_level;
3285                 qual->vgc_level_reg = vgc_level;
3286         }
3287 }
3288
3289 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3290 {
3291         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3292 }
3293 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3294
3295 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3296                        const u32 count)
3297 {
3298         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3299                 return;
3300
3301         /*
3302          * When RSSI is better then -80 increase VGC level with 0x10
3303          */
3304         rt2800_set_vgc(rt2x00dev, qual,
3305                        rt2800_get_default_vgc(rt2x00dev) +
3306                        ((qual->rssi > -80) * 0x10));
3307 }
3308 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3309
3310 /*
3311  * Initialization functions.
3312  */
3313 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3314 {
3315         u32 reg;
3316         u16 eeprom;
3317         unsigned int i;
3318         int ret;
3319
3320         rt2800_disable_wpdma(rt2x00dev);
3321
3322         ret = rt2800_drv_init_registers(rt2x00dev);
3323         if (ret)
3324                 return ret;
3325
3326         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3327         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3328         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3329         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3330         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3331         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3332
3333         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3334         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3335         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3336         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3337         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3338         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3339
3340         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3341         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3342
3343         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3344
3345         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3346         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3347         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3348         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3349         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3350         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3351         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3352         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3353
3354         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3355
3356         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3357         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3358         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3359         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3360
3361         if (rt2x00_rt(rt2x00dev, RT3290)) {
3362                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3363                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3364                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3365                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3366                 }
3367
3368                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3369                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3370                         rt2x00_set_field32(&reg, LDO0_EN, 1);
3371                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3372                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3373                 }
3374
3375                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3376                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3377                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3378                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3379                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3380
3381                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3382                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3383                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3384
3385                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3386                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3387                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3388                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3389                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3390                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3391
3392                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3393                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3394                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3395         }
3396
3397         if (rt2x00_rt(rt2x00dev, RT3071) ||
3398             rt2x00_rt(rt2x00dev, RT3090) ||
3399             rt2x00_rt(rt2x00dev, RT3290) ||
3400             rt2x00_rt(rt2x00dev, RT3390)) {
3401
3402                 if (rt2x00_rt(rt2x00dev, RT3290))
3403                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3404                                               0x00000404);
3405                 else
3406                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3407                                               0x00000400);
3408
3409                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3410                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3411                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3412                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3413                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3414                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3415                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3416                                                       0x0000002c);
3417                         else
3418                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3419                                                       0x0000000f);
3420                 } else {
3421                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3422                 }
3423         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3424                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3425
3426                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3427                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3428                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3429                 } else {
3430                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3431                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3432                 }
3433         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3434                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3435                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3436                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3437         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3438                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3439                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3440                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3441         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3442                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3443                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3444         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3445                    rt2x00_rt(rt2x00dev, RT5392) ||
3446                    rt2x00_rt(rt2x00dev, RT5592)) {
3447                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3448                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3449                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3450         } else {
3451                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3452                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3453         }
3454
3455         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3456         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3457         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3458         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3459         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3460         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3461         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3462         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3463         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3464         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3465
3466         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3467         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3468         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3469         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3470         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3471
3472         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3473         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3474         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3475             rt2x00_rt(rt2x00dev, RT2883) ||
3476             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3477                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3478         else
3479                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3480         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3481         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3482         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3483
3484         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3485         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3486         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3487         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3488         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3489         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3490         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3491         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3492         rt2800_register_write(rt2x00dev, LED_CFG, reg);
3493
3494         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3495
3496         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3497         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3498         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3499         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3500         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3501         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3502         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3503         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3504
3505         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3506         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3507         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3508         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3509         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3510         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3511         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3512         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3513         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3514
3515         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3516         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3517         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3518         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3519         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3520         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3521         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3522         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3523         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3524         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3525         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3526         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3527
3528         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3529         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3530         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3531         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3532         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3533         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3534         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3535         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3536         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3537         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3538         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3539         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3540
3541         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3542         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3543         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3544         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3545         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3546         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3547         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3548         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3549         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3550         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3551         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3552         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3553
3554         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3555         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3556         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3557         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3558         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3559         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3560         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3561         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3562         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3563         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3564         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3565         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3566
3567         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3568         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3569         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3570         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3571         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3572         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3573         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3574         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3575         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3576         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3577         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3578         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3579
3580         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3581         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3582         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3583         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3584         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3585         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3586         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3587         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3588         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3589         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3590         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3591         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3592
3593         if (rt2x00_is_usb(rt2x00dev)) {
3594                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3595
3596                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3597                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3598                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3599                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3600                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3601                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3602                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3603                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3604                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3605                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3606                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3607         }
3608
3609         /*
3610          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3611          * although it is reserved.
3612          */
3613         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3614         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3615         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3616         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3617         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3618         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3619         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3620         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3621         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3622         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3623         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3624         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3625
3626         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3627         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3628
3629         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3630         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3631         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3632                            IEEE80211_MAX_RTS_THRESHOLD);
3633         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3634         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3635
3636         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3637
3638         /*
3639          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3640          * time should be set to 16. However, the original Ralink driver uses
3641          * 16 for both and indeed using a value of 10 for CCK SIFS results in
3642          * connection problems with 11g + CTS protection. Hence, use the same
3643          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3644          */
3645         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3646         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3647         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3648         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3649         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3650         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3651         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3652
3653         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3654
3655         /*
3656          * ASIC will keep garbage value after boot, clear encryption keys.
3657          */
3658         for (i = 0; i < 4; i++)
3659                 rt2800_register_write(rt2x00dev,
3660                                          SHARED_KEY_MODE_ENTRY(i), 0);
3661
3662         for (i = 0; i < 256; i++) {
3663                 rt2800_config_wcid(rt2x00dev, NULL, i);
3664                 rt2800_delete_wcid_attr(rt2x00dev, i);
3665                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3666         }
3667
3668         /*
3669          * Clear all beacons
3670          */
3671         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3672         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3673         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3674         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3675         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3676         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3677         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3678         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3679
3680         if (rt2x00_is_usb(rt2x00dev)) {
3681                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3682                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3683                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3684         } else if (rt2x00_is_pcie(rt2x00dev)) {
3685                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3686                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3687                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3688         }
3689
3690         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3691         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3692         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3693         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3694         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3695         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3696         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3697         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3698         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3699         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3700
3701         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3702         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3703         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3704         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3705         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3706         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3707         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3708         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3709         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3710         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3711
3712         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3713         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3714         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3715         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3716         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3717         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3718         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3719         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3720         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3721         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3722
3723         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3724         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3725         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3726         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3727         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3728         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3729
3730         /*
3731          * Do not force the BA window size, we use the TXWI to set it
3732          */
3733         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3734         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3735         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3736         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3737
3738         /*
3739          * We must clear the error counters.
3740          * These registers are cleared on read,
3741          * so we may pass a useless variable to store the value.
3742          */
3743         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3744         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3745         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3746         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3747         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3748         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3749
3750         /*
3751          * Setup leadtime for pre tbtt interrupt to 6ms
3752          */
3753         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3754         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3755         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3756
3757         /*
3758          * Set up channel statistics timer
3759          */
3760         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3761         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3762         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3763         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3764         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3765         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3766         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3767
3768         return 0;
3769 }
3770
3771 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3772 {
3773         unsigned int i;
3774         u32 reg;
3775
3776         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3777                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3778                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3779                         return 0;
3780
3781                 udelay(REGISTER_BUSY_DELAY);
3782         }
3783
3784         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3785         return -EACCES;
3786 }
3787
3788 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3789 {
3790         unsigned int i;
3791         u8 value;
3792
3793         /*
3794          * BBP was enabled after firmware was loaded,
3795          * but we need to reactivate it now.
3796          */
3797         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3798         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3799         msleep(1);
3800
3801         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3802                 rt2800_bbp_read(rt2x00dev, 0, &value);
3803                 if ((value != 0xff) && (value != 0x00))
3804                         return 0;
3805                 udelay(REGISTER_BUSY_DELAY);
3806         }
3807
3808         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3809         return -EACCES;
3810 }
3811
3812 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3813 {
3814         u8 value;
3815
3816         rt2800_bbp_read(rt2x00dev, 4, &value);
3817         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3818         rt2800_bbp_write(rt2x00dev, 4, value);
3819 }
3820
3821 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3822 {
3823         rt2800_bbp_write(rt2x00dev, 142, 1);
3824         rt2800_bbp_write(rt2x00dev, 143, 57);
3825 }
3826
3827 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3828 {
3829         const u8 glrt_table[] = {
3830                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3831                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3832                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3833                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3834                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3835                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3836                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3837                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3838                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
3839         };
3840         int i;
3841
3842         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3843                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3844                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3845         }
3846 };
3847
3848 static void rt2800_init_bbb_early(struct rt2x00_dev *rt2x00dev)
3849 {
3850         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3851         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3852         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3853         rt2800_bbp_write(rt2x00dev, 69, 0x12);
3854         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3855         rt2800_bbp_write(rt2x00dev, 73, 0x10);
3856         rt2800_bbp_write(rt2x00dev, 81, 0x37);
3857         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3858         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3859         rt2800_bbp_write(rt2x00dev, 84, 0x99);
3860         rt2800_bbp_write(rt2x00dev, 86, 0x00);
3861         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3862         rt2800_bbp_write(rt2x00dev, 92, 0x00);
3863         rt2800_bbp_write(rt2x00dev, 103, 0x00);
3864         rt2800_bbp_write(rt2x00dev, 105, 0x05);
3865         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3866 }
3867
3868 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3869 {
3870         int ant, div_mode;
3871         u16 eeprom;
3872         u8 value;
3873
3874         rt2800_init_bbb_early(rt2x00dev);
3875
3876         rt2800_bbp_read(rt2x00dev, 105, &value);
3877         rt2x00_set_field8(&value, BBP105_MLD,
3878                           rt2x00dev->default_ant.rx_chain_num == 2);
3879         rt2800_bbp_write(rt2x00dev, 105, value);
3880
3881         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3882
3883         rt2800_bbp_write(rt2x00dev, 20, 0x06);
3884         rt2800_bbp_write(rt2x00dev, 31, 0x08);
3885         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3886         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3887         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3888         rt2800_bbp_write(rt2x00dev, 70, 0x05);
3889         rt2800_bbp_write(rt2x00dev, 73, 0x13);
3890         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3891         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3892         rt2800_bbp_write(rt2x00dev, 76, 0x28);
3893         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3894         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3895         rt2800_bbp_write(rt2x00dev, 86, 0x38);
3896         rt2800_bbp_write(rt2x00dev, 88, 0x90);
3897         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3898         rt2800_bbp_write(rt2x00dev, 92, 0x02);
3899         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3900         rt2800_bbp_write(rt2x00dev, 98, 0x12);
3901         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3902         rt2800_bbp_write(rt2x00dev, 104, 0x92);
3903         /* FIXME BBP105 owerwrite */
3904         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3905         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3906         rt2800_bbp_write(rt2x00dev, 128, 0x12);
3907         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3908         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3909         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3910
3911         /* Initialize GLRT (Generalized Likehood Radio Test) */
3912         rt2800_init_bbp_5592_glrt(rt2x00dev);
3913
3914         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3915
3916         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3917         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
3918         ant = (div_mode == 3) ? 1 : 0;
3919         rt2800_bbp_read(rt2x00dev, 152, &value);
3920         if (ant == 0) {
3921                 /* Main antenna */
3922                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3923         } else {
3924                 /* Auxiliary antenna */
3925                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3926         }
3927         rt2800_bbp_write(rt2x00dev, 152, value);
3928
3929         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
3930                 rt2800_bbp_read(rt2x00dev, 254, &value);
3931                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
3932                 rt2800_bbp_write(rt2x00dev, 254, value);
3933         }
3934
3935         rt2800_init_freq_calibration(rt2x00dev);
3936
3937         rt2800_bbp_write(rt2x00dev, 84, 0x19);
3938         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
3939                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3940 }
3941
3942 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3943 {
3944         unsigned int i;
3945         u16 eeprom;
3946         u8 reg_id;
3947         u8 value;
3948
3949         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3950                      rt2800_wait_bbp_ready(rt2x00dev)))
3951                 return -EACCES;
3952
3953         if (rt2x00_rt(rt2x00dev, RT5592)) {
3954                 rt2800_init_bbp_5592(rt2x00dev);
3955                 return 0;
3956         }
3957
3958         if (rt2x00_rt(rt2x00dev, RT3352)) {
3959                 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3960                 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3961         }
3962
3963         if (rt2x00_rt(rt2x00dev, RT3290) ||
3964             rt2x00_rt(rt2x00dev, RT5390) ||
3965             rt2x00_rt(rt2x00dev, RT5392))
3966                 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3967
3968         if (rt2800_is_305x_soc(rt2x00dev) ||
3969             rt2x00_rt(rt2x00dev, RT3290) ||
3970             rt2x00_rt(rt2x00dev, RT3352) ||
3971             rt2x00_rt(rt2x00dev, RT3572) ||
3972             rt2x00_rt(rt2x00dev, RT5390) ||
3973             rt2x00_rt(rt2x00dev, RT5392))
3974                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3975
3976         if (rt2x00_rt(rt2x00dev, RT3352))
3977                 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3978
3979         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3980         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3981
3982         if (rt2x00_rt(rt2x00dev, RT3290) ||
3983             rt2x00_rt(rt2x00dev, RT3352) ||
3984             rt2x00_rt(rt2x00dev, RT5390) ||
3985             rt2x00_rt(rt2x00dev, RT5392))
3986                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3987
3988         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3989                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3990                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3991         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3992                    rt2x00_rt(rt2x00dev, RT3352) ||
3993                    rt2x00_rt(rt2x00dev, RT5390) ||
3994                    rt2x00_rt(rt2x00dev, RT5392)) {
3995                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3996                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3997                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3998                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3999
4000                 if (rt2x00_rt(rt2x00dev, RT3290))
4001                         rt2800_bbp_write(rt2x00dev, 77, 0x58);
4002                 else
4003                         rt2800_bbp_write(rt2x00dev, 77, 0x59);
4004         } else {
4005                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4006                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4007         }
4008
4009         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4010
4011         if (rt2x00_rt(rt2x00dev, RT3070) ||
4012             rt2x00_rt(rt2x00dev, RT3071) ||
4013             rt2x00_rt(rt2x00dev, RT3090) ||
4014             rt2x00_rt(rt2x00dev, RT3390) ||
4015             rt2x00_rt(rt2x00dev, RT3572) ||
4016             rt2x00_rt(rt2x00dev, RT5390) ||
4017             rt2x00_rt(rt2x00dev, RT5392)) {
4018                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4019                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4020                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4021         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4022                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4023                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4024         } else if (rt2x00_rt(rt2x00dev, RT3290)) {
4025                 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4026                 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4027                 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4028                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4029         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4030                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4031                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4032                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4033         } else {
4034                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4035         }
4036
4037         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4038         if (rt2x00_rt(rt2x00dev, RT3290) ||
4039             rt2x00_rt(rt2x00dev, RT5390) ||
4040             rt2x00_rt(rt2x00dev, RT5392))
4041                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4042         else
4043                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4044
4045         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4046                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4047         else if (rt2x00_rt(rt2x00dev, RT3290) ||
4048                  rt2x00_rt(rt2x00dev, RT5390) ||
4049                  rt2x00_rt(rt2x00dev, RT5392))
4050                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4051         else
4052                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4053
4054         if (rt2x00_rt(rt2x00dev, RT3290) ||
4055             rt2x00_rt(rt2x00dev, RT3352) ||
4056             rt2x00_rt(rt2x00dev, RT5390) ||
4057             rt2x00_rt(rt2x00dev, RT5392))
4058                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4059         else
4060                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4061
4062         if (rt2x00_rt(rt2x00dev, RT3352) ||
4063             rt2x00_rt(rt2x00dev, RT5392))
4064                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4065
4066         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4067
4068         if (rt2x00_rt(rt2x00dev, RT3290) ||
4069             rt2x00_rt(rt2x00dev, RT3352) ||
4070             rt2x00_rt(rt2x00dev, RT5390) ||
4071             rt2x00_rt(rt2x00dev, RT5392))
4072                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4073         else
4074                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4075
4076         if (rt2x00_rt(rt2x00dev, RT5392)) {
4077                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4078                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4079         }
4080
4081         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4082             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4083             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
4084             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
4085             rt2x00_rt(rt2x00dev, RT3290) ||
4086             rt2x00_rt(rt2x00dev, RT3352) ||
4087             rt2x00_rt(rt2x00dev, RT3572) ||
4088             rt2x00_rt(rt2x00dev, RT5390) ||
4089             rt2x00_rt(rt2x00dev, RT5392) ||
4090             rt2800_is_305x_soc(rt2x00dev))
4091                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4092         else
4093                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4094
4095         if (rt2x00_rt(rt2x00dev, RT3290) ||
4096             rt2x00_rt(rt2x00dev, RT3352) ||
4097             rt2x00_rt(rt2x00dev, RT5390) ||
4098             rt2x00_rt(rt2x00dev, RT5392))
4099                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4100
4101         if (rt2800_is_305x_soc(rt2x00dev))
4102                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4103         else if (rt2x00_rt(rt2x00dev, RT3290))
4104                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4105         else if (rt2x00_rt(rt2x00dev, RT3352))
4106                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4107         else if (rt2x00_rt(rt2x00dev, RT5390) ||
4108                  rt2x00_rt(rt2x00dev, RT5392))
4109                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4110         else
4111                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4112
4113         if (rt2x00_rt(rt2x00dev, RT3290) ||
4114             rt2x00_rt(rt2x00dev, RT5390))
4115                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4116         else if (rt2x00_rt(rt2x00dev, RT3352))
4117                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4118         else if (rt2x00_rt(rt2x00dev, RT5392))
4119                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4120         else
4121                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4122
4123         if (rt2x00_rt(rt2x00dev, RT3352))
4124                 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4125
4126         if (rt2x00_rt(rt2x00dev, RT3290) ||
4127             rt2x00_rt(rt2x00dev, RT5390) ||
4128             rt2x00_rt(rt2x00dev, RT5392))
4129                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4130
4131         if (rt2x00_rt(rt2x00dev, RT5392)) {
4132                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4133                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4134         }
4135
4136         if (rt2x00_rt(rt2x00dev, RT3352))
4137                 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4138
4139         if (rt2x00_rt(rt2x00dev, RT3071) ||
4140             rt2x00_rt(rt2x00dev, RT3090) ||
4141             rt2x00_rt(rt2x00dev, RT3390) ||
4142             rt2x00_rt(rt2x00dev, RT3572) ||
4143             rt2x00_rt(rt2x00dev, RT5390) ||
4144             rt2x00_rt(rt2x00dev, RT5392)) {
4145                 rt2800_bbp_read(rt2x00dev, 138, &value);
4146
4147                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4148                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4149                         value |= 0x20;
4150                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4151                         value &= ~0x02;
4152
4153                 rt2800_bbp_write(rt2x00dev, 138, value);
4154         }
4155
4156         if (rt2x00_rt(rt2x00dev, RT3290)) {
4157                 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4158                 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4159                 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4160                 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4161                 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4162                 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4163                 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4164                 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4165                 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4166                 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4167
4168                 rt2800_bbp_read(rt2x00dev, 47, &value);
4169                 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4170                 rt2800_bbp_write(rt2x00dev, 47, value);
4171
4172                 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4173                 rt2800_bbp_read(rt2x00dev, 3, &value);
4174                 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4175                 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4176                 rt2800_bbp_write(rt2x00dev, 3, value);
4177         }
4178
4179         if (rt2x00_rt(rt2x00dev, RT3352)) {
4180                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4181                 /* Set ITxBF timeout to 0x9c40=1000msec */
4182                 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4183                 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4184                 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4185                 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4186                 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4187                 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4188                 /* Reprogram the inband interface to put right values in RXWI */
4189                 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4190                 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4191                 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4192                 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4193                 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4194                 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4195                 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4196                 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4197
4198                 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4199         }
4200
4201         if (rt2x00_rt(rt2x00dev, RT5390) ||
4202             rt2x00_rt(rt2x00dev, RT5392)) {
4203                 int ant, div_mode;
4204
4205                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4206                 div_mode = rt2x00_get_field16(eeprom,
4207                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
4208                 ant = (div_mode == 3) ? 1 : 0;
4209
4210                 /* check if this is a Bluetooth combo card */
4211                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4212                         u32 reg;
4213
4214                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4215                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4216                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4217                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4218                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4219                         if (ant == 0)
4220                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4221                         else if (ant == 1)
4222                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4223                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4224                 }
4225
4226                 /* This chip has hardware antenna diversity*/
4227                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4228                         rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4229                         rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4230                         rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4231                 }
4232
4233                 rt2800_bbp_read(rt2x00dev, 152, &value);
4234                 if (ant == 0)
4235                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4236                 else
4237                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4238                 rt2800_bbp_write(rt2x00dev, 152, value);
4239
4240                 rt2800_init_freq_calibration(rt2x00dev);
4241         }
4242
4243         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4244                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4245
4246                 if (eeprom != 0xffff && eeprom != 0x0000) {
4247                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4248                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4249                         rt2800_bbp_write(rt2x00dev, reg_id, value);
4250                 }
4251         }
4252
4253         return 0;
4254 }
4255
4256 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
4257                                 bool bw40, u8 rfcsr24, u8 filter_target)
4258 {
4259         unsigned int i;
4260         u8 bbp;
4261         u8 rfcsr;
4262         u8 passband;
4263         u8 stopband;
4264         u8 overtuned = 0;
4265
4266         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4267
4268         rt2800_bbp_read(rt2x00dev, 4, &bbp);
4269         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4270         rt2800_bbp_write(rt2x00dev, 4, bbp);
4271
4272         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4273         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4274         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4275
4276         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4277         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4278         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4279
4280         /*
4281          * Set power & frequency of passband test tone
4282          */
4283         rt2800_bbp_write(rt2x00dev, 24, 0);
4284
4285         for (i = 0; i < 100; i++) {
4286                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4287                 msleep(1);
4288
4289                 rt2800_bbp_read(rt2x00dev, 55, &passband);
4290                 if (passband)
4291                         break;
4292         }
4293
4294         /*
4295          * Set power & frequency of stopband test tone
4296          */
4297         rt2800_bbp_write(rt2x00dev, 24, 0x06);
4298
4299         for (i = 0; i < 100; i++) {
4300                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4301                 msleep(1);
4302
4303                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4304
4305                 if ((passband - stopband) <= filter_target) {
4306                         rfcsr24++;
4307                         overtuned += ((passband - stopband) == filter_target);
4308                 } else
4309                         break;
4310
4311                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4312         }
4313
4314         rfcsr24 -= !!overtuned;
4315
4316         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4317         return rfcsr24;
4318 }
4319
4320 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4321 {
4322         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4323         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4324         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4325         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4326         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4327         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4328         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4329         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4330         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4331         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4332         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4333         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4334         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4335         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4336         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4337         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4338         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4339         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4340         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4341         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4342         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4343         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4344         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4345         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4346         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4347         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4348         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4349         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4350         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4351         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4352         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4353         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4354 }
4355
4356 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4357 {
4358         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4359         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4360         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4361         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4362         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4363         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4364         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4365         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4366         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4367         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4368         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4369         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4370         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4371         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4372         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4373         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4374         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4375         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4376         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4377 }
4378
4379 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4380 {
4381         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4382         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4383         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4384         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4385         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4386         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4387         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4388         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4389         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4390         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4391         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4392         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4393         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4394         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4395         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4396         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4397         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4398         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4399         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4400         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4401         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4402         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4403         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4404         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4405         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4406         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4407         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4408         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4409         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4410         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4411         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4412         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4413         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4414         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4415         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4416         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4417         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4418         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4419         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4420         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4421         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4422         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4423         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4424         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4425         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4426         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4427 }
4428
4429 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4430 {
4431         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4432         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4433         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4434         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4435         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4436         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4437         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4438         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4439         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4440         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4441         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4442         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4443         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4444         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4445         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4446         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4447         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4448         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4449         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4450         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4451         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4452         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4453         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4454         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4455         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4456         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4457         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4458         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4459         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4460         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4461         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4462         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4463         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4464         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4465         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4466         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4467         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4468         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4469         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4470         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4471         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4472         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4473         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4474         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4475         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4476         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4477         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4478         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4479         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4480         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4481         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4482         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4483         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4484         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4485         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4486         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4487         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4488         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4489         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4490         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4491         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4492         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4493         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4494 }
4495
4496 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4497 {
4498         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4499         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4500         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4501         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4502         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4503         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4504         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4505         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4506         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4507         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4508         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4509         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4510         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4511         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4512         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4513         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4514         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4515         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4516         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4517         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4518         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4519         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4520         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4521         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4522         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4523         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4524         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4525         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4526         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4527         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4528         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4529         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4530 }
4531
4532 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4533 {
4534         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4535         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4536         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4537         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4538         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4539         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4540         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4541         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4542         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4543         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4544         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4545         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4546         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4547         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4548         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4549         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4550         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4551         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4552         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4553         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4554         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4555         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4556         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4557         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4558         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4559         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4560         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4561         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4562         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4563         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4564         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4565 }
4566
4567 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4568 {
4569         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4570         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4571         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4572         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4573         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4574                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4575         else
4576                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4577         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4578         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4579         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4580         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4581         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4582         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4583         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4584         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4585         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4586         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4587
4588         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4589         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4590         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4591         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4592         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4593         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4594                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4595         else
4596                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4597         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4598         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4599         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4600         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4601
4602         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4603         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4604         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4605         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4606         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4607         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4608         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4609         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4610         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4611         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4612
4613         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4614                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4615         else
4616                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4617         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4618         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4619         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4620         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4621         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4622         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4623                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4624         else
4625                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4626         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4627         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4628         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4629
4630         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4631         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4632                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4633         else
4634                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4635         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4636         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4637         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4638         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4639         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4640         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4641
4642         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4643         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4644                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4645         else
4646                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4647         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4648         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4649 }
4650
4651 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4652 {
4653         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4654         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4655         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4656         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4657         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4658         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4659         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4660         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4661         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4662         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4663         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4664         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4665         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4666         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4667         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4668         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4669         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4670         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4671         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4672         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4673         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4674         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4675         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4676         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4677         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4678         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4679         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4680         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4681         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4682         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4683         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4684         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4685         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4686         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4687         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4688         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4689         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4690         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4691         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4692         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4693         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4694         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4695         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4696         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4697         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4698         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4699         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4700         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4701         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4702         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4703         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4704         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4705         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4706         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4707         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4708         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4709         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4710         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4711         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4712 }
4713
4714 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
4715 {
4716         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
4717         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4718         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4719         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4720         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
4721         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4722         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4723         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4724         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4725         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4726         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
4727         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
4728         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
4729         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4730         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4731         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4732         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4733         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4734         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4735         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
4736         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
4737         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4738
4739         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4740         msleep(1);
4741
4742         rt2800_adjust_freq_offset(rt2x00dev);
4743 }
4744
4745 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4746 {
4747         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4748         u8 rfcsr;
4749         u8 bbp;
4750         u32 reg;
4751         u16 eeprom;
4752
4753         if (!rt2x00_rt(rt2x00dev, RT3070) &&
4754             !rt2x00_rt(rt2x00dev, RT3071) &&
4755             !rt2x00_rt(rt2x00dev, RT3090) &&
4756             !rt2x00_rt(rt2x00dev, RT3290) &&
4757             !rt2x00_rt(rt2x00dev, RT3352) &&
4758             !rt2x00_rt(rt2x00dev, RT3390) &&
4759             !rt2x00_rt(rt2x00dev, RT3572) &&
4760             !rt2x00_rt(rt2x00dev, RT5390) &&
4761             !rt2x00_rt(rt2x00dev, RT5392) &&
4762             !rt2x00_rt(rt2x00dev, RT5392) &&
4763             !rt2x00_rt(rt2x00dev, RT5592) &&
4764             !rt2800_is_305x_soc(rt2x00dev))
4765                 return 0;
4766
4767         /*
4768          * Init RF calibration.
4769          */
4770
4771         if (rt2x00_rt(rt2x00dev, RT3290) ||
4772             rt2x00_rt(rt2x00dev, RT5390) ||
4773             rt2x00_rt(rt2x00dev, RT5392)) {
4774                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4775                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4776                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4777                 msleep(1);
4778                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4779                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4780         } else {
4781                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4782                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4783                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4784                 msleep(1);
4785                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4786                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4787         }
4788
4789         if (rt2800_is_305x_soc(rt2x00dev)) {
4790                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4791                 return 0;
4792         }
4793
4794         switch (rt2x00dev->chip.rt) {
4795         case RT3070:
4796         case RT3071:
4797         case RT3090:
4798                 rt2800_init_rfcsr_30xx(rt2x00dev);
4799                 break;
4800         case RT3290:
4801                 rt2800_init_rfcsr_3290(rt2x00dev);
4802                 break;
4803         case RT3352:
4804                 rt2800_init_rfcsr_3352(rt2x00dev);
4805                 break;
4806         case RT3390:
4807                 rt2800_init_rfcsr_3390(rt2x00dev);
4808                 break;
4809         case RT3572:
4810                 rt2800_init_rfcsr_3572(rt2x00dev);
4811                 break;
4812         case RT5390:
4813                 rt2800_init_rfcsr_5390(rt2x00dev);
4814                 break;
4815         case RT5392:
4816                 rt2800_init_rfcsr_5392(rt2x00dev);
4817                 break;
4818         case RT5592:
4819                 rt2800_init_rfcsr_5592(rt2x00dev);
4820                 break;
4821         }
4822
4823         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4824                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4825                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4826                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4827                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4828         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4829                    rt2x00_rt(rt2x00dev, RT3090)) {
4830                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4831
4832                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4833                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4834                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4835
4836                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4837                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4838                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4839                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4840                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4841                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4842                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4843                         else
4844                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4845                 }
4846                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4847
4848                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4849                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4850                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4851         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4852                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4853                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4854                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4855         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4856                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4857                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4858                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4859
4860                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4861                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4862                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4863                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4864                 msleep(1);
4865                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4866                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4867                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4868                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4869         }
4870
4871         /*
4872          * Set RX Filter calibration for 20MHz and 40MHz
4873          */
4874         if (rt2x00_rt(rt2x00dev, RT3070)) {
4875                 drv_data->calibration_bw20 =
4876                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4877                 drv_data->calibration_bw40 =
4878                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4879         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4880                    rt2x00_rt(rt2x00dev, RT3090) ||
4881                    rt2x00_rt(rt2x00dev, RT3352) ||
4882                    rt2x00_rt(rt2x00dev, RT3390) ||
4883                    rt2x00_rt(rt2x00dev, RT3572)) {
4884                 drv_data->calibration_bw20 =
4885                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4886                 drv_data->calibration_bw40 =
4887                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4888         }
4889
4890         /*
4891          * Save BBP 25 & 26 values for later use in channel switching
4892          */
4893         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4894         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4895
4896         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4897             !rt2x00_rt(rt2x00dev, RT5392)) {
4898                 /*
4899                  * Set back to initial state
4900                  */
4901                 rt2800_bbp_write(rt2x00dev, 24, 0);
4902
4903                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4904                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4905                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4906
4907                 /*
4908                  * Set BBP back to BW20
4909                  */
4910                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4911                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4912                 rt2800_bbp_write(rt2x00dev, 4, bbp);
4913         }
4914
4915         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4916             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4917             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4918             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E) ||
4919             rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
4920                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4921
4922         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4923         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4924         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4925
4926         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4927             !rt2x00_rt(rt2x00dev, RT5392)) {
4928                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4929                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4930                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4931                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4932                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4933                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4934                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4935                                       &rt2x00dev->cap_flags))
4936                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4937                 }
4938                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4939                                   drv_data->txmixer_gain_24g);
4940                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4941         }
4942
4943         if (rt2x00_rt(rt2x00dev, RT3090) ||
4944             rt2x00_rt(rt2x00dev, RT5592)) {
4945                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4946
4947                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
4948                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4949                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4950                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4951                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4952                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4953
4954                 rt2800_bbp_write(rt2x00dev, 138, bbp);
4955         }
4956
4957         if (rt2x00_rt(rt2x00dev, RT3071) ||
4958             rt2x00_rt(rt2x00dev, RT3090) ||
4959             rt2x00_rt(rt2x00dev, RT3390)) {
4960                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4961                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4962                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4963                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4964                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4965                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4966                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4967
4968                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4969                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4970                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4971
4972                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4973                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4974                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4975
4976                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4977                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4978                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4979         }
4980
4981         if (rt2x00_rt(rt2x00dev, RT3070)) {
4982                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4983                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4984                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4985                 else
4986                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4987                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4988                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4989                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4990                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4991         }
4992
4993         if (rt2x00_rt(rt2x00dev, RT3290)) {
4994                 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4995                 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4996                 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4997         }
4998
4999         if (rt2x00_rt(rt2x00dev, RT5390) ||
5000             rt2x00_rt(rt2x00dev, RT5392) ||
5001             rt2x00_rt(rt2x00dev, RT5592)) {
5002                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5003                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5004                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5005
5006                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5007                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5008                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5009
5010                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5011                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5012                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5013         }
5014
5015         return 0;
5016 }
5017
5018 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5019 {
5020         u32 reg;
5021         u16 word;
5022
5023         /*
5024          * Initialize all registers.
5025          */
5026         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
5027                      rt2800_init_registers(rt2x00dev) ||
5028                      rt2800_init_bbp(rt2x00dev) ||
5029                      rt2800_init_rfcsr(rt2x00dev)))
5030                 return -EIO;
5031
5032         /*
5033          * Send signal to firmware during boot time.
5034          */
5035         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5036
5037         if (rt2x00_is_usb(rt2x00dev) &&
5038             (rt2x00_rt(rt2x00dev, RT3070) ||
5039              rt2x00_rt(rt2x00dev, RT3071) ||
5040              rt2x00_rt(rt2x00dev, RT3572))) {
5041                 udelay(200);
5042                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5043                 udelay(10);
5044         }
5045
5046         /*
5047          * Enable RX.
5048          */
5049         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5050         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5051         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5052         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5053
5054         udelay(50);
5055
5056         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5057         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5058         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5059         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5060         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5061         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5062
5063         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5064         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5065         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5066         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5067
5068         /*
5069          * Initialize LED control
5070          */
5071         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
5072         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
5073                            word & 0xff, (word >> 8) & 0xff);
5074
5075         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5076         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
5077                            word & 0xff, (word >> 8) & 0xff);
5078
5079         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5080         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
5081                            word & 0xff, (word >> 8) & 0xff);
5082
5083         return 0;
5084 }
5085 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5086
5087 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5088 {
5089         u32 reg;
5090
5091         rt2800_disable_wpdma(rt2x00dev);
5092
5093         /* Wait for DMA, ignore error */
5094         rt2800_wait_wpdma_ready(rt2x00dev);
5095
5096         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5097         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5098         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5099         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5100 }
5101 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
5102
5103 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5104 {
5105         u32 reg;
5106         u16 efuse_ctrl_reg;
5107
5108         if (rt2x00_rt(rt2x00dev, RT3290))
5109                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5110         else
5111                 efuse_ctrl_reg = EFUSE_CTRL;
5112
5113         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
5114         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5115 }
5116 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5117
5118 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5119 {
5120         u32 reg;
5121         u16 efuse_ctrl_reg;
5122         u16 efuse_data0_reg;
5123         u16 efuse_data1_reg;
5124         u16 efuse_data2_reg;
5125         u16 efuse_data3_reg;
5126
5127         if (rt2x00_rt(rt2x00dev, RT3290)) {
5128                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5129                 efuse_data0_reg = EFUSE_DATA0_3290;
5130                 efuse_data1_reg = EFUSE_DATA1_3290;
5131                 efuse_data2_reg = EFUSE_DATA2_3290;
5132                 efuse_data3_reg = EFUSE_DATA3_3290;
5133         } else {
5134                 efuse_ctrl_reg = EFUSE_CTRL;
5135                 efuse_data0_reg = EFUSE_DATA0;
5136                 efuse_data1_reg = EFUSE_DATA1;
5137                 efuse_data2_reg = EFUSE_DATA2;
5138                 efuse_data3_reg = EFUSE_DATA3;
5139         }
5140         mutex_lock(&rt2x00dev->csr_mutex);
5141
5142         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5143         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5144         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5145         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5146         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5147
5148         /* Wait until the EEPROM has been loaded */
5149         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5150         /* Apparently the data is read from end to start */
5151         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5152         /* The returned value is in CPU order, but eeprom is le */
5153         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5154         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5155         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5156         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5157         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5158         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5159         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5160
5161         mutex_unlock(&rt2x00dev->csr_mutex);
5162 }
5163
5164 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5165 {
5166         unsigned int i;
5167
5168         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5169                 rt2800_efuse_read(rt2x00dev, i);
5170
5171         return 0;
5172 }
5173 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5174
5175 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5176 {
5177         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5178         u16 word;
5179         u8 *mac;
5180         u8 default_lna_gain;
5181         int retval;
5182
5183         /*
5184          * Read the EEPROM.
5185          */
5186         retval = rt2800_read_eeprom(rt2x00dev);
5187         if (retval)
5188                 return retval;
5189
5190         /*
5191          * Start validation of the data that has been read.
5192          */
5193         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5194         if (!is_valid_ether_addr(mac)) {
5195                 eth_random_addr(mac);
5196                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
5197         }
5198
5199         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5200         if (word == 0xffff) {
5201                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5202                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5203                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5204                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5205                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5206         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5207                    rt2x00_rt(rt2x00dev, RT2872)) {
5208                 /*
5209                  * There is a max of 2 RX streams for RT28x0 series
5210                  */
5211                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5212                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5213                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5214         }
5215
5216         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5217         if (word == 0xffff) {
5218                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5219                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5220                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5221                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5222                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5223                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5224                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5225                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5226                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5227                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5228                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5229                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5230                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5231                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5232                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5233                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5234                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
5235         }
5236
5237         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5238         if ((word & 0x00ff) == 0x00ff) {
5239                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5240                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5241                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
5242         }
5243         if ((word & 0xff00) == 0xff00) {
5244                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5245                                    LED_MODE_TXRX_ACTIVITY);
5246                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5247                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5248                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5249                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5250                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5251                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
5252         }
5253
5254         /*
5255          * During the LNA validation we are going to use
5256          * lna0 as correct value. Note that EEPROM_LNA
5257          * is never validated.
5258          */
5259         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5260         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5261
5262         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5263         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5264                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5265         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5266                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5267         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5268
5269         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5270         if ((word & 0x00ff) != 0x00ff) {
5271                 drv_data->txmixer_gain_24g =
5272                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5273         } else {
5274                 drv_data->txmixer_gain_24g = 0;
5275         }
5276
5277         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5278         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5279                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5280         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5281             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5282                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5283                                    default_lna_gain);
5284         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5285
5286         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5287         if ((word & 0x00ff) != 0x00ff) {
5288                 drv_data->txmixer_gain_5g =
5289                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5290         } else {
5291                 drv_data->txmixer_gain_5g = 0;
5292         }
5293
5294         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5295         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5296                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5297         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5298                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5299         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5300
5301         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5302         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5303                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5304         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5305             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5306                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5307                                    default_lna_gain);
5308         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5309
5310         return 0;
5311 }
5312
5313 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5314 {
5315         u32 reg;
5316         u16 value;
5317         u16 eeprom;
5318
5319         /*
5320          * Read EEPROM word for configuration.
5321          */
5322         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5323
5324         /*
5325          * Identify RF chipset by EEPROM value
5326          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5327          * RT53xx: defined in "EEPROM_CHIP_ID" field
5328          */
5329         if (rt2x00_rt(rt2x00dev, RT3290))
5330                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
5331         else
5332                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
5333
5334         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
5335             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
5336             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
5337                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
5338         else
5339                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5340
5341         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
5342                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
5343
5344         switch (rt2x00dev->chip.rt) {
5345         case RT2860:
5346         case RT2872:
5347         case RT2883:
5348         case RT3070:
5349         case RT3071:
5350         case RT3090:
5351         case RT3290:
5352         case RT3352:
5353         case RT3390:
5354         case RT3572:
5355         case RT5390:
5356         case RT5392:
5357         case RT5592:
5358                 break;
5359         default:
5360                 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
5361                 return -ENODEV;
5362         }
5363
5364         switch (rt2x00dev->chip.rf) {
5365         case RF2820:
5366         case RF2850:
5367         case RF2720:
5368         case RF2750:
5369         case RF3020:
5370         case RF2020:
5371         case RF3021:
5372         case RF3022:
5373         case RF3052:
5374         case RF3290:
5375         case RF3320:
5376         case RF3322:
5377         case RF5360:
5378         case RF5370:
5379         case RF5372:
5380         case RF5390:
5381         case RF5392:
5382         case RF5592:
5383                 break;
5384         default:
5385                 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
5386                       rt2x00dev->chip.rf);
5387                 return -ENODEV;
5388         }
5389
5390         /*
5391          * Identify default antenna configuration.
5392          */
5393         rt2x00dev->default_ant.tx_chain_num =
5394             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5395         rt2x00dev->default_ant.rx_chain_num =
5396             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5397
5398         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5399
5400         if (rt2x00_rt(rt2x00dev, RT3070) ||
5401             rt2x00_rt(rt2x00dev, RT3090) ||
5402             rt2x00_rt(rt2x00dev, RT3352) ||
5403             rt2x00_rt(rt2x00dev, RT3390)) {
5404                 value = rt2x00_get_field16(eeprom,
5405                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5406                 switch (value) {
5407                 case 0:
5408                 case 1:
5409                 case 2:
5410                         rt2x00dev->default_ant.tx = ANTENNA_A;
5411                         rt2x00dev->default_ant.rx = ANTENNA_A;
5412                         break;
5413                 case 3:
5414                         rt2x00dev->default_ant.tx = ANTENNA_A;
5415                         rt2x00dev->default_ant.rx = ANTENNA_B;
5416                         break;
5417                 }
5418         } else {
5419                 rt2x00dev->default_ant.tx = ANTENNA_A;
5420                 rt2x00dev->default_ant.rx = ANTENNA_A;
5421         }
5422
5423         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5424                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5425                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5426         }
5427
5428         /*
5429          * Determine external LNA informations.
5430          */
5431         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5432                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5433         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5434                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5435
5436         /*
5437          * Detect if this device has an hardware controlled radio.
5438          */
5439         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5440                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5441
5442         /*
5443          * Detect if this device has Bluetooth co-existence.
5444          */
5445         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5446                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5447
5448         /*
5449          * Read frequency offset and RF programming sequence.
5450          */
5451         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5452         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5453
5454         /*
5455          * Store led settings, for correct led behaviour.
5456          */
5457 #ifdef CONFIG_RT2X00_LIB_LEDS
5458         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5459         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5460         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5461
5462         rt2x00dev->led_mcu_reg = eeprom;
5463 #endif /* CONFIG_RT2X00_LIB_LEDS */
5464
5465         /*
5466          * Check if support EIRP tx power limit feature.
5467          */
5468         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5469
5470         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5471                                         EIRP_MAX_TX_POWER_LIMIT)
5472                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5473
5474         return 0;
5475 }
5476
5477 /*
5478  * RF value list for rt28xx
5479  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5480  */
5481 static const struct rf_channel rf_vals[] = {
5482         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5483         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5484         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5485         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5486         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5487         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5488         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5489         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5490         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5491         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5492         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5493         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5494         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5495         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5496
5497         /* 802.11 UNI / HyperLan 2 */
5498         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5499         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5500         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5501         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5502         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5503         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5504         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5505         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5506         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5507         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5508         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5509         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5510
5511         /* 802.11 HyperLan 2 */
5512         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5513         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5514         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5515         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5516         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5517         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5518         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5519         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5520         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5521         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5522         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5523         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5524         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5525         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5526         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5527         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5528
5529         /* 802.11 UNII */
5530         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5531         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5532         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5533         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5534         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5535         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5536         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5537         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5538         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5539         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5540         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5541
5542         /* 802.11 Japan */
5543         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5544         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5545         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5546         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5547         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5548         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5549         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5550 };
5551
5552 /*
5553  * RF value list for rt3xxx
5554  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5555  */
5556 static const struct rf_channel rf_vals_3x[] = {
5557         {1,  241, 2, 2 },
5558         {2,  241, 2, 7 },
5559         {3,  242, 2, 2 },
5560         {4,  242, 2, 7 },
5561         {5,  243, 2, 2 },
5562         {6,  243, 2, 7 },
5563         {7,  244, 2, 2 },
5564         {8,  244, 2, 7 },
5565         {9,  245, 2, 2 },
5566         {10, 245, 2, 7 },
5567         {11, 246, 2, 2 },
5568         {12, 246, 2, 7 },
5569         {13, 247, 2, 2 },
5570         {14, 248, 2, 4 },
5571
5572         /* 802.11 UNI / HyperLan 2 */
5573         {36, 0x56, 0, 4},
5574         {38, 0x56, 0, 6},
5575         {40, 0x56, 0, 8},
5576         {44, 0x57, 0, 0},
5577         {46, 0x57, 0, 2},
5578         {48, 0x57, 0, 4},
5579         {52, 0x57, 0, 8},
5580         {54, 0x57, 0, 10},
5581         {56, 0x58, 0, 0},
5582         {60, 0x58, 0, 4},
5583         {62, 0x58, 0, 6},
5584         {64, 0x58, 0, 8},
5585
5586         /* 802.11 HyperLan 2 */
5587         {100, 0x5b, 0, 8},
5588         {102, 0x5b, 0, 10},
5589         {104, 0x5c, 0, 0},
5590         {108, 0x5c, 0, 4},
5591         {110, 0x5c, 0, 6},
5592         {112, 0x5c, 0, 8},
5593         {116, 0x5d, 0, 0},
5594         {118, 0x5d, 0, 2},
5595         {120, 0x5d, 0, 4},
5596         {124, 0x5d, 0, 8},
5597         {126, 0x5d, 0, 10},
5598         {128, 0x5e, 0, 0},
5599         {132, 0x5e, 0, 4},
5600         {134, 0x5e, 0, 6},
5601         {136, 0x5e, 0, 8},
5602         {140, 0x5f, 0, 0},
5603
5604         /* 802.11 UNII */
5605         {149, 0x5f, 0, 9},
5606         {151, 0x5f, 0, 11},
5607         {153, 0x60, 0, 1},
5608         {157, 0x60, 0, 5},
5609         {159, 0x60, 0, 7},
5610         {161, 0x60, 0, 9},
5611         {165, 0x61, 0, 1},
5612         {167, 0x61, 0, 3},
5613         {169, 0x61, 0, 5},
5614         {171, 0x61, 0, 7},
5615         {173, 0x61, 0, 9},
5616 };
5617
5618 static const struct rf_channel rf_vals_5592_xtal20[] = {
5619         /* Channel, N, K, mod, R */
5620         {1, 482, 4, 10, 3},
5621         {2, 483, 4, 10, 3},
5622         {3, 484, 4, 10, 3},
5623         {4, 485, 4, 10, 3},
5624         {5, 486, 4, 10, 3},
5625         {6, 487, 4, 10, 3},
5626         {7, 488, 4, 10, 3},
5627         {8, 489, 4, 10, 3},
5628         {9, 490, 4, 10, 3},
5629         {10, 491, 4, 10, 3},
5630         {11, 492, 4, 10, 3},
5631         {12, 493, 4, 10, 3},
5632         {13, 494, 4, 10, 3},
5633         {14, 496, 8, 10, 3},
5634         {36, 172, 8, 12, 1},
5635         {38, 173, 0, 12, 1},
5636         {40, 173, 4, 12, 1},
5637         {42, 173, 8, 12, 1},
5638         {44, 174, 0, 12, 1},
5639         {46, 174, 4, 12, 1},
5640         {48, 174, 8, 12, 1},
5641         {50, 175, 0, 12, 1},
5642         {52, 175, 4, 12, 1},
5643         {54, 175, 8, 12, 1},
5644         {56, 176, 0, 12, 1},
5645         {58, 176, 4, 12, 1},
5646         {60, 176, 8, 12, 1},
5647         {62, 177, 0, 12, 1},
5648         {64, 177, 4, 12, 1},
5649         {100, 183, 4, 12, 1},
5650         {102, 183, 8, 12, 1},
5651         {104, 184, 0, 12, 1},
5652         {106, 184, 4, 12, 1},
5653         {108, 184, 8, 12, 1},
5654         {110, 185, 0, 12, 1},
5655         {112, 185, 4, 12, 1},
5656         {114, 185, 8, 12, 1},
5657         {116, 186, 0, 12, 1},
5658         {118, 186, 4, 12, 1},
5659         {120, 186, 8, 12, 1},
5660         {122, 187, 0, 12, 1},
5661         {124, 187, 4, 12, 1},
5662         {126, 187, 8, 12, 1},
5663         {128, 188, 0, 12, 1},
5664         {130, 188, 4, 12, 1},
5665         {132, 188, 8, 12, 1},
5666         {134, 189, 0, 12, 1},
5667         {136, 189, 4, 12, 1},
5668         {138, 189, 8, 12, 1},
5669         {140, 190, 0, 12, 1},
5670         {149, 191, 6, 12, 1},
5671         {151, 191, 10, 12, 1},
5672         {153, 192, 2, 12, 1},
5673         {155, 192, 6, 12, 1},
5674         {157, 192, 10, 12, 1},
5675         {159, 193, 2, 12, 1},
5676         {161, 193, 6, 12, 1},
5677         {165, 194, 2, 12, 1},
5678         {184, 164, 0, 12, 1},
5679         {188, 164, 4, 12, 1},
5680         {192, 165, 8, 12, 1},
5681         {196, 166, 0, 12, 1},
5682 };
5683
5684 static const struct rf_channel rf_vals_5592_xtal40[] = {
5685         /* Channel, N, K, mod, R */
5686         {1, 241, 2, 10, 3},
5687         {2, 241, 7, 10, 3},
5688         {3, 242, 2, 10, 3},
5689         {4, 242, 7, 10, 3},
5690         {5, 243, 2, 10, 3},
5691         {6, 243, 7, 10, 3},
5692         {7, 244, 2, 10, 3},
5693         {8, 244, 7, 10, 3},
5694         {9, 245, 2, 10, 3},
5695         {10, 245, 7, 10, 3},
5696         {11, 246, 2, 10, 3},
5697         {12, 246, 7, 10, 3},
5698         {13, 247, 2, 10, 3},
5699         {14, 248, 4, 10, 3},
5700         {36, 86, 4, 12, 1},
5701         {38, 86, 6, 12, 1},
5702         {40, 86, 8, 12, 1},
5703         {42, 86, 10, 12, 1},
5704         {44, 87, 0, 12, 1},
5705         {46, 87, 2, 12, 1},
5706         {48, 87, 4, 12, 1},
5707         {50, 87, 6, 12, 1},
5708         {52, 87, 8, 12, 1},
5709         {54, 87, 10, 12, 1},
5710         {56, 88, 0, 12, 1},
5711         {58, 88, 2, 12, 1},
5712         {60, 88, 4, 12, 1},
5713         {62, 88, 6, 12, 1},
5714         {64, 88, 8, 12, 1},
5715         {100, 91, 8, 12, 1},
5716         {102, 91, 10, 12, 1},
5717         {104, 92, 0, 12, 1},
5718         {106, 92, 2, 12, 1},
5719         {108, 92, 4, 12, 1},
5720         {110, 92, 6, 12, 1},
5721         {112, 92, 8, 12, 1},
5722         {114, 92, 10, 12, 1},
5723         {116, 93, 0, 12, 1},
5724         {118, 93, 2, 12, 1},
5725         {120, 93, 4, 12, 1},
5726         {122, 93, 6, 12, 1},
5727         {124, 93, 8, 12, 1},
5728         {126, 93, 10, 12, 1},
5729         {128, 94, 0, 12, 1},
5730         {130, 94, 2, 12, 1},
5731         {132, 94, 4, 12, 1},
5732         {134, 94, 6, 12, 1},
5733         {136, 94, 8, 12, 1},
5734         {138, 94, 10, 12, 1},
5735         {140, 95, 0, 12, 1},
5736         {149, 95, 9, 12, 1},
5737         {151, 95, 11, 12, 1},
5738         {153, 96, 1, 12, 1},
5739         {155, 96, 3, 12, 1},
5740         {157, 96, 5, 12, 1},
5741         {159, 96, 7, 12, 1},
5742         {161, 96, 9, 12, 1},
5743         {165, 97, 1, 12, 1},
5744         {184, 82, 0, 12, 1},
5745         {188, 82, 4, 12, 1},
5746         {192, 82, 8, 12, 1},
5747         {196, 83, 0, 12, 1},
5748 };
5749
5750 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5751 {
5752         struct hw_mode_spec *spec = &rt2x00dev->spec;
5753         struct channel_info *info;
5754         char *default_power1;
5755         char *default_power2;
5756         unsigned int i;
5757         u16 eeprom;
5758         u32 reg;
5759
5760         /*
5761          * Disable powersaving as default on PCI devices.
5762          */
5763         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5764                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5765
5766         /*
5767          * Initialize all hw fields.
5768          */
5769         rt2x00dev->hw->flags =
5770             IEEE80211_HW_SIGNAL_DBM |
5771             IEEE80211_HW_SUPPORTS_PS |
5772             IEEE80211_HW_PS_NULLFUNC_STACK |
5773             IEEE80211_HW_AMPDU_AGGREGATION |
5774             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5775
5776         /*
5777          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5778          * unless we are capable of sending the buffered frames out after the
5779          * DTIM transmission using rt2x00lib_beacondone. This will send out
5780          * multicast and broadcast traffic immediately instead of buffering it
5781          * infinitly and thus dropping it after some time.
5782          */
5783         if (!rt2x00_is_usb(rt2x00dev))
5784                 rt2x00dev->hw->flags |=
5785                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5786
5787         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5788         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5789                                 rt2x00_eeprom_addr(rt2x00dev,
5790                                                    EEPROM_MAC_ADDR_0));
5791
5792         /*
5793          * As rt2800 has a global fallback table we cannot specify
5794          * more then one tx rate per frame but since the hw will
5795          * try several rates (based on the fallback table) we should
5796          * initialize max_report_rates to the maximum number of rates
5797          * we are going to try. Otherwise mac80211 will truncate our
5798          * reported tx rates and the rc algortihm will end up with
5799          * incorrect data.
5800          */
5801         rt2x00dev->hw->max_rates = 1;
5802         rt2x00dev->hw->max_report_rates = 7;
5803         rt2x00dev->hw->max_rate_tries = 1;
5804
5805         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5806
5807         /*
5808          * Initialize hw_mode information.
5809          */
5810         spec->supported_bands = SUPPORT_BAND_2GHZ;
5811         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5812
5813         if (rt2x00_rf(rt2x00dev, RF2820) ||
5814             rt2x00_rf(rt2x00dev, RF2720)) {
5815                 spec->num_channels = 14;
5816                 spec->channels = rf_vals;
5817         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5818                    rt2x00_rf(rt2x00dev, RF2750)) {
5819                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5820                 spec->num_channels = ARRAY_SIZE(rf_vals);
5821                 spec->channels = rf_vals;
5822         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5823                    rt2x00_rf(rt2x00dev, RF2020) ||
5824                    rt2x00_rf(rt2x00dev, RF3021) ||
5825                    rt2x00_rf(rt2x00dev, RF3022) ||
5826                    rt2x00_rf(rt2x00dev, RF3290) ||
5827                    rt2x00_rf(rt2x00dev, RF3320) ||
5828                    rt2x00_rf(rt2x00dev, RF3322) ||
5829                    rt2x00_rf(rt2x00dev, RF5360) ||
5830                    rt2x00_rf(rt2x00dev, RF5370) ||
5831                    rt2x00_rf(rt2x00dev, RF5372) ||
5832                    rt2x00_rf(rt2x00dev, RF5390) ||
5833                    rt2x00_rf(rt2x00dev, RF5392)) {
5834                 spec->num_channels = 14;
5835                 spec->channels = rf_vals_3x;
5836         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5837                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5838                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5839                 spec->channels = rf_vals_3x;
5840         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5841                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5842
5843                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5844                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5845                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5846                         spec->channels = rf_vals_5592_xtal40;
5847                 } else {
5848                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5849                         spec->channels = rf_vals_5592_xtal20;
5850                 }
5851         }
5852
5853         if (WARN_ON_ONCE(!spec->channels))
5854                 return -ENODEV;
5855
5856         /*
5857          * Initialize HT information.
5858          */
5859         if (!rt2x00_rf(rt2x00dev, RF2020))
5860                 spec->ht.ht_supported = true;
5861         else
5862                 spec->ht.ht_supported = false;
5863
5864         spec->ht.cap =
5865             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5866             IEEE80211_HT_CAP_GRN_FLD |
5867             IEEE80211_HT_CAP_SGI_20 |
5868             IEEE80211_HT_CAP_SGI_40;
5869
5870         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5871                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5872
5873         spec->ht.cap |=
5874             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5875                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5876
5877         spec->ht.ampdu_factor = 3;
5878         spec->ht.ampdu_density = 4;
5879         spec->ht.mcs.tx_params =
5880             IEEE80211_HT_MCS_TX_DEFINED |
5881             IEEE80211_HT_MCS_TX_RX_DIFF |
5882             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5883                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5884
5885         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5886         case 3:
5887                 spec->ht.mcs.rx_mask[2] = 0xff;
5888         case 2:
5889                 spec->ht.mcs.rx_mask[1] = 0xff;
5890         case 1:
5891                 spec->ht.mcs.rx_mask[0] = 0xff;
5892                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5893                 break;
5894         }
5895
5896         /*
5897          * Create channel information array
5898          */
5899         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5900         if (!info)
5901                 return -ENOMEM;
5902
5903         spec->channels_info = info;
5904
5905         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5906         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5907
5908         for (i = 0; i < 14; i++) {
5909                 info[i].default_power1 = default_power1[i];
5910                 info[i].default_power2 = default_power2[i];
5911         }
5912
5913         if (spec->num_channels > 14) {
5914                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5915                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5916
5917                 for (i = 14; i < spec->num_channels; i++) {
5918                         info[i].default_power1 = default_power1[i];
5919                         info[i].default_power2 = default_power2[i];
5920                 }
5921         }
5922
5923         switch (rt2x00dev->chip.rf) {
5924         case RF2020:
5925         case RF3020:
5926         case RF3021:
5927         case RF3022:
5928         case RF3320:
5929         case RF3052:
5930         case RF3290:
5931         case RF5360:
5932         case RF5370:
5933         case RF5372:
5934         case RF5390:
5935         case RF5392:
5936                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5937                 break;
5938         }
5939
5940         return 0;
5941 }
5942
5943 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5944 {
5945         int retval;
5946         u32 reg;
5947
5948         /*
5949          * Allocate eeprom data.
5950          */
5951         retval = rt2800_validate_eeprom(rt2x00dev);
5952         if (retval)
5953                 return retval;
5954
5955         retval = rt2800_init_eeprom(rt2x00dev);
5956         if (retval)
5957                 return retval;
5958
5959         /*
5960          * Enable rfkill polling by setting GPIO direction of the
5961          * rfkill switch GPIO pin correctly.
5962          */
5963         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5964         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5965         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5966
5967         /*
5968          * Initialize hw specifications.
5969          */
5970         retval = rt2800_probe_hw_mode(rt2x00dev);
5971         if (retval)
5972                 return retval;
5973
5974         /*
5975          * Set device capabilities.
5976          */
5977         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5978         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5979         if (!rt2x00_is_usb(rt2x00dev))
5980                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5981
5982         /*
5983          * Set device requirements.
5984          */
5985         if (!rt2x00_is_soc(rt2x00dev))
5986                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5987         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5988         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5989         if (!rt2800_hwcrypt_disabled(rt2x00dev))
5990                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5991         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5992         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5993         if (rt2x00_is_usb(rt2x00dev))
5994                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5995         else {
5996                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5997                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5998         }
5999
6000         /*
6001          * Set the rssi offset.
6002          */
6003         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6004
6005         return 0;
6006 }
6007 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
6008
6009 /*
6010  * IEEE80211 stack callback functions.
6011  */
6012 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6013                          u16 *iv16)
6014 {
6015         struct rt2x00_dev *rt2x00dev = hw->priv;
6016         struct mac_iveiv_entry iveiv_entry;
6017         u32 offset;
6018
6019         offset = MAC_IVEIV_ENTRY(hw_key_idx);
6020         rt2800_register_multiread(rt2x00dev, offset,
6021                                       &iveiv_entry, sizeof(iveiv_entry));
6022
6023         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6024         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
6025 }
6026 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
6027
6028 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
6029 {
6030         struct rt2x00_dev *rt2x00dev = hw->priv;
6031         u32 reg;
6032         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6033
6034         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6035         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6036         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6037
6038         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6039         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6040         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6041
6042         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6043         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6044         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6045
6046         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6047         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6048         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6049
6050         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6051         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6052         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6053
6054         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6055         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6056         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6057
6058         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6059         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6060         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6061
6062         return 0;
6063 }
6064 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
6065
6066 int rt2800_conf_tx(struct ieee80211_hw *hw,
6067                    struct ieee80211_vif *vif, u16 queue_idx,
6068                    const struct ieee80211_tx_queue_params *params)
6069 {
6070         struct rt2x00_dev *rt2x00dev = hw->priv;
6071         struct data_queue *queue;
6072         struct rt2x00_field32 field;
6073         int retval;
6074         u32 reg;
6075         u32 offset;
6076
6077         /*
6078          * First pass the configuration through rt2x00lib, that will
6079          * update the queue settings and validate the input. After that
6080          * we are free to update the registers based on the value
6081          * in the queue parameter.
6082          */
6083         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
6084         if (retval)
6085                 return retval;
6086
6087         /*
6088          * We only need to perform additional register initialization
6089          * for WMM queues/
6090          */
6091         if (queue_idx >= 4)
6092                 return 0;
6093
6094         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
6095
6096         /* Update WMM TXOP register */
6097         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6098         field.bit_offset = (queue_idx & 1) * 16;
6099         field.bit_mask = 0xffff << field.bit_offset;
6100
6101         rt2800_register_read(rt2x00dev, offset, &reg);
6102         rt2x00_set_field32(&reg, field, queue->txop);
6103         rt2800_register_write(rt2x00dev, offset, reg);
6104
6105         /* Update WMM registers */
6106         field.bit_offset = queue_idx * 4;
6107         field.bit_mask = 0xf << field.bit_offset;
6108
6109         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6110         rt2x00_set_field32(&reg, field, queue->aifs);
6111         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6112
6113         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6114         rt2x00_set_field32(&reg, field, queue->cw_min);
6115         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6116
6117         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6118         rt2x00_set_field32(&reg, field, queue->cw_max);
6119         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6120
6121         /* Update EDCA registers */
6122         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6123
6124         rt2800_register_read(rt2x00dev, offset, &reg);
6125         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6126         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6127         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6128         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6129         rt2800_register_write(rt2x00dev, offset, reg);
6130
6131         return 0;
6132 }
6133 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6134
6135 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6136 {
6137         struct rt2x00_dev *rt2x00dev = hw->priv;
6138         u64 tsf;
6139         u32 reg;
6140
6141         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6142         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6143         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6144         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6145
6146         return tsf;
6147 }
6148 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6149
6150 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6151                         enum ieee80211_ampdu_mlme_action action,
6152                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6153                         u8 buf_size)
6154 {
6155         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6156         int ret = 0;
6157
6158         /*
6159          * Don't allow aggregation for stations the hardware isn't aware
6160          * of because tx status reports for frames to an unknown station
6161          * always contain wcid=255 and thus we can't distinguish between
6162          * multiple stations which leads to unwanted situations when the
6163          * hw reorders frames due to aggregation.
6164          */
6165         if (sta_priv->wcid < 0)
6166                 return 1;
6167
6168         switch (action) {
6169         case IEEE80211_AMPDU_RX_START:
6170         case IEEE80211_AMPDU_RX_STOP:
6171                 /*
6172                  * The hw itself takes care of setting up BlockAck mechanisms.
6173                  * So, we only have to allow mac80211 to nagotiate a BlockAck
6174                  * agreement. Once that is done, the hw will BlockAck incoming
6175                  * AMPDUs without further setup.
6176                  */
6177                 break;
6178         case IEEE80211_AMPDU_TX_START:
6179                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6180                 break;
6181         case IEEE80211_AMPDU_TX_STOP_CONT:
6182         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6183         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6184                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6185                 break;
6186         case IEEE80211_AMPDU_TX_OPERATIONAL:
6187                 break;
6188         default:
6189                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
6190         }
6191
6192         return ret;
6193 }
6194 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6195
6196 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6197                       struct survey_info *survey)
6198 {
6199         struct rt2x00_dev *rt2x00dev = hw->priv;
6200         struct ieee80211_conf *conf = &hw->conf;
6201         u32 idle, busy, busy_ext;
6202
6203         if (idx != 0)
6204                 return -ENOENT;
6205
6206         survey->channel = conf->channel;
6207
6208         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6209         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6210         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6211
6212         if (idle || busy) {
6213                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6214                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
6215                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6216
6217                 survey->channel_time = (idle + busy) / 1000;
6218                 survey->channel_time_busy = busy / 1000;
6219                 survey->channel_time_ext_busy = busy_ext / 1000;
6220         }
6221
6222         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6223                 survey->filled |= SURVEY_INFO_IN_USE;
6224
6225         return 0;
6226
6227 }
6228 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6229
6230 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6231 MODULE_VERSION(DRV_VERSION);
6232 MODULE_DESCRIPTION("Ralink RT2800 library");
6233 MODULE_LICENSE("GPL");