drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 225         [EEPROM_CHIP_ID]                = 0x0000,
 226         [EEPROM_VERSION]                = 0x0001,
 227         [EEPROM_MAC_ADDR_0]             = 0x0002,
 228         [EEPROM_MAC_ADDR_1]             = 0x0003,
 229         [EEPROM_MAC_ADDR_2]             = 0x0004,
 230         [EEPROM_NIC_CONF0]              = 0x001a,
 231         [EEPROM_NIC_CONF1]              = 0x001b,
 232         [EEPROM_FREQ]                   = 0x001d,
 233         [EEPROM_LED_AG_CONF]            = 0x001e,
 234         [EEPROM_LED_ACT_CONF]           = 0x001f,
 235         [EEPROM_LED_POLARITY]           = 0x0020,
 236         [EEPROM_NIC_CONF2]              = 0x0021,
 237         [EEPROM_LNA]                    = 0x0022,
 238         [EEPROM_RSSI_BG]                = 0x0023,
 239         [EEPROM_RSSI_BG2]               = 0x0024,
 240         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 241         [EEPROM_RSSI_A]                 = 0x0025,
 242         [EEPROM_RSSI_A2]                = 0x0026,
 243         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 244         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 245         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 246         [EEPROM_TXPOWER_BG1]            = 0x0029,
 247         [EEPROM_TXPOWER_BG2]            = 0x0030,
 248         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 249         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 250         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 251         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 252         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 253         [EEPROM_TXPOWER_A1]             = 0x003c,
 254         [EEPROM_TXPOWER_A2]             = 0x0053,
 255         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 256         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 257         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 258         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 259         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 260         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 261         [EEPROM_BBP_START]              = 0x0078,
 262 };
 263
 264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 265         [EEPROM_CHIP_ID]                = 0x0000,
 266         [EEPROM_VERSION]                = 0x0001,
 267         [EEPROM_MAC_ADDR_0]             = 0x0002,
 268         [EEPROM_MAC_ADDR_1]             = 0x0003,
 269         [EEPROM_MAC_ADDR_2]             = 0x0004,
 270         [EEPROM_NIC_CONF0]              = 0x001a,
 271         [EEPROM_NIC_CONF1]              = 0x001b,
 272         [EEPROM_NIC_CONF2]              = 0x001c,
 273         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 274         [EEPROM_FREQ]                   = 0x0022,
 275         [EEPROM_LED_AG_CONF]            = 0x0023,
 276         [EEPROM_LED_ACT_CONF]           = 0x0024,
 277         [EEPROM_LED_POLARITY]           = 0x0025,
 278         [EEPROM_LNA]                    = 0x0026,
 279         [EEPROM_EXT_LNA2]               = 0x0027,
 280         [EEPROM_RSSI_BG]                = 0x0028,
 281         [EEPROM_TXPOWER_DELTA]          = 0x0028, /* Overlaps with RSSI_BG */
 282         [EEPROM_RSSI_BG2]               = 0x0029,
 283         [EEPROM_TXMIXER_GAIN_BG]        = 0x0029, /* Overlaps with RSSI_BG2 */
 284         [EEPROM_RSSI_A]                 = 0x002a,
 285         [EEPROM_RSSI_A2]                = 0x002b,
 286         [EEPROM_TXMIXER_GAIN_A]         = 0x002b, /* Overlaps with RSSI_A2 */
 287         [EEPROM_TXPOWER_BG1]            = 0x0030,
 288         [EEPROM_TXPOWER_BG2]            = 0x0037,
 289         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 290         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 291         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 292         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 293         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 294         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 295         [EEPROM_TXPOWER_A1]             = 0x004b,
 296         [EEPROM_TXPOWER_A2]             = 0x0065,
 297         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 298         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 299         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 300         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 301         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 302         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 303         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 304 };
 305
 306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 307                                              const enum rt2800_eeprom_word word)
 308 {
 309         const unsigned int *map;
 310         unsigned int index;
 311
 312         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 313                       "%s: invalid EEPROM word %d\n",
 314                       wiphy_name(rt2x00dev->hw->wiphy), word))
 315                 return 0;
 316
 317         if (rt2x00_rt(rt2x00dev, RT3593))
 318                 map = rt2800_eeprom_map_ext;
 319         else
 320                 map = rt2800_eeprom_map;
 321
 322         index = map[word];
 323
 324         /* Index 0 is valid only for EEPROM_CHIP_ID.
 325          * Otherwise it means that the offset of the
 326          * given word is not initialized in the map,
 327          * or that the field is not usable on the
 328          * actual chipset.
 329          */
 330         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 331                   "%s: invalid access of EEPROM word %d\n",
 332                   wiphy_name(rt2x00dev->hw->wiphy), word);
 333
 334         return index;
 335 }
 336
 337 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 338                                 const enum rt2800_eeprom_word word)
 339 {
 340         unsigned int index;
 341
 342         index = rt2800_eeprom_word_index(rt2x00dev, word);
 343         return rt2x00_eeprom_addr(rt2x00dev, index);
 344 }
 345
 346 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 347                                const enum rt2800_eeprom_word word, u16 *data)
 348 {
 349         unsigned int index;
 350
 351         index = rt2800_eeprom_word_index(rt2x00dev, word);
 352         rt2x00_eeprom_read(rt2x00dev, index, data);
 353 }
 354
 355 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 356                                 const enum rt2800_eeprom_word word, u16 data)
 357 {
 358         unsigned int index;
 359
 360         index = rt2800_eeprom_word_index(rt2x00dev, word);
 361         rt2x00_eeprom_write(rt2x00dev, index, data);
 362 }
 363
 364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 365                                           const enum rt2800_eeprom_word array,
 366                                           unsigned int offset,
 367                                           u16 *data)
 368 {
 369         unsigned int index;
 370
 371         index = rt2800_eeprom_word_index(rt2x00dev, array);
 372         rt2x00_eeprom_read(rt2x00dev, index + offset, data);
 373 }
 374
 375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 376 {
 377         u32 reg;
 378         int i, count;
 379
 380         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 381         if (rt2x00_get_field32(reg, WLAN_EN))
 382                 return 0;
 383
 384         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 385         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 386         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 387         rt2x00_set_field32(&reg, WLAN_EN, 1);
 388         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 389
 390         udelay(REGISTER_BUSY_DELAY);
 391
 392         count = 0;
 393         do {
 394                 /*
 395                  * Check PLL_LD & XTAL_RDY.
 396                  */
 397                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 398                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 399                         if (rt2x00_get_field32(reg, PLL_LD) &&
 400                             rt2x00_get_field32(reg, XTAL_RDY))
 401                                 break;
 402                         udelay(REGISTER_BUSY_DELAY);
 403                 }
 404
 405                 if (i >= REGISTER_BUSY_COUNT) {
 406
 407                         if (count >= 10)
 408                                 return -EIO;
 409
 410                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 411                         udelay(REGISTER_BUSY_DELAY);
 412                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 413                         udelay(REGISTER_BUSY_DELAY);
 414                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 415                         udelay(REGISTER_BUSY_DELAY);
 416                         count++;
 417                 } else {
 418                         count = 0;
 419                 }
 420
 421                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 422                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 423                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 424                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 425                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 426                 udelay(10);
 427                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 428                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 429                 udelay(10);
 430                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 431         } while (count != 0);
 432
 433         return 0;
 434 }
 435
 436 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 437                         const u8 command, const u8 token,
 438                         const u8 arg0, const u8 arg1)
 439 {
 440         u32 reg;
 441
 442         /*
 443          * SOC devices don't support MCU requests.
 444          */
 445         if (rt2x00_is_soc(rt2x00dev))
 446                 return;
 447
 448         mutex_lock(&rt2x00dev->csr_mutex);
 449
 450         /*
 451          * Wait until the MCU becomes available, afterwards we
 452          * can safely write the new data into the register.
 453          */
 454         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 455                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 456                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 457                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 458                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 459                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 460
 461                 reg = 0;
 462                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 463                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 464         }
 465
 466         mutex_unlock(&rt2x00dev->csr_mutex);
 467 }
 468 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 469
 470 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 471 {
 472         unsigned int i = 0;
 473         u32 reg;
 474
 475         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 476                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 477                 if (reg && reg != ~0)
 478                         return 0;
 479                 msleep(1);
 480         }
 481
 482         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 483         return -EBUSY;
 484 }
 485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 486
 487 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 488 {
 489         unsigned int i;
 490         u32 reg;
 491
 492         /*
 493          * Some devices are really slow to respond here. Wait a whole second
 494          * before timing out.
 495          */
 496         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 497                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 498                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 499                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 500                         return 0;
 501
 502                 msleep(10);
 503         }
 504
 505         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 506         return -EACCES;
 507 }
 508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 509
 510 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 511 {
 512         u32 reg;
 513
 514         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 515         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 516         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 517         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 518         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 519         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 520         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 521 }
 522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 523
 524 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 525                                unsigned short *txwi_size,
 526                                unsigned short *rxwi_size)
 527 {
 528         switch (rt2x00dev->chip.rt) {
 529         case RT3593:
 530                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 531                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 532                 break;
 533
 534         case RT5592:
 535                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 536                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 537                 break;
 538
 539         default:
 540                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 541                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 542                 break;
 543         }
 544 }
 545 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 546
 547 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 548 {
 549         u16 fw_crc;
 550         u16 crc;
 551
 552         /*
 553          * The last 2 bytes in the firmware array are the crc checksum itself,
 554          * this means that we should never pass those 2 bytes to the crc
 555          * algorithm.
 556          */
 557         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 558
 559         /*
 560          * Use the crc ccitt algorithm.
 561          * This will return the same value as the legacy driver which
 562          * used bit ordering reversion on the both the firmware bytes
 563          * before input input as well as on the final output.
 564          * Obviously using crc ccitt directly is much more efficient.
 565          */
 566         crc = crc_ccitt(~0, data, len - 2);
 567
 568         /*
 569          * There is a small difference between the crc-itu-t + bitrev and
 570          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 571          * will be swapped, use swab16 to convert the crc to the correct
 572          * value.
 573          */
 574         crc = swab16(crc);
 575
 576         return fw_crc == crc;
 577 }
 578
 579 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 580                           const u8 *data, const size_t len)
 581 {
 582         size_t offset = 0;
 583         size_t fw_len;
 584         bool multiple;
 585
 586         /*
 587          * PCI(e) & SOC devices require firmware with a length
 588          * of 8kb. USB devices require firmware files with a length
 589          * of 4kb. Certain USB chipsets however require different firmware,
 590          * which Ralink only provides attached to the original firmware
 591          * file. Thus for USB devices, firmware files have a length
 592          * which is a multiple of 4kb. The firmware for rt3290 chip also
 593          * have a length which is a multiple of 4kb.
 594          */
 595         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 596                 fw_len = 4096;
 597         else
 598                 fw_len = 8192;
 599
 600         multiple = true;
 601         /*
 602          * Validate the firmware length
 603          */
 604         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 605                 return FW_BAD_LENGTH;
 606
 607         /*
 608          * Check if the chipset requires one of the upper parts
 609          * of the firmware.
 610          */
 611         if (rt2x00_is_usb(rt2x00dev) &&
 612             !rt2x00_rt(rt2x00dev, RT2860) &&
 613             !rt2x00_rt(rt2x00dev, RT2872) &&
 614             !rt2x00_rt(rt2x00dev, RT3070) &&
 615             ((len / fw_len) == 1))
 616                 return FW_BAD_VERSION;
 617
 618         /*
 619          * 8kb firmware files must be checked as if it were
 620          * 2 separate firmware files.
 621          */
 622         while (offset < len) {
 623                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 624                         return FW_BAD_CRC;
 625
 626                 offset += fw_len;
 627         }
 628
 629         return FW_OK;
 630 }
 631 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 632
 633 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 634                          const u8 *data, const size_t len)
 635 {
 636         unsigned int i;
 637         u32 reg;
 638         int retval;
 639
 640         if (rt2x00_rt(rt2x00dev, RT3290)) {
 641                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 642                 if (retval)
 643                         return -EBUSY;
 644         }
 645
 646         /*
 647          * If driver doesn't wake up firmware here,
 648          * rt2800_load_firmware will hang forever when interface is up again.
 649          */
 650         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 651
 652         /*
 653          * Wait for stable hardware.
 654          */
 655         if (rt2800_wait_csr_ready(rt2x00dev))
 656                 return -EBUSY;
 657
 658         if (rt2x00_is_pci(rt2x00dev)) {
 659                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 660                     rt2x00_rt(rt2x00dev, RT3572) ||
 661                     rt2x00_rt(rt2x00dev, RT5390) ||
 662                     rt2x00_rt(rt2x00dev, RT5392)) {
 663                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 664                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 665                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 666                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 667                 }
 668                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 669         }
 670
 671         rt2800_disable_wpdma(rt2x00dev);
 672
 673         /*
 674          * Write firmware to the device.
 675          */
 676         rt2800_drv_write_firmware(rt2x00dev, data, len);
 677
 678         /*
 679          * Wait for device to stabilize.
 680          */
 681         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 682                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 683                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 684                         break;
 685                 msleep(1);
 686         }
 687
 688         if (i == REGISTER_BUSY_COUNT) {
 689                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 690                 return -EBUSY;
 691         }
 692
 693         /*
 694          * Disable DMA, will be reenabled later when enabling
 695          * the radio.
 696          */
 697         rt2800_disable_wpdma(rt2x00dev);
 698
 699         /*
 700          * Initialize firmware.
 701          */
 702         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 703         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 704         if (rt2x00_is_usb(rt2x00dev)) {
 705                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 706                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 707         }
 708         msleep(1);
 709
 710         return 0;
 711 }
 712 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 713
 714 void rt2800_write_tx_data(struct queue_entry *entry,
 715                           struct txentry_desc *txdesc)
 716 {
 717         __le32 *txwi = rt2800_drv_get_txwi(entry);
 718         u32 word;
 719         int i;
 720
 721         /*
 722          * Initialize TX Info descriptor
 723          */
 724         rt2x00_desc_read(txwi, 0, &word);
 725         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 726                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 727         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 728                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 729         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 730         rt2x00_set_field32(&word, TXWI_W0_TS,
 731                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 732         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 733                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 734         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 735                            txdesc->u.ht.mpdu_density);
 736         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 737         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 738         rt2x00_set_field32(&word, TXWI_W0_BW,
 739                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 740         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 741                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 742         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 743         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 744         rt2x00_desc_write(txwi, 0, word);
 745
 746         rt2x00_desc_read(txwi, 1, &word);
 747         rt2x00_set_field32(&word, TXWI_W1_ACK,
 748                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 749         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 750                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 751         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 752         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 753                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 754                            txdesc->key_idx : txdesc->u.ht.wcid);
 755         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 756                            txdesc->length);
 757         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 758         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 759         rt2x00_desc_write(txwi, 1, word);
 760
 761         /*
 762          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 763          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 764          * When TXD_W3_WIV is set to 1 it will use the IV data
 765          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 766          * crypto entry in the registers should be used to encrypt the frame.
 767          *
 768          * Nulify all remaining words as well, we don't know how to program them.
 769          */
 770         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 771                 _rt2x00_desc_write(txwi, i, 0);
 772 }
 773 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 774
 775 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 776 {
 777         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 778         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 779         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 780         u16 eeprom;
 781         u8 offset0;
 782         u8 offset1;
 783         u8 offset2;
 784
 785         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 786                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 787                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 788                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 789                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 790                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 791         } else {
 792                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 793                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 794                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 795                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 796                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 797         }
 798
 799         /*
 800          * Convert the value from the descriptor into the RSSI value
 801          * If the value in the descriptor is 0, it is considered invalid
 802          * and the default (extremely low) rssi value is assumed
 803          */
 804         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 805         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 806         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 807
 808         /*
 809          * mac80211 only accepts a single RSSI value. Calculating the
 810          * average doesn't deliver a fair answer either since -60:-60 would
 811          * be considered equally good as -50:-70 while the second is the one
 812          * which gives less energy...
 813          */
 814         rssi0 = max(rssi0, rssi1);
 815         return (int)max(rssi0, rssi2);
 816 }
 817
 818 void rt2800_process_rxwi(struct queue_entry *entry,
 819                          struct rxdone_entry_desc *rxdesc)
 820 {
 821         __le32 *rxwi = (__le32 *) entry->skb->data;
 822         u32 word;
 823
 824         rt2x00_desc_read(rxwi, 0, &word);
 825
 826         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 827         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 828
 829         rt2x00_desc_read(rxwi, 1, &word);
 830
 831         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 832                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 833
 834         if (rt2x00_get_field32(word, RXWI_W1_BW))
 835                 rxdesc->flags |= RX_FLAG_40MHZ;
 836
 837         /*
 838          * Detect RX rate, always use MCS as signal type.
 839          */
 840         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 841         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 842         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 843
 844         /*
 845          * Mask of 0x8 bit to remove the short preamble flag.
 846          */
 847         if (rxdesc->rate_mode == RATE_MODE_CCK)
 848                 rxdesc->signal &= ~0x8;
 849
 850         rt2x00_desc_read(rxwi, 2, &word);
 851
 852         /*
 853          * Convert descriptor AGC value to RSSI value.
 854          */
 855         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 856         /*
 857          * Remove RXWI descriptor from start of the buffer.
 858          */
 859         skb_pull(entry->skb, entry->queue->winfo_size);
 860 }
 861 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 862
 863 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 864 {
 865         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 866         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 867         struct txdone_entry_desc txdesc;
 868         u32 word;
 869         u16 mcs, real_mcs;
 870         int aggr, ampdu;
 871
 872         /*
 873          * Obtain the status about this packet.
 874          */
 875         txdesc.flags = 0;
 876         rt2x00_desc_read(txwi, 0, &word);
 877
 878         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 879         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 880
 881         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 882         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 883
 884         /*
 885          * If a frame was meant to be sent as a single non-aggregated MPDU
 886          * but ended up in an aggregate the used tx rate doesn't correlate
 887          * with the one specified in the TXWI as the whole aggregate is sent
 888          * with the same rate.
 889          *
 890          * For example: two frames are sent to rt2x00, the first one sets
 891          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 892          * and requests MCS15. If the hw aggregates both frames into one
 893          * AMDPU the tx status for both frames will contain MCS7 although
 894          * the frame was sent successfully.
 895          *
 896          * Hence, replace the requested rate with the real tx rate to not
 897          * confuse the rate control algortihm by providing clearly wrong
 898          * data.
 899          */
 900         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 901                 skbdesc->tx_rate_idx = real_mcs;
 902                 mcs = real_mcs;
 903         }
 904
 905         if (aggr == 1 || ampdu == 1)
 906                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 907
 908         /*
 909          * Ralink has a retry mechanism using a global fallback
 910          * table. We setup this fallback table to try the immediate
 911          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 912          * always contains the MCS used for the last transmission, be
 913          * it successful or not.
 914          */
 915         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 916                 /*
 917                  * Transmission succeeded. The number of retries is
 918                  * mcs - real_mcs
 919                  */
 920                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 921                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 922         } else {
 923                 /*
 924                  * Transmission failed. The number of retries is
 925                  * always 7 in this case (for a total number of 8
 926                  * frames sent).
 927                  */
 928                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 929                 txdesc.retry = rt2x00dev->long_retry;
 930         }
 931
 932         /*
 933          * the frame was retried at least once
 934          * -> hw used fallback rates
 935          */
 936         if (txdesc.retry)
 937                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 938
 939         rt2x00lib_txdone(entry, &txdesc);
 940 }
 941 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 942
 943 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
 944                                           unsigned int index)
 945 {
 946         return HW_BEACON_BASE(index);
 947 }
 948
 949 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
 950                                           unsigned int index)
 951 {
 952         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
 953 }
 954
 955 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 956 {
 957         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 958         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 959         unsigned int beacon_base;
 960         unsigned int padding_len;
 961         u32 orig_reg, reg;
 962         const int txwi_desc_size = entry->queue->winfo_size;
 963
 964         /*
 965          * Disable beaconing while we are reloading the beacon data,
 966          * otherwise we might be sending out invalid data.
 967          */
 968         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 969         orig_reg = reg;
 970         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 971         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 972
 973         /*
 974          * Add space for the TXWI in front of the skb.
 975          */
 976         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
 977
 978         /*
 979          * Register descriptor details in skb frame descriptor.
 980          */
 981         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 982         skbdesc->desc = entry->skb->data;
 983         skbdesc->desc_len = txwi_desc_size;
 984
 985         /*
 986          * Add the TXWI for the beacon to the skb.
 987          */
 988         rt2800_write_tx_data(entry, txdesc);
 989
 990         /*
 991          * Dump beacon to userspace through debugfs.
 992          */
 993         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 994
 995         /*
 996          * Write entire beacon with TXWI and padding to register.
 997          */
 998         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 999         if (padding_len && skb_pad(entry->skb, padding_len)) {
1000                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1001                 /* skb freed by skb_pad() on failure */
1002                 entry->skb = NULL;
1003                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1004                 return;
1005         }
1006
1007         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1008
1009         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1010                                    entry->skb->len + padding_len);
1011
1012         /*
1013          * Enable beaconing again.
1014          */
1015         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1016         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1017
1018         /*
1019          * Clean up beacon skb.
1020          */
1021         dev_kfree_skb_any(entry->skb);
1022         entry->skb = NULL;
1023 }
1024 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1025
1026 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1027                                                 unsigned int index)
1028 {
1029         int i;
1030         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1031         unsigned int beacon_base;
1032
1033         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1034
1035         /*
1036          * For the Beacon base registers we only need to clear
1037          * the whole TXWI which (when set to 0) will invalidate
1038          * the entire beacon.
1039          */
1040         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1041                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1042 }
1043
1044 void rt2800_clear_beacon(struct queue_entry *entry)
1045 {
1046         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1047         u32 reg;
1048
1049         /*
1050          * Disable beaconing while we are reloading the beacon data,
1051          * otherwise we might be sending out invalid data.
1052          */
1053         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1054         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1055         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1056
1057         /*
1058          * Clear beacon.
1059          */
1060         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1061
1062         /*
1063          * Enabled beaconing again.
1064          */
1065         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1066         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1067 }
1068 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1069
1070 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1071 const struct rt2x00debug rt2800_rt2x00debug = {
1072         .owner  = THIS_MODULE,
1073         .csr    = {
1074                 .read           = rt2800_register_read,
1075                 .write          = rt2800_register_write,
1076                 .flags          = RT2X00DEBUGFS_OFFSET,
1077                 .word_base      = CSR_REG_BASE,
1078                 .word_size      = sizeof(u32),
1079                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1080         },
1081         .eeprom = {
1082                 /* NOTE: The local EEPROM access functions can't
1083                  * be used here, use the generic versions instead.
1084                  */
1085                 .read           = rt2x00_eeprom_read,
1086                 .write          = rt2x00_eeprom_write,
1087                 .word_base      = EEPROM_BASE,
1088                 .word_size      = sizeof(u16),
1089                 .word_count     = EEPROM_SIZE / sizeof(u16),
1090         },
1091         .bbp    = {
1092                 .read           = rt2800_bbp_read,
1093                 .write          = rt2800_bbp_write,
1094                 .word_base      = BBP_BASE,
1095                 .word_size      = sizeof(u8),
1096                 .word_count     = BBP_SIZE / sizeof(u8),
1097         },
1098         .rf     = {
1099                 .read           = rt2x00_rf_read,
1100                 .write          = rt2800_rf_write,
1101                 .word_base      = RF_BASE,
1102                 .word_size      = sizeof(u32),
1103                 .word_count     = RF_SIZE / sizeof(u32),
1104         },
1105         .rfcsr  = {
1106                 .read           = rt2800_rfcsr_read,
1107                 .write          = rt2800_rfcsr_write,
1108                 .word_base      = RFCSR_BASE,
1109                 .word_size      = sizeof(u8),
1110                 .word_count     = RFCSR_SIZE / sizeof(u8),
1111         },
1112 };
1113 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1114 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1115
1116 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1117 {
1118         u32 reg;
1119
1120         if (rt2x00_rt(rt2x00dev, RT3290)) {
1121                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1122                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1123         } else {
1124                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1125                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1126         }
1127 }
1128 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1129
1130 #ifdef CONFIG_RT2X00_LIB_LEDS
1131 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1132                                   enum led_brightness brightness)
1133 {
1134         struct rt2x00_led *led =
1135             container_of(led_cdev, struct rt2x00_led, led_dev);
1136         unsigned int enabled = brightness != LED_OFF;
1137         unsigned int bg_mode =
1138             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1139         unsigned int polarity =
1140                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1141                                    EEPROM_FREQ_LED_POLARITY);
1142         unsigned int ledmode =
1143                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1144                                    EEPROM_FREQ_LED_MODE);
1145         u32 reg;
1146
1147         /* Check for SoC (SOC devices don't support MCU requests) */
1148         if (rt2x00_is_soc(led->rt2x00dev)) {
1149                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1150
1151                 /* Set LED Polarity */
1152                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1153
1154                 /* Set LED Mode */
1155                 if (led->type == LED_TYPE_RADIO) {
1156                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1157                                            enabled ? 3 : 0);
1158                 } else if (led->type == LED_TYPE_ASSOC) {
1159                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1160                                            enabled ? 3 : 0);
1161                 } else if (led->type == LED_TYPE_QUALITY) {
1162                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1163                                            enabled ? 3 : 0);
1164                 }
1165
1166                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1167
1168         } else {
1169                 if (led->type == LED_TYPE_RADIO) {
1170                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1171                                               enabled ? 0x20 : 0);
1172                 } else if (led->type == LED_TYPE_ASSOC) {
1173                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1174                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1175                 } else if (led->type == LED_TYPE_QUALITY) {
1176                         /*
1177                          * The brightness is divided into 6 levels (0 - 5),
1178                          * The specs tell us the following levels:
1179                          *      0, 1 ,3, 7, 15, 31
1180                          * to determine the level in a simple way we can simply
1181                          * work with bitshifting:
1182                          *      (1 << level) - 1
1183                          */
1184                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1185                                               (1 << brightness / (LED_FULL / 6)) - 1,
1186                                               polarity);
1187                 }
1188         }
1189 }
1190
1191 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1192                      struct rt2x00_led *led, enum led_type type)
1193 {
1194         led->rt2x00dev = rt2x00dev;
1195         led->type = type;
1196         led->led_dev.brightness_set = rt2800_brightness_set;
1197         led->flags = LED_INITIALIZED;
1198 }
1199 #endif /* CONFIG_RT2X00_LIB_LEDS */
1200
1201 /*
1202  * Configuration handlers.
1203  */
1204 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1205                                const u8 *address,
1206                                int wcid)
1207 {
1208         struct mac_wcid_entry wcid_entry;
1209         u32 offset;
1210
1211         offset = MAC_WCID_ENTRY(wcid);
1212
1213         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1214         if (address)
1215                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1216
1217         rt2800_register_multiwrite(rt2x00dev, offset,
1218                                       &wcid_entry, sizeof(wcid_entry));
1219 }
1220
1221 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1222 {
1223         u32 offset;
1224         offset = MAC_WCID_ATTR_ENTRY(wcid);
1225         rt2800_register_write(rt2x00dev, offset, 0);
1226 }
1227
1228 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1229                                            int wcid, u32 bssidx)
1230 {
1231         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1232         u32 reg;
1233
1234         /*
1235          * The BSS Idx numbers is split in a main value of 3 bits,
1236          * and a extended field for adding one additional bit to the value.
1237          */
1238         rt2800_register_read(rt2x00dev, offset, &reg);
1239         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1240         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1241                            (bssidx & 0x8) >> 3);
1242         rt2800_register_write(rt2x00dev, offset, reg);
1243 }
1244
1245 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1246                                            struct rt2x00lib_crypto *crypto,
1247                                            struct ieee80211_key_conf *key)
1248 {
1249         struct mac_iveiv_entry iveiv_entry;
1250         u32 offset;
1251         u32 reg;
1252
1253         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1254
1255         if (crypto->cmd == SET_KEY) {
1256                 rt2800_register_read(rt2x00dev, offset, &reg);
1257                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1258                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1259                 /*
1260                  * Both the cipher as the BSS Idx numbers are split in a main
1261                  * value of 3 bits, and a extended field for adding one additional
1262                  * bit to the value.
1263                  */
1264                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1265                                    (crypto->cipher & 0x7));
1266                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1267                                    (crypto->cipher & 0x8) >> 3);
1268                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1269                 rt2800_register_write(rt2x00dev, offset, reg);
1270         } else {
1271                 /* Delete the cipher without touching the bssidx */
1272                 rt2800_register_read(rt2x00dev, offset, &reg);
1273                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1274                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1275                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1276                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1277                 rt2800_register_write(rt2x00dev, offset, reg);
1278         }
1279
1280         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1281
1282         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1283         if ((crypto->cipher == CIPHER_TKIP) ||
1284             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1285             (crypto->cipher == CIPHER_AES))
1286                 iveiv_entry.iv[3] |= 0x20;
1287         iveiv_entry.iv[3] |= key->keyidx << 6;
1288         rt2800_register_multiwrite(rt2x00dev, offset,
1289                                       &iveiv_entry, sizeof(iveiv_entry));
1290 }
1291
1292 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1293                              struct rt2x00lib_crypto *crypto,
1294                              struct ieee80211_key_conf *key)
1295 {
1296         struct hw_key_entry key_entry;
1297         struct rt2x00_field32 field;
1298         u32 offset;
1299         u32 reg;
1300
1301         if (crypto->cmd == SET_KEY) {
1302                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1303
1304                 memcpy(key_entry.key, crypto->key,
1305                        sizeof(key_entry.key));
1306                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1307                        sizeof(key_entry.tx_mic));
1308                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1309                        sizeof(key_entry.rx_mic));
1310
1311                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1312                 rt2800_register_multiwrite(rt2x00dev, offset,
1313                                               &key_entry, sizeof(key_entry));
1314         }
1315
1316         /*
1317          * The cipher types are stored over multiple registers
1318          * starting with SHARED_KEY_MODE_BASE each word will have
1319          * 32 bits and contains the cipher types for 2 bssidx each.
1320          * Using the correct defines correctly will cause overhead,
1321          * so just calculate the correct offset.
1322          */
1323         field.bit_offset = 4 * (key->hw_key_idx % 8);
1324         field.bit_mask = 0x7 << field.bit_offset;
1325
1326         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1327
1328         rt2800_register_read(rt2x00dev, offset, &reg);
1329         rt2x00_set_field32(&reg, field,
1330                            (crypto->cmd == SET_KEY) * crypto->cipher);
1331         rt2800_register_write(rt2x00dev, offset, reg);
1332
1333         /*
1334          * Update WCID information
1335          */
1336         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1337         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1338                                        crypto->bssidx);
1339         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1340
1341         return 0;
1342 }
1343 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1344
1345 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1346 {
1347         struct mac_wcid_entry wcid_entry;
1348         int idx;
1349         u32 offset;
1350
1351         /*
1352          * Search for the first free WCID entry and return the corresponding
1353          * index.
1354          *
1355          * Make sure the WCID starts _after_ the last possible shared key
1356          * entry (>32).
1357          *
1358          * Since parts of the pairwise key table might be shared with
1359          * the beacon frame buffers 6 & 7 we should only write into the
1360          * first 222 entries.
1361          */
1362         for (idx = 33; idx <= 222; idx++) {
1363                 offset = MAC_WCID_ENTRY(idx);
1364                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1365                                           sizeof(wcid_entry));
1366                 if (is_broadcast_ether_addr(wcid_entry.mac))
1367                         return idx;
1368         }
1369
1370         /*
1371          * Use -1 to indicate that we don't have any more space in the WCID
1372          * table.
1373          */
1374         return -1;
1375 }
1376
1377 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1378                                struct rt2x00lib_crypto *crypto,
1379                                struct ieee80211_key_conf *key)
1380 {
1381         struct hw_key_entry key_entry;
1382         u32 offset;
1383
1384         if (crypto->cmd == SET_KEY) {
1385                 /*
1386                  * Allow key configuration only for STAs that are
1387                  * known by the hw.
1388                  */
1389                 if (crypto->wcid < 0)
1390                         return -ENOSPC;
1391                 key->hw_key_idx = crypto->wcid;
1392
1393                 memcpy(key_entry.key, crypto->key,
1394                        sizeof(key_entry.key));
1395                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1396                        sizeof(key_entry.tx_mic));
1397                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1398                        sizeof(key_entry.rx_mic));
1399
1400                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1401                 rt2800_register_multiwrite(rt2x00dev, offset,
1402                                               &key_entry, sizeof(key_entry));
1403         }
1404
1405         /*
1406          * Update WCID information
1407          */
1408         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1409
1410         return 0;
1411 }
1412 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1413
1414 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1415                    struct ieee80211_sta *sta)
1416 {
1417         int wcid;
1418         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1419
1420         /*
1421          * Find next free WCID.
1422          */
1423         wcid = rt2800_find_wcid(rt2x00dev);
1424
1425         /*
1426          * Store selected wcid even if it is invalid so that we can
1427          * later decide if the STA is uploaded into the hw.
1428          */
1429         sta_priv->wcid = wcid;
1430
1431         /*
1432          * No space left in the device, however, we can still communicate
1433          * with the STA -> No error.
1434          */
1435         if (wcid < 0)
1436                 return 0;
1437
1438         /*
1439          * Clean up WCID attributes and write STA address to the device.
1440          */
1441         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1442         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1443         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1444                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1445         return 0;
1446 }
1447 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1448
1449 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1450 {
1451         /*
1452          * Remove WCID entry, no need to clean the attributes as they will
1453          * get renewed when the WCID is reused.
1454          */
1455         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1456
1457         return 0;
1458 }
1459 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1460
1461 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1462                           const unsigned int filter_flags)
1463 {
1464         u32 reg;
1465
1466         /*
1467          * Start configuration steps.
1468          * Note that the version error will always be dropped
1469          * and broadcast frames will always be accepted since
1470          * there is no filter for it at this time.
1471          */
1472         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1473         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1474                            !(filter_flags & FIF_FCSFAIL));
1475         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1476                            !(filter_flags & FIF_PLCPFAIL));
1477         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1478                            !(filter_flags & FIF_PROMISC_IN_BSS));
1479         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1480         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1481         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1482                            !(filter_flags & FIF_ALLMULTI));
1483         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1484         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1485         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1486                            !(filter_flags & FIF_CONTROL));
1487         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1488                            !(filter_flags & FIF_CONTROL));
1489         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1490                            !(filter_flags & FIF_CONTROL));
1491         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1492                            !(filter_flags & FIF_CONTROL));
1493         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1494                            !(filter_flags & FIF_CONTROL));
1495         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1496                            !(filter_flags & FIF_PSPOLL));
1497         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1498         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1499                            !(filter_flags & FIF_CONTROL));
1500         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1501                            !(filter_flags & FIF_CONTROL));
1502         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1503 }
1504 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1505
1506 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1507                         struct rt2x00intf_conf *conf, const unsigned int flags)
1508 {
1509         u32 reg;
1510         bool update_bssid = false;
1511
1512         if (flags & CONFIG_UPDATE_TYPE) {
1513                 /*
1514                  * Enable synchronisation.
1515                  */
1516                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1517                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1518                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1519
1520                 if (conf->sync == TSF_SYNC_AP_NONE) {
1521                         /*
1522                          * Tune beacon queue transmit parameters for AP mode
1523                          */
1524                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1525                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1526                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1527                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1528                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1529                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1530                 } else {
1531                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1532                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1533                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1534                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1535                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1536                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1537                 }
1538         }
1539
1540         if (flags & CONFIG_UPDATE_MAC) {
1541                 if (flags & CONFIG_UPDATE_TYPE &&
1542                     conf->sync == TSF_SYNC_AP_NONE) {
1543                         /*
1544                          * The BSSID register has to be set to our own mac
1545                          * address in AP mode.
1546                          */
1547                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1548                         update_bssid = true;
1549                 }
1550
1551                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1552                         reg = le32_to_cpu(conf->mac[1]);
1553                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1554                         conf->mac[1] = cpu_to_le32(reg);
1555                 }
1556
1557                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1558                                               conf->mac, sizeof(conf->mac));
1559         }
1560
1561         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1562                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1563                         reg = le32_to_cpu(conf->bssid[1]);
1564                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1565                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1566                         conf->bssid[1] = cpu_to_le32(reg);
1567                 }
1568
1569                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1570                                               conf->bssid, sizeof(conf->bssid));
1571         }
1572 }
1573 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1574
1575 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1576                                     struct rt2x00lib_erp *erp)
1577 {
1578         bool any_sta_nongf = !!(erp->ht_opmode &
1579                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1580         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1581         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1582         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1583         u32 reg;
1584
1585         /* default protection rate for HT20: OFDM 24M */
1586         mm20_rate = gf20_rate = 0x4004;
1587
1588         /* default protection rate for HT40: duplicate OFDM 24M */
1589         mm40_rate = gf40_rate = 0x4084;
1590
1591         switch (protection) {
1592         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1593                 /*
1594                  * All STAs in this BSS are HT20/40 but there might be
1595                  * STAs not supporting greenfield mode.
1596                  * => Disable protection for HT transmissions.
1597                  */
1598                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1599
1600                 break;
1601         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1602                 /*
1603                  * All STAs in this BSS are HT20 or HT20/40 but there
1604                  * might be STAs not supporting greenfield mode.
1605                  * => Protect all HT40 transmissions.
1606                  */
1607                 mm20_mode = gf20_mode = 0;
1608                 mm40_mode = gf40_mode = 2;
1609
1610                 break;
1611         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1612                 /*
1613                  * Nonmember protection:
1614                  * According to 802.11n we _should_ protect all
1615                  * HT transmissions (but we don't have to).
1616                  *
1617                  * But if cts_protection is enabled we _shall_ protect
1618                  * all HT transmissions using a CCK rate.
1619                  *
1620                  * And if any station is non GF we _shall_ protect
1621                  * GF transmissions.
1622                  *
1623                  * We decide to protect everything
1624                  * -> fall through to mixed mode.
1625                  */
1626         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1627                 /*
1628                  * Legacy STAs are present
1629                  * => Protect all HT transmissions.
1630                  */
1631                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1632
1633                 /*
1634                  * If erp protection is needed we have to protect HT
1635                  * transmissions with CCK 11M long preamble.
1636                  */
1637                 if (erp->cts_protection) {
1638                         /* don't duplicate RTS/CTS in CCK mode */
1639                         mm20_rate = mm40_rate = 0x0003;
1640                         gf20_rate = gf40_rate = 0x0003;
1641                 }
1642                 break;
1643         }
1644
1645         /* check for STAs not supporting greenfield mode */
1646         if (any_sta_nongf)
1647                 gf20_mode = gf40_mode = 2;
1648
1649         /* Update HT protection config */
1650         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1651         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1652         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1653         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1654
1655         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1656         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1657         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1658         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1659
1660         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1661         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1662         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1663         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1664
1665         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1666         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1667         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1668         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1669 }
1670
1671 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1672                        u32 changed)
1673 {
1674         u32 reg;
1675
1676         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1677                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1678                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1679                                    !!erp->short_preamble);
1680                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1681                                    !!erp->short_preamble);
1682                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1683         }
1684
1685         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1686                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1687                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1688                                    erp->cts_protection ? 2 : 0);
1689                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1690         }
1691
1692         if (changed & BSS_CHANGED_BASIC_RATES) {
1693                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1694                                          erp->basic_rates);
1695                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1696         }
1697
1698         if (changed & BSS_CHANGED_ERP_SLOT) {
1699                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1700                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1701                                    erp->slot_time);
1702                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1703
1704                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1705                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1706                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1707         }
1708
1709         if (changed & BSS_CHANGED_BEACON_INT) {
1710                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1711                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1712                                    erp->beacon_int * 16);
1713                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1714         }
1715
1716         if (changed & BSS_CHANGED_HT)
1717                 rt2800_config_ht_opmode(rt2x00dev, erp);
1718 }
1719 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1720
1721 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1722 {
1723         u32 reg;
1724         u16 eeprom;
1725         u8 led_ctrl, led_g_mode, led_r_mode;
1726
1727         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1728         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1729                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1730                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1731         } else {
1732                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1733                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1734         }
1735         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1736
1737         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1738         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1739         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1740         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1741             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1742                 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1743                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1744                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1745                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1746                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1747                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1748                 } else {
1749                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1750                                            (led_g_mode << 2) | led_r_mode, 1);
1751                 }
1752         }
1753 }
1754
1755 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1756                                      enum antenna ant)
1757 {
1758         u32 reg;
1759         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1760         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1761
1762         if (rt2x00_is_pci(rt2x00dev)) {
1763                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1764                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1765                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1766         } else if (rt2x00_is_usb(rt2x00dev))
1767                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1768                                    eesk_pin, 0);
1769
1770         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1771         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1772         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1773         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1774 }
1775
1776 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1777 {
1778         u8 r1;
1779         u8 r3;
1780         u16 eeprom;
1781
1782         rt2800_bbp_read(rt2x00dev, 1, &r1);
1783         rt2800_bbp_read(rt2x00dev, 3, &r3);
1784
1785         if (rt2x00_rt(rt2x00dev, RT3572) &&
1786             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1787                 rt2800_config_3572bt_ant(rt2x00dev);
1788
1789         /*
1790          * Configure the TX antenna.
1791          */
1792         switch (ant->tx_chain_num) {
1793         case 1:
1794                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1795                 break;
1796         case 2:
1797                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1798                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1799                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1800                 else
1801                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1802                 break;
1803         case 3:
1804                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1805                 break;
1806         }
1807
1808         /*
1809          * Configure the RX antenna.
1810          */
1811         switch (ant->rx_chain_num) {
1812         case 1:
1813                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1814                     rt2x00_rt(rt2x00dev, RT3090) ||
1815                     rt2x00_rt(rt2x00dev, RT3352) ||
1816                     rt2x00_rt(rt2x00dev, RT3390)) {
1817                         rt2800_eeprom_read(rt2x00dev,
1818                                            EEPROM_NIC_CONF1, &eeprom);
1819                         if (rt2x00_get_field16(eeprom,
1820                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1821                                 rt2800_set_ant_diversity(rt2x00dev,
1822                                                 rt2x00dev->default_ant.rx);
1823                 }
1824                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1825                 break;
1826         case 2:
1827                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1828                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1829                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1830                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1831                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1832                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1833                 } else {
1834                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1835                 }
1836                 break;
1837         case 3:
1838                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1839                 break;
1840         }
1841
1842         rt2800_bbp_write(rt2x00dev, 3, r3);
1843         rt2800_bbp_write(rt2x00dev, 1, r1);
1844
1845         if (rt2x00_rt(rt2x00dev, RT3593)) {
1846                 if (ant->rx_chain_num == 1)
1847                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1848                 else
1849                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
1850         }
1851 }
1852 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1853
1854 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1855                                    struct rt2x00lib_conf *libconf)
1856 {
1857         u16 eeprom;
1858         short lna_gain;
1859
1860         if (libconf->rf.channel <= 14) {
1861                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1862                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1863         } else if (libconf->rf.channel <= 64) {
1864                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1865                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1866         } else if (libconf->rf.channel <= 128) {
1867                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1868                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1869                         lna_gain = rt2x00_get_field16(eeprom,
1870                                                       EEPROM_EXT_LNA2_A1);
1871                 } else {
1872                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1873                         lna_gain = rt2x00_get_field16(eeprom,
1874                                                       EEPROM_RSSI_BG2_LNA_A1);
1875                 }
1876         } else {
1877                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1878                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1879                         lna_gain = rt2x00_get_field16(eeprom,
1880                                                       EEPROM_EXT_LNA2_A2);
1881                 } else {
1882                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1883                         lna_gain = rt2x00_get_field16(eeprom,
1884                                                       EEPROM_RSSI_A2_LNA_A2);
1885                 }
1886         }
1887
1888         rt2x00dev->lna_gain = lna_gain;
1889 }
1890
1891 #define FREQ_OFFSET_BOUND       0x5f
1892
1893 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1894 {
1895         u8 freq_offset, prev_freq_offset;
1896         u8 rfcsr, prev_rfcsr;
1897
1898         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1899         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1900
1901         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1902         prev_rfcsr = rfcsr;
1903
1904         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1905         if (rfcsr == prev_rfcsr)
1906                 return;
1907
1908         if (rt2x00_is_usb(rt2x00dev)) {
1909                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1910                                    freq_offset, prev_rfcsr);
1911                 return;
1912         }
1913
1914         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1915         while (prev_freq_offset != freq_offset) {
1916                 if (prev_freq_offset < freq_offset)
1917                         prev_freq_offset++;
1918                 else
1919                         prev_freq_offset--;
1920
1921                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1922                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1923
1924                 usleep_range(1000, 1500);
1925         }
1926 }
1927
1928 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1929                                          struct ieee80211_conf *conf,
1930                                          struct rf_channel *rf,
1931                                          struct channel_info *info)
1932 {
1933         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1934
1935         if (rt2x00dev->default_ant.tx_chain_num == 1)
1936                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1937
1938         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1939                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1940                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1941         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1942                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1943
1944         if (rf->channel > 14) {
1945                 /*
1946                  * When TX power is below 0, we should increase it by 7 to
1947                  * make it a positive value (Minimum value is -7).
1948                  * However this means that values between 0 and 7 have
1949                  * double meaning, and we should set a 7DBm boost flag.
1950                  */
1951                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1952                                    (info->default_power1 >= 0));
1953
1954                 if (info->default_power1 < 0)
1955                         info->default_power1 += 7;
1956
1957                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1958
1959                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1960                                    (info->default_power2 >= 0));
1961
1962                 if (info->default_power2 < 0)
1963                         info->default_power2 += 7;
1964
1965                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1966         } else {
1967                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1968                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1969         }
1970
1971         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1972
1973         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1974         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1975         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1976         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1977
1978         udelay(200);
1979
1980         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1981         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1982         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1983         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1984
1985         udelay(200);
1986
1987         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1988         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1989         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1990         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1991 }
1992
1993 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1994                                          struct ieee80211_conf *conf,
1995                                          struct rf_channel *rf,
1996                                          struct channel_info *info)
1997 {
1998         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1999         u8 rfcsr, calib_tx, calib_rx;
2000
2001         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2002
2003         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2004         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2005         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2006
2007         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2008         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2009         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2010
2011         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2012         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2013         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2014
2015         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2016         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2017         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2018
2019         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2020         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2021         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2022                           rt2x00dev->default_ant.rx_chain_num <= 1);
2023         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2024                           rt2x00dev->default_ant.rx_chain_num <= 2);
2025         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2026         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2027                           rt2x00dev->default_ant.tx_chain_num <= 1);
2028         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2029                           rt2x00dev->default_ant.tx_chain_num <= 2);
2030         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2031
2032         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2033         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2034         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2035         msleep(1);
2036         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2037         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2038
2039         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2040         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2041         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2042
2043         if (rt2x00_rt(rt2x00dev, RT3390)) {
2044                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2045                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2046         } else {
2047                 if (conf_is_ht40(conf)) {
2048                         calib_tx = drv_data->calibration_bw40;
2049                         calib_rx = drv_data->calibration_bw40;
2050                 } else {
2051                         calib_tx = drv_data->calibration_bw20;
2052                         calib_rx = drv_data->calibration_bw20;
2053                 }
2054         }
2055
2056         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2057         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2058         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2059
2060         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2061         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2062         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2063
2064         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2065         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2066         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2067
2068         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2069         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2070         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2071         msleep(1);
2072         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2073         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2074 }
2075
2076 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2077                                          struct ieee80211_conf *conf,
2078                                          struct rf_channel *rf,
2079                                          struct channel_info *info)
2080 {
2081         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2082         u8 rfcsr;
2083         u32 reg;
2084
2085         if (rf->channel <= 14) {
2086                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2087                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2088         } else {
2089                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2090                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2091         }
2092
2093         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2094         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2095
2096         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2097         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2098         if (rf->channel <= 14)
2099                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2100         else
2101                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2102         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2103
2104         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2105         if (rf->channel <= 14)
2106                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2107         else
2108                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2109         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2110
2111         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2112         if (rf->channel <= 14) {
2113                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2114                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2115                                   info->default_power1);
2116         } else {
2117                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2118                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2119                                 (info->default_power1 & 0x3) |
2120                                 ((info->default_power1 & 0xC) << 1));
2121         }
2122         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2123
2124         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2125         if (rf->channel <= 14) {
2126                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2127                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2128                                   info->default_power2);
2129         } else {
2130                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2131                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2132                                 (info->default_power2 & 0x3) |
2133                                 ((info->default_power2 & 0xC) << 1));
2134         }
2135         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2136
2137         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2138         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2139         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2140         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2141         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2142         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2143         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2144         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2145                 if (rf->channel <= 14) {
2146                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2147                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2148                 }
2149                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2150                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2151         } else {
2152                 switch (rt2x00dev->default_ant.tx_chain_num) {
2153                 case 1:
2154                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2155                 case 2:
2156                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2157                         break;
2158                 }
2159
2160                 switch (rt2x00dev->default_ant.rx_chain_num) {
2161                 case 1:
2162                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2163                 case 2:
2164                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2165                         break;
2166                 }
2167         }
2168         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2169
2170         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2171         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2172         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2173
2174         if (conf_is_ht40(conf)) {
2175                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2176                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2177         } else {
2178                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2179                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2180         }
2181
2182         if (rf->channel <= 14) {
2183                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2184                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2185                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2186                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2187                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2188                 rfcsr = 0x4c;
2189                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2190                                   drv_data->txmixer_gain_24g);
2191                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2192                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2193                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2194                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2195                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2196                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2197                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2198                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2199         } else {
2200                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2201                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2202                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2203                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2204                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2205                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2206                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2207                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2208                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2209                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2210                 rfcsr = 0x7a;
2211                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2212                                   drv_data->txmixer_gain_5g);
2213                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2214                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2215                 if (rf->channel <= 64) {
2216                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2217                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2218                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2219                 } else if (rf->channel <= 128) {
2220                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2221                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2222                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2223                 } else {
2224                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2225                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2226                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2227                 }
2228                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2229                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2230                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2231         }
2232
2233         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2234         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2235         if (rf->channel <= 14)
2236                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2237         else
2238                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2239         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2240
2241         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2242         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2243         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2244 }
2245
2246 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2247                                          struct ieee80211_conf *conf,
2248                                          struct rf_channel *rf,
2249                                          struct channel_info *info)
2250 {
2251         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2252         u8 txrx_agc_fc;
2253         u8 txrx_h20m;
2254         u8 rfcsr;
2255         u8 bbp;
2256         const bool txbf_enabled = false; /* TODO */
2257
2258         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2259         rt2800_bbp_read(rt2x00dev, 109, &bbp);
2260         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2261         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2262         rt2800_bbp_write(rt2x00dev, 109, bbp);
2263
2264         rt2800_bbp_read(rt2x00dev, 110, &bbp);
2265         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2266         rt2800_bbp_write(rt2x00dev, 110, bbp);
2267
2268         if (rf->channel <= 14) {
2269                 /* Restore BBP 25 & 26 for 2.4 GHz */
2270                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2271                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2272         } else {
2273                 /* Hard code BBP 25 & 26 for 5GHz */
2274
2275                 /* Enable IQ Phase correction */
2276                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2277                 /* Setup IQ Phase correction value */
2278                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2279         }
2280
2281         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2282         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2283
2284         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2285         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2286         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2287
2288         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2289         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2290         if (rf->channel <= 14)
2291                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2292         else
2293                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2294         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2295
2296         rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2297         if (rf->channel <= 14) {
2298                 rfcsr = 0;
2299                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2300                                   info->default_power1 & 0x1f);
2301         } else {
2302                 if (rt2x00_is_usb(rt2x00dev))
2303                         rfcsr = 0x40;
2304
2305                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2306                                   ((info->default_power1 & 0x18) << 1) |
2307                                   (info->default_power1 & 7));
2308         }
2309         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2310
2311         rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2312         if (rf->channel <= 14) {
2313                 rfcsr = 0;
2314                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2315                                   info->default_power2 & 0x1f);
2316         } else {
2317                 if (rt2x00_is_usb(rt2x00dev))
2318                         rfcsr = 0x40;
2319
2320                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2321                                   ((info->default_power2 & 0x18) << 1) |
2322                                   (info->default_power2 & 7));
2323         }
2324         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2325
2326         rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2327         if (rf->channel <= 14) {
2328                 rfcsr = 0;
2329                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2330                                   info->default_power3 & 0x1f);
2331         } else {
2332                 if (rt2x00_is_usb(rt2x00dev))
2333                         rfcsr = 0x40;
2334
2335                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2336                                   ((info->default_power3 & 0x18) << 1) |
2337                                   (info->default_power3 & 7));
2338         }
2339         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2340
2341         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2342         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2343         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2344         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2345         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2346         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2347         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2348         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2349         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2350
2351         switch (rt2x00dev->default_ant.tx_chain_num) {
2352         case 3:
2353                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2354                 /* fallthrough */
2355         case 2:
2356                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2357                 /* fallthrough */
2358         case 1:
2359                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2360                 break;
2361         }
2362
2363         switch (rt2x00dev->default_ant.rx_chain_num) {
2364         case 3:
2365                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2366                 /* fallthrough */
2367         case 2:
2368                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2369                 /* fallthrough */
2370         case 1:
2371                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2372                 break;
2373         }
2374         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2375
2376         rt2800_adjust_freq_offset(rt2x00dev);
2377
2378         if (conf_is_ht40(conf)) {
2379                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2380                                                 RFCSR24_TX_AGC_FC);
2381                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2382                                               RFCSR24_TX_H20M);
2383         } else {
2384                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2385                                                 RFCSR24_TX_AGC_FC);
2386                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2387                                               RFCSR24_TX_H20M);
2388         }
2389
2390         /* NOTE: the reference driver does not writes the new value
2391          * back to RFCSR 32
2392          */
2393         rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2394         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2395
2396         if (rf->channel <= 14)
2397                 rfcsr = 0xa0;
2398         else
2399                 rfcsr = 0x80;
2400         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2401
2402         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2403         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2404         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2405         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2406
2407         /* Band selection */
2408         rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2409         if (rf->channel <= 14)
2410                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2411         else
2412                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2413         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2414
2415         rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2416         if (rf->channel <= 14)
2417                 rfcsr = 0x3c;
2418         else
2419                 rfcsr = 0x20;
2420         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2421
2422         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2423         if (rf->channel <= 14)
2424                 rfcsr = 0x1a;
2425         else
2426                 rfcsr = 0x12;
2427         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2428
2429         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2430         if (rf->channel >= 1 && rf->channel <= 14)
2431                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2432         else if (rf->channel >= 36 && rf->channel <= 64)
2433                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2434         else if (rf->channel >= 100 && rf->channel <= 128)
2435                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2436         else
2437                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2438         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2439
2440         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2441         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2442         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2443
2444         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2445
2446         if (rf->channel <= 14) {
2447                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2448                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2449         } else {
2450                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2451                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2452         }
2453
2454         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2455         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2456         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2457
2458         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2459         if (rf->channel <= 14) {
2460                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2461                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2462         } else {
2463                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2464                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2465         }
2466         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2467
2468         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2469         if (rf->channel <= 14)
2470                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2471         else
2472                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2473
2474         if (txbf_enabled)
2475                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2476
2477         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2478
2479         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2480         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2481         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2482
2483         rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2484         if (rf->channel <= 14)
2485                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2486         else
2487                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2488         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2489
2490         if (rf->channel <= 14) {
2491                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2492                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2493         } else {
2494                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2495                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2496         }
2497
2498         /* Initiate VCO calibration */
2499         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2500         if (rf->channel <= 14) {
2501                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2502         } else {
2503                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2504                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2505                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2506                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2507                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2508                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2509         }
2510         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2511
2512         if (rf->channel >= 1 && rf->channel <= 14) {
2513                 rfcsr = 0x23;
2514                 if (txbf_enabled)
2515                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2516                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2517
2518                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2519         } else if (rf->channel >= 36 && rf->channel <= 64) {
2520                 rfcsr = 0x36;
2521                 if (txbf_enabled)
2522                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2523                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2524
2525                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2526         } else if (rf->channel >= 100 && rf->channel <= 128) {
2527                 rfcsr = 0x32;
2528                 if (txbf_enabled)
2529                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2530                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2531
2532                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2533         } else {
2534                 rfcsr = 0x30;
2535                 if (txbf_enabled)
2536                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2537                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2538
2539                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2540         }
2541 }
2542
2543 #define POWER_BOUND             0x27
2544 #define POWER_BOUND_5G          0x2b
2545
2546 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2547                                          struct ieee80211_conf *conf,
2548                                          struct rf_channel *rf,
2549                                          struct channel_info *info)
2550 {
2551         u8 rfcsr;
2552
2553         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2554         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2555         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2556         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2557         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2558
2559         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2560         if (info->default_power1 > POWER_BOUND)
2561                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2562         else
2563                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2564         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2565
2566         rt2800_adjust_freq_offset(rt2x00dev);
2567
2568         if (rf->channel <= 14) {
2569                 if (rf->channel == 6)
2570                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2571                 else
2572                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2573
2574                 if (rf->channel >= 1 && rf->channel <= 6)
2575                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2576                 else if (rf->channel >= 7 && rf->channel <= 11)
2577                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2578                 else if (rf->channel >= 12 && rf->channel <= 14)
2579                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2580         }
2581 }
2582
2583 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2584                                          struct ieee80211_conf *conf,
2585                                          struct rf_channel *rf,
2586                                          struct channel_info *info)
2587 {
2588         u8 rfcsr;
2589
2590         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2591         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2592
2593         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2594         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2595         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2596
2597         if (info->default_power1 > POWER_BOUND)
2598                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2599         else
2600                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2601
2602         if (info->default_power2 > POWER_BOUND)
2603                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2604         else
2605                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2606
2607         rt2800_adjust_freq_offset(rt2x00dev);
2608
2609         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2610         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2611         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2612
2613         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2614                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2615         else
2616                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2617
2618         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2619                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2620         else
2621                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2622
2623         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2624         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2625
2626         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2627
2628         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2629 }
2630
2631 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2632                                          struct ieee80211_conf *conf,
2633                                          struct rf_channel *rf,
2634                                          struct channel_info *info)
2635 {
2636         u8 rfcsr;
2637
2638         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2639         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2640         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2641         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2642         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2643
2644         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2645         if (info->default_power1 > POWER_BOUND)
2646                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2647         else
2648                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2649         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2650
2651         if (rt2x00_rt(rt2x00dev, RT5392)) {
2652                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2653                 if (info->default_power1 > POWER_BOUND)
2654                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2655                 else
2656                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2657                                           info->default_power2);
2658                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2659         }
2660
2661         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2662         if (rt2x00_rt(rt2x00dev, RT5392)) {
2663                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2664                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2665         }
2666         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2667         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2668         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2669         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2670         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2671
2672         rt2800_adjust_freq_offset(rt2x00dev);
2673
2674         if (rf->channel <= 14) {
2675                 int idx = rf->channel-1;
2676
2677                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2678                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2679                                 /* r55/r59 value array of channel 1~14 */
2680                                 static const char r55_bt_rev[] = {0x83, 0x83,
2681                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2682                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2683                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2684                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2685                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2686
2687                                 rt2800_rfcsr_write(rt2x00dev, 55,
2688                                                    r55_bt_rev[idx]);
2689                                 rt2800_rfcsr_write(rt2x00dev, 59,
2690                                                    r59_bt_rev[idx]);
2691                         } else {
2692                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2693                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2694                                         0x88, 0x88, 0x86, 0x85, 0x84};
2695
2696                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2697                         }
2698                 } else {
2699                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2700                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2701                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2702                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2703                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2704                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2705                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2706
2707                                 rt2800_rfcsr_write(rt2x00dev, 55,
2708                                                    r55_nonbt_rev[idx]);
2709                                 rt2800_rfcsr_write(rt2x00dev, 59,
2710                                                    r59_nonbt_rev[idx]);
2711                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2712                                    rt2x00_rt(rt2x00dev, RT5392)) {
2713                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2714                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2715                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2716
2717                                 rt2800_rfcsr_write(rt2x00dev, 59,
2718                                                    r59_non_bt[idx]);
2719                         }
2720                 }
2721         }
2722 }
2723
2724 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2725                                          struct ieee80211_conf *conf,
2726                                          struct rf_channel *rf,
2727                                          struct channel_info *info)
2728 {
2729         u8 rfcsr, ep_reg;
2730         u32 reg;
2731         int power_bound;
2732
2733         /* TODO */
2734         const bool is_11b = false;
2735         const bool is_type_ep = false;
2736
2737         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2738         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2739                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2740         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2741
2742         /* Order of values on rf_channel entry: N, K, mod, R */
2743         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2744
2745         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2746         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2747         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2748         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2749         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2750
2751         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2752         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2753         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2754         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2755
2756         if (rf->channel <= 14) {
2757                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2758                 /* FIXME: RF11 owerwrite ? */
2759                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2760                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2761                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2762                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2763                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2764                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2765                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2766                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2767                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2768                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2769                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2770                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2771                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2772                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2773                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2774                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2775                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2776                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2777                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2778                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2779                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2780                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2781                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2782                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2783                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2784                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2785                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2786                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2787
2788                 /* TODO RF27 <- tssi */
2789
2790                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2791                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2792                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2793
2794                 if (is_11b) {
2795                         /* CCK */
2796                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2797                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2798                         if (is_type_ep)
2799                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2800                         else
2801                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2802                 } else {
2803                         /* OFDM */
2804                         if (is_type_ep)
2805                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2806                         else
2807                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2808                 }
2809
2810                 power_bound = POWER_BOUND;
2811                 ep_reg = 0x2;
2812         } else {
2813                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2814                 /* FIMXE: RF11 overwrite */
2815                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2816                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2817                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2818                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2819                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2820                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2821                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2822                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2823                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2824                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2825                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2826                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2827                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2828                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2829
2830                 /* TODO RF27 <- tssi */
2831
2832                 if (rf->channel >= 36 && rf->channel <= 64) {
2833
2834                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2835                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2836                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2837                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2838                         if (rf->channel <= 50)
2839                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2840                         else if (rf->channel >= 52)
2841                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2842                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2843                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2844                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2845                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2846                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2847                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2848                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2849                         if (rf->channel <= 50) {
2850                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2851                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2852                         } else if (rf->channel >= 52) {
2853                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2854                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2855                         }
2856
2857                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2858                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2859                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2860
2861                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2862
2863                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2864                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2865                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2866                         if (rf->channel <= 153) {
2867                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2868                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2869                         } else if (rf->channel >= 155) {
2870                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2871                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2872                         }
2873                         if (rf->channel <= 138) {
2874                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2875                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2876                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2877                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2878                         } else if (rf->channel >= 140) {
2879                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2880                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2881                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2882                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2883                         }
2884                         if (rf->channel <= 124)
2885                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2886                         else if (rf->channel >= 126)
2887                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2888                         if (rf->channel <= 138)
2889                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2890                         else if (rf->channel >= 140)
2891                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2892                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2893                         if (rf->channel <= 138)
2894                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2895                         else if (rf->channel >= 140)
2896                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2897                         if (rf->channel <= 128)
2898                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2899                         else if (rf->channel >= 130)
2900                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2901                         if (rf->channel <= 116)
2902                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2903                         else if (rf->channel >= 118)
2904                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2905                         if (rf->channel <= 138)
2906                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2907                         else if (rf->channel >= 140)
2908                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2909                         if (rf->channel <= 116)
2910                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2911                         else if (rf->channel >= 118)
2912                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2913                 }
2914
2915                 power_bound = POWER_BOUND_5G;
2916                 ep_reg = 0x3;
2917         }
2918
2919         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2920         if (info->default_power1 > power_bound)
2921                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2922         else
2923                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2924         if (is_type_ep)
2925                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2926         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2927
2928         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2929         if (info->default_power2 > power_bound)
2930                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2931         else
2932                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2933         if (is_type_ep)
2934                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2935         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2936
2937         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2938         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2939         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2940
2941         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2942                           rt2x00dev->default_ant.tx_chain_num >= 1);
2943         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2944                           rt2x00dev->default_ant.tx_chain_num == 2);
2945         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2946
2947         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2948                           rt2x00dev->default_ant.rx_chain_num >= 1);
2949         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2950                           rt2x00dev->default_ant.rx_chain_num == 2);
2951         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2952
2953         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2954         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2955
2956         if (conf_is_ht40(conf))
2957                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2958         else
2959                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2960
2961         if (!is_11b) {
2962                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2963                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2964         }
2965
2966         /* TODO proper frequency adjustment */
2967         rt2800_adjust_freq_offset(rt2x00dev);
2968
2969         /* TODO merge with others */
2970         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2971         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2972         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2973
2974         /* BBP settings */
2975         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2976         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2977         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2978
2979         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2980         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2981         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2982         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2983
2984         /* GLRT band configuration */
2985         rt2800_bbp_write(rt2x00dev, 195, 128);
2986         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2987         rt2800_bbp_write(rt2x00dev, 195, 129);
2988         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2989         rt2800_bbp_write(rt2x00dev, 195, 130);
2990         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2991         rt2800_bbp_write(rt2x00dev, 195, 131);
2992         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2993         rt2800_bbp_write(rt2x00dev, 195, 133);
2994         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2995         rt2800_bbp_write(rt2x00dev, 195, 124);
2996         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2997 }
2998
2999 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3000                                            const unsigned int word,
3001                                            const u8 value)
3002 {
3003         u8 chain, reg;
3004
3005         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3006                 rt2800_bbp_read(rt2x00dev, 27, &reg);
3007                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3008                 rt2800_bbp_write(rt2x00dev, 27, reg);
3009
3010                 rt2800_bbp_write(rt2x00dev, word, value);
3011         }
3012 }
3013
3014 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3015 {
3016         u8 cal;
3017
3018         /* TX0 IQ Gain */
3019         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3020         if (channel <= 14)
3021                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3022         else if (channel >= 36 && channel <= 64)
3023                 cal = rt2x00_eeprom_byte(rt2x00dev,
3024                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3025         else if (channel >= 100 && channel <= 138)
3026                 cal = rt2x00_eeprom_byte(rt2x00dev,
3027                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3028         else if (channel >= 140 && channel <= 165)
3029                 cal = rt2x00_eeprom_byte(rt2x00dev,
3030                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3031         else
3032                 cal = 0;
3033         rt2800_bbp_write(rt2x00dev, 159, cal);
3034
3035         /* TX0 IQ Phase */
3036         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3037         if (channel <= 14)
3038                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3039         else if (channel >= 36 && channel <= 64)
3040                 cal = rt2x00_eeprom_byte(rt2x00dev,
3041                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3042         else if (channel >= 100 && channel <= 138)
3043                 cal = rt2x00_eeprom_byte(rt2x00dev,
3044                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3045         else if (channel >= 140 && channel <= 165)
3046                 cal = rt2x00_eeprom_byte(rt2x00dev,
3047                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3048         else
3049                 cal = 0;
3050         rt2800_bbp_write(rt2x00dev, 159, cal);
3051
3052         /* TX1 IQ Gain */
3053         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3054         if (channel <= 14)
3055                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3056         else if (channel >= 36 && channel <= 64)
3057                 cal = rt2x00_eeprom_byte(rt2x00dev,
3058                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3059         else if (channel >= 100 && channel <= 138)
3060                 cal = rt2x00_eeprom_byte(rt2x00dev,
3061                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3062         else if (channel >= 140 && channel <= 165)
3063                 cal = rt2x00_eeprom_byte(rt2x00dev,
3064                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3065         else
3066                 cal = 0;
3067         rt2800_bbp_write(rt2x00dev, 159, cal);
3068
3069         /* TX1 IQ Phase */
3070         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3071         if (channel <= 14)
3072                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3073         else if (channel >= 36 && channel <= 64)
3074                 cal = rt2x00_eeprom_byte(rt2x00dev,
3075                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3076         else if (channel >= 100 && channel <= 138)
3077                 cal = rt2x00_eeprom_byte(rt2x00dev,
3078                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3079         else if (channel >= 140 && channel <= 165)
3080                 cal = rt2x00_eeprom_byte(rt2x00dev,
3081                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3082         else
3083                 cal = 0;
3084         rt2800_bbp_write(rt2x00dev, 159, cal);
3085
3086         /* FIXME: possible RX0, RX1 callibration ? */
3087
3088         /* RF IQ compensation control */
3089         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3090         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3091         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3092
3093         /* RF IQ imbalance compensation control */
3094         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3095         cal = rt2x00_eeprom_byte(rt2x00dev,
3096                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3097         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3098 }
3099
3100 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3101                                   unsigned int channel,
3102                                   char txpower)
3103 {
3104         if (rt2x00_rt(rt2x00dev, RT3593))
3105                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3106
3107         if (channel <= 14)
3108                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3109
3110         if (rt2x00_rt(rt2x00dev, RT3593))
3111                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3112                                MAX_A_TXPOWER_3593);
3113         else
3114                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3115 }
3116
3117 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3118                                   struct ieee80211_conf *conf,
3119                                   struct rf_channel *rf,
3120                                   struct channel_info *info)
3121 {
3122         u32 reg;
3123         unsigned int tx_pin;
3124         u8 bbp, rfcsr;
3125
3126         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3127                                                      info->default_power1);
3128         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3129                                                      info->default_power2);
3130         if (rt2x00dev->default_ant.tx_chain_num > 2)
3131                 info->default_power3 =
3132                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3133                                               info->default_power3);
3134
3135         switch (rt2x00dev->chip.rf) {
3136         case RF2020:
3137         case RF3020:
3138         case RF3021:
3139         case RF3022:
3140         case RF3320:
3141                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3142                 break;
3143         case RF3052:
3144                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3145                 break;
3146         case RF3053:
3147                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3148                 break;
3149         case RF3290:
3150                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3151                 break;
3152         case RF3322:
3153                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3154                 break;
3155         case RF5360:
3156         case RF5370:
3157         case RF5372:
3158         case RF5390:
3159         case RF5392:
3160                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3161                 break;
3162         case RF5592:
3163                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3164                 break;
3165         default:
3166                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3167         }
3168
3169         if (rt2x00_rf(rt2x00dev, RF3290) ||
3170             rt2x00_rf(rt2x00dev, RF3322) ||
3171             rt2x00_rf(rt2x00dev, RF5360) ||
3172             rt2x00_rf(rt2x00dev, RF5370) ||
3173             rt2x00_rf(rt2x00dev, RF5372) ||
3174             rt2x00_rf(rt2x00dev, RF5390) ||
3175             rt2x00_rf(rt2x00dev, RF5392)) {
3176                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3177                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3178                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3179                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3180
3181                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3182                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3183                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3184         }
3185
3186         /*
3187          * Change BBP settings
3188          */
3189         if (rt2x00_rt(rt2x00dev, RT3352)) {
3190                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3191                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3192                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3193                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3194         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3195                 if (rf->channel > 14) {
3196                         /* Disable CCK Packet detection on 5GHz */
3197                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
3198                 } else {
3199                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3200                 }
3201
3202                 if (conf_is_ht40(conf))
3203                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
3204                 else
3205                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
3206
3207                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3208                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3209                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3210                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3211         } else {
3212                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3213                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3214                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3215                 rt2800_bbp_write(rt2x00dev, 86, 0);
3216         }
3217
3218         if (rf->channel <= 14) {
3219                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3220                     !rt2x00_rt(rt2x00dev, RT5392)) {
3221                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3222                                      &rt2x00dev->cap_flags)) {
3223                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3224                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3225                         } else {
3226                                 if (rt2x00_rt(rt2x00dev, RT3593))
3227                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3228                                 else
3229                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
3230                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3231                         }
3232                         if (rt2x00_rt(rt2x00dev, RT3593))
3233                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3234                 }
3235
3236         } else {
3237                 if (rt2x00_rt(rt2x00dev, RT3572))
3238                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
3239                 else if (rt2x00_rt(rt2x00dev, RT3593))
3240                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
3241                 else
3242                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3243
3244                 if (rt2x00_rt(rt2x00dev, RT3593))
3245                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3246
3247                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
3248                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
3249                 else
3250                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
3251         }
3252
3253         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3254         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3255         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3256         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3257         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3258
3259         if (rt2x00_rt(rt2x00dev, RT3572))
3260                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3261
3262         tx_pin = 0;
3263
3264         switch (rt2x00dev->default_ant.tx_chain_num) {
3265         case 3:
3266                 /* Turn on tertiary PAs */
3267                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3268                                    rf->channel > 14);
3269                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3270                                    rf->channel <= 14);
3271                 /* fall-through */
3272         case 2:
3273                 /* Turn on secondary PAs */
3274                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3275                                    rf->channel > 14);
3276                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3277                                    rf->channel <= 14);
3278                 /* fall-through */
3279         case 1:
3280                 /* Turn on primary PAs */
3281                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3282                                    rf->channel > 14);
3283                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
3284                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3285                 else
3286                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3287                                            rf->channel <= 14);
3288                 break;
3289         }
3290
3291         switch (rt2x00dev->default_ant.rx_chain_num) {
3292         case 3:
3293                 /* Turn on tertiary LNAs */
3294                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3295                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3296                 /* fall-through */
3297         case 2:
3298                 /* Turn on secondary LNAs */
3299                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3300                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3301                 /* fall-through */
3302         case 1:
3303                 /* Turn on primary LNAs */
3304                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3305                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3306                 break;
3307         }
3308
3309         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3310         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3311
3312         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3313
3314         if (rt2x00_rt(rt2x00dev, RT3572))
3315                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3316
3317         if (rt2x00_rt(rt2x00dev, RT3593)) {
3318                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3319
3320                 /* Band selection */
3321                 if (rt2x00_is_usb(rt2x00dev) ||
3322                     rt2x00_is_pcie(rt2x00dev)) {
3323                         /* GPIO #8 controls all paths */
3324                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3325                         if (rf->channel <= 14)
3326                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3327                         else
3328                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3329                 }
3330
3331                 /* LNA PE control. */
3332                 if (rt2x00_is_usb(rt2x00dev)) {
3333                         /* GPIO #4 controls PE0 and PE1,
3334                          * GPIO #7 controls PE2
3335                          */
3336                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3337                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3338
3339                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3340                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3341                 } else if (rt2x00_is_pcie(rt2x00dev)) {
3342                         /* GPIO #4 controls PE0, PE1 and PE2 */
3343                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3344                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3345                 }
3346
3347                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3348
3349                 /* AGC init */
3350                 if (rf->channel <= 14)
3351                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
3352                 else
3353                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3354
3355                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3356
3357                 usleep_range(1000, 1500);
3358         }
3359
3360         if (rt2x00_rt(rt2x00dev, RT5592)) {
3361                 rt2800_bbp_write(rt2x00dev, 195, 141);
3362                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3363
3364                 /* AGC init */
3365                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3366                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3367
3368                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3369         }
3370
3371         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3372         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3373         rt2800_bbp_write(rt2x00dev, 4, bbp);
3374
3375         rt2800_bbp_read(rt2x00dev, 3, &bbp);
3376         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3377         rt2800_bbp_write(rt2x00dev, 3, bbp);
3378
3379         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3380                 if (conf_is_ht40(conf)) {
3381                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3382                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3383                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
3384                 } else {
3385                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
3386                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
3387                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
3388                 }
3389         }
3390
3391         msleep(1);
3392
3393         /*
3394          * Clear channel statistic counters
3395          */
3396         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3397         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3398         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3399
3400         /*
3401          * Clear update flag
3402          */
3403         if (rt2x00_rt(rt2x00dev, RT3352)) {
3404                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3405                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3406                 rt2800_bbp_write(rt2x00dev, 49, bbp);
3407         }
3408 }
3409
3410 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3411 {
3412         u8 tssi_bounds[9];
3413         u8 current_tssi;
3414         u16 eeprom;
3415         u8 step;
3416         int i;
3417
3418         /*
3419          * First check if temperature compensation is supported.
3420          */
3421         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3422         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3423                 return 0;
3424
3425         /*
3426          * Read TSSI boundaries for temperature compensation from
3427          * the EEPROM.
3428          *
3429          * Array idx               0    1    2    3    4    5    6    7    8
3430          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3431          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3432          */
3433         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3434                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3435                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3436                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
3437                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3438                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
3439
3440                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3441                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3442                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
3443                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3444                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3445
3446                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3447                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3448                                         EEPROM_TSSI_BOUND_BG3_REF);
3449                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3450                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3451
3452                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3453                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3454                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3455                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3456                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3457
3458                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3459                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3460                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3461
3462                 step = rt2x00_get_field16(eeprom,
3463                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3464         } else {
3465                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3466                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3467                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3468                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3469                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3470
3471                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3472                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3473                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3474                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3475                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3476
3477                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3478                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3479                                         EEPROM_TSSI_BOUND_A3_REF);
3480                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3481                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3482
3483                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3484                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3485                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3486                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3487                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3488
3489                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3490                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3491                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3492
3493                 step = rt2x00_get_field16(eeprom,
3494                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3495         }
3496
3497         /*
3498          * Check if temperature compensation is supported.
3499          */
3500         if (tssi_bounds[4] == 0xff || step == 0xff)
3501                 return 0;
3502
3503         /*
3504          * Read current TSSI (BBP 49).
3505          */
3506         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3507
3508         /*
3509          * Compare TSSI value (BBP49) with the compensation boundaries
3510          * from the EEPROM and increase or decrease tx power.
3511          */
3512         for (i = 0; i <= 3; i++) {
3513                 if (current_tssi > tssi_bounds[i])
3514                         break;
3515         }
3516
3517         if (i == 4) {
3518                 for (i = 8; i >= 5; i--) {
3519                         if (current_tssi < tssi_bounds[i])
3520                                 break;
3521                 }
3522         }
3523
3524         return (i - 4) * step;
3525 }
3526
3527 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3528                                       enum ieee80211_band band)
3529 {
3530         u16 eeprom;
3531         u8 comp_en;
3532         u8 comp_type;
3533         int comp_value = 0;
3534
3535         rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3536
3537         /*
3538          * HT40 compensation not required.
3539          */
3540         if (eeprom == 0xffff ||
3541             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3542                 return 0;
3543
3544         if (band == IEEE80211_BAND_2GHZ) {
3545                 comp_en = rt2x00_get_field16(eeprom,
3546                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
3547                 if (comp_en) {
3548                         comp_type = rt2x00_get_field16(eeprom,
3549                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
3550                         comp_value = rt2x00_get_field16(eeprom,
3551                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
3552                         if (!comp_type)
3553                                 comp_value = -comp_value;
3554                 }
3555         } else {
3556                 comp_en = rt2x00_get_field16(eeprom,
3557                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
3558                 if (comp_en) {
3559                         comp_type = rt2x00_get_field16(eeprom,
3560                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
3561                         comp_value = rt2x00_get_field16(eeprom,
3562                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
3563                         if (!comp_type)
3564                                 comp_value = -comp_value;
3565                 }
3566         }
3567
3568         return comp_value;
3569 }
3570
3571 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3572                                         int power_level, int max_power)
3573 {
3574         int delta;
3575
3576         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3577                 return 0;
3578
3579         /*
3580          * XXX: We don't know the maximum transmit power of our hardware since
3581          * the EEPROM doesn't expose it. We only know that we are calibrated
3582          * to 100% tx power.
3583          *
3584          * Hence, we assume the regulatory limit that cfg80211 calulated for
3585          * the current channel is our maximum and if we are requested to lower
3586          * the value we just reduce our tx power accordingly.
3587          */
3588         delta = power_level - max_power;
3589         return min(delta, 0);
3590 }
3591
3592 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3593                                    enum ieee80211_band band, int power_level,
3594                                    u8 txpower, int delta)
3595 {
3596         u16 eeprom;
3597         u8 criterion;
3598         u8 eirp_txpower;
3599         u8 eirp_txpower_criterion;
3600         u8 reg_limit;
3601
3602         if (rt2x00_rt(rt2x00dev, RT3593))
3603                 return min_t(u8, txpower, 0xc);
3604
3605         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3606                 /*
3607                  * Check if eirp txpower exceed txpower_limit.
3608                  * We use OFDM 6M as criterion and its eirp txpower
3609                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
3610                  * .11b data rate need add additional 4dbm
3611                  * when calculating eirp txpower.
3612                  */
3613                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3614                                               1, &eeprom);
3615                 criterion = rt2x00_get_field16(eeprom,
3616                                                EEPROM_TXPOWER_BYRATE_RATE0);
3617
3618                 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3619                                    &eeprom);
3620
3621                 if (band == IEEE80211_BAND_2GHZ)
3622                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3623                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3624                 else
3625                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3626                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3627
3628                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3629                                (is_rate_b ? 4 : 0) + delta;
3630
3631                 reg_limit = (eirp_txpower > power_level) ?
3632                                         (eirp_txpower - power_level) : 0;
3633         } else
3634                 reg_limit = 0;
3635
3636         txpower = max(0, txpower + delta - reg_limit);
3637         return min_t(u8, txpower, 0xc);
3638 }
3639
3640
3641 enum {
3642         TX_PWR_CFG_0_IDX,
3643         TX_PWR_CFG_1_IDX,
3644         TX_PWR_CFG_2_IDX,
3645         TX_PWR_CFG_3_IDX,
3646         TX_PWR_CFG_4_IDX,
3647         TX_PWR_CFG_5_IDX,
3648         TX_PWR_CFG_6_IDX,
3649         TX_PWR_CFG_7_IDX,
3650         TX_PWR_CFG_8_IDX,
3651         TX_PWR_CFG_9_IDX,
3652         TX_PWR_CFG_0_EXT_IDX,
3653         TX_PWR_CFG_1_EXT_IDX,
3654         TX_PWR_CFG_2_EXT_IDX,
3655         TX_PWR_CFG_3_EXT_IDX,
3656         TX_PWR_CFG_4_EXT_IDX,
3657         TX_PWR_CFG_IDX_COUNT,
3658 };
3659
3660 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3661                                          struct ieee80211_channel *chan,
3662                                          int power_level)
3663 {
3664         u8 txpower;
3665         u16 eeprom;
3666         u32 regs[TX_PWR_CFG_IDX_COUNT];
3667         unsigned int offset;
3668         enum ieee80211_band band = chan->band;
3669         int delta;
3670         int i;
3671
3672         memset(regs, '\0', sizeof(regs));
3673
3674         /* TODO: adapt TX power reduction from the rt28xx code */
3675
3676         /* calculate temperature compensation delta */
3677         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3678
3679         if (band == IEEE80211_BAND_5GHZ)
3680                 offset = 16;
3681         else
3682                 offset = 0;
3683
3684         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3685                 offset += 8;
3686
3687         /* read the next four txpower values */
3688         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3689                                       offset, &eeprom);
3690
3691         /* CCK 1MBS,2MBS */
3692         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3693         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3694                                             txpower, delta);
3695         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3696                            TX_PWR_CFG_0_CCK1_CH0, txpower);
3697         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3698                            TX_PWR_CFG_0_CCK1_CH1, txpower);
3699         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3700                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3701
3702         /* CCK 5.5MBS,11MBS */
3703         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3704         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3705                                             txpower, delta);
3706         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3707                            TX_PWR_CFG_0_CCK5_CH0, txpower);
3708         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3709                            TX_PWR_CFG_0_CCK5_CH1, txpower);
3710         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3711                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3712
3713         /* OFDM 6MBS,9MBS */
3714         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3715         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3716                                             txpower, delta);
3717         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3718                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
3719         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3720                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
3721         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3722                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3723
3724         /* OFDM 12MBS,18MBS */
3725         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3726         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3727                                             txpower, delta);
3728         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3729                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
3730         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3731                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
3732         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3733                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3734
3735         /* read the next four txpower values */
3736         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3737                                       offset + 1, &eeprom);
3738
3739         /* OFDM 24MBS,36MBS */
3740         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3741         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3742                                             txpower, delta);
3743         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3744                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
3745         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3746                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
3747         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3748                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3749
3750         /* OFDM 48MBS */
3751         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3752         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3753                                             txpower, delta);
3754         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3755                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
3756         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3757                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
3758         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3759                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3760
3761         /* OFDM 54MBS */
3762         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3763         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3764                                             txpower, delta);
3765         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3766                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
3767         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3768                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
3769         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3770                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
3771
3772         /* read the next four txpower values */
3773         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3774                                       offset + 2, &eeprom);
3775
3776         /* MCS 0,1 */
3777         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3778         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3779                                             txpower, delta);
3780         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3781                            TX_PWR_CFG_1_MCS0_CH0, txpower);
3782         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3783                            TX_PWR_CFG_1_MCS0_CH1, txpower);
3784         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3785                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3786
3787         /* MCS 2,3 */
3788         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3789         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3790                                             txpower, delta);
3791         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3792                            TX_PWR_CFG_1_MCS2_CH0, txpower);
3793         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3794                            TX_PWR_CFG_1_MCS2_CH1, txpower);
3795         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3796                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3797
3798         /* MCS 4,5 */
3799         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3800         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3801                                             txpower, delta);
3802         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3803                            TX_PWR_CFG_2_MCS4_CH0, txpower);
3804         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3805                            TX_PWR_CFG_2_MCS4_CH1, txpower);
3806         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3807                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3808
3809         /* MCS 6 */
3810         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3811         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3812                                             txpower, delta);
3813         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3814                            TX_PWR_CFG_2_MCS6_CH0, txpower);
3815         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3816                            TX_PWR_CFG_2_MCS6_CH1, txpower);
3817         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3818                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3819
3820         /* read the next four txpower values */
3821         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3822                                       offset + 3, &eeprom);
3823
3824         /* MCS 7 */
3825         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3826         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3827                                             txpower, delta);
3828         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3829                            TX_PWR_CFG_7_MCS7_CH0, txpower);
3830         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3831                            TX_PWR_CFG_7_MCS7_CH1, txpower);
3832         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3833                            TX_PWR_CFG_7_MCS7_CH2, txpower);
3834
3835         /* MCS 8,9 */
3836         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3837         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3838                                             txpower, delta);
3839         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3840                            TX_PWR_CFG_2_MCS8_CH0, txpower);
3841         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3842                            TX_PWR_CFG_2_MCS8_CH1, txpower);
3843         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3844                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3845
3846         /* MCS 10,11 */
3847         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3848         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3849                                             txpower, delta);
3850         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3851                            TX_PWR_CFG_2_MCS10_CH0, txpower);
3852         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3853                            TX_PWR_CFG_2_MCS10_CH1, txpower);
3854         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3855                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3856
3857         /* MCS 12,13 */
3858         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3859         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3860                                             txpower, delta);
3861         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3862                            TX_PWR_CFG_3_MCS12_CH0, txpower);
3863         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3864                            TX_PWR_CFG_3_MCS12_CH1, txpower);
3865         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3866                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3867
3868         /* read the next four txpower values */
3869         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3870                                       offset + 4, &eeprom);
3871
3872         /* MCS 14 */
3873         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3874         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3875                                             txpower, delta);
3876         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3877                            TX_PWR_CFG_3_MCS14_CH0, txpower);
3878         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3879                            TX_PWR_CFG_3_MCS14_CH1, txpower);
3880         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3881                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3882
3883         /* MCS 15 */
3884         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3885         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3886                                             txpower, delta);
3887         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3888                            TX_PWR_CFG_8_MCS15_CH0, txpower);
3889         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3890                            TX_PWR_CFG_8_MCS15_CH1, txpower);
3891         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3892                            TX_PWR_CFG_8_MCS15_CH2, txpower);
3893
3894         /* MCS 16,17 */
3895         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3896         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3897                                             txpower, delta);
3898         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3899                            TX_PWR_CFG_5_MCS16_CH0, txpower);
3900         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3901                            TX_PWR_CFG_5_MCS16_CH1, txpower);
3902         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3903                            TX_PWR_CFG_5_MCS16_CH2, txpower);
3904
3905         /* MCS 18,19 */
3906         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3907         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3908                                             txpower, delta);
3909         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3910                            TX_PWR_CFG_5_MCS18_CH0, txpower);
3911         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3912                            TX_PWR_CFG_5_MCS18_CH1, txpower);
3913         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3914                            TX_PWR_CFG_5_MCS18_CH2, txpower);
3915
3916         /* read the next four txpower values */
3917         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3918                                       offset + 5, &eeprom);
3919
3920         /* MCS 20,21 */
3921         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3922         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3923                                             txpower, delta);
3924         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3925                            TX_PWR_CFG_6_MCS20_CH0, txpower);
3926         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3927                            TX_PWR_CFG_6_MCS20_CH1, txpower);
3928         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3929                            TX_PWR_CFG_6_MCS20_CH2, txpower);
3930
3931         /* MCS 22 */
3932         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3933         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3934                                             txpower, delta);
3935         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3936                            TX_PWR_CFG_6_MCS22_CH0, txpower);
3937         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3938                            TX_PWR_CFG_6_MCS22_CH1, txpower);
3939         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3940                            TX_PWR_CFG_6_MCS22_CH2, txpower);
3941
3942         /* MCS 23 */
3943         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3944         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3945                                             txpower, delta);
3946         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3947                            TX_PWR_CFG_8_MCS23_CH0, txpower);
3948         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3949                            TX_PWR_CFG_8_MCS23_CH1, txpower);
3950         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3951                            TX_PWR_CFG_8_MCS23_CH2, txpower);
3952
3953         /* read the next four txpower values */
3954         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3955                                       offset + 6, &eeprom);
3956
3957         /* STBC, MCS 0,1 */
3958         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3959         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3960                                             txpower, delta);
3961         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3962                            TX_PWR_CFG_3_STBC0_CH0, txpower);
3963         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3964                            TX_PWR_CFG_3_STBC0_CH1, txpower);
3965         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3966                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3967
3968         /* STBC, MCS 2,3 */
3969         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3970         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3971                                             txpower, delta);
3972         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3973                            TX_PWR_CFG_3_STBC2_CH0, txpower);
3974         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3975                            TX_PWR_CFG_3_STBC2_CH1, txpower);
3976         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3977                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3978
3979         /* STBC, MCS 4,5 */
3980         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3981         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3982                                             txpower, delta);
3983         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3984         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3985         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3986                            txpower);
3987
3988         /* STBC, MCS 6 */
3989         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3990         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3991                                             txpower, delta);
3992         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3993         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3994         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3995                            txpower);
3996
3997         /* read the next four txpower values */
3998         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3999                                       offset + 7, &eeprom);
4000
4001         /* STBC, MCS 7 */
4002         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4003         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4004                                             txpower, delta);
4005         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4006                            TX_PWR_CFG_9_STBC7_CH0, txpower);
4007         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4008                            TX_PWR_CFG_9_STBC7_CH1, txpower);
4009         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4010                            TX_PWR_CFG_9_STBC7_CH2, txpower);
4011
4012         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4013         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4014         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4015         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4016         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4017         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4018         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4019         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4020         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4021         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4022
4023         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4024                               regs[TX_PWR_CFG_0_EXT_IDX]);
4025         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4026                               regs[TX_PWR_CFG_1_EXT_IDX]);
4027         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4028                               regs[TX_PWR_CFG_2_EXT_IDX]);
4029         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4030                               regs[TX_PWR_CFG_3_EXT_IDX]);
4031         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4032                               regs[TX_PWR_CFG_4_EXT_IDX]);
4033
4034         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4035                 rt2x00_dbg(rt2x00dev,
4036                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4037                            (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4038                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4039                                                                 '4' : '2',
4040                            (i > TX_PWR_CFG_9_IDX) ?
4041                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
4042                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4043                            (unsigned long) regs[i]);
4044 }
4045
4046 /*
4047  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4048  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4049  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4050  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4051  * Reference per rate transmit power values are located in the EEPROM at
4052  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4053  * current conditions (i.e. band, bandwidth, temperature, user settings).
4054  */
4055 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4056                                          struct ieee80211_channel *chan,
4057                                          int power_level)
4058 {
4059         u8 txpower, r1;
4060         u16 eeprom;
4061         u32 reg, offset;
4062         int i, is_rate_b, delta, power_ctrl;
4063         enum ieee80211_band band = chan->band;
4064
4065         /*
4066          * Calculate HT40 compensation. For 40MHz we need to add or subtract
4067          * value read from EEPROM (different for 2GHz and for 5GHz).
4068          */
4069         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4070
4071         /*
4072          * Calculate temperature compensation. Depends on measurement of current
4073          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4074          * to temperature or maybe other factors) is smaller or bigger than
4075          * expected. We adjust it, based on TSSI reference and boundaries values
4076          * provided in EEPROM.
4077          */
4078         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4079
4080         /*
4081          * Decrease power according to user settings, on devices with unknown
4082          * maximum tx power. For other devices we take user power_level into
4083          * consideration on rt2800_compensate_txpower().
4084          */
4085         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4086                                               chan->max_power);
4087
4088         /*
4089          * BBP_R1 controls TX power for all rates, it allow to set the following
4090          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4091          *
4092          * TODO: we do not use +6 dBm option to do not increase power beyond
4093          * regulatory limit, however this could be utilized for devices with
4094          * CAPABILITY_POWER_LIMIT.
4095          *
4096          * TODO: add different temperature compensation code for RT3290 & RT5390
4097          * to allow to use BBP_R1 for those chips.
4098          */
4099         if (!rt2x00_rt(rt2x00dev, RT3290) &&
4100             !rt2x00_rt(rt2x00dev, RT5390)) {
4101                 rt2800_bbp_read(rt2x00dev, 1, &r1);
4102                 if (delta <= -12) {
4103                         power_ctrl = 2;
4104                         delta += 12;
4105                 } else if (delta <= -6) {
4106                         power_ctrl = 1;
4107                         delta += 6;
4108                 } else {
4109                         power_ctrl = 0;
4110                 }
4111                 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4112                 rt2800_bbp_write(rt2x00dev, 1, r1);
4113         }
4114
4115         offset = TX_PWR_CFG_0;
4116
4117         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4118                 /* just to be safe */
4119                 if (offset > TX_PWR_CFG_4)
4120                         break;
4121
4122                 rt2800_register_read(rt2x00dev, offset, &reg);
4123
4124                 /* read the next four txpower values */
4125                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4126                                               i, &eeprom);
4127
4128                 is_rate_b = i ? 0 : 1;
4129                 /*
4130                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4131                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4132                  * TX_PWR_CFG_4: unknown
4133                  */
4134                 txpower = rt2x00_get_field16(eeprom,
4135                                              EEPROM_TXPOWER_BYRATE_RATE0);
4136                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4137                                              power_level, txpower, delta);
4138                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4139
4140                 /*
4141                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4142                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4143                  * TX_PWR_CFG_4: unknown
4144                  */
4145                 txpower = rt2x00_get_field16(eeprom,
4146                                              EEPROM_TXPOWER_BYRATE_RATE1);
4147                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4148                                              power_level, txpower, delta);
4149                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4150
4151                 /*
4152                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4153                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4154                  * TX_PWR_CFG_4: unknown
4155                  */
4156                 txpower = rt2x00_get_field16(eeprom,
4157                                              EEPROM_TXPOWER_BYRATE_RATE2);
4158                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4159                                              power_level, txpower, delta);
4160                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4161
4162                 /*
4163                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4164                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4165                  * TX_PWR_CFG_4: unknown
4166                  */
4167                 txpower = rt2x00_get_field16(eeprom,
4168                                              EEPROM_TXPOWER_BYRATE_RATE3);
4169                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4170                                              power_level, txpower, delta);
4171                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4172
4173                 /* read the next four txpower values */
4174                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4175                                               i + 1, &eeprom);
4176
4177                 is_rate_b = 0;
4178                 /*
4179                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4180                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4181                  * TX_PWR_CFG_4: unknown
4182                  */
4183                 txpower = rt2x00_get_field16(eeprom,
4184                                              EEPROM_TXPOWER_BYRATE_RATE0);
4185                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4186                                              power_level, txpower, delta);
4187                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4188
4189                 /*
4190                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4191                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4192                  * TX_PWR_CFG_4: unknown
4193                  */
4194                 txpower = rt2x00_get_field16(eeprom,
4195                                              EEPROM_TXPOWER_BYRATE_RATE1);
4196                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4197                                              power_level, txpower, delta);
4198                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4199
4200                 /*
4201                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4202                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4203                  * TX_PWR_CFG_4: unknown
4204                  */
4205                 txpower = rt2x00_get_field16(eeprom,
4206                                              EEPROM_TXPOWER_BYRATE_RATE2);
4207                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4208                                              power_level, txpower, delta);
4209                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4210
4211                 /*
4212                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4213                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4214                  * TX_PWR_CFG_4: unknown
4215                  */
4216                 txpower = rt2x00_get_field16(eeprom,
4217                                              EEPROM_TXPOWER_BYRATE_RATE3);
4218                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4219                                              power_level, txpower, delta);
4220                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4221
4222                 rt2800_register_write(rt2x00dev, offset, reg);
4223
4224                 /* next TX_PWR_CFG register */
4225                 offset += 4;
4226         }
4227 }
4228
4229 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4230                                   struct ieee80211_channel *chan,
4231                                   int power_level)
4232 {
4233         if (rt2x00_rt(rt2x00dev, RT3593))
4234                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4235         else
4236                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4237 }
4238
4239 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4240 {
4241         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4242                               rt2x00dev->tx_power);
4243 }
4244 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4245
4246 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4247 {
4248         u32     tx_pin;
4249         u8      rfcsr;
4250
4251         /*
4252          * A voltage-controlled oscillator(VCO) is an electronic oscillator
4253          * designed to be controlled in oscillation frequency by a voltage
4254          * input. Maybe the temperature will affect the frequency of
4255          * oscillation to be shifted. The VCO calibration will be called
4256          * periodically to adjust the frequency to be precision.
4257         */
4258
4259         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4260         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4261         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4262
4263         switch (rt2x00dev->chip.rf) {
4264         case RF2020:
4265         case RF3020:
4266         case RF3021:
4267         case RF3022:
4268         case RF3320:
4269         case RF3052:
4270                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4271                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4272                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4273                 break;
4274         case RF3053:
4275         case RF3290:
4276         case RF5360:
4277         case RF5370:
4278         case RF5372:
4279         case RF5390:
4280         case RF5392:
4281                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4282                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4283                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4284                 break;
4285         default:
4286                 return;
4287         }
4288
4289         mdelay(1);
4290
4291         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4292         if (rt2x00dev->rf_channel <= 14) {
4293                 switch (rt2x00dev->default_ant.tx_chain_num) {
4294                 case 3:
4295                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4296                         /* fall through */
4297                 case 2:
4298                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4299                         /* fall through */
4300                 case 1:
4301                 default:
4302                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4303                         break;
4304                 }
4305         } else {
4306                 switch (rt2x00dev->default_ant.tx_chain_num) {
4307                 case 3:
4308                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4309                         /* fall through */
4310                 case 2:
4311                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4312                         /* fall through */
4313                 case 1:
4314                 default:
4315                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4316                         break;
4317                 }
4318         }
4319         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4320
4321 }
4322 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4323
4324 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4325                                       struct rt2x00lib_conf *libconf)
4326 {
4327         u32 reg;
4328
4329         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4330         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4331                            libconf->conf->short_frame_max_tx_count);
4332         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4333                            libconf->conf->long_frame_max_tx_count);
4334         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4335 }
4336
4337 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4338                              struct rt2x00lib_conf *libconf)
4339 {
4340         enum dev_state state =
4341             (libconf->conf->flags & IEEE80211_CONF_PS) ?
4342                 STATE_SLEEP : STATE_AWAKE;
4343         u32 reg;
4344
4345         if (state == STATE_SLEEP) {
4346                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4347
4348                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4349                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4350                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4351                                    libconf->conf->listen_interval - 1);
4352                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4353                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4354
4355                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4356         } else {
4357                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4358                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4359                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4360                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4361                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4362
4363                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4364         }
4365 }
4366
4367 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4368                    struct rt2x00lib_conf *libconf,
4369                    const unsigned int flags)
4370 {
4371         /* Always recalculate LNA gain before changing configuration */
4372         rt2800_config_lna_gain(rt2x00dev, libconf);
4373
4374         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4375                 rt2800_config_channel(rt2x00dev, libconf->conf,
4376                                       &libconf->rf, &libconf->channel);
4377                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4378                                       libconf->conf->power_level);
4379         }
4380         if (flags & IEEE80211_CONF_CHANGE_POWER)
4381                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4382                                       libconf->conf->power_level);
4383         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4384                 rt2800_config_retry_limit(rt2x00dev, libconf);
4385         if (flags & IEEE80211_CONF_CHANGE_PS)
4386                 rt2800_config_ps(rt2x00dev, libconf);
4387 }
4388 EXPORT_SYMBOL_GPL(rt2800_config);
4389
4390 /*
4391  * Link tuning
4392  */
4393 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4394 {
4395         u32 reg;
4396
4397         /*
4398          * Update FCS error count from register.
4399          */
4400         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4401         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4402 }
4403 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4404
4405 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4406 {
4407         u8 vgc;
4408
4409         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4410                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4411                     rt2x00_rt(rt2x00dev, RT3071) ||
4412                     rt2x00_rt(rt2x00dev, RT3090) ||
4413                     rt2x00_rt(rt2x00dev, RT3290) ||
4414                     rt2x00_rt(rt2x00dev, RT3390) ||
4415                     rt2x00_rt(rt2x00dev, RT3572) ||
4416                     rt2x00_rt(rt2x00dev, RT5390) ||
4417                     rt2x00_rt(rt2x00dev, RT5392) ||
4418                     rt2x00_rt(rt2x00dev, RT5592))
4419                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4420                 else
4421                         vgc = 0x2e + rt2x00dev->lna_gain;
4422         } else { /* 5GHZ band */
4423                 if (rt2x00_rt(rt2x00dev, RT3572))
4424                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
4425                 else if (rt2x00_rt(rt2x00dev, RT5592))
4426                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4427                 else {
4428                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4429                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4430                         else
4431                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4432                 }
4433         }
4434
4435         return vgc;
4436 }
4437
4438 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4439                                   struct link_qual *qual, u8 vgc_level)
4440 {
4441         if (qual->vgc_level != vgc_level) {
4442                 if (rt2x00_rt(rt2x00dev, RT5592)) {
4443                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4444                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4445                 } else
4446                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4447                 qual->vgc_level = vgc_level;
4448                 qual->vgc_level_reg = vgc_level;
4449         }
4450 }
4451
4452 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4453 {
4454         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4455 }
4456 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4457
4458 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4459                        const u32 count)
4460 {
4461         u8 vgc;
4462
4463         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4464                 return;
4465         /*
4466          * When RSSI is better then -80 increase VGC level with 0x10, except
4467          * for rt5592 chip.
4468          */
4469
4470         vgc = rt2800_get_default_vgc(rt2x00dev);
4471
4472         if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4473                 vgc += 0x20;
4474         else if (qual->rssi > -80)
4475                 vgc += 0x10;
4476
4477         rt2800_set_vgc(rt2x00dev, qual, vgc);
4478 }
4479 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4480
4481 /*
4482  * Initialization functions.
4483  */
4484 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4485 {
4486         u32 reg;
4487         u16 eeprom;
4488         unsigned int i;
4489         int ret;
4490
4491         rt2800_disable_wpdma(rt2x00dev);
4492
4493         ret = rt2800_drv_init_registers(rt2x00dev);
4494         if (ret)
4495                 return ret;
4496
4497         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4498         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0,
4499                            rt2800_get_beacon_offset(rt2x00dev, 0));
4500         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1,
4501                            rt2800_get_beacon_offset(rt2x00dev, 1));
4502         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2,
4503                            rt2800_get_beacon_offset(rt2x00dev, 2));
4504         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3,
4505                            rt2800_get_beacon_offset(rt2x00dev, 3));
4506         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4507
4508         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4509         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4,
4510                            rt2800_get_beacon_offset(rt2x00dev, 4));
4511         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5,
4512                            rt2800_get_beacon_offset(rt2x00dev, 5));
4513         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6,
4514                            rt2800_get_beacon_offset(rt2x00dev, 6));
4515         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7,
4516                            rt2800_get_beacon_offset(rt2x00dev, 7));
4517         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4518
4519         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4520         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4521
4522         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4523
4524         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4525         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4526         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4527         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4528         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4529         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4530         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4531         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4532
4533         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4534
4535         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4536         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4537         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4538         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4539
4540         if (rt2x00_rt(rt2x00dev, RT3290)) {
4541                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4542                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4543                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4544                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4545                 }
4546
4547                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4548                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4549                         rt2x00_set_field32(&reg, LDO0_EN, 1);
4550                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4551                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4552                 }
4553
4554                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4555                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4556                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4557                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4558                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4559
4560                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4561                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4562                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4563
4564                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4565                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4566                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4567                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4568                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4569                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4570
4571                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4572                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4573                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4574         }
4575
4576         if (rt2x00_rt(rt2x00dev, RT3071) ||
4577             rt2x00_rt(rt2x00dev, RT3090) ||
4578             rt2x00_rt(rt2x00dev, RT3290) ||
4579             rt2x00_rt(rt2x00dev, RT3390)) {
4580
4581                 if (rt2x00_rt(rt2x00dev, RT3290))
4582                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4583                                               0x00000404);
4584                 else
4585                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4586                                               0x00000400);
4587
4588                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4589                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4590                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4591                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4592                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4593                                            &eeprom);
4594                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4595                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4596                                                       0x0000002c);
4597                         else
4598                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4599                                                       0x0000000f);
4600                 } else {
4601                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4602                 }
4603         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4604                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4605
4606                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4607                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4608                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4609                 } else {
4610                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4611                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4612                 }
4613         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4614                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4615                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4616                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4617         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4618                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4619                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4620                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4621         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4622                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4623                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4624         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4625                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4626                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4627                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4628                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4629                                            &eeprom);
4630                         if (rt2x00_get_field16(eeprom,
4631                                                EEPROM_NIC_CONF1_DAC_TEST))
4632                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4633                                                       0x0000001f);
4634                         else
4635                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4636                                                       0x0000000f);
4637                 } else {
4638                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4639                                               0x00000000);
4640                 }
4641         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4642                    rt2x00_rt(rt2x00dev, RT5392) ||
4643                    rt2x00_rt(rt2x00dev, RT5592)) {
4644                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4645                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4646                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4647         } else {
4648                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4649                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4650         }
4651
4652         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4653         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4654         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4655         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4656         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4657         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4658         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4659         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4660         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4661         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4662
4663         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4664         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4665         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4666         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4667         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4668
4669         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4670         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4671         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4672             rt2x00_rt(rt2x00dev, RT2883) ||
4673             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4674                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4675         else
4676                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4677         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4678         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4679         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4680
4681         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4682         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4683         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4684         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4685         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4686         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4687         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4688         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4689         rt2800_register_write(rt2x00dev, LED_CFG, reg);
4690
4691         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4692
4693         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4694         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4695         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4696         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4697         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4698         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4699         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4700         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4701
4702         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4703         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4704         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4705         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4706         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4707         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4708         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4709         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4710         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4711
4712         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4713         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4714         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4715         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4716         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4717         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4718         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4719         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4720         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4721         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4722         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4723         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4724
4725         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4726         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4727         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4728         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4729         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4730         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4731         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4732         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4733         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4734         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4735         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4736         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4737
4738         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4739         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4740         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4741         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4742         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4743         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4744         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4745         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4746         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4747         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4748         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4749         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4750
4751         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4752         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4753         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4754         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4755         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4756         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4757         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4758         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4759         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4760         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4761         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4762         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4763
4764         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4765         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4766         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4767         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4768         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4769         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4770         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4771         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4772         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4773         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4774         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4775         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4776
4777         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4778         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4779         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4780         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4781         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4782         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4783         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4784         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4785         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4786         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4787         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4788         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4789
4790         if (rt2x00_is_usb(rt2x00dev)) {
4791                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4792
4793                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4794                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4795                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4796                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4797                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4798                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4799                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4800                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4801                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4802                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4803                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4804         }
4805
4806         /*
4807          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4808          * although it is reserved.
4809          */
4810         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4811         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4812         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4813         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4814         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4815         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4816         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4817         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4818         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4819         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4820         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4821         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4822
4823         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4824         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4825
4826         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4827         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4828         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4829                            IEEE80211_MAX_RTS_THRESHOLD);
4830         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4831         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4832
4833         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4834
4835         /*
4836          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4837          * time should be set to 16. However, the original Ralink driver uses
4838          * 16 for both and indeed using a value of 10 for CCK SIFS results in
4839          * connection problems with 11g + CTS protection. Hence, use the same
4840          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4841          */
4842         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4843         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4844         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4845         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4846         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4847         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4848         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4849
4850         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4851
4852         /*
4853          * ASIC will keep garbage value after boot, clear encryption keys.
4854          */
4855         for (i = 0; i < 4; i++)
4856                 rt2800_register_write(rt2x00dev,
4857                                          SHARED_KEY_MODE_ENTRY(i), 0);
4858
4859         for (i = 0; i < 256; i++) {
4860                 rt2800_config_wcid(rt2x00dev, NULL, i);
4861                 rt2800_delete_wcid_attr(rt2x00dev, i);
4862                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4863         }
4864
4865         /*
4866          * Clear all beacons
4867          */
4868         for (i = 0; i < 8; i++)
4869                 rt2800_clear_beacon_register(rt2x00dev, i);
4870
4871         if (rt2x00_is_usb(rt2x00dev)) {
4872                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4873                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4874                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4875         } else if (rt2x00_is_pcie(rt2x00dev)) {
4876                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4877                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4878                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4879         }
4880
4881         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4882         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4883         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4884         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4885         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4886         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4887         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4888         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4889         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4890         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4891
4892         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4893         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4894         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4895         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4896         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4897         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4898         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4899         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4900         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4901         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4902
4903         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4904         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4905         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4906         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4907         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4908         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4909         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4910         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4911         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4912         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4913
4914         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4915         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4916         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4917         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4918         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4919         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4920
4921         /*
4922          * Do not force the BA window size, we use the TXWI to set it
4923          */
4924         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4925         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4926         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4927         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4928
4929         /*
4930          * We must clear the error counters.
4931          * These registers are cleared on read,
4932          * so we may pass a useless variable to store the value.
4933          */
4934         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4935         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4936         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4937         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4938         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4939         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4940
4941         /*
4942          * Setup leadtime for pre tbtt interrupt to 6ms
4943          */
4944         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4945         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4946         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4947
4948         /*
4949          * Set up channel statistics timer
4950          */
4951         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4952         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4953         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4954         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4955         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4956         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4957         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4958
4959         return 0;
4960 }
4961
4962 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4963 {
4964         unsigned int i;
4965         u32 reg;
4966
4967         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4968                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4969                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4970                         return 0;
4971
4972                 udelay(REGISTER_BUSY_DELAY);
4973         }
4974
4975         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4976         return -EACCES;
4977 }
4978
4979 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4980 {
4981         unsigned int i;
4982         u8 value;
4983
4984         /*
4985          * BBP was enabled after firmware was loaded,
4986          * but we need to reactivate it now.
4987          */
4988         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4989         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4990         msleep(1);
4991
4992         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4993                 rt2800_bbp_read(rt2x00dev, 0, &value);
4994                 if ((value != 0xff) && (value != 0x00))
4995                         return 0;
4996                 udelay(REGISTER_BUSY_DELAY);
4997         }
4998
4999         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5000         return -EACCES;
5001 }
5002
5003 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5004 {
5005         u8 value;
5006
5007         rt2800_bbp_read(rt2x00dev, 4, &value);
5008         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5009         rt2800_bbp_write(rt2x00dev, 4, value);
5010 }
5011
5012 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5013 {
5014         rt2800_bbp_write(rt2x00dev, 142, 1);
5015         rt2800_bbp_write(rt2x00dev, 143, 57);
5016 }
5017
5018 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5019 {
5020         const u8 glrt_table[] = {
5021                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5022                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5023                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5024                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5025                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5026                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5027                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5028                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5029                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
5030         };
5031         int i;
5032
5033         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5034                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5035                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5036         }
5037 };
5038
5039 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5040 {
5041         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5042         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5043         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5044         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5045         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5046         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5047         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5048         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5049         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5050         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5051         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5052         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5053         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5054         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5055         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5056         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5057 }
5058
5059 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5060 {
5061         u16 eeprom;
5062         u8 value;
5063
5064         rt2800_bbp_read(rt2x00dev, 138, &value);
5065         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5066         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5067                 value |= 0x20;
5068         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5069                 value &= ~0x02;
5070         rt2800_bbp_write(rt2x00dev, 138, value);
5071 }
5072
5073 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5074 {
5075         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5076
5077         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5078         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5079
5080         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5081         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5082
5083         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5084
5085         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5086         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5087
5088         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5089
5090         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5091
5092         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5093
5094         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5095
5096         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5097
5098         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5099
5100         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5101
5102         rt2800_bbp_write(rt2x00dev, 105, 0x01);
5103
5104         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5105 }
5106
5107 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5108 {
5109         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5110         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5111
5112         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5113                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5114                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5115         } else {
5116                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5117                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5118         }
5119
5120         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5121
5122         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5123
5124         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5125
5126         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5127
5128         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5129                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5130         else
5131                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5132
5133         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5134
5135         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5136
5137         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5138
5139         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5140
5141         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5142
5143         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5144 }
5145
5146 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5147 {
5148         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5149         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5150
5151         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5152         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5153
5154         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5155
5156         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5157         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5158         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5159
5160         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5161
5162         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5163
5164         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5165
5166         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5167
5168         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5169
5170         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5171
5172         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5173             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5174             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5175                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5176         else
5177                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5178
5179         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5180
5181         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5182
5183         if (rt2x00_rt(rt2x00dev, RT3071) ||
5184             rt2x00_rt(rt2x00dev, RT3090))
5185                 rt2800_disable_unused_dac_adc(rt2x00dev);
5186 }
5187
5188 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5189 {
5190         u8 value;
5191
5192         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5193
5194         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5195
5196         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5197         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5198
5199         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5200
5201         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5202         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5203         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5204         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5205
5206         rt2800_bbp_write(rt2x00dev, 77, 0x58);
5207
5208         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5209
5210         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5211         rt2800_bbp_write(rt2x00dev, 79, 0x18);
5212         rt2800_bbp_write(rt2x00dev, 80, 0x09);
5213         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5214
5215         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5216
5217         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5218
5219         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5220
5221         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5222
5223         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5224
5225         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5226
5227         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5228
5229         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5230
5231         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5232
5233         rt2800_bbp_write(rt2x00dev, 106, 0x03);
5234
5235         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5236
5237         rt2800_bbp_write(rt2x00dev, 67, 0x24);
5238         rt2800_bbp_write(rt2x00dev, 143, 0x04);
5239         rt2800_bbp_write(rt2x00dev, 142, 0x99);
5240         rt2800_bbp_write(rt2x00dev, 150, 0x30);
5241         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5242         rt2800_bbp_write(rt2x00dev, 152, 0x20);
5243         rt2800_bbp_write(rt2x00dev, 153, 0x34);
5244         rt2800_bbp_write(rt2x00dev, 154, 0x40);
5245         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5246         rt2800_bbp_write(rt2x00dev, 253, 0x04);
5247
5248         rt2800_bbp_read(rt2x00dev, 47, &value);
5249         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5250         rt2800_bbp_write(rt2x00dev, 47, value);
5251
5252         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5253         rt2800_bbp_read(rt2x00dev, 3, &value);
5254         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5255         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5256         rt2800_bbp_write(rt2x00dev, 3, value);
5257 }
5258
5259 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5260 {
5261         rt2800_bbp_write(rt2x00dev, 3, 0x00);
5262         rt2800_bbp_write(rt2x00dev, 4, 0x50);
5263
5264         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5265
5266         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5267
5268         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5269         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5270
5271         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5272
5273         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5274         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5275         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5276         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5277
5278         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5279
5280         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5281
5282         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5283         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5284         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5285
5286         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5287
5288         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5289
5290         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5291
5292         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5293
5294         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5295
5296         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5297
5298         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5299
5300         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5301
5302         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5303
5304         rt2800_bbp_write(rt2x00dev, 105, 0x34);
5305
5306         rt2800_bbp_write(rt2x00dev, 106, 0x05);
5307
5308         rt2800_bbp_write(rt2x00dev, 120, 0x50);
5309
5310         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5311
5312         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5313         /* Set ITxBF timeout to 0x9c40=1000msec */
5314         rt2800_bbp_write(rt2x00dev, 179, 0x02);
5315         rt2800_bbp_write(rt2x00dev, 180, 0x00);
5316         rt2800_bbp_write(rt2x00dev, 182, 0x40);
5317         rt2800_bbp_write(rt2x00dev, 180, 0x01);
5318         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5319         rt2800_bbp_write(rt2x00dev, 179, 0x00);
5320         /* Reprogram the inband interface to put right values in RXWI */
5321         rt2800_bbp_write(rt2x00dev, 142, 0x04);
5322         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5323         rt2800_bbp_write(rt2x00dev, 142, 0x06);
5324         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5325         rt2800_bbp_write(rt2x00dev, 142, 0x07);
5326         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5327         rt2800_bbp_write(rt2x00dev, 142, 0x08);
5328         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5329
5330         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5331 }
5332
5333 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5334 {
5335         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5336         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5337
5338         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5339         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5340
5341         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5342
5343         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5344         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5345         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5346
5347         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5348
5349         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5350
5351         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5352
5353         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5354
5355         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5356
5357         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5358
5359         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5360                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5361         else
5362                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5363
5364         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5365
5366         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5367
5368         rt2800_disable_unused_dac_adc(rt2x00dev);
5369 }
5370
5371 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5372 {
5373         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5374
5375         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5376         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5377
5378         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5379         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5380
5381         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5382
5383         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5384         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5385         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5386
5387         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5388
5389         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5390
5391         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5392
5393         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5394
5395         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5396
5397         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5398
5399         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5400
5401         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5402
5403         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5404
5405         rt2800_disable_unused_dac_adc(rt2x00dev);
5406 }
5407
5408 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5409 {
5410         rt2800_init_bbp_early(rt2x00dev);
5411
5412         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5413         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5414         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5415         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5416
5417         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5418
5419         /* Enable DC filter */
5420         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5421                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5422 }
5423
5424 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5425 {
5426         int ant, div_mode;
5427         u16 eeprom;
5428         u8 value;
5429
5430         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5431
5432         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5433
5434         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5435         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5436
5437         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5438
5439         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5440         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5441         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5442         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5443
5444         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5445
5446         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5447
5448         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5449         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5450         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5451
5452         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5453
5454         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5455
5456         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5457
5458         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5459
5460         if (rt2x00_rt(rt2x00dev, RT5392))
5461                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5462
5463         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5464
5465         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5466
5467         if (rt2x00_rt(rt2x00dev, RT5392)) {
5468                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5469                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5470         }
5471
5472         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5473
5474         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5475
5476         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5477
5478         if (rt2x00_rt(rt2x00dev, RT5390))
5479                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5480         else if (rt2x00_rt(rt2x00dev, RT5392))
5481                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5482         else
5483                 WARN_ON(1);
5484
5485         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5486
5487         if (rt2x00_rt(rt2x00dev, RT5392)) {
5488                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5489                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5490         }
5491
5492         rt2800_disable_unused_dac_adc(rt2x00dev);
5493
5494         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5495         div_mode = rt2x00_get_field16(eeprom,
5496                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
5497         ant = (div_mode == 3) ? 1 : 0;
5498
5499         /* check if this is a Bluetooth combo card */
5500         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5501                 u32 reg;
5502
5503                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5504                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5505                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5506                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5507                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5508                 if (ant == 0)
5509                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5510                 else if (ant == 1)
5511                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5512                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5513         }
5514
5515         /* This chip has hardware antenna diversity*/
5516         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5517                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5518                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5519                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5520         }
5521
5522         rt2800_bbp_read(rt2x00dev, 152, &value);
5523         if (ant == 0)
5524                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5525         else
5526                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5527         rt2800_bbp_write(rt2x00dev, 152, value);
5528
5529         rt2800_init_freq_calibration(rt2x00dev);
5530 }
5531
5532 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5533 {
5534         int ant, div_mode;
5535         u16 eeprom;
5536         u8 value;
5537
5538         rt2800_init_bbp_early(rt2x00dev);
5539
5540         rt2800_bbp_read(rt2x00dev, 105, &value);
5541         rt2x00_set_field8(&value, BBP105_MLD,
5542                           rt2x00dev->default_ant.rx_chain_num == 2);
5543         rt2800_bbp_write(rt2x00dev, 105, value);
5544
5545         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5546
5547         rt2800_bbp_write(rt2x00dev, 20, 0x06);
5548         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5549         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5550         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5551         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5552         rt2800_bbp_write(rt2x00dev, 70, 0x05);
5553         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5554         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5555         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5556         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5557         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5558         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5559         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5560         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5561         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5562         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5563         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5564         rt2800_bbp_write(rt2x00dev, 98, 0x12);
5565         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5566         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5567         /* FIXME BBP105 owerwrite */
5568         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5569         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5570         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5571         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5572         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5573         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5574
5575         /* Initialize GLRT (Generalized Likehood Radio Test) */
5576         rt2800_init_bbp_5592_glrt(rt2x00dev);
5577
5578         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5579
5580         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5581         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5582         ant = (div_mode == 3) ? 1 : 0;
5583         rt2800_bbp_read(rt2x00dev, 152, &value);
5584         if (ant == 0) {
5585                 /* Main antenna */
5586                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5587         } else {
5588                 /* Auxiliary antenna */
5589                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5590         }
5591         rt2800_bbp_write(rt2x00dev, 152, value);
5592
5593         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5594                 rt2800_bbp_read(rt2x00dev, 254, &value);
5595                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5596                 rt2800_bbp_write(rt2x00dev, 254, value);
5597         }
5598
5599         rt2800_init_freq_calibration(rt2x00dev);
5600
5601         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5602         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5603                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5604 }
5605
5606 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5607 {
5608         unsigned int i;
5609         u16 eeprom;
5610         u8 reg_id;
5611         u8 value;
5612
5613         if (rt2800_is_305x_soc(rt2x00dev))
5614                 rt2800_init_bbp_305x_soc(rt2x00dev);
5615
5616         switch (rt2x00dev->chip.rt) {
5617         case RT2860:
5618         case RT2872:
5619         case RT2883:
5620                 rt2800_init_bbp_28xx(rt2x00dev);
5621                 break;
5622         case RT3070:
5623         case RT3071:
5624         case RT3090:
5625                 rt2800_init_bbp_30xx(rt2x00dev);
5626                 break;
5627         case RT3290:
5628                 rt2800_init_bbp_3290(rt2x00dev);
5629                 break;
5630         case RT3352:
5631                 rt2800_init_bbp_3352(rt2x00dev);
5632                 break;
5633         case RT3390:
5634                 rt2800_init_bbp_3390(rt2x00dev);
5635                 break;
5636         case RT3572:
5637                 rt2800_init_bbp_3572(rt2x00dev);
5638                 break;
5639         case RT3593:
5640                 rt2800_init_bbp_3593(rt2x00dev);
5641                 return;
5642         case RT5390:
5643         case RT5392:
5644                 rt2800_init_bbp_53xx(rt2x00dev);
5645                 break;
5646         case RT5592:
5647                 rt2800_init_bbp_5592(rt2x00dev);
5648                 return;
5649         }
5650
5651         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5652                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5653                                               &eeprom);
5654
5655                 if (eeprom != 0xffff && eeprom != 0x0000) {
5656                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5657                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5658                         rt2800_bbp_write(rt2x00dev, reg_id, value);
5659                 }
5660         }
5661 }
5662
5663 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5664 {
5665         u32 reg;
5666
5667         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5668         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5669         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5670 }
5671
5672 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5673                                 u8 filter_target)
5674 {
5675         unsigned int i;
5676         u8 bbp;
5677         u8 rfcsr;
5678         u8 passband;
5679         u8 stopband;
5680         u8 overtuned = 0;
5681         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5682
5683         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5684
5685         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5686         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5687         rt2800_bbp_write(rt2x00dev, 4, bbp);
5688
5689         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5690         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5691         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5692
5693         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5694         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5695         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5696
5697         /*
5698          * Set power & frequency of passband test tone
5699          */
5700         rt2800_bbp_write(rt2x00dev, 24, 0);
5701
5702         for (i = 0; i < 100; i++) {
5703                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5704                 msleep(1);
5705
5706                 rt2800_bbp_read(rt2x00dev, 55, &passband);
5707                 if (passband)
5708                         break;
5709         }
5710
5711         /*
5712          * Set power & frequency of stopband test tone
5713          */
5714         rt2800_bbp_write(rt2x00dev, 24, 0x06);
5715
5716         for (i = 0; i < 100; i++) {
5717                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5718                 msleep(1);
5719
5720                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5721
5722                 if ((passband - stopband) <= filter_target) {
5723                         rfcsr24++;
5724                         overtuned += ((passband - stopband) == filter_target);
5725                 } else
5726                         break;
5727
5728                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5729         }
5730
5731         rfcsr24 -= !!overtuned;
5732
5733         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5734         return rfcsr24;
5735 }
5736
5737 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5738                                        const unsigned int rf_reg)
5739 {
5740         u8 rfcsr;
5741
5742         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5743         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5744         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5745         msleep(1);
5746         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5747         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5748 }
5749
5750 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5751 {
5752         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5753         u8 filter_tgt_bw20;
5754         u8 filter_tgt_bw40;
5755         u8 rfcsr, bbp;
5756
5757         /*
5758          * TODO: sync filter_tgt values with vendor driver
5759          */
5760         if (rt2x00_rt(rt2x00dev, RT3070)) {
5761                 filter_tgt_bw20 = 0x16;
5762                 filter_tgt_bw40 = 0x19;
5763         } else {
5764                 filter_tgt_bw20 = 0x13;
5765                 filter_tgt_bw40 = 0x15;
5766         }
5767
5768         drv_data->calibration_bw20 =
5769                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5770         drv_data->calibration_bw40 =
5771                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5772
5773         /*
5774          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5775          */
5776         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5777         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5778
5779         /*
5780          * Set back to initial state
5781          */
5782         rt2800_bbp_write(rt2x00dev, 24, 0);
5783
5784         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5785         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5786         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5787
5788         /*
5789          * Set BBP back to BW20
5790          */
5791         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5792         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5793         rt2800_bbp_write(rt2x00dev, 4, bbp);
5794 }
5795
5796 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5797 {
5798         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5799         u8 min_gain, rfcsr, bbp;
5800         u16 eeprom;
5801
5802         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5803
5804         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5805         if (rt2x00_rt(rt2x00dev, RT3070) ||
5806             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5807             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5808             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5809                 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5810                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5811         }
5812
5813         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5814         if (drv_data->txmixer_gain_24g >= min_gain) {
5815                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5816                                   drv_data->txmixer_gain_24g);
5817         }
5818
5819         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5820
5821         if (rt2x00_rt(rt2x00dev, RT3090)) {
5822                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5823                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5824                 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5825                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5826                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5827                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5828                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5829                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5830         }
5831
5832         if (rt2x00_rt(rt2x00dev, RT3070)) {
5833                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5834                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5835                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5836                 else
5837                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5838                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5839                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5840                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5841                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5842         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5843                    rt2x00_rt(rt2x00dev, RT3090) ||
5844                    rt2x00_rt(rt2x00dev, RT3390)) {
5845                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5846                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5847                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5848                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5849                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5850                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5851                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5852
5853                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5854                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5855                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5856
5857                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5858                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5859                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5860
5861                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5862                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5863                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5864         }
5865 }
5866
5867 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5868 {
5869         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5870         u8 rfcsr;
5871         u8 tx_gain;
5872
5873         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5874         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5875         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5876
5877         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5878         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5879                                     RFCSR17_TXMIXER_GAIN);
5880         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5881         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5882
5883         rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5884         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5885         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5886
5887         rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5888         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5889         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5890
5891         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5892         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5893         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5894         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5895
5896         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5897         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5898         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5899
5900         /* TODO: enable stream mode */
5901 }
5902
5903 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5904 {
5905         u8 reg;
5906         u16 eeprom;
5907
5908         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5909         rt2800_bbp_read(rt2x00dev, 138, &reg);
5910         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5911         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5912                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5913         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5914                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5915         rt2800_bbp_write(rt2x00dev, 138, reg);
5916
5917         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5918         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5919         rt2800_rfcsr_write(rt2x00dev, 38, reg);
5920
5921         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5922         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5923         rt2800_rfcsr_write(rt2x00dev, 39, reg);
5924
5925         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5926
5927         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5928         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5929         rt2800_rfcsr_write(rt2x00dev, 30, reg);
5930 }
5931
5932 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5933 {
5934         rt2800_rf_init_calibration(rt2x00dev, 30);
5935
5936         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5937         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5938         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5939         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5940         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5941         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5942         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5943         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5944         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5945         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5946         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5947         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5948         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5949         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5950         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5951         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5952         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5953         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5954         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5955         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5956         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5957         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5958         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5959         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5960         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5961         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5962         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5963         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5964         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5965         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5966         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5967         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5968 }
5969
5970 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5971 {
5972         u8 rfcsr;
5973         u16 eeprom;
5974         u32 reg;
5975
5976         /* XXX vendor driver do this only for 3070 */
5977         rt2800_rf_init_calibration(rt2x00dev, 30);
5978
5979         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5980         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5981         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5982         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5983         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5984         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5985         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5986         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5987         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5988         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5989         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5990         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5991         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5992         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5993         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5994         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5995         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5996         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
5997         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
5998
5999         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6000                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6001                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6002                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6003                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6004         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6005                    rt2x00_rt(rt2x00dev, RT3090)) {
6006                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6007
6008                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6009                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6010                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6011
6012                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6013                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6014                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6015                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6016                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6017                                            &eeprom);
6018                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6019                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6020                         else
6021                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6022                 }
6023                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6024
6025                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6026                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6027                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6028         }
6029
6030         rt2800_rx_filter_calibration(rt2x00dev);
6031
6032         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6033             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6034             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6035                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6036
6037         rt2800_led_open_drain_enable(rt2x00dev);
6038         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6039 }
6040
6041 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6042 {
6043         u8 rfcsr;
6044
6045         rt2800_rf_init_calibration(rt2x00dev, 2);
6046
6047         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6048         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6049         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6050         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6051         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6052         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6053         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6054         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6055         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6056         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6057         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6058         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6059         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6060         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6061         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6062         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6063         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6064         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6065         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6066         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6067         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6068         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6069         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6070         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6071         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6072         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6073         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6074         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6075         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6076         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6077         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6078         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6079         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6080         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6081         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6082         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6083         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6084         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6085         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6086         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6087         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6088         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6089         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6090         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6091         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6092         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6093
6094         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6095         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6096         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6097
6098         rt2800_led_open_drain_enable(rt2x00dev);
6099         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6100 }
6101
6102 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6103 {
6104         rt2800_rf_init_calibration(rt2x00dev, 30);
6105
6106         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6107         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6108         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6109         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6110         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6111         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6112         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6113         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6114         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6115         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6116         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6117         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6118         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6119         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6120         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6121         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6122         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6123         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6124         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6125         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6126         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6127         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6128         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6129         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6130         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6131         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6132         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6133         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6134         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6135         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6136         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6137         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6138         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6139         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6140         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6141         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6142         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6143         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6144         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6145         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6146         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6147         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6148         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6149         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6150         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6151         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6152         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6153         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6154         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6155         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6156         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6157         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6158         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6159         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6160         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6161         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6162         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6163         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6164         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6165         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6166         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6167         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6168         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6169
6170         rt2800_rx_filter_calibration(rt2x00dev);
6171         rt2800_led_open_drain_enable(rt2x00dev);
6172         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6173 }
6174
6175 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6176 {
6177         u32 reg;
6178
6179         rt2800_rf_init_calibration(rt2x00dev, 30);
6180
6181         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6182         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6183         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6184         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6185         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6186         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6187         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6188         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6189         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6190         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6191         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6192         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6193         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6194         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6195         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6196         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6197         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6198         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6199         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6200         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6201         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6202         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6203         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6204         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6205         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6206         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6207         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6208         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6209         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6210         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6211         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6212         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6213
6214         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6215         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6216         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6217
6218         rt2800_rx_filter_calibration(rt2x00dev);
6219
6220         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6221                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6222
6223         rt2800_led_open_drain_enable(rt2x00dev);
6224         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6225 }
6226
6227 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6228 {
6229         u8 rfcsr;
6230         u32 reg;
6231
6232         rt2800_rf_init_calibration(rt2x00dev, 30);
6233
6234         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6235         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6236         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6237         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6238         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6239         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6240         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6241         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6242         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6243         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6244         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6245         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6246         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6247         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6248         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6249         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6250         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6251         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6252         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6253         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6254         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6255         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6256         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6257         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6258         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6259         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6260         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6261         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6262         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6263         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6264         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6265
6266         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6267         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6268         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6269
6270         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6271         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6272         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6273         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6274         msleep(1);
6275         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6276         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6277         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6278         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6279
6280         rt2800_rx_filter_calibration(rt2x00dev);
6281         rt2800_led_open_drain_enable(rt2x00dev);
6282         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6283 }
6284
6285 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6286 {
6287         u8 bbp;
6288         bool txbf_enabled = false; /* FIXME */
6289
6290         rt2800_bbp_read(rt2x00dev, 105, &bbp);
6291         if (rt2x00dev->default_ant.rx_chain_num == 1)
6292                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6293         else
6294                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6295         rt2800_bbp_write(rt2x00dev, 105, bbp);
6296
6297         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6298
6299         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6300         rt2800_bbp_write(rt2x00dev, 82, 0x82);
6301         rt2800_bbp_write(rt2x00dev, 106, 0x05);
6302         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6303         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6304         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6305         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6306         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6307
6308         if (txbf_enabled)
6309                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6310         else
6311                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6312
6313         /* SNR mapping */
6314         rt2800_bbp_write(rt2x00dev, 142, 6);
6315         rt2800_bbp_write(rt2x00dev, 143, 160);
6316         rt2800_bbp_write(rt2x00dev, 142, 7);
6317         rt2800_bbp_write(rt2x00dev, 143, 161);
6318         rt2800_bbp_write(rt2x00dev, 142, 8);
6319         rt2800_bbp_write(rt2x00dev, 143, 162);
6320
6321         /* ADC/DAC control */
6322         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6323
6324         /* RX AGC energy lower bound in log2 */
6325         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6326
6327         /* FIXME: BBP 105 owerwrite? */
6328         rt2800_bbp_write(rt2x00dev, 105, 0x04);
6329
6330 }
6331
6332 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6333 {
6334         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6335         u32 reg;
6336         u8 rfcsr;
6337
6338         /* Disable GPIO #4 and #7 function for LAN PE control */
6339         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6340         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6341         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6342         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6343
6344         /* Initialize default register values */
6345         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6346         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6347         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6348         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6349         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6350         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6351         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6352         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6353         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6354         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6355         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6356         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6357         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6358         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6359         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6360         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6361         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6362         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6363         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6364         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6365         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6366         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6367         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6368         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6369         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6370         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6371         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6372         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6373         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6374         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6375         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6376         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6377
6378         /* Initiate calibration */
6379         /* TODO: use rt2800_rf_init_calibration ? */
6380         rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6381         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6382         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6383
6384         rt2800_adjust_freq_offset(rt2x00dev);
6385
6386         rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6387         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6388         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6389
6390         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6391         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6392         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6393         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6394         usleep_range(1000, 1500);
6395         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6396         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6397         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6398
6399         /* Set initial values for RX filter calibration */
6400         drv_data->calibration_bw20 = 0x1f;
6401         drv_data->calibration_bw40 = 0x2f;
6402
6403         /* Save BBP 25 & 26 values for later use in channel switching */
6404         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6405         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6406
6407         rt2800_led_open_drain_enable(rt2x00dev);
6408         rt2800_normal_mode_setup_3593(rt2x00dev);
6409
6410         rt3593_post_bbp_init(rt2x00dev);
6411
6412         /* TODO: enable stream mode support */
6413 }
6414
6415 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6416 {
6417         rt2800_rf_init_calibration(rt2x00dev, 2);
6418
6419         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6420         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6421         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6422         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6423         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6424                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6425         else
6426                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6427         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6428         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6429         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6430         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
6431         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6432         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6433         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6434         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6435         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6436         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6437
6438         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6439         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6440         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6441         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6442         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6443         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6444                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6445         else
6446                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6447         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6448         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6449         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6450         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6451
6452         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6453         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6454         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6455         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6456         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6457         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6458         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6459         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6460         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6461         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6462
6463         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6464                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6465         else
6466                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6467         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6468         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6469         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6470         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6471         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6472         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6473                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6474         else
6475                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6476         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6477         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6478         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6479
6480         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6481         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6482                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6483         else
6484                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6485         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6486         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6487         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6488         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6489         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6490         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6491
6492         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6493         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6494                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6495         else
6496                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6497         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6498         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6499
6500         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6501
6502         rt2800_led_open_drain_enable(rt2x00dev);
6503 }
6504
6505 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6506 {
6507         rt2800_rf_init_calibration(rt2x00dev, 2);
6508
6509         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6510         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6511         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6512         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6513         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6514         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6515         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6516         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6517         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6518         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6519         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6520         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6521         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6522         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6523         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6524         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6525         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6526         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6527         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6528         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6529         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6530         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6531         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6532         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6533         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6534         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6535         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6536         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6537         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6538         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6539         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6540         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6541         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6542         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6543         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6544         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6545         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6546         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6547         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6548         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6549         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6550         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6551         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6552         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6553         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6554         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6555         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6556         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6557         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6558         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6559         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6560         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6561         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6562         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6563         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6564         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6565         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6566         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6567         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6568
6569         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6570
6571         rt2800_led_open_drain_enable(rt2x00dev);
6572 }
6573
6574 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6575 {
6576         rt2800_rf_init_calibration(rt2x00dev, 30);
6577
6578         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6579         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6580         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6581         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6582         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6583         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6584         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6585         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6586         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6587         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6588         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6589         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6590         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6591         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6592         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6593         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6594         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6595         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6596         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6597         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6598         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6599         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6600
6601         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6602         msleep(1);
6603
6604         rt2800_adjust_freq_offset(rt2x00dev);
6605
6606         /* Enable DC filter */
6607         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6608                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6609
6610         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6611
6612         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6613                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6614
6615         rt2800_led_open_drain_enable(rt2x00dev);
6616 }
6617
6618 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6619 {
6620         if (rt2800_is_305x_soc(rt2x00dev)) {
6621                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6622                 return;
6623         }
6624
6625         switch (rt2x00dev->chip.rt) {
6626         case RT3070:
6627         case RT3071:
6628         case RT3090:
6629                 rt2800_init_rfcsr_30xx(rt2x00dev);
6630                 break;
6631         case RT3290:
6632                 rt2800_init_rfcsr_3290(rt2x00dev);
6633                 break;
6634         case RT3352:
6635                 rt2800_init_rfcsr_3352(rt2x00dev);
6636                 break;
6637         case RT3390:
6638                 rt2800_init_rfcsr_3390(rt2x00dev);
6639                 break;
6640         case RT3572:
6641                 rt2800_init_rfcsr_3572(rt2x00dev);
6642                 break;
6643         case RT3593:
6644                 rt2800_init_rfcsr_3593(rt2x00dev);
6645                 break;
6646         case RT5390:
6647                 rt2800_init_rfcsr_5390(rt2x00dev);
6648                 break;
6649         case RT5392:
6650                 rt2800_init_rfcsr_5392(rt2x00dev);
6651                 break;
6652         case RT5592:
6653                 rt2800_init_rfcsr_5592(rt2x00dev);
6654                 break;
6655         }
6656 }
6657
6658 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6659 {
6660         u32 reg;
6661         u16 word;
6662
6663         /*
6664          * Initialize MAC registers.
6665          */
6666         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6667                      rt2800_init_registers(rt2x00dev)))
6668                 return -EIO;
6669
6670         /*
6671          * Wait BBP/RF to wake up.
6672          */
6673         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6674                 return -EIO;
6675
6676         /*
6677          * Send signal during boot time to initialize firmware.
6678          */
6679         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6680         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6681         if (rt2x00_is_usb(rt2x00dev))
6682                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6683         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6684         msleep(1);
6685
6686         /*
6687          * Make sure BBP is up and running.
6688          */
6689         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
6690                 return -EIO;
6691
6692         /*
6693          * Initialize BBP/RF registers.
6694          */
6695         rt2800_init_bbp(rt2x00dev);
6696         rt2800_init_rfcsr(rt2x00dev);
6697
6698         if (rt2x00_is_usb(rt2x00dev) &&
6699             (rt2x00_rt(rt2x00dev, RT3070) ||
6700              rt2x00_rt(rt2x00dev, RT3071) ||
6701              rt2x00_rt(rt2x00dev, RT3572))) {
6702                 udelay(200);
6703                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6704                 udelay(10);
6705         }
6706
6707         /*
6708          * Enable RX.
6709          */
6710         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6711         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6712         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6713         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6714
6715         udelay(50);
6716
6717         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6718         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6719         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6720         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6721         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6722         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6723
6724         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6725         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6726         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6727         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6728
6729         /*
6730          * Initialize LED control
6731          */
6732         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6733         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6734                            word & 0xff, (word >> 8) & 0xff);
6735
6736         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6737         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6738                            word & 0xff, (word >> 8) & 0xff);
6739
6740         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6741         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6742                            word & 0xff, (word >> 8) & 0xff);
6743
6744         return 0;
6745 }
6746 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6747
6748 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6749 {
6750         u32 reg;
6751
6752         rt2800_disable_wpdma(rt2x00dev);
6753
6754         /* Wait for DMA, ignore error */
6755         rt2800_wait_wpdma_ready(rt2x00dev);
6756
6757         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6758         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6759         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6760         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6761 }
6762 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6763
6764 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6765 {
6766         u32 reg;
6767         u16 efuse_ctrl_reg;
6768
6769         if (rt2x00_rt(rt2x00dev, RT3290))
6770                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6771         else
6772                 efuse_ctrl_reg = EFUSE_CTRL;
6773
6774         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6775         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6776 }
6777 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6778
6779 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6780 {
6781         u32 reg;
6782         u16 efuse_ctrl_reg;
6783         u16 efuse_data0_reg;
6784         u16 efuse_data1_reg;
6785         u16 efuse_data2_reg;
6786         u16 efuse_data3_reg;
6787
6788         if (rt2x00_rt(rt2x00dev, RT3290)) {
6789                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6790                 efuse_data0_reg = EFUSE_DATA0_3290;
6791                 efuse_data1_reg = EFUSE_DATA1_3290;
6792                 efuse_data2_reg = EFUSE_DATA2_3290;
6793                 efuse_data3_reg = EFUSE_DATA3_3290;
6794         } else {
6795                 efuse_ctrl_reg = EFUSE_CTRL;
6796                 efuse_data0_reg = EFUSE_DATA0;
6797                 efuse_data1_reg = EFUSE_DATA1;
6798                 efuse_data2_reg = EFUSE_DATA2;
6799                 efuse_data3_reg = EFUSE_DATA3;
6800         }
6801         mutex_lock(&rt2x00dev->csr_mutex);
6802
6803         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6804         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6805         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6806         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6807         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6808
6809         /* Wait until the EEPROM has been loaded */
6810         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6811         /* Apparently the data is read from end to start */
6812         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6813         /* The returned value is in CPU order, but eeprom is le */
6814         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6815         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6816         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6817         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6818         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6819         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6820         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6821
6822         mutex_unlock(&rt2x00dev->csr_mutex);
6823 }
6824
6825 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6826 {
6827         unsigned int i;
6828
6829         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6830                 rt2800_efuse_read(rt2x00dev, i);
6831
6832         return 0;
6833 }
6834 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6835
6836 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6837 {
6838         u16 word;
6839
6840         if (rt2x00_rt(rt2x00dev, RT3593))
6841                 return 0;
6842
6843         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6844         if ((word & 0x00ff) != 0x00ff)
6845                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6846
6847         return 0;
6848 }
6849
6850 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6851 {
6852         u16 word;
6853
6854         if (rt2x00_rt(rt2x00dev, RT3593))
6855                 return 0;
6856
6857         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6858         if ((word & 0x00ff) != 0x00ff)
6859                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6860
6861         return 0;
6862 }
6863
6864 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6865 {
6866         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6867         u16 word;
6868         u8 *mac;
6869         u8 default_lna_gain;
6870         int retval;
6871
6872         /*
6873          * Read the EEPROM.
6874          */
6875         retval = rt2800_read_eeprom(rt2x00dev);
6876         if (retval)
6877                 return retval;
6878
6879         /*
6880          * Start validation of the data that has been read.
6881          */
6882         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6883         if (!is_valid_ether_addr(mac)) {
6884                 eth_random_addr(mac);
6885                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6886         }
6887
6888         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6889         if (word == 0xffff) {
6890                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6891                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6892                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6893                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6894                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6895         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6896                    rt2x00_rt(rt2x00dev, RT2872)) {
6897                 /*
6898                  * There is a max of 2 RX streams for RT28x0 series
6899                  */
6900                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6901                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6902                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6903         }
6904
6905         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6906         if (word == 0xffff) {
6907                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6908                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6909                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6910                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6911                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6912                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6913                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6914                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6915                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6916                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6917                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6918                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6919                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6920                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6921                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6922                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6923                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6924         }
6925
6926         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6927         if ((word & 0x00ff) == 0x00ff) {
6928                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6929                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6930                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6931         }
6932         if ((word & 0xff00) == 0xff00) {
6933                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6934                                    LED_MODE_TXRX_ACTIVITY);
6935                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6936                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6937                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6938                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6939                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6940                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6941         }
6942
6943         /*
6944          * During the LNA validation we are going to use
6945          * lna0 as correct value. Note that EEPROM_LNA
6946          * is never validated.
6947          */
6948         rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6949         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6950
6951         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6952         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6953                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6954         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6955                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6956         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6957
6958         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6959
6960         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6961         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6962                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6963         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6964                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6965                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6966                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6967                                            default_lna_gain);
6968         }
6969         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6970
6971         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
6972
6973         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6974         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6975                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6976         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6977                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6978         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6979
6980         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6981         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6982                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6983         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6984                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6985                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6986                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6987                                            default_lna_gain);
6988         }
6989         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6990
6991         if (rt2x00_rt(rt2x00dev, RT3593)) {
6992                 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6993                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6994                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6995                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6996                                            default_lna_gain);
6997                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6998                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6999                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7000                                            default_lna_gain);
7001                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7002         }
7003
7004         return 0;
7005 }
7006
7007 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
7008 {
7009         u16 value;
7010         u16 eeprom;
7011         u16 rf;
7012
7013         /*
7014          * Read EEPROM word for configuration.
7015          */
7016         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7017
7018         /*
7019          * Identify RF chipset by EEPROM value
7020          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7021          * RT53xx: defined in "EEPROM_CHIP_ID" field
7022          */
7023         if (rt2x00_rt(rt2x00dev, RT3290) ||
7024             rt2x00_rt(rt2x00dev, RT5390) ||
7025             rt2x00_rt(rt2x00dev, RT5392))
7026                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
7027         else
7028                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7029
7030         switch (rf) {
7031         case RF2820:
7032         case RF2850:
7033         case RF2720:
7034         case RF2750:
7035         case RF3020:
7036         case RF2020:
7037         case RF3021:
7038         case RF3022:
7039         case RF3052:
7040         case RF3053:
7041         case RF3290:
7042         case RF3320:
7043         case RF3322:
7044         case RF5360:
7045         case RF5370:
7046         case RF5372:
7047         case RF5390:
7048         case RF5392:
7049         case RF5592:
7050                 break;
7051         default:
7052                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7053                            rf);
7054                 return -ENODEV;
7055         }
7056
7057         rt2x00_set_rf(rt2x00dev, rf);
7058
7059         /*
7060          * Identify default antenna configuration.
7061          */
7062         rt2x00dev->default_ant.tx_chain_num =
7063             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
7064         rt2x00dev->default_ant.rx_chain_num =
7065             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7066
7067         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7068
7069         if (rt2x00_rt(rt2x00dev, RT3070) ||
7070             rt2x00_rt(rt2x00dev, RT3090) ||
7071             rt2x00_rt(rt2x00dev, RT3352) ||
7072             rt2x00_rt(rt2x00dev, RT3390)) {
7073                 value = rt2x00_get_field16(eeprom,
7074                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7075                 switch (value) {
7076                 case 0:
7077                 case 1:
7078                 case 2:
7079                         rt2x00dev->default_ant.tx = ANTENNA_A;
7080                         rt2x00dev->default_ant.rx = ANTENNA_A;
7081                         break;
7082                 case 3:
7083                         rt2x00dev->default_ant.tx = ANTENNA_A;
7084                         rt2x00dev->default_ant.rx = ANTENNA_B;
7085                         break;
7086                 }
7087         } else {
7088                 rt2x00dev->default_ant.tx = ANTENNA_A;
7089                 rt2x00dev->default_ant.rx = ANTENNA_A;
7090         }
7091
7092         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7093                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7094                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7095         }
7096
7097         /*
7098          * Determine external LNA informations.
7099          */
7100         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7101                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7102         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7103                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7104
7105         /*
7106          * Detect if this device has an hardware controlled radio.
7107          */
7108         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7109                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7110
7111         /*
7112          * Detect if this device has Bluetooth co-existence.
7113          */
7114         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7115                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7116
7117         /*
7118          * Read frequency offset and RF programming sequence.
7119          */
7120         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7121         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7122
7123         /*
7124          * Store led settings, for correct led behaviour.
7125          */
7126 #ifdef CONFIG_RT2X00_LIB_LEDS
7127         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7128         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7129         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7130
7131         rt2x00dev->led_mcu_reg = eeprom;
7132 #endif /* CONFIG_RT2X00_LIB_LEDS */
7133
7134         /*
7135          * Check if support EIRP tx power limit feature.
7136          */
7137         rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7138
7139         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7140                                         EIRP_MAX_TX_POWER_LIMIT)
7141                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7142
7143         return 0;
7144 }
7145
7146 /*
7147  * RF value list for rt28xx
7148  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7149  */
7150 static const struct rf_channel rf_vals[] = {
7151         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7152         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7153         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7154         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7155         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7156         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7157         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7158         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7159         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7160         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7161         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7162         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7163         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7164         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7165
7166         /* 802.11 UNI / HyperLan 2 */
7167         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7168         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7169         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7170         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7171         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7172         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7173         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7174         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7175         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7176         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7177         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7178         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7179
7180         /* 802.11 HyperLan 2 */
7181         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7182         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7183         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7184         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7185         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7186         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7187         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7188         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7189         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7190         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7191         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7192         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7193         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7194         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7195         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7196         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7197
7198         /* 802.11 UNII */
7199         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7200         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7201         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7202         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7203         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7204         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7205         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7206         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7207         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7208         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7209         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7210
7211         /* 802.11 Japan */
7212         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7213         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7214         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7215         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7216         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7217         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7218         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7219 };
7220
7221 /*
7222  * RF value list for rt3xxx
7223  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
7224  */
7225 static const struct rf_channel rf_vals_3x[] = {
7226         {1,  241, 2, 2 },
7227         {2,  241, 2, 7 },
7228         {3,  242, 2, 2 },
7229         {4,  242, 2, 7 },
7230         {5,  243, 2, 2 },
7231         {6,  243, 2, 7 },
7232         {7,  244, 2, 2 },
7233         {8,  244, 2, 7 },
7234         {9,  245, 2, 2 },
7235         {10, 245, 2, 7 },
7236         {11, 246, 2, 2 },
7237         {12, 246, 2, 7 },
7238         {13, 247, 2, 2 },
7239         {14, 248, 2, 4 },
7240
7241         /* 802.11 UNI / HyperLan 2 */
7242         {36, 0x56, 0, 4},
7243         {38, 0x56, 0, 6},
7244         {40, 0x56, 0, 8},
7245         {44, 0x57, 0, 0},
7246         {46, 0x57, 0, 2},
7247         {48, 0x57, 0, 4},
7248         {52, 0x57, 0, 8},
7249         {54, 0x57, 0, 10},
7250         {56, 0x58, 0, 0},
7251         {60, 0x58, 0, 4},
7252         {62, 0x58, 0, 6},
7253         {64, 0x58, 0, 8},
7254
7255         /* 802.11 HyperLan 2 */
7256         {100, 0x5b, 0, 8},
7257         {102, 0x5b, 0, 10},
7258         {104, 0x5c, 0, 0},
7259         {108, 0x5c, 0, 4},
7260         {110, 0x5c, 0, 6},
7261         {112, 0x5c, 0, 8},
7262         {116, 0x5d, 0, 0},
7263         {118, 0x5d, 0, 2},
7264         {120, 0x5d, 0, 4},
7265         {124, 0x5d, 0, 8},
7266         {126, 0x5d, 0, 10},
7267         {128, 0x5e, 0, 0},
7268         {132, 0x5e, 0, 4},
7269         {134, 0x5e, 0, 6},
7270         {136, 0x5e, 0, 8},
7271         {140, 0x5f, 0, 0},
7272
7273         /* 802.11 UNII */
7274         {149, 0x5f, 0, 9},
7275         {151, 0x5f, 0, 11},
7276         {153, 0x60, 0, 1},
7277         {157, 0x60, 0, 5},
7278         {159, 0x60, 0, 7},
7279         {161, 0x60, 0, 9},
7280         {165, 0x61, 0, 1},
7281         {167, 0x61, 0, 3},
7282         {169, 0x61, 0, 5},
7283         {171, 0x61, 0, 7},
7284         {173, 0x61, 0, 9},
7285 };
7286
7287 static const struct rf_channel rf_vals_5592_xtal20[] = {
7288         /* Channel, N, K, mod, R */
7289         {1, 482, 4, 10, 3},
7290         {2, 483, 4, 10, 3},
7291         {3, 484, 4, 10, 3},
7292         {4, 485, 4, 10, 3},
7293         {5, 486, 4, 10, 3},
7294         {6, 487, 4, 10, 3},
7295         {7, 488, 4, 10, 3},
7296         {8, 489, 4, 10, 3},
7297         {9, 490, 4, 10, 3},
7298         {10, 491, 4, 10, 3},
7299         {11, 492, 4, 10, 3},
7300         {12, 493, 4, 10, 3},
7301         {13, 494, 4, 10, 3},
7302         {14, 496, 8, 10, 3},
7303         {36, 172, 8, 12, 1},
7304         {38, 173, 0, 12, 1},
7305         {40, 173, 4, 12, 1},
7306         {42, 173, 8, 12, 1},
7307         {44, 174, 0, 12, 1},
7308         {46, 174, 4, 12, 1},
7309         {48, 174, 8, 12, 1},
7310         {50, 175, 0, 12, 1},
7311         {52, 175, 4, 12, 1},
7312         {54, 175, 8, 12, 1},
7313         {56, 176, 0, 12, 1},
7314         {58, 176, 4, 12, 1},
7315         {60, 176, 8, 12, 1},
7316         {62, 177, 0, 12, 1},
7317         {64, 177, 4, 12, 1},
7318         {100, 183, 4, 12, 1},
7319         {102, 183, 8, 12, 1},
7320         {104, 184, 0, 12, 1},
7321         {106, 184, 4, 12, 1},
7322         {108, 184, 8, 12, 1},
7323         {110, 185, 0, 12, 1},
7324         {112, 185, 4, 12, 1},
7325         {114, 185, 8, 12, 1},
7326         {116, 186, 0, 12, 1},
7327         {118, 186, 4, 12, 1},
7328         {120, 186, 8, 12, 1},
7329         {122, 187, 0, 12, 1},
7330         {124, 187, 4, 12, 1},
7331         {126, 187, 8, 12, 1},
7332         {128, 188, 0, 12, 1},
7333         {130, 188, 4, 12, 1},
7334         {132, 188, 8, 12, 1},
7335         {134, 189, 0, 12, 1},
7336         {136, 189, 4, 12, 1},
7337         {138, 189, 8, 12, 1},
7338         {140, 190, 0, 12, 1},
7339         {149, 191, 6, 12, 1},
7340         {151, 191, 10, 12, 1},
7341         {153, 192, 2, 12, 1},
7342         {155, 192, 6, 12, 1},
7343         {157, 192, 10, 12, 1},
7344         {159, 193, 2, 12, 1},
7345         {161, 193, 6, 12, 1},
7346         {165, 194, 2, 12, 1},
7347         {184, 164, 0, 12, 1},
7348         {188, 164, 4, 12, 1},
7349         {192, 165, 8, 12, 1},
7350         {196, 166, 0, 12, 1},
7351 };
7352
7353 static const struct rf_channel rf_vals_5592_xtal40[] = {
7354         /* Channel, N, K, mod, R */
7355         {1, 241, 2, 10, 3},
7356         {2, 241, 7, 10, 3},
7357         {3, 242, 2, 10, 3},
7358         {4, 242, 7, 10, 3},
7359         {5, 243, 2, 10, 3},
7360         {6, 243, 7, 10, 3},
7361         {7, 244, 2, 10, 3},
7362         {8, 244, 7, 10, 3},
7363         {9, 245, 2, 10, 3},
7364         {10, 245, 7, 10, 3},
7365         {11, 246, 2, 10, 3},
7366         {12, 246, 7, 10, 3},
7367         {13, 247, 2, 10, 3},
7368         {14, 248, 4, 10, 3},
7369         {36, 86, 4, 12, 1},
7370         {38, 86, 6, 12, 1},
7371         {40, 86, 8, 12, 1},
7372         {42, 86, 10, 12, 1},
7373         {44, 87, 0, 12, 1},
7374         {46, 87, 2, 12, 1},
7375         {48, 87, 4, 12, 1},
7376         {50, 87, 6, 12, 1},
7377         {52, 87, 8, 12, 1},
7378         {54, 87, 10, 12, 1},
7379         {56, 88, 0, 12, 1},
7380         {58, 88, 2, 12, 1},
7381         {60, 88, 4, 12, 1},
7382         {62, 88, 6, 12, 1},
7383         {64, 88, 8, 12, 1},
7384         {100, 91, 8, 12, 1},
7385         {102, 91, 10, 12, 1},
7386         {104, 92, 0, 12, 1},
7387         {106, 92, 2, 12, 1},
7388         {108, 92, 4, 12, 1},
7389         {110, 92, 6, 12, 1},
7390         {112, 92, 8, 12, 1},
7391         {114, 92, 10, 12, 1},
7392         {116, 93, 0, 12, 1},
7393         {118, 93, 2, 12, 1},
7394         {120, 93, 4, 12, 1},
7395         {122, 93, 6, 12, 1},
7396         {124, 93, 8, 12, 1},
7397         {126, 93, 10, 12, 1},
7398         {128, 94, 0, 12, 1},
7399         {130, 94, 2, 12, 1},
7400         {132, 94, 4, 12, 1},
7401         {134, 94, 6, 12, 1},
7402         {136, 94, 8, 12, 1},
7403         {138, 94, 10, 12, 1},
7404         {140, 95, 0, 12, 1},
7405         {149, 95, 9, 12, 1},
7406         {151, 95, 11, 12, 1},
7407         {153, 96, 1, 12, 1},
7408         {155, 96, 3, 12, 1},
7409         {157, 96, 5, 12, 1},
7410         {159, 96, 7, 12, 1},
7411         {161, 96, 9, 12, 1},
7412         {165, 97, 1, 12, 1},
7413         {184, 82, 0, 12, 1},
7414         {188, 82, 4, 12, 1},
7415         {192, 82, 8, 12, 1},
7416         {196, 83, 0, 12, 1},
7417 };
7418
7419 static const struct rf_channel rf_vals_3053[] = {
7420         /* Channel, N, R, K */
7421         {1, 241, 2, 2},
7422         {2, 241, 2, 7},
7423         {3, 242, 2, 2},
7424         {4, 242, 2, 7},
7425         {5, 243, 2, 2},
7426         {6, 243, 2, 7},
7427         {7, 244, 2, 2},
7428         {8, 244, 2, 7},
7429         {9, 245, 2, 2},
7430         {10, 245, 2, 7},
7431         {11, 246, 2, 2},
7432         {12, 246, 2, 7},
7433         {13, 247, 2, 2},
7434         {14, 248, 2, 4},
7435
7436         {36, 0x56, 0, 4},
7437         {38, 0x56, 0, 6},
7438         {40, 0x56, 0, 8},
7439         {44, 0x57, 0, 0},
7440         {46, 0x57, 0, 2},
7441         {48, 0x57, 0, 4},
7442         {52, 0x57, 0, 8},
7443         {54, 0x57, 0, 10},
7444         {56, 0x58, 0, 0},
7445         {60, 0x58, 0, 4},
7446         {62, 0x58, 0, 6},
7447         {64, 0x58, 0, 8},
7448
7449         {100, 0x5B, 0, 8},
7450         {102, 0x5B, 0, 10},
7451         {104, 0x5C, 0, 0},
7452         {108, 0x5C, 0, 4},
7453         {110, 0x5C, 0, 6},
7454         {112, 0x5C, 0, 8},
7455
7456         /* NOTE: Channel 114 has been removed intentionally.
7457          * The EEPROM contains no TX power values for that,
7458          * and it is disabled in the vendor driver as well.
7459          */
7460
7461         {116, 0x5D, 0, 0},
7462         {118, 0x5D, 0, 2},
7463         {120, 0x5D, 0, 4},
7464         {124, 0x5D, 0, 8},
7465         {126, 0x5D, 0, 10},
7466         {128, 0x5E, 0, 0},
7467         {132, 0x5E, 0, 4},
7468         {134, 0x5E, 0, 6},
7469         {136, 0x5E, 0, 8},
7470         {140, 0x5F, 0, 0},
7471
7472         {149, 0x5F, 0, 9},
7473         {151, 0x5F, 0, 11},
7474         {153, 0x60, 0, 1},
7475         {157, 0x60, 0, 5},
7476         {159, 0x60, 0, 7},
7477         {161, 0x60, 0, 9},
7478         {165, 0x61, 0, 1},
7479         {167, 0x61, 0, 3},
7480         {169, 0x61, 0, 5},
7481         {171, 0x61, 0, 7},
7482         {173, 0x61, 0, 9},
7483 };
7484
7485 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7486 {
7487         struct hw_mode_spec *spec = &rt2x00dev->spec;
7488         struct channel_info *info;
7489         char *default_power1;
7490         char *default_power2;
7491         char *default_power3;
7492         unsigned int i;
7493         u16 eeprom;
7494         u32 reg;
7495
7496         /*
7497          * Disable powersaving as default on PCI devices.
7498          */
7499         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
7500                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7501
7502         /*
7503          * Initialize all hw fields.
7504          */
7505         rt2x00dev->hw->flags =
7506             IEEE80211_HW_SIGNAL_DBM |
7507             IEEE80211_HW_SUPPORTS_PS |
7508             IEEE80211_HW_PS_NULLFUNC_STACK |
7509             IEEE80211_HW_AMPDU_AGGREGATION |
7510             IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7511             IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
7512
7513         /*
7514          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7515          * unless we are capable of sending the buffered frames out after the
7516          * DTIM transmission using rt2x00lib_beacondone. This will send out
7517          * multicast and broadcast traffic immediately instead of buffering it
7518          * infinitly and thus dropping it after some time.
7519          */
7520         if (!rt2x00_is_usb(rt2x00dev))
7521                 rt2x00dev->hw->flags |=
7522                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7523
7524         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7525         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7526                                 rt2800_eeprom_addr(rt2x00dev,
7527                                                    EEPROM_MAC_ADDR_0));
7528
7529         /*
7530          * As rt2800 has a global fallback table we cannot specify
7531          * more then one tx rate per frame but since the hw will
7532          * try several rates (based on the fallback table) we should
7533          * initialize max_report_rates to the maximum number of rates
7534          * we are going to try. Otherwise mac80211 will truncate our
7535          * reported tx rates and the rc algortihm will end up with
7536          * incorrect data.
7537          */
7538         rt2x00dev->hw->max_rates = 1;
7539         rt2x00dev->hw->max_report_rates = 7;
7540         rt2x00dev->hw->max_rate_tries = 1;
7541
7542         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7543
7544         /*
7545          * Initialize hw_mode information.
7546          */
7547         spec->supported_bands = SUPPORT_BAND_2GHZ;
7548         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7549
7550         if (rt2x00_rf(rt2x00dev, RF2820) ||
7551             rt2x00_rf(rt2x00dev, RF2720)) {
7552                 spec->num_channels = 14;
7553                 spec->channels = rf_vals;
7554         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7555                    rt2x00_rf(rt2x00dev, RF2750)) {
7556                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7557                 spec->num_channels = ARRAY_SIZE(rf_vals);
7558                 spec->channels = rf_vals;
7559         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7560                    rt2x00_rf(rt2x00dev, RF2020) ||
7561                    rt2x00_rf(rt2x00dev, RF3021) ||
7562                    rt2x00_rf(rt2x00dev, RF3022) ||
7563                    rt2x00_rf(rt2x00dev, RF3290) ||
7564                    rt2x00_rf(rt2x00dev, RF3320) ||
7565                    rt2x00_rf(rt2x00dev, RF3322) ||
7566                    rt2x00_rf(rt2x00dev, RF5360) ||
7567                    rt2x00_rf(rt2x00dev, RF5370) ||
7568                    rt2x00_rf(rt2x00dev, RF5372) ||
7569                    rt2x00_rf(rt2x00dev, RF5390) ||
7570                    rt2x00_rf(rt2x00dev, RF5392)) {
7571                 spec->num_channels = 14;
7572                 spec->channels = rf_vals_3x;
7573         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7574                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7575                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7576                 spec->channels = rf_vals_3x;
7577         } else if (rt2x00_rf(rt2x00dev, RF3053)) {
7578                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7579                 spec->num_channels = ARRAY_SIZE(rf_vals_3053);
7580                 spec->channels = rf_vals_3053;
7581         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7582                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7583
7584                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7585                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7586                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7587                         spec->channels = rf_vals_5592_xtal40;
7588                 } else {
7589                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7590                         spec->channels = rf_vals_5592_xtal20;
7591                 }
7592         }
7593
7594         if (WARN_ON_ONCE(!spec->channels))
7595                 return -ENODEV;
7596
7597         /*
7598          * Initialize HT information.
7599          */
7600         if (!rt2x00_rf(rt2x00dev, RF2020))
7601                 spec->ht.ht_supported = true;
7602         else
7603                 spec->ht.ht_supported = false;
7604
7605         spec->ht.cap =
7606             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7607             IEEE80211_HT_CAP_GRN_FLD |
7608             IEEE80211_HT_CAP_SGI_20 |
7609             IEEE80211_HT_CAP_SGI_40;
7610
7611         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7612                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7613
7614         spec->ht.cap |=
7615             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7616                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7617
7618         spec->ht.ampdu_factor = 3;
7619         spec->ht.ampdu_density = 4;
7620         spec->ht.mcs.tx_params =
7621             IEEE80211_HT_MCS_TX_DEFINED |
7622             IEEE80211_HT_MCS_TX_RX_DIFF |
7623             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7624                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7625
7626         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7627         case 3:
7628                 spec->ht.mcs.rx_mask[2] = 0xff;
7629         case 2:
7630                 spec->ht.mcs.rx_mask[1] = 0xff;
7631         case 1:
7632                 spec->ht.mcs.rx_mask[0] = 0xff;
7633                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7634                 break;
7635         }
7636
7637         /*
7638          * Create channel information array
7639          */
7640         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7641         if (!info)
7642                 return -ENOMEM;
7643
7644         spec->channels_info = info;
7645
7646         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7647         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7648
7649         if (rt2x00dev->default_ant.tx_chain_num > 2)
7650                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7651                                                     EEPROM_EXT_TXPOWER_BG3);
7652         else
7653                 default_power3 = NULL;
7654
7655         for (i = 0; i < 14; i++) {
7656                 info[i].default_power1 = default_power1[i];
7657                 info[i].default_power2 = default_power2[i];
7658                 if (default_power3)
7659                         info[i].default_power3 = default_power3[i];
7660         }
7661
7662         if (spec->num_channels > 14) {
7663                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7664                                                     EEPROM_TXPOWER_A1);
7665                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7666                                                     EEPROM_TXPOWER_A2);
7667
7668                 if (rt2x00dev->default_ant.tx_chain_num > 2)
7669                         default_power3 =
7670                                 rt2800_eeprom_addr(rt2x00dev,
7671                                                    EEPROM_EXT_TXPOWER_A3);
7672                 else
7673                         default_power3 = NULL;
7674
7675                 for (i = 14; i < spec->num_channels; i++) {
7676                         info[i].default_power1 = default_power1[i - 14];
7677                         info[i].default_power2 = default_power2[i - 14];
7678                         if (default_power3)
7679                                 info[i].default_power3 = default_power3[i - 14];
7680                 }
7681         }
7682
7683         switch (rt2x00dev->chip.rf) {
7684         case RF2020:
7685         case RF3020:
7686         case RF3021:
7687         case RF3022:
7688         case RF3320:
7689         case RF3052:
7690         case RF3053:
7691         case RF3290:
7692         case RF5360:
7693         case RF5370:
7694         case RF5372:
7695         case RF5390:
7696         case RF5392:
7697                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7698                 break;
7699         }
7700
7701         return 0;
7702 }
7703
7704 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7705 {
7706         u32 reg;
7707         u32 rt;
7708         u32 rev;
7709
7710         if (rt2x00_rt(rt2x00dev, RT3290))
7711                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7712         else
7713                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7714
7715         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7716         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7717
7718         switch (rt) {
7719         case RT2860:
7720         case RT2872:
7721         case RT2883:
7722         case RT3070:
7723         case RT3071:
7724         case RT3090:
7725         case RT3290:
7726         case RT3352:
7727         case RT3390:
7728         case RT3572:
7729         case RT3593:
7730         case RT5390:
7731         case RT5392:
7732         case RT5592:
7733                 break;
7734         default:
7735                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7736                            rt, rev);
7737                 return -ENODEV;
7738         }
7739
7740         rt2x00_set_rt(rt2x00dev, rt, rev);
7741
7742         return 0;
7743 }
7744
7745 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7746 {
7747         int retval;
7748         u32 reg;
7749
7750         retval = rt2800_probe_rt(rt2x00dev);
7751         if (retval)
7752                 return retval;
7753
7754         /*
7755          * Allocate eeprom data.
7756          */
7757         retval = rt2800_validate_eeprom(rt2x00dev);
7758         if (retval)
7759                 return retval;
7760
7761         retval = rt2800_init_eeprom(rt2x00dev);
7762         if (retval)
7763                 return retval;
7764
7765         /*
7766          * Enable rfkill polling by setting GPIO direction of the
7767          * rfkill switch GPIO pin correctly.
7768          */
7769         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7770         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7771         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7772
7773         /*
7774          * Initialize hw specifications.
7775          */
7776         retval = rt2800_probe_hw_mode(rt2x00dev);
7777         if (retval)
7778                 return retval;
7779
7780         /*
7781          * Set device capabilities.
7782          */
7783         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7784         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7785         if (!rt2x00_is_usb(rt2x00dev))
7786                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7787
7788         /*
7789          * Set device requirements.
7790          */
7791         if (!rt2x00_is_soc(rt2x00dev))
7792                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7793         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7794         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7795         if (!rt2800_hwcrypt_disabled(rt2x00dev))
7796                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7797         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7798         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7799         if (rt2x00_is_usb(rt2x00dev))
7800                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7801         else {
7802                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7803                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7804         }
7805
7806         /*
7807          * Set the rssi offset.
7808          */
7809         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7810
7811         return 0;
7812 }
7813 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7814
7815 /*
7816  * IEEE80211 stack callback functions.
7817  */
7818 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7819                          u16 *iv16)
7820 {
7821         struct rt2x00_dev *rt2x00dev = hw->priv;
7822         struct mac_iveiv_entry iveiv_entry;
7823         u32 offset;
7824
7825         offset = MAC_IVEIV_ENTRY(hw_key_idx);
7826         rt2800_register_multiread(rt2x00dev, offset,
7827                                       &iveiv_entry, sizeof(iveiv_entry));
7828
7829         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7830         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7831 }
7832 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7833
7834 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7835 {
7836         struct rt2x00_dev *rt2x00dev = hw->priv;
7837         u32 reg;
7838         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7839
7840         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7841         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7842         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7843
7844         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7845         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7846         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7847
7848         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7849         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7850         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7851
7852         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7853         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7854         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7855
7856         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7857         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7858         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7859
7860         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7861         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7862         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7863
7864         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7865         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7866         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7867
7868         return 0;
7869 }
7870 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7871
7872 int rt2800_conf_tx(struct ieee80211_hw *hw,
7873                    struct ieee80211_vif *vif, u16 queue_idx,
7874                    const struct ieee80211_tx_queue_params *params)
7875 {
7876         struct rt2x00_dev *rt2x00dev = hw->priv;
7877         struct data_queue *queue;
7878         struct rt2x00_field32 field;
7879         int retval;
7880         u32 reg;
7881         u32 offset;
7882
7883         /*
7884          * First pass the configuration through rt2x00lib, that will
7885          * update the queue settings and validate the input. After that
7886          * we are free to update the registers based on the value
7887          * in the queue parameter.
7888          */
7889         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7890         if (retval)
7891                 return retval;
7892
7893         /*
7894          * We only need to perform additional register initialization
7895          * for WMM queues/
7896          */
7897         if (queue_idx >= 4)
7898                 return 0;
7899
7900         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7901
7902         /* Update WMM TXOP register */
7903         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7904         field.bit_offset = (queue_idx & 1) * 16;
7905         field.bit_mask = 0xffff << field.bit_offset;
7906
7907         rt2800_register_read(rt2x00dev, offset, &reg);
7908         rt2x00_set_field32(&reg, field, queue->txop);
7909         rt2800_register_write(rt2x00dev, offset, reg);
7910
7911         /* Update WMM registers */
7912         field.bit_offset = queue_idx * 4;
7913         field.bit_mask = 0xf << field.bit_offset;
7914
7915         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7916         rt2x00_set_field32(&reg, field, queue->aifs);
7917         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7918
7919         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7920         rt2x00_set_field32(&reg, field, queue->cw_min);
7921         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7922
7923         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7924         rt2x00_set_field32(&reg, field, queue->cw_max);
7925         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7926
7927         /* Update EDCA registers */
7928         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7929
7930         rt2800_register_read(rt2x00dev, offset, &reg);
7931         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7932         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7933         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7934         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7935         rt2800_register_write(rt2x00dev, offset, reg);
7936
7937         return 0;
7938 }
7939 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7940
7941 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7942 {
7943         struct rt2x00_dev *rt2x00dev = hw->priv;
7944         u64 tsf;
7945         u32 reg;
7946
7947         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7948         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7949         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7950         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7951
7952         return tsf;
7953 }
7954 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7955
7956 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7957                         enum ieee80211_ampdu_mlme_action action,
7958                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7959                         u8 buf_size)
7960 {
7961         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7962         int ret = 0;
7963
7964         /*
7965          * Don't allow aggregation for stations the hardware isn't aware
7966          * of because tx status reports for frames to an unknown station
7967          * always contain wcid=255 and thus we can't distinguish between
7968          * multiple stations which leads to unwanted situations when the
7969          * hw reorders frames due to aggregation.
7970          */
7971         if (sta_priv->wcid < 0)
7972                 return 1;
7973
7974         switch (action) {
7975         case IEEE80211_AMPDU_RX_START:
7976         case IEEE80211_AMPDU_RX_STOP:
7977                 /*
7978                  * The hw itself takes care of setting up BlockAck mechanisms.
7979                  * So, we only have to allow mac80211 to nagotiate a BlockAck
7980                  * agreement. Once that is done, the hw will BlockAck incoming
7981                  * AMPDUs without further setup.
7982                  */
7983                 break;
7984         case IEEE80211_AMPDU_TX_START:
7985                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7986                 break;
7987         case IEEE80211_AMPDU_TX_STOP_CONT:
7988         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7989         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7990                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7991                 break;
7992         case IEEE80211_AMPDU_TX_OPERATIONAL:
7993                 break;
7994         default:
7995                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7996                             "Unknown AMPDU action\n");
7997         }
7998
7999         return ret;
8000 }
8001 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
8002
8003 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
8004                       struct survey_info *survey)
8005 {
8006         struct rt2x00_dev *rt2x00dev = hw->priv;
8007         struct ieee80211_conf *conf = &hw->conf;
8008         u32 idle, busy, busy_ext;
8009
8010         if (idx != 0)
8011                 return -ENOENT;
8012
8013         survey->channel = conf->chandef.chan;
8014
8015         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8016         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8017         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8018
8019         if (idle || busy) {
8020                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
8021                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
8022                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
8023
8024                 survey->channel_time = (idle + busy) / 1000;
8025                 survey->channel_time_busy = busy / 1000;
8026                 survey->channel_time_ext_busy = busy_ext / 1000;
8027         }
8028
8029         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8030                 survey->filled |= SURVEY_INFO_IN_USE;
8031
8032         return 0;
8033
8034 }
8035 EXPORT_SYMBOL_GPL(rt2800_get_survey);
8036
8037 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8038 MODULE_VERSION(DRV_VERSION);
8039 MODULE_DESCRIPTION("Ralink RT2800 library");
8040 MODULE_LICENSE("GPL");