drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 225 {
 226         u32 reg;
 227         int i, count;
 228
 229         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 230         if (rt2x00_get_field32(reg, WLAN_EN))
 231                 return 0;
 232
 233         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 234         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 235         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 236         rt2x00_set_field32(&reg, WLAN_EN, 1);
 237         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 238
 239         udelay(REGISTER_BUSY_DELAY);
 240
 241         count = 0;
 242         do {
 243                 /*
 244                  * Check PLL_LD & XTAL_RDY.
 245                  */
 246                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 247                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 248                         if (rt2x00_get_field32(reg, PLL_LD) &&
 249                             rt2x00_get_field32(reg, XTAL_RDY))
 250                                 break;
 251                         udelay(REGISTER_BUSY_DELAY);
 252                 }
 253
 254                 if (i >= REGISTER_BUSY_COUNT) {
 255
 256                         if (count >= 10)
 257                                 return -EIO;
 258
 259                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 260                         udelay(REGISTER_BUSY_DELAY);
 261                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 262                         udelay(REGISTER_BUSY_DELAY);
 263                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 264                         udelay(REGISTER_BUSY_DELAY);
 265                         count++;
 266                 } else {
 267                         count = 0;
 268                 }
 269
 270                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 271                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 272                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 273                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 274                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 275                 udelay(10);
 276                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 277                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 278                 udelay(10);
 279                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 280         } while (count != 0);
 281
 282         return 0;
 283 }
 284
 285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 286                         const u8 command, const u8 token,
 287                         const u8 arg0, const u8 arg1)
 288 {
 289         u32 reg;
 290
 291         /*
 292          * SOC devices don't support MCU requests.
 293          */
 294         if (rt2x00_is_soc(rt2x00dev))
 295                 return;
 296
 297         mutex_lock(&rt2x00dev->csr_mutex);
 298
 299         /*
 300          * Wait until the MCU becomes available, afterwards we
 301          * can safely write the new data into the register.
 302          */
 303         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 304                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 305                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 306                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 307                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 308                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 309
 310                 reg = 0;
 311                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 312                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 313         }
 314
 315         mutex_unlock(&rt2x00dev->csr_mutex);
 316 }
 317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 318
 319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 320 {
 321         unsigned int i = 0;
 322         u32 reg;
 323
 324         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 325                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 326                 if (reg && reg != ~0)
 327                         return 0;
 328                 msleep(1);
 329         }
 330
 331         ERROR(rt2x00dev, "Unstable hardware.\n");
 332         return -EBUSY;
 333 }
 334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 335
 336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 337 {
 338         unsigned int i;
 339         u32 reg;
 340
 341         /*
 342          * Some devices are really slow to respond here. Wait a whole second
 343          * before timing out.
 344          */
 345         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 346                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 347                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 348                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 349                         return 0;
 350
 351                 msleep(10);
 352         }
 353
 354         ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
 355         return -EACCES;
 356 }
 357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 358
 359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 360 {
 361         u32 reg;
 362
 363         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 364         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 365         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 366         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 367         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 368         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 369         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 370 }
 371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 372
 373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 374 {
 375         u16 fw_crc;
 376         u16 crc;
 377
 378         /*
 379          * The last 2 bytes in the firmware array are the crc checksum itself,
 380          * this means that we should never pass those 2 bytes to the crc
 381          * algorithm.
 382          */
 383         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 384
 385         /*
 386          * Use the crc ccitt algorithm.
 387          * This will return the same value as the legacy driver which
 388          * used bit ordering reversion on the both the firmware bytes
 389          * before input input as well as on the final output.
 390          * Obviously using crc ccitt directly is much more efficient.
 391          */
 392         crc = crc_ccitt(~0, data, len - 2);
 393
 394         /*
 395          * There is a small difference between the crc-itu-t + bitrev and
 396          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 397          * will be swapped, use swab16 to convert the crc to the correct
 398          * value.
 399          */
 400         crc = swab16(crc);
 401
 402         return fw_crc == crc;
 403 }
 404
 405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 406                           const u8 *data, const size_t len)
 407 {
 408         size_t offset = 0;
 409         size_t fw_len;
 410         bool multiple;
 411
 412         /*
 413          * PCI(e) & SOC devices require firmware with a length
 414          * of 8kb. USB devices require firmware files with a length
 415          * of 4kb. Certain USB chipsets however require different firmware,
 416          * which Ralink only provides attached to the original firmware
 417          * file. Thus for USB devices, firmware files have a length
 418          * which is a multiple of 4kb. The firmware for rt3290 chip also
 419          * have a length which is a multiple of 4kb.
 420          */
 421         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 422                 fw_len = 4096;
 423         else
 424                 fw_len = 8192;
 425
 426         multiple = true;
 427         /*
 428          * Validate the firmware length
 429          */
 430         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 431                 return FW_BAD_LENGTH;
 432
 433         /*
 434          * Check if the chipset requires one of the upper parts
 435          * of the firmware.
 436          */
 437         if (rt2x00_is_usb(rt2x00dev) &&
 438             !rt2x00_rt(rt2x00dev, RT2860) &&
 439             !rt2x00_rt(rt2x00dev, RT2872) &&
 440             !rt2x00_rt(rt2x00dev, RT3070) &&
 441             ((len / fw_len) == 1))
 442                 return FW_BAD_VERSION;
 443
 444         /*
 445          * 8kb firmware files must be checked as if it were
 446          * 2 separate firmware files.
 447          */
 448         while (offset < len) {
 449                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 450                         return FW_BAD_CRC;
 451
 452                 offset += fw_len;
 453         }
 454
 455         return FW_OK;
 456 }
 457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 458
 459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 460                          const u8 *data, const size_t len)
 461 {
 462         unsigned int i;
 463         u32 reg;
 464         int retval;
 465
 466         if (rt2x00_rt(rt2x00dev, RT3290)) {
 467                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 468                 if (retval)
 469                         return -EBUSY;
 470         }
 471
 472         /*
 473          * If driver doesn't wake up firmware here,
 474          * rt2800_load_firmware will hang forever when interface is up again.
 475          */
 476         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 477
 478         /*
 479          * Wait for stable hardware.
 480          */
 481         if (rt2800_wait_csr_ready(rt2x00dev))
 482                 return -EBUSY;
 483
 484         if (rt2x00_is_pci(rt2x00dev)) {
 485                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 486                     rt2x00_rt(rt2x00dev, RT3572) ||
 487                     rt2x00_rt(rt2x00dev, RT5390) ||
 488                     rt2x00_rt(rt2x00dev, RT5392)) {
 489                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 490                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 491                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 492                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 493                 }
 494                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 495         }
 496
 497         rt2800_disable_wpdma(rt2x00dev);
 498
 499         /*
 500          * Write firmware to the device.
 501          */
 502         rt2800_drv_write_firmware(rt2x00dev, data, len);
 503
 504         /*
 505          * Wait for device to stabilize.
 506          */
 507         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 508                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 509                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 510                         break;
 511                 msleep(1);
 512         }
 513
 514         if (i == REGISTER_BUSY_COUNT) {
 515                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 516                 return -EBUSY;
 517         }
 518
 519         /*
 520          * Disable DMA, will be reenabled later when enabling
 521          * the radio.
 522          */
 523         rt2800_disable_wpdma(rt2x00dev);
 524
 525         /*
 526          * Initialize firmware.
 527          */
 528         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 529         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 530         if (rt2x00_is_usb(rt2x00dev)) {
 531                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 532                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 533         }
 534         msleep(1);
 535
 536         return 0;
 537 }
 538 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 539
 540 void rt2800_write_tx_data(struct queue_entry *entry,
 541                           struct txentry_desc *txdesc)
 542 {
 543         __le32 *txwi = rt2800_drv_get_txwi(entry);
 544         u32 word;
 545
 546         /*
 547          * Initialize TX Info descriptor
 548          */
 549         rt2x00_desc_read(txwi, 0, &word);
 550         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 551                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 552         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 553                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 554         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 555         rt2x00_set_field32(&word, TXWI_W0_TS,
 556                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 557         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 558                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 559         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 560                            txdesc->u.ht.mpdu_density);
 561         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 562         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 563         rt2x00_set_field32(&word, TXWI_W0_BW,
 564                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 565         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 566                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 567         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 568         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 569         rt2x00_desc_write(txwi, 0, word);
 570
 571         rt2x00_desc_read(txwi, 1, &word);
 572         rt2x00_set_field32(&word, TXWI_W1_ACK,
 573                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 574         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 575                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 576         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 577         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 578                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 579                            txdesc->key_idx : txdesc->u.ht.wcid);
 580         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 581                            txdesc->length);
 582         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 583         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 584         rt2x00_desc_write(txwi, 1, word);
 585
 586         /*
 587          * Always write 0 to IV/EIV fields, hardware will insert the IV
 588          * from the IVEIV register when TXD_W3_WIV is set to 0.
 589          * When TXD_W3_WIV is set to 1 it will use the IV data
 590          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 591          * crypto entry in the registers should be used to encrypt the frame.
 592          */
 593         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 594         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 595 }
 596 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 597
 598 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 599 {
 600         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 601         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 602         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 603         u16 eeprom;
 604         u8 offset0;
 605         u8 offset1;
 606         u8 offset2;
 607
 608         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 609                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 610                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 611                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 612                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 613                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 614         } else {
 615                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 616                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 617                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 618                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 619                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 620         }
 621
 622         /*
 623          * Convert the value from the descriptor into the RSSI value
 624          * If the value in the descriptor is 0, it is considered invalid
 625          * and the default (extremely low) rssi value is assumed
 626          */
 627         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 628         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 629         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 630
 631         /*
 632          * mac80211 only accepts a single RSSI value. Calculating the
 633          * average doesn't deliver a fair answer either since -60:-60 would
 634          * be considered equally good as -50:-70 while the second is the one
 635          * which gives less energy...
 636          */
 637         rssi0 = max(rssi0, rssi1);
 638         return (int)max(rssi0, rssi2);
 639 }
 640
 641 void rt2800_process_rxwi(struct queue_entry *entry,
 642                          struct rxdone_entry_desc *rxdesc)
 643 {
 644         __le32 *rxwi = (__le32 *) entry->skb->data;
 645         u32 word;
 646
 647         rt2x00_desc_read(rxwi, 0, &word);
 648
 649         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 650         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 651
 652         rt2x00_desc_read(rxwi, 1, &word);
 653
 654         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 655                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 656
 657         if (rt2x00_get_field32(word, RXWI_W1_BW))
 658                 rxdesc->flags |= RX_FLAG_40MHZ;
 659
 660         /*
 661          * Detect RX rate, always use MCS as signal type.
 662          */
 663         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 664         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 665         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 666
 667         /*
 668          * Mask of 0x8 bit to remove the short preamble flag.
 669          */
 670         if (rxdesc->rate_mode == RATE_MODE_CCK)
 671                 rxdesc->signal &= ~0x8;
 672
 673         rt2x00_desc_read(rxwi, 2, &word);
 674
 675         /*
 676          * Convert descriptor AGC value to RSSI value.
 677          */
 678         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 679 }
 680 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 681
 682 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 683 {
 684         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 685         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 686         struct txdone_entry_desc txdesc;
 687         u32 word;
 688         u16 mcs, real_mcs;
 689         int aggr, ampdu;
 690
 691         /*
 692          * Obtain the status about this packet.
 693          */
 694         txdesc.flags = 0;
 695         rt2x00_desc_read(txwi, 0, &word);
 696
 697         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 698         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 699
 700         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 701         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 702
 703         /*
 704          * If a frame was meant to be sent as a single non-aggregated MPDU
 705          * but ended up in an aggregate the used tx rate doesn't correlate
 706          * with the one specified in the TXWI as the whole aggregate is sent
 707          * with the same rate.
 708          *
 709          * For example: two frames are sent to rt2x00, the first one sets
 710          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 711          * and requests MCS15. If the hw aggregates both frames into one
 712          * AMDPU the tx status for both frames will contain MCS7 although
 713          * the frame was sent successfully.
 714          *
 715          * Hence, replace the requested rate with the real tx rate to not
 716          * confuse the rate control algortihm by providing clearly wrong
 717          * data.
 718          */
 719         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 720                 skbdesc->tx_rate_idx = real_mcs;
 721                 mcs = real_mcs;
 722         }
 723
 724         if (aggr == 1 || ampdu == 1)
 725                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 726
 727         /*
 728          * Ralink has a retry mechanism using a global fallback
 729          * table. We setup this fallback table to try the immediate
 730          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 731          * always contains the MCS used for the last transmission, be
 732          * it successful or not.
 733          */
 734         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 735                 /*
 736                  * Transmission succeeded. The number of retries is
 737                  * mcs - real_mcs
 738                  */
 739                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 740                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 741         } else {
 742                 /*
 743                  * Transmission failed. The number of retries is
 744                  * always 7 in this case (for a total number of 8
 745                  * frames sent).
 746                  */
 747                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 748                 txdesc.retry = rt2x00dev->long_retry;
 749         }
 750
 751         /*
 752          * the frame was retried at least once
 753          * -> hw used fallback rates
 754          */
 755         if (txdesc.retry)
 756                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 757
 758         rt2x00lib_txdone(entry, &txdesc);
 759 }
 760 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 761
 762 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 763 {
 764         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 765         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 766         unsigned int beacon_base;
 767         unsigned int padding_len;
 768         u32 orig_reg, reg;
 769
 770         /*
 771          * Disable beaconing while we are reloading the beacon data,
 772          * otherwise we might be sending out invalid data.
 773          */
 774         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 775         orig_reg = reg;
 776         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 777         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 778
 779         /*
 780          * Add space for the TXWI in front of the skb.
 781          */
 782         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 783
 784         /*
 785          * Register descriptor details in skb frame descriptor.
 786          */
 787         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 788         skbdesc->desc = entry->skb->data;
 789         skbdesc->desc_len = TXWI_DESC_SIZE;
 790
 791         /*
 792          * Add the TXWI for the beacon to the skb.
 793          */
 794         rt2800_write_tx_data(entry, txdesc);
 795
 796         /*
 797          * Dump beacon to userspace through debugfs.
 798          */
 799         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 800
 801         /*
 802          * Write entire beacon with TXWI and padding to register.
 803          */
 804         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 805         if (padding_len && skb_pad(entry->skb, padding_len)) {
 806                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 807                 /* skb freed by skb_pad() on failure */
 808                 entry->skb = NULL;
 809                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 810                 return;
 811         }
 812
 813         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 814         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 815                                    entry->skb->len + padding_len);
 816
 817         /*
 818          * Enable beaconing again.
 819          */
 820         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 821         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 822
 823         /*
 824          * Clean up beacon skb.
 825          */
 826         dev_kfree_skb_any(entry->skb);
 827         entry->skb = NULL;
 828 }
 829 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 830
 831 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 832                                                 unsigned int beacon_base)
 833 {
 834         int i;
 835
 836         /*
 837          * For the Beacon base registers we only need to clear
 838          * the whole TXWI which (when set to 0) will invalidate
 839          * the entire beacon.
 840          */
 841         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 842                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 843 }
 844
 845 void rt2800_clear_beacon(struct queue_entry *entry)
 846 {
 847         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 848         u32 reg;
 849
 850         /*
 851          * Disable beaconing while we are reloading the beacon data,
 852          * otherwise we might be sending out invalid data.
 853          */
 854         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 855         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 856         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 857
 858         /*
 859          * Clear beacon.
 860          */
 861         rt2800_clear_beacon_register(rt2x00dev,
 862                                      HW_BEACON_OFFSET(entry->entry_idx));
 863
 864         /*
 865          * Enabled beaconing again.
 866          */
 867         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 868         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 869 }
 870 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 871
 872 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 873 const struct rt2x00debug rt2800_rt2x00debug = {
 874         .owner  = THIS_MODULE,
 875         .csr    = {
 876                 .read           = rt2800_register_read,
 877                 .write          = rt2800_register_write,
 878                 .flags          = RT2X00DEBUGFS_OFFSET,
 879                 .word_base      = CSR_REG_BASE,
 880                 .word_size      = sizeof(u32),
 881                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 882         },
 883         .eeprom = {
 884                 .read           = rt2x00_eeprom_read,
 885                 .write          = rt2x00_eeprom_write,
 886                 .word_base      = EEPROM_BASE,
 887                 .word_size      = sizeof(u16),
 888                 .word_count     = EEPROM_SIZE / sizeof(u16),
 889         },
 890         .bbp    = {
 891                 .read           = rt2800_bbp_read,
 892                 .write          = rt2800_bbp_write,
 893                 .word_base      = BBP_BASE,
 894                 .word_size      = sizeof(u8),
 895                 .word_count     = BBP_SIZE / sizeof(u8),
 896         },
 897         .rf     = {
 898                 .read           = rt2x00_rf_read,
 899                 .write          = rt2800_rf_write,
 900                 .word_base      = RF_BASE,
 901                 .word_size      = sizeof(u32),
 902                 .word_count     = RF_SIZE / sizeof(u32),
 903         },
 904         .rfcsr  = {
 905                 .read           = rt2800_rfcsr_read,
 906                 .write          = rt2800_rfcsr_write,
 907                 .word_base      = RFCSR_BASE,
 908                 .word_size      = sizeof(u8),
 909                 .word_count     = RFCSR_SIZE / sizeof(u8),
 910         },
 911 };
 912 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 913 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 914
 915 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 916 {
 917         u32 reg;
 918
 919         if (rt2x00_rt(rt2x00dev, RT3290)) {
 920                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 921                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
 922         } else {
 923                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
 924                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
 925         }
 926 }
 927 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 928
 929 #ifdef CONFIG_RT2X00_LIB_LEDS
 930 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 931                                   enum led_brightness brightness)
 932 {
 933         struct rt2x00_led *led =
 934             container_of(led_cdev, struct rt2x00_led, led_dev);
 935         unsigned int enabled = brightness != LED_OFF;
 936         unsigned int bg_mode =
 937             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 938         unsigned int polarity =
 939                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 940                                    EEPROM_FREQ_LED_POLARITY);
 941         unsigned int ledmode =
 942                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 943                                    EEPROM_FREQ_LED_MODE);
 944         u32 reg;
 945
 946         /* Check for SoC (SOC devices don't support MCU requests) */
 947         if (rt2x00_is_soc(led->rt2x00dev)) {
 948                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 949
 950                 /* Set LED Polarity */
 951                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 952
 953                 /* Set LED Mode */
 954                 if (led->type == LED_TYPE_RADIO) {
 955                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 956                                            enabled ? 3 : 0);
 957                 } else if (led->type == LED_TYPE_ASSOC) {
 958                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 959                                            enabled ? 3 : 0);
 960                 } else if (led->type == LED_TYPE_QUALITY) {
 961                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 962                                            enabled ? 3 : 0);
 963                 }
 964
 965                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 966
 967         } else {
 968                 if (led->type == LED_TYPE_RADIO) {
 969                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 970                                               enabled ? 0x20 : 0);
 971                 } else if (led->type == LED_TYPE_ASSOC) {
 972                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 973                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 974                 } else if (led->type == LED_TYPE_QUALITY) {
 975                         /*
 976                          * The brightness is divided into 6 levels (0 - 5),
 977                          * The specs tell us the following levels:
 978                          *      0, 1 ,3, 7, 15, 31
 979                          * to determine the level in a simple way we can simply
 980                          * work with bitshifting:
 981                          *      (1 << level) - 1
 982                          */
 983                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 984                                               (1 << brightness / (LED_FULL / 6)) - 1,
 985                                               polarity);
 986                 }
 987         }
 988 }
 989
 990 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 991                      struct rt2x00_led *led, enum led_type type)
 992 {
 993         led->rt2x00dev = rt2x00dev;
 994         led->type = type;
 995         led->led_dev.brightness_set = rt2800_brightness_set;
 996         led->flags = LED_INITIALIZED;
 997 }
 998 #endif /* CONFIG_RT2X00_LIB_LEDS */
 999
1000 /*
1001  * Configuration handlers.
1002  */
1003 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1004                                const u8 *address,
1005                                int wcid)
1006 {
1007         struct mac_wcid_entry wcid_entry;
1008         u32 offset;
1009
1010         offset = MAC_WCID_ENTRY(wcid);
1011
1012         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1013         if (address)
1014                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1015
1016         rt2800_register_multiwrite(rt2x00dev, offset,
1017                                       &wcid_entry, sizeof(wcid_entry));
1018 }
1019
1020 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1021 {
1022         u32 offset;
1023         offset = MAC_WCID_ATTR_ENTRY(wcid);
1024         rt2800_register_write(rt2x00dev, offset, 0);
1025 }
1026
1027 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1028                                            int wcid, u32 bssidx)
1029 {
1030         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1031         u32 reg;
1032
1033         /*
1034          * The BSS Idx numbers is split in a main value of 3 bits,
1035          * and a extended field for adding one additional bit to the value.
1036          */
1037         rt2800_register_read(rt2x00dev, offset, &reg);
1038         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1039         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1040                            (bssidx & 0x8) >> 3);
1041         rt2800_register_write(rt2x00dev, offset, reg);
1042 }
1043
1044 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1045                                            struct rt2x00lib_crypto *crypto,
1046                                            struct ieee80211_key_conf *key)
1047 {
1048         struct mac_iveiv_entry iveiv_entry;
1049         u32 offset;
1050         u32 reg;
1051
1052         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1053
1054         if (crypto->cmd == SET_KEY) {
1055                 rt2800_register_read(rt2x00dev, offset, &reg);
1056                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1057                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1058                 /*
1059                  * Both the cipher as the BSS Idx numbers are split in a main
1060                  * value of 3 bits, and a extended field for adding one additional
1061                  * bit to the value.
1062                  */
1063                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1064                                    (crypto->cipher & 0x7));
1065                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1066                                    (crypto->cipher & 0x8) >> 3);
1067                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1068                 rt2800_register_write(rt2x00dev, offset, reg);
1069         } else {
1070                 /* Delete the cipher without touching the bssidx */
1071                 rt2800_register_read(rt2x00dev, offset, &reg);
1072                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1073                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1074                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1075                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1076                 rt2800_register_write(rt2x00dev, offset, reg);
1077         }
1078
1079         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1080
1081         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1082         if ((crypto->cipher == CIPHER_TKIP) ||
1083             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1084             (crypto->cipher == CIPHER_AES))
1085                 iveiv_entry.iv[3] |= 0x20;
1086         iveiv_entry.iv[3] |= key->keyidx << 6;
1087         rt2800_register_multiwrite(rt2x00dev, offset,
1088                                       &iveiv_entry, sizeof(iveiv_entry));
1089 }
1090
1091 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1092                              struct rt2x00lib_crypto *crypto,
1093                              struct ieee80211_key_conf *key)
1094 {
1095         struct hw_key_entry key_entry;
1096         struct rt2x00_field32 field;
1097         u32 offset;
1098         u32 reg;
1099
1100         if (crypto->cmd == SET_KEY) {
1101                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1102
1103                 memcpy(key_entry.key, crypto->key,
1104                        sizeof(key_entry.key));
1105                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1106                        sizeof(key_entry.tx_mic));
1107                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1108                        sizeof(key_entry.rx_mic));
1109
1110                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1111                 rt2800_register_multiwrite(rt2x00dev, offset,
1112                                               &key_entry, sizeof(key_entry));
1113         }
1114
1115         /*
1116          * The cipher types are stored over multiple registers
1117          * starting with SHARED_KEY_MODE_BASE each word will have
1118          * 32 bits and contains the cipher types for 2 bssidx each.
1119          * Using the correct defines correctly will cause overhead,
1120          * so just calculate the correct offset.
1121          */
1122         field.bit_offset = 4 * (key->hw_key_idx % 8);
1123         field.bit_mask = 0x7 << field.bit_offset;
1124
1125         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1126
1127         rt2800_register_read(rt2x00dev, offset, &reg);
1128         rt2x00_set_field32(&reg, field,
1129                            (crypto->cmd == SET_KEY) * crypto->cipher);
1130         rt2800_register_write(rt2x00dev, offset, reg);
1131
1132         /*
1133          * Update WCID information
1134          */
1135         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1136         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1137                                        crypto->bssidx);
1138         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1139
1140         return 0;
1141 }
1142 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1143
1144 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1145 {
1146         struct mac_wcid_entry wcid_entry;
1147         int idx;
1148         u32 offset;
1149
1150         /*
1151          * Search for the first free WCID entry and return the corresponding
1152          * index.
1153          *
1154          * Make sure the WCID starts _after_ the last possible shared key
1155          * entry (>32).
1156          *
1157          * Since parts of the pairwise key table might be shared with
1158          * the beacon frame buffers 6 & 7 we should only write into the
1159          * first 222 entries.
1160          */
1161         for (idx = 33; idx <= 222; idx++) {
1162                 offset = MAC_WCID_ENTRY(idx);
1163                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1164                                           sizeof(wcid_entry));
1165                 if (is_broadcast_ether_addr(wcid_entry.mac))
1166                         return idx;
1167         }
1168
1169         /*
1170          * Use -1 to indicate that we don't have any more space in the WCID
1171          * table.
1172          */
1173         return -1;
1174 }
1175
1176 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1177                                struct rt2x00lib_crypto *crypto,
1178                                struct ieee80211_key_conf *key)
1179 {
1180         struct hw_key_entry key_entry;
1181         u32 offset;
1182
1183         if (crypto->cmd == SET_KEY) {
1184                 /*
1185                  * Allow key configuration only for STAs that are
1186                  * known by the hw.
1187                  */
1188                 if (crypto->wcid < 0)
1189                         return -ENOSPC;
1190                 key->hw_key_idx = crypto->wcid;
1191
1192                 memcpy(key_entry.key, crypto->key,
1193                        sizeof(key_entry.key));
1194                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1195                        sizeof(key_entry.tx_mic));
1196                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1197                        sizeof(key_entry.rx_mic));
1198
1199                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1200                 rt2800_register_multiwrite(rt2x00dev, offset,
1201                                               &key_entry, sizeof(key_entry));
1202         }
1203
1204         /*
1205          * Update WCID information
1206          */
1207         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1208
1209         return 0;
1210 }
1211 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1212
1213 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1214                    struct ieee80211_sta *sta)
1215 {
1216         int wcid;
1217         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1218
1219         /*
1220          * Find next free WCID.
1221          */
1222         wcid = rt2800_find_wcid(rt2x00dev);
1223
1224         /*
1225          * Store selected wcid even if it is invalid so that we can
1226          * later decide if the STA is uploaded into the hw.
1227          */
1228         sta_priv->wcid = wcid;
1229
1230         /*
1231          * No space left in the device, however, we can still communicate
1232          * with the STA -> No error.
1233          */
1234         if (wcid < 0)
1235                 return 0;
1236
1237         /*
1238          * Clean up WCID attributes and write STA address to the device.
1239          */
1240         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1241         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1242         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1243                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1244         return 0;
1245 }
1246 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1247
1248 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1249 {
1250         /*
1251          * Remove WCID entry, no need to clean the attributes as they will
1252          * get renewed when the WCID is reused.
1253          */
1254         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1255
1256         return 0;
1257 }
1258 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1259
1260 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1261                           const unsigned int filter_flags)
1262 {
1263         u32 reg;
1264
1265         /*
1266          * Start configuration steps.
1267          * Note that the version error will always be dropped
1268          * and broadcast frames will always be accepted since
1269          * there is no filter for it at this time.
1270          */
1271         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1272         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1273                            !(filter_flags & FIF_FCSFAIL));
1274         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1275                            !(filter_flags & FIF_PLCPFAIL));
1276         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1277                            !(filter_flags & FIF_PROMISC_IN_BSS));
1278         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1279         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1280         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1281                            !(filter_flags & FIF_ALLMULTI));
1282         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1283         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1284         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1285                            !(filter_flags & FIF_CONTROL));
1286         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1287                            !(filter_flags & FIF_CONTROL));
1288         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1289                            !(filter_flags & FIF_CONTROL));
1290         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1291                            !(filter_flags & FIF_CONTROL));
1292         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1293                            !(filter_flags & FIF_CONTROL));
1294         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1295                            !(filter_flags & FIF_PSPOLL));
1296         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1297         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1298                            !(filter_flags & FIF_CONTROL));
1299         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1300                            !(filter_flags & FIF_CONTROL));
1301         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1302 }
1303 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1304
1305 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1306                         struct rt2x00intf_conf *conf, const unsigned int flags)
1307 {
1308         u32 reg;
1309         bool update_bssid = false;
1310
1311         if (flags & CONFIG_UPDATE_TYPE) {
1312                 /*
1313                  * Enable synchronisation.
1314                  */
1315                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1316                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1317                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1318
1319                 if (conf->sync == TSF_SYNC_AP_NONE) {
1320                         /*
1321                          * Tune beacon queue transmit parameters for AP mode
1322                          */
1323                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1324                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1325                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1326                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1327                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1328                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1329                 } else {
1330                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1331                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1332                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1333                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1334                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1335                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1336                 }
1337         }
1338
1339         if (flags & CONFIG_UPDATE_MAC) {
1340                 if (flags & CONFIG_UPDATE_TYPE &&
1341                     conf->sync == TSF_SYNC_AP_NONE) {
1342                         /*
1343                          * The BSSID register has to be set to our own mac
1344                          * address in AP mode.
1345                          */
1346                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1347                         update_bssid = true;
1348                 }
1349
1350                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1351                         reg = le32_to_cpu(conf->mac[1]);
1352                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1353                         conf->mac[1] = cpu_to_le32(reg);
1354                 }
1355
1356                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1357                                               conf->mac, sizeof(conf->mac));
1358         }
1359
1360         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1361                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1362                         reg = le32_to_cpu(conf->bssid[1]);
1363                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1364                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1365                         conf->bssid[1] = cpu_to_le32(reg);
1366                 }
1367
1368                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1369                                               conf->bssid, sizeof(conf->bssid));
1370         }
1371 }
1372 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1373
1374 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1375                                     struct rt2x00lib_erp *erp)
1376 {
1377         bool any_sta_nongf = !!(erp->ht_opmode &
1378                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1379         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1380         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1381         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1382         u32 reg;
1383
1384         /* default protection rate for HT20: OFDM 24M */
1385         mm20_rate = gf20_rate = 0x4004;
1386
1387         /* default protection rate for HT40: duplicate OFDM 24M */
1388         mm40_rate = gf40_rate = 0x4084;
1389
1390         switch (protection) {
1391         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1392                 /*
1393                  * All STAs in this BSS are HT20/40 but there might be
1394                  * STAs not supporting greenfield mode.
1395                  * => Disable protection for HT transmissions.
1396                  */
1397                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1398
1399                 break;
1400         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1401                 /*
1402                  * All STAs in this BSS are HT20 or HT20/40 but there
1403                  * might be STAs not supporting greenfield mode.
1404                  * => Protect all HT40 transmissions.
1405                  */
1406                 mm20_mode = gf20_mode = 0;
1407                 mm40_mode = gf40_mode = 2;
1408
1409                 break;
1410         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1411                 /*
1412                  * Nonmember protection:
1413                  * According to 802.11n we _should_ protect all
1414                  * HT transmissions (but we don't have to).
1415                  *
1416                  * But if cts_protection is enabled we _shall_ protect
1417                  * all HT transmissions using a CCK rate.
1418                  *
1419                  * And if any station is non GF we _shall_ protect
1420                  * GF transmissions.
1421                  *
1422                  * We decide to protect everything
1423                  * -> fall through to mixed mode.
1424                  */
1425         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1426                 /*
1427                  * Legacy STAs are present
1428                  * => Protect all HT transmissions.
1429                  */
1430                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1431
1432                 /*
1433                  * If erp protection is needed we have to protect HT
1434                  * transmissions with CCK 11M long preamble.
1435                  */
1436                 if (erp->cts_protection) {
1437                         /* don't duplicate RTS/CTS in CCK mode */
1438                         mm20_rate = mm40_rate = 0x0003;
1439                         gf20_rate = gf40_rate = 0x0003;
1440                 }
1441                 break;
1442         }
1443
1444         /* check for STAs not supporting greenfield mode */
1445         if (any_sta_nongf)
1446                 gf20_mode = gf40_mode = 2;
1447
1448         /* Update HT protection config */
1449         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1450         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1451         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1452         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1453
1454         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1455         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1456         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1457         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1458
1459         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1460         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1461         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1462         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1463
1464         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1465         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1466         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1467         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1468 }
1469
1470 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1471                        u32 changed)
1472 {
1473         u32 reg;
1474
1475         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1476                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1477                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1478                                    !!erp->short_preamble);
1479                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1480                                    !!erp->short_preamble);
1481                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1482         }
1483
1484         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1485                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1486                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1487                                    erp->cts_protection ? 2 : 0);
1488                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1489         }
1490
1491         if (changed & BSS_CHANGED_BASIC_RATES) {
1492                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1493                                          erp->basic_rates);
1494                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1495         }
1496
1497         if (changed & BSS_CHANGED_ERP_SLOT) {
1498                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1499                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1500                                    erp->slot_time);
1501                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1502
1503                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1504                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1505                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1506         }
1507
1508         if (changed & BSS_CHANGED_BEACON_INT) {
1509                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1510                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1511                                    erp->beacon_int * 16);
1512                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1513         }
1514
1515         if (changed & BSS_CHANGED_HT)
1516                 rt2800_config_ht_opmode(rt2x00dev, erp);
1517 }
1518 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1519
1520 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1521 {
1522         u32 reg;
1523         u16 eeprom;
1524         u8 led_ctrl, led_g_mode, led_r_mode;
1525
1526         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1527         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1528                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1529                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1530         } else {
1531                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1532                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1533         }
1534         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1535
1536         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1537         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1538         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1539         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1540             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1541                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1542                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1543                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1544                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1545                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1546                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1547                 } else {
1548                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1549                                            (led_g_mode << 2) | led_r_mode, 1);
1550                 }
1551         }
1552 }
1553
1554 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1555                                      enum antenna ant)
1556 {
1557         u32 reg;
1558         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1559         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1560
1561         if (rt2x00_is_pci(rt2x00dev)) {
1562                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1563                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1564                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1565         } else if (rt2x00_is_usb(rt2x00dev))
1566                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1567                                    eesk_pin, 0);
1568
1569         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1570         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1571         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1572         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1573 }
1574
1575 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1576 {
1577         u8 r1;
1578         u8 r3;
1579         u16 eeprom;
1580
1581         rt2800_bbp_read(rt2x00dev, 1, &r1);
1582         rt2800_bbp_read(rt2x00dev, 3, &r3);
1583
1584         if (rt2x00_rt(rt2x00dev, RT3572) &&
1585             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1586                 rt2800_config_3572bt_ant(rt2x00dev);
1587
1588         /*
1589          * Configure the TX antenna.
1590          */
1591         switch (ant->tx_chain_num) {
1592         case 1:
1593                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1594                 break;
1595         case 2:
1596                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1597                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1598                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1599                 else
1600                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1601                 break;
1602         case 3:
1603                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1604                 break;
1605         }
1606
1607         /*
1608          * Configure the RX antenna.
1609          */
1610         switch (ant->rx_chain_num) {
1611         case 1:
1612                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1613                     rt2x00_rt(rt2x00dev, RT3090) ||
1614                     rt2x00_rt(rt2x00dev, RT3352) ||
1615                     rt2x00_rt(rt2x00dev, RT3390)) {
1616                         rt2x00_eeprom_read(rt2x00dev,
1617                                            EEPROM_NIC_CONF1, &eeprom);
1618                         if (rt2x00_get_field16(eeprom,
1619                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1620                                 rt2800_set_ant_diversity(rt2x00dev,
1621                                                 rt2x00dev->default_ant.rx);
1622                 }
1623                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1624                 break;
1625         case 2:
1626                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1627                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1628                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1629                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1630                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1631                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1632                 } else {
1633                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1634                 }
1635                 break;
1636         case 3:
1637                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1638                 break;
1639         }
1640
1641         rt2800_bbp_write(rt2x00dev, 3, r3);
1642         rt2800_bbp_write(rt2x00dev, 1, r1);
1643 }
1644 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1645
1646 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1647                                    struct rt2x00lib_conf *libconf)
1648 {
1649         u16 eeprom;
1650         short lna_gain;
1651
1652         if (libconf->rf.channel <= 14) {
1653                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1654                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1655         } else if (libconf->rf.channel <= 64) {
1656                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1657                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1658         } else if (libconf->rf.channel <= 128) {
1659                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1660                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1661         } else {
1662                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1663                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1664         }
1665
1666         rt2x00dev->lna_gain = lna_gain;
1667 }
1668
1669 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1670                                          struct ieee80211_conf *conf,
1671                                          struct rf_channel *rf,
1672                                          struct channel_info *info)
1673 {
1674         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1675
1676         if (rt2x00dev->default_ant.tx_chain_num == 1)
1677                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1678
1679         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1680                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1681                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1682         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1683                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1684
1685         if (rf->channel > 14) {
1686                 /*
1687                  * When TX power is below 0, we should increase it by 7 to
1688                  * make it a positive value (Minimum value is -7).
1689                  * However this means that values between 0 and 7 have
1690                  * double meaning, and we should set a 7DBm boost flag.
1691                  */
1692                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1693                                    (info->default_power1 >= 0));
1694
1695                 if (info->default_power1 < 0)
1696                         info->default_power1 += 7;
1697
1698                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1699
1700                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1701                                    (info->default_power2 >= 0));
1702
1703                 if (info->default_power2 < 0)
1704                         info->default_power2 += 7;
1705
1706                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1707         } else {
1708                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1709                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1710         }
1711
1712         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1713
1714         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1715         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1716         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1717         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1718
1719         udelay(200);
1720
1721         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1722         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1723         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1724         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1725
1726         udelay(200);
1727
1728         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1729         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1730         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1731         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1732 }
1733
1734 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1735                                          struct ieee80211_conf *conf,
1736                                          struct rf_channel *rf,
1737                                          struct channel_info *info)
1738 {
1739         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1740         u8 rfcsr, calib_tx, calib_rx;
1741
1742         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1743
1744         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1745         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1746         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1747
1748         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1749         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1750         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1751
1752         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1753         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1754         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1755
1756         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1757         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1758         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1759
1760         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1761         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1762         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1763                           rt2x00dev->default_ant.rx_chain_num <= 1);
1764         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1765                           rt2x00dev->default_ant.rx_chain_num <= 2);
1766         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1767         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1768                           rt2x00dev->default_ant.tx_chain_num <= 1);
1769         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1770                           rt2x00dev->default_ant.tx_chain_num <= 2);
1771         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1772
1773         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1774         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1775         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1776         msleep(1);
1777         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1778         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1779
1780         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1781         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1782         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1783
1784         if (rt2x00_rt(rt2x00dev, RT3390)) {
1785                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1786                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1787         } else {
1788                 if (conf_is_ht40(conf)) {
1789                         calib_tx = drv_data->calibration_bw40;
1790                         calib_rx = drv_data->calibration_bw40;
1791                 } else {
1792                         calib_tx = drv_data->calibration_bw20;
1793                         calib_rx = drv_data->calibration_bw20;
1794                 }
1795         }
1796
1797         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1798         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1799         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1800
1801         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1802         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1803         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1804
1805         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1806         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1807         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1808
1809         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1810         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1811         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1812         msleep(1);
1813         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1814         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1815 }
1816
1817 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1818                                          struct ieee80211_conf *conf,
1819                                          struct rf_channel *rf,
1820                                          struct channel_info *info)
1821 {
1822         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1823         u8 rfcsr;
1824         u32 reg;
1825
1826         if (rf->channel <= 14) {
1827                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1828                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1829         } else {
1830                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1831                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1832         }
1833
1834         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1835         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1836
1837         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1838         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1839         if (rf->channel <= 14)
1840                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1841         else
1842                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1843         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1844
1845         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1846         if (rf->channel <= 14)
1847                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1848         else
1849                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1850         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1851
1852         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1853         if (rf->channel <= 14) {
1854                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1855                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1856                                   info->default_power1);
1857         } else {
1858                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1859                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1860                                 (info->default_power1 & 0x3) |
1861                                 ((info->default_power1 & 0xC) << 1));
1862         }
1863         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1864
1865         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1866         if (rf->channel <= 14) {
1867                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1868                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1869                                   info->default_power2);
1870         } else {
1871                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1872                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1873                                 (info->default_power2 & 0x3) |
1874                                 ((info->default_power2 & 0xC) << 1));
1875         }
1876         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1877
1878         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1879         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1880         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1881         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1882         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1883         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1884         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1885         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1886                 if (rf->channel <= 14) {
1887                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1888                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1889                 }
1890                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1891                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1892         } else {
1893                 switch (rt2x00dev->default_ant.tx_chain_num) {
1894                 case 1:
1895                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1896                 case 2:
1897                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1898                         break;
1899                 }
1900
1901                 switch (rt2x00dev->default_ant.rx_chain_num) {
1902                 case 1:
1903                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1904                 case 2:
1905                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1906                         break;
1907                 }
1908         }
1909         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1910
1911         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1912         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1913         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1914
1915         if (conf_is_ht40(conf)) {
1916                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1917                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1918         } else {
1919                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1920                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1921         }
1922
1923         if (rf->channel <= 14) {
1924                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1925                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1926                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1927                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1928                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1929                 rfcsr = 0x4c;
1930                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1931                                   drv_data->txmixer_gain_24g);
1932                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1933                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1934                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1935                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1936                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1937                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1938                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1939                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1940         } else {
1941                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1942                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1943                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1944                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1945                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1946                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1947                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1948                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1949                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1950                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1951                 rfcsr = 0x7a;
1952                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1953                                   drv_data->txmixer_gain_5g);
1954                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1955                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1956                 if (rf->channel <= 64) {
1957                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1958                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1959                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1960                 } else if (rf->channel <= 128) {
1961                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1962                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1963                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1964                 } else {
1965                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1966                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1967                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1968                 }
1969                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1970                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1971                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1972         }
1973
1974         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1975         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1976         if (rf->channel <= 14)
1977                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1978         else
1979                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1980         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1981
1982         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1983         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1984         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1985 }
1986
1987 #define POWER_BOUND             0x27
1988 #define POWER_BOUND_5G          0x2b
1989 #define FREQ_OFFSET_BOUND       0x5f
1990
1991 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1992 {
1993         u8 rfcsr;
1994
1995         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1996         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
1997                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
1998         else
1999                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2000         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2001 }
2002
2003 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2004                                          struct ieee80211_conf *conf,
2005                                          struct rf_channel *rf,
2006                                          struct channel_info *info)
2007 {
2008         u8 rfcsr;
2009
2010         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2011         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2012         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2013         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2014         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2015
2016         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2017         if (info->default_power1 > POWER_BOUND)
2018                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2019         else
2020                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2021         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2022
2023         rt2800_adjust_freq_offset(rt2x00dev);
2024
2025         if (rf->channel <= 14) {
2026                 if (rf->channel == 6)
2027                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2028                 else
2029                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2030
2031                 if (rf->channel >= 1 && rf->channel <= 6)
2032                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2033                 else if (rf->channel >= 7 && rf->channel <= 11)
2034                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2035                 else if (rf->channel >= 12 && rf->channel <= 14)
2036                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2037         }
2038 }
2039
2040 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2041                                          struct ieee80211_conf *conf,
2042                                          struct rf_channel *rf,
2043                                          struct channel_info *info)
2044 {
2045         u8 rfcsr;
2046
2047         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2048         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2049
2050         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2051         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2052         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2053
2054         if (info->default_power1 > POWER_BOUND)
2055                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2056         else
2057                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2058
2059         if (info->default_power2 > POWER_BOUND)
2060                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2061         else
2062                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2063
2064         rt2800_adjust_freq_offset(rt2x00dev);
2065
2066         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2067         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2068         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2069
2070         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2071                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2072         else
2073                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2074
2075         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2076                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2077         else
2078                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2079
2080         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2081         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2082
2083         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2084
2085         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2086 }
2087
2088 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2089                                          struct ieee80211_conf *conf,
2090                                          struct rf_channel *rf,
2091                                          struct channel_info *info)
2092 {
2093         u8 rfcsr;
2094
2095         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2096         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2097         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2098         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2099         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2100
2101         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2102         if (info->default_power1 > POWER_BOUND)
2103                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2104         else
2105                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2106         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2107
2108         if (rt2x00_rt(rt2x00dev, RT5392)) {
2109                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2110                 if (info->default_power1 > POWER_BOUND)
2111                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2112                 else
2113                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2114                                           info->default_power2);
2115                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2116         }
2117
2118         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2119         if (rt2x00_rt(rt2x00dev, RT5392)) {
2120                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2121                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2122         }
2123         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2124         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2125         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2126         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2127         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2128
2129         rt2800_adjust_freq_offset(rt2x00dev);
2130
2131         if (rf->channel <= 14) {
2132                 int idx = rf->channel-1;
2133
2134                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2135                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2136                                 /* r55/r59 value array of channel 1~14 */
2137                                 static const char r55_bt_rev[] = {0x83, 0x83,
2138                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2139                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2140                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2141                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2142                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2143
2144                                 rt2800_rfcsr_write(rt2x00dev, 55,
2145                                                    r55_bt_rev[idx]);
2146                                 rt2800_rfcsr_write(rt2x00dev, 59,
2147                                                    r59_bt_rev[idx]);
2148                         } else {
2149                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2150                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2151                                         0x88, 0x88, 0x86, 0x85, 0x84};
2152
2153                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2154                         }
2155                 } else {
2156                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2157                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2158                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2159                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2160                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2161                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2162                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2163
2164                                 rt2800_rfcsr_write(rt2x00dev, 55,
2165                                                    r55_nonbt_rev[idx]);
2166                                 rt2800_rfcsr_write(rt2x00dev, 59,
2167                                                    r59_nonbt_rev[idx]);
2168                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2169                                    rt2x00_rt(rt2x00dev, RT5392)) {
2170                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2171                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2172                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2173
2174                                 rt2800_rfcsr_write(rt2x00dev, 59,
2175                                                    r59_non_bt[idx]);
2176                         }
2177                 }
2178         }
2179 }
2180
2181 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2182                                          struct ieee80211_conf *conf,
2183                                          struct rf_channel *rf,
2184                                          struct channel_info *info)
2185 {
2186         u8 rfcsr, ep_reg;
2187         u32 reg;
2188         int power_bound;
2189
2190         /* TODO */
2191         const bool is_11b = false;
2192         const bool is_type_ep = false;
2193
2194         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2195         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2196                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2197         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2198
2199         /* Order of values on rf_channel entry: N, K, mod, R */
2200         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2201
2202         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2203         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2204         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2205         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2206         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2207
2208         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2209         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2210         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2211         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2212
2213         if (rf->channel <= 14) {
2214                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2215                 /* FIXME: RF11 owerwrite ? */
2216                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2217                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2218                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2219                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2220                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2221                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2222                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2223                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2224                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2225                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2226                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2227                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2228                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2229                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2230                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2231                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2232                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2233                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2234                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2235                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2236                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2237                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2238                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2239                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2240                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2241                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2242                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2243                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2244
2245                 /* TODO RF27 <- tssi */
2246
2247                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2248                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2249                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2250
2251                 if (is_11b) {
2252                         /* CCK */
2253                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2254                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2255                         if (is_type_ep)
2256                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2257                         else
2258                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2259                 } else {
2260                         /* OFDM */
2261                         if (is_type_ep)
2262                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2263                         else
2264                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2265                 }
2266
2267                 power_bound = POWER_BOUND;
2268                 ep_reg = 0x2;
2269         } else {
2270                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2271                 /* FIMXE: RF11 overwrite */
2272                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2273                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2274                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2275                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2276                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2277                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2278                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2279                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2280                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2281                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2282                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2283                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2284                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2285                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2286
2287                 /* TODO RF27 <- tssi */
2288
2289                 if (rf->channel >= 36 && rf->channel <= 64) {
2290
2291                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2292                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2293                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2294                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2295                         if (rf->channel <= 50)
2296                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2297                         else if (rf->channel >= 52)
2298                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2299                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2300                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2301                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2302                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2303                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2304                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2305                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2306                         if (rf->channel <= 50) {
2307                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2308                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2309                         } else if (rf->channel >= 52) {
2310                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2311                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2312                         }
2313
2314                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2315                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2316                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2317
2318                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2319
2320                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2321                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2322                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2323                         if (rf->channel <= 153) {
2324                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2325                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2326                         } else if (rf->channel >= 155) {
2327                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2328                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2329                         }
2330                         if (rf->channel <= 138) {
2331                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2332                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2333                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2334                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2335                         } else if (rf->channel >= 140) {
2336                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2337                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2338                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2339                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2340                         }
2341                         if (rf->channel <= 124)
2342                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2343                         else if (rf->channel >= 126)
2344                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2345                         if (rf->channel <= 138)
2346                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2347                         else if (rf->channel >= 140)
2348                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2349                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2350                         if (rf->channel <= 138)
2351                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2352                         else if (rf->channel >= 140)
2353                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2354                         if (rf->channel <= 128)
2355                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2356                         else if (rf->channel >= 130)
2357                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2358                         if (rf->channel <= 116)
2359                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2360                         else if (rf->channel >= 118)
2361                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2362                         if (rf->channel <= 138)
2363                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2364                         else if (rf->channel >= 140)
2365                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2366                         if (rf->channel <= 116)
2367                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2368                         else if (rf->channel >= 118)
2369                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2370                 }
2371
2372                 power_bound = POWER_BOUND_5G;
2373                 ep_reg = 0x3;
2374         }
2375
2376         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2377         if (info->default_power1 > power_bound)
2378                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2379         else
2380                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2381         if (is_type_ep)
2382                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2383         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2384
2385         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2386         if (info->default_power1 > power_bound)
2387                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2388         else
2389                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2390         if (is_type_ep)
2391                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2392         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2393
2394         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2395         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2396         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2397
2398         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2399                           rt2x00dev->default_ant.tx_chain_num >= 1);
2400         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2401                           rt2x00dev->default_ant.tx_chain_num == 2);
2402         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2403
2404         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2405                           rt2x00dev->default_ant.rx_chain_num >= 1);
2406         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2407                           rt2x00dev->default_ant.rx_chain_num == 2);
2408         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2409
2410         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2411         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2412
2413         if (conf_is_ht40(conf))
2414                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2415         else
2416                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2417
2418         if (!is_11b) {
2419                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2420                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2421         }
2422
2423         /* TODO proper frequency adjustment */
2424         rt2800_adjust_freq_offset(rt2x00dev);
2425
2426         /* TODO merge with others */
2427         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2428         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2429         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2430
2431         /* BBP settings */
2432         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2433         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2434         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2435
2436         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2437         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2438         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2439         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2440
2441         /* GLRT band configuration */
2442         rt2800_bbp_write(rt2x00dev, 195, 128);
2443         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2444         rt2800_bbp_write(rt2x00dev, 195, 129);
2445         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2446         rt2800_bbp_write(rt2x00dev, 195, 130);
2447         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2448         rt2800_bbp_write(rt2x00dev, 195, 131);
2449         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2450         rt2800_bbp_write(rt2x00dev, 195, 133);
2451         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2452         rt2800_bbp_write(rt2x00dev, 195, 124);
2453         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2454 }
2455
2456 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2457                                            const unsigned int word,
2458                                            const u8 value)
2459 {
2460         u8 chain, reg;
2461
2462         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2463                 rt2800_bbp_read(rt2x00dev, 27, &reg);
2464                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
2465                 rt2800_bbp_write(rt2x00dev, 27, reg);
2466
2467                 rt2800_bbp_write(rt2x00dev, word, value);
2468         }
2469 }
2470
2471
2472 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2473 {
2474         u8 cal;
2475
2476         /* TODO */
2477         if (WARN_ON_ONCE(channel > 14))
2478                 return;
2479
2480         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2481         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2482         rt2800_bbp_write(rt2x00dev, 159, cal);
2483
2484         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2485         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2486         rt2800_bbp_write(rt2x00dev, 159, cal);
2487
2488         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2489         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2490         rt2800_bbp_write(rt2x00dev, 159, cal);
2491
2492         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2493         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2494         rt2800_bbp_write(rt2x00dev, 159, cal);
2495
2496         /* RF IQ compensation control */
2497         rt2800_bbp_write(rt2x00dev, 158, 0x04);
2498         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2499         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2500
2501         /* RF IQ imbalance compensation control */
2502         rt2800_bbp_write(rt2x00dev, 158, 0x03);
2503         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2504         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2505 }
2506
2507 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2508                                   struct ieee80211_conf *conf,
2509                                   struct rf_channel *rf,
2510                                   struct channel_info *info)
2511 {
2512         u32 reg;
2513         unsigned int tx_pin;
2514         u8 bbp, rfcsr;
2515
2516         if (rf->channel <= 14) {
2517                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2518                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2519         } else {
2520                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2521                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2522         }
2523
2524         switch (rt2x00dev->chip.rf) {
2525         case RF2020:
2526         case RF3020:
2527         case RF3021:
2528         case RF3022:
2529         case RF3320:
2530                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2531                 break;
2532         case RF3052:
2533                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2534                 break;
2535         case RF3290:
2536                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2537                 break;
2538         case RF3322:
2539                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2540                 break;
2541         case RF5360:
2542         case RF5370:
2543         case RF5372:
2544         case RF5390:
2545         case RF5392:
2546                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2547                 break;
2548         case RF5592:
2549                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2550                 break;
2551         default:
2552                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2553         }
2554
2555         if (rt2x00_rf(rt2x00dev, RF3290) ||
2556             rt2x00_rf(rt2x00dev, RF3322) ||
2557             rt2x00_rf(rt2x00dev, RF5360) ||
2558             rt2x00_rf(rt2x00dev, RF5370) ||
2559             rt2x00_rf(rt2x00dev, RF5372) ||
2560             rt2x00_rf(rt2x00dev, RF5390) ||
2561             rt2x00_rf(rt2x00dev, RF5392)) {
2562                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2563                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2564                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2565                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2566
2567                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2568                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2569                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2570         }
2571
2572         /*
2573          * Change BBP settings
2574          */
2575         if (rt2x00_rt(rt2x00dev, RT3352)) {
2576                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2577                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2578                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2579                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2580         } else {
2581                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2582                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2583                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2584                 rt2800_bbp_write(rt2x00dev, 86, 0);
2585         }
2586
2587         if (rf->channel <= 14) {
2588                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2589                     !rt2x00_rt(rt2x00dev, RT5392)) {
2590                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2591                                      &rt2x00dev->cap_flags)) {
2592                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2593                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2594                         } else {
2595                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2596                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2597                         }
2598                 }
2599         } else {
2600                 if (rt2x00_rt(rt2x00dev, RT3572))
2601                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2602                 else
2603                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2604
2605                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2606                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2607                 else
2608                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2609         }
2610
2611         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2612         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2613         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2614         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2615         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2616
2617         if (rt2x00_rt(rt2x00dev, RT3572))
2618                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2619
2620         tx_pin = 0;
2621
2622         /* Turn on unused PA or LNA when not using 1T or 1R */
2623         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2624                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2625                                    rf->channel > 14);
2626                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2627                                    rf->channel <= 14);
2628         }
2629
2630         /* Turn on unused PA or LNA when not using 1T or 1R */
2631         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2632                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2633                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2634         }
2635
2636         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2637         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2638         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2639         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2640         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2641                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2642         else
2643                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2644                                    rf->channel <= 14);
2645         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2646
2647         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2648
2649         if (rt2x00_rt(rt2x00dev, RT3572))
2650                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2651
2652         if (rt2x00_rt(rt2x00dev, RT5592)) {
2653                 rt2800_bbp_write(rt2x00dev, 195, 141);
2654                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2655
2656                 /* AGC init */
2657                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2658                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2659
2660                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2661         }
2662
2663         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2664         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2665         rt2800_bbp_write(rt2x00dev, 4, bbp);
2666
2667         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2668         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2669         rt2800_bbp_write(rt2x00dev, 3, bbp);
2670
2671         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2672                 if (conf_is_ht40(conf)) {
2673                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2674                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2675                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2676                 } else {
2677                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2678                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2679                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2680                 }
2681         }
2682
2683         msleep(1);
2684
2685         /*
2686          * Clear channel statistic counters
2687          */
2688         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2689         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2690         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2691
2692         /*
2693          * Clear update flag
2694          */
2695         if (rt2x00_rt(rt2x00dev, RT3352)) {
2696                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2697                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2698                 rt2800_bbp_write(rt2x00dev, 49, bbp);
2699         }
2700 }
2701
2702 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2703 {
2704         u8 tssi_bounds[9];
2705         u8 current_tssi;
2706         u16 eeprom;
2707         u8 step;
2708         int i;
2709
2710         /*
2711          * Read TSSI boundaries for temperature compensation from
2712          * the EEPROM.
2713          *
2714          * Array idx               0    1    2    3    4    5    6    7    8
2715          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2716          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2717          */
2718         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2719                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2720                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2721                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2722                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2723                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2724
2725                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2726                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2727                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2728                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2729                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2730
2731                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2732                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2733                                         EEPROM_TSSI_BOUND_BG3_REF);
2734                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2735                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2736
2737                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2738                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2739                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2740                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2741                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2742
2743                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2744                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2745                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2746
2747                 step = rt2x00_get_field16(eeprom,
2748                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2749         } else {
2750                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2751                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2752                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2753                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2754                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2755
2756                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2757                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2758                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2759                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2760                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2761
2762                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2763                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2764                                         EEPROM_TSSI_BOUND_A3_REF);
2765                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2766                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2767
2768                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2769                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2770                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2771                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2772                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2773
2774                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2775                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2776                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2777
2778                 step = rt2x00_get_field16(eeprom,
2779                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2780         }
2781
2782         /*
2783          * Check if temperature compensation is supported.
2784          */
2785         if (tssi_bounds[4] == 0xff || step == 0xff)
2786                 return 0;
2787
2788         /*
2789          * Read current TSSI (BBP 49).
2790          */
2791         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2792
2793         /*
2794          * Compare TSSI value (BBP49) with the compensation boundaries
2795          * from the EEPROM and increase or decrease tx power.
2796          */
2797         for (i = 0; i <= 3; i++) {
2798                 if (current_tssi > tssi_bounds[i])
2799                         break;
2800         }
2801
2802         if (i == 4) {
2803                 for (i = 8; i >= 5; i--) {
2804                         if (current_tssi < tssi_bounds[i])
2805                                 break;
2806                 }
2807         }
2808
2809         return (i - 4) * step;
2810 }
2811
2812 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2813                                       enum ieee80211_band band)
2814 {
2815         u16 eeprom;
2816         u8 comp_en;
2817         u8 comp_type;
2818         int comp_value = 0;
2819
2820         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2821
2822         /*
2823          * HT40 compensation not required.
2824          */
2825         if (eeprom == 0xffff ||
2826             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2827                 return 0;
2828
2829         if (band == IEEE80211_BAND_2GHZ) {
2830                 comp_en = rt2x00_get_field16(eeprom,
2831                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2832                 if (comp_en) {
2833                         comp_type = rt2x00_get_field16(eeprom,
2834                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2835                         comp_value = rt2x00_get_field16(eeprom,
2836                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2837                         if (!comp_type)
2838                                 comp_value = -comp_value;
2839                 }
2840         } else {
2841                 comp_en = rt2x00_get_field16(eeprom,
2842                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2843                 if (comp_en) {
2844                         comp_type = rt2x00_get_field16(eeprom,
2845                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2846                         comp_value = rt2x00_get_field16(eeprom,
2847                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2848                         if (!comp_type)
2849                                 comp_value = -comp_value;
2850                 }
2851         }
2852
2853         return comp_value;
2854 }
2855
2856 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2857                                         int power_level, int max_power)
2858 {
2859         int delta;
2860
2861         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2862                 return 0;
2863
2864         /*
2865          * XXX: We don't know the maximum transmit power of our hardware since
2866          * the EEPROM doesn't expose it. We only know that we are calibrated
2867          * to 100% tx power.
2868          *
2869          * Hence, we assume the regulatory limit that cfg80211 calulated for
2870          * the current channel is our maximum and if we are requested to lower
2871          * the value we just reduce our tx power accordingly.
2872          */
2873         delta = power_level - max_power;
2874         return min(delta, 0);
2875 }
2876
2877 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2878                                    enum ieee80211_band band, int power_level,
2879                                    u8 txpower, int delta)
2880 {
2881         u16 eeprom;
2882         u8 criterion;
2883         u8 eirp_txpower;
2884         u8 eirp_txpower_criterion;
2885         u8 reg_limit;
2886
2887         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2888                 /*
2889                  * Check if eirp txpower exceed txpower_limit.
2890                  * We use OFDM 6M as criterion and its eirp txpower
2891                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2892                  * .11b data rate need add additional 4dbm
2893                  * when calculating eirp txpower.
2894                  */
2895                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2896                                    &eeprom);
2897                 criterion = rt2x00_get_field16(eeprom,
2898                                                EEPROM_TXPOWER_BYRATE_RATE0);
2899
2900                 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2901                                    &eeprom);
2902
2903                 if (band == IEEE80211_BAND_2GHZ)
2904                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2905                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2906                 else
2907                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2908                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2909
2910                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2911                                (is_rate_b ? 4 : 0) + delta;
2912
2913                 reg_limit = (eirp_txpower > power_level) ?
2914                                         (eirp_txpower - power_level) : 0;
2915         } else
2916                 reg_limit = 0;
2917
2918         txpower = max(0, txpower + delta - reg_limit);
2919         return min_t(u8, txpower, 0xc);
2920 }
2921
2922 /*
2923  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2924  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2925  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2926  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2927  * Reference per rate transmit power values are located in the EEPROM at
2928  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2929  * current conditions (i.e. band, bandwidth, temperature, user settings).
2930  */
2931 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2932                                   struct ieee80211_channel *chan,
2933                                   int power_level)
2934 {
2935         u8 txpower, r1;
2936         u16 eeprom;
2937         u32 reg, offset;
2938         int i, is_rate_b, delta, power_ctrl;
2939         enum ieee80211_band band = chan->band;
2940
2941         /*
2942          * Calculate HT40 compensation. For 40MHz we need to add or subtract
2943          * value read from EEPROM (different for 2GHz and for 5GHz).
2944          */
2945         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2946
2947         /*
2948          * Calculate temperature compensation. Depends on measurement of current
2949          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
2950          * to temperature or maybe other factors) is smaller or bigger than
2951          * expected. We adjust it, based on TSSI reference and boundaries values
2952          * provided in EEPROM.
2953          */
2954         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2955
2956         /*
2957          * Decrease power according to user settings, on devices with unknown
2958          * maximum tx power. For other devices we take user power_level into
2959          * consideration on rt2800_compensate_txpower().
2960          */
2961         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
2962                                               chan->max_power);
2963
2964         /*
2965          * BBP_R1 controls TX power for all rates, it allow to set the following
2966          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2967          *
2968          * TODO: we do not use +6 dBm option to do not increase power beyond
2969          * regulatory limit, however this could be utilized for devices with
2970          * CAPABILITY_POWER_LIMIT.
2971          */
2972         rt2800_bbp_read(rt2x00dev, 1, &r1);
2973         if (delta <= -12) {
2974                 power_ctrl = 2;
2975                 delta += 12;
2976         } else if (delta <= -6) {
2977                 power_ctrl = 1;
2978                 delta += 6;
2979         } else {
2980                 power_ctrl = 0;
2981         }
2982         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
2983         rt2800_bbp_write(rt2x00dev, 1, r1);
2984         offset = TX_PWR_CFG_0;
2985
2986         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2987                 /* just to be safe */
2988                 if (offset > TX_PWR_CFG_4)
2989                         break;
2990
2991                 rt2800_register_read(rt2x00dev, offset, &reg);
2992
2993                 /* read the next four txpower values */
2994                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2995                                    &eeprom);
2996
2997                 is_rate_b = i ? 0 : 1;
2998                 /*
2999                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3000                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3001                  * TX_PWR_CFG_4: unknown
3002                  */
3003                 txpower = rt2x00_get_field16(eeprom,
3004                                              EEPROM_TXPOWER_BYRATE_RATE0);
3005                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3006                                              power_level, txpower, delta);
3007                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
3008
3009                 /*
3010                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3011                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3012                  * TX_PWR_CFG_4: unknown
3013                  */
3014                 txpower = rt2x00_get_field16(eeprom,
3015                                              EEPROM_TXPOWER_BYRATE_RATE1);
3016                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3017                                              power_level, txpower, delta);
3018                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
3019
3020                 /*
3021                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3022                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
3023                  * TX_PWR_CFG_4: unknown
3024                  */
3025                 txpower = rt2x00_get_field16(eeprom,
3026                                              EEPROM_TXPOWER_BYRATE_RATE2);
3027                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3028                                              power_level, txpower, delta);
3029                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
3030
3031                 /*
3032                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3033                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
3034                  * TX_PWR_CFG_4: unknown
3035                  */
3036                 txpower = rt2x00_get_field16(eeprom,
3037                                              EEPROM_TXPOWER_BYRATE_RATE3);
3038                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3039                                              power_level, txpower, delta);
3040                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
3041
3042                 /* read the next four txpower values */
3043                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
3044                                    &eeprom);
3045
3046                 is_rate_b = 0;
3047                 /*
3048                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3049                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3050                  * TX_PWR_CFG_4: unknown
3051                  */
3052                 txpower = rt2x00_get_field16(eeprom,
3053                                              EEPROM_TXPOWER_BYRATE_RATE0);
3054                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3055                                              power_level, txpower, delta);
3056                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3057
3058                 /*
3059                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3060                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3061                  * TX_PWR_CFG_4: unknown
3062                  */
3063                 txpower = rt2x00_get_field16(eeprom,
3064                                              EEPROM_TXPOWER_BYRATE_RATE1);
3065                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3066                                              power_level, txpower, delta);
3067                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3068
3069                 /*
3070                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3071                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3072                  * TX_PWR_CFG_4: unknown
3073                  */
3074                 txpower = rt2x00_get_field16(eeprom,
3075                                              EEPROM_TXPOWER_BYRATE_RATE2);
3076                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3077                                              power_level, txpower, delta);
3078                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3079
3080                 /*
3081                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3082                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3083                  * TX_PWR_CFG_4: unknown
3084                  */
3085                 txpower = rt2x00_get_field16(eeprom,
3086                                              EEPROM_TXPOWER_BYRATE_RATE3);
3087                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3088                                              power_level, txpower, delta);
3089                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3090
3091                 rt2800_register_write(rt2x00dev, offset, reg);
3092
3093                 /* next TX_PWR_CFG register */
3094                 offset += 4;
3095         }
3096 }
3097
3098 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3099 {
3100         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
3101                               rt2x00dev->tx_power);
3102 }
3103 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3104
3105 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3106 {
3107         u32     tx_pin;
3108         u8      rfcsr;
3109
3110         /*
3111          * A voltage-controlled oscillator(VCO) is an electronic oscillator
3112          * designed to be controlled in oscillation frequency by a voltage
3113          * input. Maybe the temperature will affect the frequency of
3114          * oscillation to be shifted. The VCO calibration will be called
3115          * periodically to adjust the frequency to be precision.
3116         */
3117
3118         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3119         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3120         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3121
3122         switch (rt2x00dev->chip.rf) {
3123         case RF2020:
3124         case RF3020:
3125         case RF3021:
3126         case RF3022:
3127         case RF3320:
3128         case RF3052:
3129                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3130                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3131                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3132                 break;
3133         case RF3290:
3134         case RF5360:
3135         case RF5370:
3136         case RF5372:
3137         case RF5390:
3138         case RF5392:
3139                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3140                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3141                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3142                 break;
3143         default:
3144                 return;
3145         }
3146
3147         mdelay(1);
3148
3149         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3150         if (rt2x00dev->rf_channel <= 14) {
3151                 switch (rt2x00dev->default_ant.tx_chain_num) {
3152                 case 3:
3153                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3154                         /* fall through */
3155                 case 2:
3156                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3157                         /* fall through */
3158                 case 1:
3159                 default:
3160                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3161                         break;
3162                 }
3163         } else {
3164                 switch (rt2x00dev->default_ant.tx_chain_num) {
3165                 case 3:
3166                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3167                         /* fall through */
3168                 case 2:
3169                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3170                         /* fall through */
3171                 case 1:
3172                 default:
3173                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3174                         break;
3175                 }
3176         }
3177         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3178
3179 }
3180 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3181
3182 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3183                                       struct rt2x00lib_conf *libconf)
3184 {
3185         u32 reg;
3186
3187         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3188         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3189                            libconf->conf->short_frame_max_tx_count);
3190         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3191                            libconf->conf->long_frame_max_tx_count);
3192         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3193 }
3194
3195 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3196                              struct rt2x00lib_conf *libconf)
3197 {
3198         enum dev_state state =
3199             (libconf->conf->flags & IEEE80211_CONF_PS) ?
3200                 STATE_SLEEP : STATE_AWAKE;
3201         u32 reg;
3202
3203         if (state == STATE_SLEEP) {
3204                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3205
3206                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3207                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3208                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3209                                    libconf->conf->listen_interval - 1);
3210                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3211                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3212
3213                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3214         } else {
3215                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3216                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3217                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3218                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3219                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3220
3221                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3222         }
3223 }
3224
3225 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3226                    struct rt2x00lib_conf *libconf,
3227                    const unsigned int flags)
3228 {
3229         /* Always recalculate LNA gain before changing configuration */
3230         rt2800_config_lna_gain(rt2x00dev, libconf);
3231
3232         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3233                 rt2800_config_channel(rt2x00dev, libconf->conf,
3234                                       &libconf->rf, &libconf->channel);
3235                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3236                                       libconf->conf->power_level);
3237         }
3238         if (flags & IEEE80211_CONF_CHANGE_POWER)
3239                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3240                                       libconf->conf->power_level);
3241         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3242                 rt2800_config_retry_limit(rt2x00dev, libconf);
3243         if (flags & IEEE80211_CONF_CHANGE_PS)
3244                 rt2800_config_ps(rt2x00dev, libconf);
3245 }
3246 EXPORT_SYMBOL_GPL(rt2800_config);
3247
3248 /*
3249  * Link tuning
3250  */
3251 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3252 {
3253         u32 reg;
3254
3255         /*
3256          * Update FCS error count from register.
3257          */
3258         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3259         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3260 }
3261 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3262
3263 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3264 {
3265         u8 vgc;
3266
3267         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3268                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3269                     rt2x00_rt(rt2x00dev, RT3071) ||
3270                     rt2x00_rt(rt2x00dev, RT3090) ||
3271                     rt2x00_rt(rt2x00dev, RT3290) ||
3272                     rt2x00_rt(rt2x00dev, RT3390) ||
3273                     rt2x00_rt(rt2x00dev, RT3572) ||
3274                     rt2x00_rt(rt2x00dev, RT5390) ||
3275                     rt2x00_rt(rt2x00dev, RT5392) ||
3276                     rt2x00_rt(rt2x00dev, RT5592))
3277                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3278                 else
3279                         vgc = 0x2e + rt2x00dev->lna_gain;
3280         } else { /* 5GHZ band */
3281                 if (rt2x00_rt(rt2x00dev, RT3572))
3282                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3283                 else if (rt2x00_rt(rt2x00dev, RT5592))
3284                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
3285                 else {
3286                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3287                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3288                         else
3289                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3290                 }
3291         }
3292
3293         return vgc;
3294 }
3295
3296 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3297                                   struct link_qual *qual, u8 vgc_level)
3298 {
3299         if (qual->vgc_level != vgc_level) {
3300                 if (rt2x00_rt(rt2x00dev, RT5592)) {
3301                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3302                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3303                 } else
3304                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3305                 qual->vgc_level = vgc_level;
3306                 qual->vgc_level_reg = vgc_level;
3307         }
3308 }
3309
3310 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3311 {
3312         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3313 }
3314 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3315
3316 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3317                        const u32 count)
3318 {
3319         u8 vgc;
3320
3321         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3322                 return;
3323         /*
3324          * When RSSI is better then -80 increase VGC level with 0x10, except
3325          * for rt5592 chip.
3326          */
3327
3328         vgc = rt2800_get_default_vgc(rt2x00dev);
3329
3330         if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3331                 vgc += 0x20;
3332         else if (qual->rssi > -80)
3333                 vgc += 0x10;
3334
3335         rt2800_set_vgc(rt2x00dev, qual, vgc);
3336 }
3337 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3338
3339 /*
3340  * Initialization functions.
3341  */
3342 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3343 {
3344         u32 reg;
3345         u16 eeprom;
3346         unsigned int i;
3347         int ret;
3348
3349         rt2800_disable_wpdma(rt2x00dev);
3350
3351         ret = rt2800_drv_init_registers(rt2x00dev);
3352         if (ret)
3353                 return ret;
3354
3355         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3356         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3357         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3358         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3359         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3360         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3361
3362         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3363         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3364         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3365         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3366         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3367         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3368
3369         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3370         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3371
3372         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3373
3374         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3375         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3376         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3377         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3378         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3379         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3380         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3381         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3382
3383         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3384
3385         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3386         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3387         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3388         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3389
3390         if (rt2x00_rt(rt2x00dev, RT3290)) {
3391                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3392                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3393                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3394                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3395                 }
3396
3397                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3398                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3399                         rt2x00_set_field32(&reg, LDO0_EN, 1);
3400                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3401                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3402                 }
3403
3404                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3405                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3406                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3407                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3408                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3409
3410                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3411                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3412                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3413
3414                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3415                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3416                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3417                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3418                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3419                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3420
3421                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3422                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3423                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3424         }
3425
3426         if (rt2x00_rt(rt2x00dev, RT3071) ||
3427             rt2x00_rt(rt2x00dev, RT3090) ||
3428             rt2x00_rt(rt2x00dev, RT3290) ||
3429             rt2x00_rt(rt2x00dev, RT3390)) {
3430
3431                 if (rt2x00_rt(rt2x00dev, RT3290))
3432                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3433                                               0x00000404);
3434                 else
3435                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3436                                               0x00000400);
3437
3438                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3439                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3440                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3441                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3442                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3443                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3444                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3445                                                       0x0000002c);
3446                         else
3447                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3448                                                       0x0000000f);
3449                 } else {
3450                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3451                 }
3452         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3453                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3454
3455                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3456                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3457                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3458                 } else {
3459                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3460                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3461                 }
3462         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3463                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3464                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3465                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3466         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3467                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3468                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3469                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3470         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3471                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3472                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3473         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3474                    rt2x00_rt(rt2x00dev, RT5392) ||
3475                    rt2x00_rt(rt2x00dev, RT5592)) {
3476                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3477                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3478                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3479         } else {
3480                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3481                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3482         }
3483
3484         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3485         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3486         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3487         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3488         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3489         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3490         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3491         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3492         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3493         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3494
3495         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3496         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3497         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3498         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3499         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3500
3501         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3502         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3503         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3504             rt2x00_rt(rt2x00dev, RT2883) ||
3505             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3506                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3507         else
3508                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3509         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3510         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3511         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3512
3513         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3514         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3515         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3516         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3517         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3518         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3519         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3520         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3521         rt2800_register_write(rt2x00dev, LED_CFG, reg);
3522
3523         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3524
3525         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3526         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3527         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3528         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3529         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3530         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3531         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3532         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3533
3534         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3535         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3536         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3537         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3538         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3539         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3540         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3541         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3542         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3543
3544         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3545         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3546         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3547         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3548         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3549         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3550         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3551         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3552         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3553         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3554         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3555         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3556
3557         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3558         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3559         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3560         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3561         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3562         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3563         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3564         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3565         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3566         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3567         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3568         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3569
3570         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3571         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3572         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3573         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3574         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3575         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3576         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3577         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3578         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3579         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3580         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3581         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3582
3583         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3584         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3585         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3586         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3587         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3588         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3589         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3590         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3591         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3592         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3593         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3594         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3595
3596         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3597         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3598         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3599         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3600         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3601         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3602         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3603         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3604         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3605         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3606         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3607         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3608
3609         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3610         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3611         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3612         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3613         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3614         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3615         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3616         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3617         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3618         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3619         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3620         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3621
3622         if (rt2x00_is_usb(rt2x00dev)) {
3623                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3624
3625                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3626                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3627                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3628                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3629                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3630                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3631                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3632                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3633                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3634                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3635                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3636         }
3637
3638         /*
3639          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3640          * although it is reserved.
3641          */
3642         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3643         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3644         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3645         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3646         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3647         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3648         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3649         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3650         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3651         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3652         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3653         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3654
3655         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3656         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3657
3658         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3659         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3660         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3661                            IEEE80211_MAX_RTS_THRESHOLD);
3662         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3663         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3664
3665         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3666
3667         /*
3668          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3669          * time should be set to 16. However, the original Ralink driver uses
3670          * 16 for both and indeed using a value of 10 for CCK SIFS results in
3671          * connection problems with 11g + CTS protection. Hence, use the same
3672          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3673          */
3674         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3675         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3676         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3677         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3678         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3679         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3680         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3681
3682         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3683
3684         /*
3685          * ASIC will keep garbage value after boot, clear encryption keys.
3686          */
3687         for (i = 0; i < 4; i++)
3688                 rt2800_register_write(rt2x00dev,
3689                                          SHARED_KEY_MODE_ENTRY(i), 0);
3690
3691         for (i = 0; i < 256; i++) {
3692                 rt2800_config_wcid(rt2x00dev, NULL, i);
3693                 rt2800_delete_wcid_attr(rt2x00dev, i);
3694                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3695         }
3696
3697         /*
3698          * Clear all beacons
3699          */
3700         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3701         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3702         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3703         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3704         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3705         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3706         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3707         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3708
3709         if (rt2x00_is_usb(rt2x00dev)) {
3710                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3711                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3712                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3713         } else if (rt2x00_is_pcie(rt2x00dev)) {
3714                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3715                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3716                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3717         }
3718
3719         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3720         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3721         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3722         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3723         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3724         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3725         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3726         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3727         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3728         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3729
3730         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3731         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3732         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3733         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3734         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3735         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3736         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3737         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3738         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3739         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3740
3741         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3742         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3743         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3744         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3745         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3746         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3747         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3748         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3749         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3750         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3751
3752         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3753         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3754         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3755         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3756         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3757         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3758
3759         /*
3760          * Do not force the BA window size, we use the TXWI to set it
3761          */
3762         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3763         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3764         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3765         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3766
3767         /*
3768          * We must clear the error counters.
3769          * These registers are cleared on read,
3770          * so we may pass a useless variable to store the value.
3771          */
3772         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3773         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3774         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3775         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3776         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3777         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3778
3779         /*
3780          * Setup leadtime for pre tbtt interrupt to 6ms
3781          */
3782         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3783         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3784         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3785
3786         /*
3787          * Set up channel statistics timer
3788          */
3789         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3790         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3791         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3792         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3793         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3794         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3795         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3796
3797         return 0;
3798 }
3799
3800 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3801 {
3802         unsigned int i;
3803         u32 reg;
3804
3805         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3806                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3807                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3808                         return 0;
3809
3810                 udelay(REGISTER_BUSY_DELAY);
3811         }
3812
3813         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3814         return -EACCES;
3815 }
3816
3817 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3818 {
3819         unsigned int i;
3820         u8 value;
3821
3822         /*
3823          * BBP was enabled after firmware was loaded,
3824          * but we need to reactivate it now.
3825          */
3826         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3827         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3828         msleep(1);
3829
3830         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3831                 rt2800_bbp_read(rt2x00dev, 0, &value);
3832                 if ((value != 0xff) && (value != 0x00))
3833                         return 0;
3834                 udelay(REGISTER_BUSY_DELAY);
3835         }
3836
3837         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3838         return -EACCES;
3839 }
3840
3841 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3842 {
3843         u8 value;
3844
3845         rt2800_bbp_read(rt2x00dev, 4, &value);
3846         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3847         rt2800_bbp_write(rt2x00dev, 4, value);
3848 }
3849
3850 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3851 {
3852         rt2800_bbp_write(rt2x00dev, 142, 1);
3853         rt2800_bbp_write(rt2x00dev, 143, 57);
3854 }
3855
3856 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3857 {
3858         const u8 glrt_table[] = {
3859                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3860                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3861                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3862                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3863                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3864                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3865                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3866                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3867                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
3868         };
3869         int i;
3870
3871         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3872                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3873                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3874         }
3875 };
3876
3877 static void rt2800_init_bbb_early(struct rt2x00_dev *rt2x00dev)
3878 {
3879         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3880         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3881         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3882         rt2800_bbp_write(rt2x00dev, 69, 0x12);
3883         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3884         rt2800_bbp_write(rt2x00dev, 73, 0x10);
3885         rt2800_bbp_write(rt2x00dev, 81, 0x37);
3886         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3887         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3888         rt2800_bbp_write(rt2x00dev, 84, 0x99);
3889         rt2800_bbp_write(rt2x00dev, 86, 0x00);
3890         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3891         rt2800_bbp_write(rt2x00dev, 92, 0x00);
3892         rt2800_bbp_write(rt2x00dev, 103, 0x00);
3893         rt2800_bbp_write(rt2x00dev, 105, 0x05);
3894         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3895 }
3896
3897 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3898 {
3899         int ant, div_mode;
3900         u16 eeprom;
3901         u8 value;
3902
3903         rt2800_init_bbb_early(rt2x00dev);
3904
3905         rt2800_bbp_read(rt2x00dev, 105, &value);
3906         rt2x00_set_field8(&value, BBP105_MLD,
3907                           rt2x00dev->default_ant.rx_chain_num == 2);
3908         rt2800_bbp_write(rt2x00dev, 105, value);
3909
3910         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3911
3912         rt2800_bbp_write(rt2x00dev, 20, 0x06);
3913         rt2800_bbp_write(rt2x00dev, 31, 0x08);
3914         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3915         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3916         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3917         rt2800_bbp_write(rt2x00dev, 70, 0x05);
3918         rt2800_bbp_write(rt2x00dev, 73, 0x13);
3919         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3920         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3921         rt2800_bbp_write(rt2x00dev, 76, 0x28);
3922         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3923         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3924         rt2800_bbp_write(rt2x00dev, 86, 0x38);
3925         rt2800_bbp_write(rt2x00dev, 88, 0x90);
3926         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3927         rt2800_bbp_write(rt2x00dev, 92, 0x02);
3928         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3929         rt2800_bbp_write(rt2x00dev, 98, 0x12);
3930         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3931         rt2800_bbp_write(rt2x00dev, 104, 0x92);
3932         /* FIXME BBP105 owerwrite */
3933         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3934         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3935         rt2800_bbp_write(rt2x00dev, 128, 0x12);
3936         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3937         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3938         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3939
3940         /* Initialize GLRT (Generalized Likehood Radio Test) */
3941         rt2800_init_bbp_5592_glrt(rt2x00dev);
3942
3943         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3944
3945         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3946         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
3947         ant = (div_mode == 3) ? 1 : 0;
3948         rt2800_bbp_read(rt2x00dev, 152, &value);
3949         if (ant == 0) {
3950                 /* Main antenna */
3951                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3952         } else {
3953                 /* Auxiliary antenna */
3954                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3955         }
3956         rt2800_bbp_write(rt2x00dev, 152, value);
3957
3958         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
3959                 rt2800_bbp_read(rt2x00dev, 254, &value);
3960                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
3961                 rt2800_bbp_write(rt2x00dev, 254, value);
3962         }
3963
3964         rt2800_init_freq_calibration(rt2x00dev);
3965
3966         rt2800_bbp_write(rt2x00dev, 84, 0x19);
3967         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
3968                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3969 }
3970
3971 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3972 {
3973         unsigned int i;
3974         u16 eeprom;
3975         u8 reg_id;
3976         u8 value;
3977
3978         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3979                      rt2800_wait_bbp_ready(rt2x00dev)))
3980                 return -EACCES;
3981
3982         if (rt2x00_rt(rt2x00dev, RT5592)) {
3983                 rt2800_init_bbp_5592(rt2x00dev);
3984                 return 0;
3985         }
3986
3987         if (rt2x00_rt(rt2x00dev, RT3352)) {
3988                 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3989                 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3990         }
3991
3992         if (rt2x00_rt(rt2x00dev, RT3290) ||
3993             rt2x00_rt(rt2x00dev, RT5390) ||
3994             rt2x00_rt(rt2x00dev, RT5392))
3995                 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3996
3997         if (rt2800_is_305x_soc(rt2x00dev) ||
3998             rt2x00_rt(rt2x00dev, RT3290) ||
3999             rt2x00_rt(rt2x00dev, RT3352) ||
4000             rt2x00_rt(rt2x00dev, RT3572) ||
4001             rt2x00_rt(rt2x00dev, RT5390) ||
4002             rt2x00_rt(rt2x00dev, RT5392))
4003                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4004
4005         if (rt2x00_rt(rt2x00dev, RT3352))
4006                 rt2800_bbp_write(rt2x00dev, 47, 0x48);
4007
4008         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4009         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4010
4011         if (rt2x00_rt(rt2x00dev, RT3290) ||
4012             rt2x00_rt(rt2x00dev, RT3352) ||
4013             rt2x00_rt(rt2x00dev, RT5390) ||
4014             rt2x00_rt(rt2x00dev, RT5392))
4015                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4016
4017         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4018                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4019                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4020         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
4021                    rt2x00_rt(rt2x00dev, RT3352) ||
4022                    rt2x00_rt(rt2x00dev, RT5390) ||
4023                    rt2x00_rt(rt2x00dev, RT5392)) {
4024                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4025                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4026                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4027                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4028
4029                 if (rt2x00_rt(rt2x00dev, RT3290))
4030                         rt2800_bbp_write(rt2x00dev, 77, 0x58);
4031                 else
4032                         rt2800_bbp_write(rt2x00dev, 77, 0x59);
4033         } else {
4034                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4035                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4036         }
4037
4038         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4039
4040         if (rt2x00_rt(rt2x00dev, RT3070) ||
4041             rt2x00_rt(rt2x00dev, RT3071) ||
4042             rt2x00_rt(rt2x00dev, RT3090) ||
4043             rt2x00_rt(rt2x00dev, RT3390) ||
4044             rt2x00_rt(rt2x00dev, RT3572) ||
4045             rt2x00_rt(rt2x00dev, RT5390) ||
4046             rt2x00_rt(rt2x00dev, RT5392)) {
4047                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4048                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4049                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4050         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4051                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4052                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4053         } else if (rt2x00_rt(rt2x00dev, RT3290)) {
4054                 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4055                 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4056                 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4057                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4058         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4059                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4060                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4061                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4062         } else {
4063                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4064         }
4065
4066         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4067         if (rt2x00_rt(rt2x00dev, RT3290) ||
4068             rt2x00_rt(rt2x00dev, RT5390) ||
4069             rt2x00_rt(rt2x00dev, RT5392))
4070                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4071         else
4072                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4073
4074         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4075                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4076         else if (rt2x00_rt(rt2x00dev, RT3290) ||
4077                  rt2x00_rt(rt2x00dev, RT5390) ||
4078                  rt2x00_rt(rt2x00dev, RT5392))
4079                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4080         else
4081                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4082
4083         if (rt2x00_rt(rt2x00dev, RT3290) ||
4084             rt2x00_rt(rt2x00dev, RT3352) ||
4085             rt2x00_rt(rt2x00dev, RT5390) ||
4086             rt2x00_rt(rt2x00dev, RT5392))
4087                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4088         else
4089                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4090
4091         if (rt2x00_rt(rt2x00dev, RT3352) ||
4092             rt2x00_rt(rt2x00dev, RT5392))
4093                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4094
4095         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4096
4097         if (rt2x00_rt(rt2x00dev, RT3290) ||
4098             rt2x00_rt(rt2x00dev, RT3352) ||
4099             rt2x00_rt(rt2x00dev, RT5390) ||
4100             rt2x00_rt(rt2x00dev, RT5392))
4101                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4102         else
4103                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4104
4105         if (rt2x00_rt(rt2x00dev, RT5392)) {
4106                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4107                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4108         }
4109
4110         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4111             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4112             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
4113             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
4114             rt2x00_rt(rt2x00dev, RT3290) ||
4115             rt2x00_rt(rt2x00dev, RT3352) ||
4116             rt2x00_rt(rt2x00dev, RT3572) ||
4117             rt2x00_rt(rt2x00dev, RT5390) ||
4118             rt2x00_rt(rt2x00dev, RT5392) ||
4119             rt2800_is_305x_soc(rt2x00dev))
4120                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4121         else
4122                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4123
4124         if (rt2x00_rt(rt2x00dev, RT3290) ||
4125             rt2x00_rt(rt2x00dev, RT3352) ||
4126             rt2x00_rt(rt2x00dev, RT5390) ||
4127             rt2x00_rt(rt2x00dev, RT5392))
4128                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4129
4130         if (rt2800_is_305x_soc(rt2x00dev))
4131                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4132         else if (rt2x00_rt(rt2x00dev, RT3290))
4133                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4134         else if (rt2x00_rt(rt2x00dev, RT3352))
4135                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4136         else if (rt2x00_rt(rt2x00dev, RT5390) ||
4137                  rt2x00_rt(rt2x00dev, RT5392))
4138                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4139         else
4140                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4141
4142         if (rt2x00_rt(rt2x00dev, RT3290) ||
4143             rt2x00_rt(rt2x00dev, RT5390))
4144                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4145         else if (rt2x00_rt(rt2x00dev, RT3352))
4146                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4147         else if (rt2x00_rt(rt2x00dev, RT5392))
4148                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4149         else
4150                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4151
4152         if (rt2x00_rt(rt2x00dev, RT3352))
4153                 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4154
4155         if (rt2x00_rt(rt2x00dev, RT3290) ||
4156             rt2x00_rt(rt2x00dev, RT5390) ||
4157             rt2x00_rt(rt2x00dev, RT5392))
4158                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4159
4160         if (rt2x00_rt(rt2x00dev, RT5392)) {
4161                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4162                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4163         }
4164
4165         if (rt2x00_rt(rt2x00dev, RT3352))
4166                 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4167
4168         if (rt2x00_rt(rt2x00dev, RT3071) ||
4169             rt2x00_rt(rt2x00dev, RT3090) ||
4170             rt2x00_rt(rt2x00dev, RT3390) ||
4171             rt2x00_rt(rt2x00dev, RT3572) ||
4172             rt2x00_rt(rt2x00dev, RT5390) ||
4173             rt2x00_rt(rt2x00dev, RT5392)) {
4174                 rt2800_bbp_read(rt2x00dev, 138, &value);
4175
4176                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4177                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4178                         value |= 0x20;
4179                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4180                         value &= ~0x02;
4181
4182                 rt2800_bbp_write(rt2x00dev, 138, value);
4183         }
4184
4185         if (rt2x00_rt(rt2x00dev, RT3290)) {
4186                 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4187                 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4188                 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4189                 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4190                 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4191                 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4192                 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4193                 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4194                 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4195                 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4196
4197                 rt2800_bbp_read(rt2x00dev, 47, &value);
4198                 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4199                 rt2800_bbp_write(rt2x00dev, 47, value);
4200
4201                 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4202                 rt2800_bbp_read(rt2x00dev, 3, &value);
4203                 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4204                 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4205                 rt2800_bbp_write(rt2x00dev, 3, value);
4206         }
4207
4208         if (rt2x00_rt(rt2x00dev, RT3352)) {
4209                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4210                 /* Set ITxBF timeout to 0x9c40=1000msec */
4211                 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4212                 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4213                 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4214                 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4215                 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4216                 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4217                 /* Reprogram the inband interface to put right values in RXWI */
4218                 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4219                 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4220                 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4221                 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4222                 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4223                 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4224                 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4225                 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4226
4227                 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4228         }
4229
4230         if (rt2x00_rt(rt2x00dev, RT5390) ||
4231             rt2x00_rt(rt2x00dev, RT5392)) {
4232                 int ant, div_mode;
4233
4234                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4235                 div_mode = rt2x00_get_field16(eeprom,
4236                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
4237                 ant = (div_mode == 3) ? 1 : 0;
4238
4239                 /* check if this is a Bluetooth combo card */
4240                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4241                         u32 reg;
4242
4243                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4244                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4245                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4246                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4247                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4248                         if (ant == 0)
4249                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4250                         else if (ant == 1)
4251                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4252                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4253                 }
4254
4255                 /* This chip has hardware antenna diversity*/
4256                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4257                         rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4258                         rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4259                         rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4260                 }
4261
4262                 rt2800_bbp_read(rt2x00dev, 152, &value);
4263                 if (ant == 0)
4264                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4265                 else
4266                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4267                 rt2800_bbp_write(rt2x00dev, 152, value);
4268
4269                 rt2800_init_freq_calibration(rt2x00dev);
4270         }
4271
4272         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4273                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4274
4275                 if (eeprom != 0xffff && eeprom != 0x0000) {
4276                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4277                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4278                         rt2800_bbp_write(rt2x00dev, reg_id, value);
4279                 }
4280         }
4281
4282         return 0;
4283 }
4284
4285 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
4286                                 bool bw40, u8 rfcsr24, u8 filter_target)
4287 {
4288         unsigned int i;
4289         u8 bbp;
4290         u8 rfcsr;
4291         u8 passband;
4292         u8 stopband;
4293         u8 overtuned = 0;
4294
4295         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4296
4297         rt2800_bbp_read(rt2x00dev, 4, &bbp);
4298         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4299         rt2800_bbp_write(rt2x00dev, 4, bbp);
4300
4301         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4302         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4303         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4304
4305         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4306         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4307         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4308
4309         /*
4310          * Set power & frequency of passband test tone
4311          */
4312         rt2800_bbp_write(rt2x00dev, 24, 0);
4313
4314         for (i = 0; i < 100; i++) {
4315                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4316                 msleep(1);
4317
4318                 rt2800_bbp_read(rt2x00dev, 55, &passband);
4319                 if (passband)
4320                         break;
4321         }
4322
4323         /*
4324          * Set power & frequency of stopband test tone
4325          */
4326         rt2800_bbp_write(rt2x00dev, 24, 0x06);
4327
4328         for (i = 0; i < 100; i++) {
4329                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4330                 msleep(1);
4331
4332                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4333
4334                 if ((passband - stopband) <= filter_target) {
4335                         rfcsr24++;
4336                         overtuned += ((passband - stopband) == filter_target);
4337                 } else
4338                         break;
4339
4340                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4341         }
4342
4343         rfcsr24 -= !!overtuned;
4344
4345         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4346         return rfcsr24;
4347 }
4348
4349 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4350 {
4351         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4352         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4353         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4354         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4355         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4356         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4357         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4358         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4359         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4360         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4361         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4362         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4363         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4364         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4365         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4366         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4367         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4368         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4369         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4370         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4371         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4372         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4373         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4374         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4375         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4376         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4377         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4378         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4379         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4380         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4381         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4382         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4383 }
4384
4385 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4386 {
4387         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4388         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4389         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4390         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4391         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4392         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4393         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4394         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4395         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4396         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4397         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4398         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4399         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4400         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4401         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4402         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4403         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4404         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4405         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4406 }
4407
4408 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4409 {
4410         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4411         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4412         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4413         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4414         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4415         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4416         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4417         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4418         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4419         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4420         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4421         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4422         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4423         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4424         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4425         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4426         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4427         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4428         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4429         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4430         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4431         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4432         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4433         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4434         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4435         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4436         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4437         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4438         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4439         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4440         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4441         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4442         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4443         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4444         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4445         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4446         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4447         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4448         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4449         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4450         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4451         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4452         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4453         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4454         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4455         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4456 }
4457
4458 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4459 {
4460         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4461         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4462         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4463         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4464         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4465         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4466         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4467         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4468         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4469         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4470         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4471         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4472         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4473         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4474         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4475         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4476         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4477         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4478         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4479         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4480         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4481         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4482         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4483         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4484         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4485         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4486         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4487         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4488         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4489         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4490         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4491         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4492         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4493         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4494         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4495         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4496         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4497         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4498         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4499         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4500         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4501         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4502         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4503         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4504         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4505         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4506         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4507         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4508         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4509         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4510         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4511         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4512         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4513         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4514         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4515         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4516         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4517         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4518         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4519         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4520         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4521         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4522         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4523 }
4524
4525 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4526 {
4527         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4528         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4529         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4530         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4531         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4532         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4533         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4534         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4535         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4536         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4537         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4538         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4539         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4540         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4541         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4542         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4543         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4544         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4545         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4546         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4547         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4548         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4549         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4550         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4551         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4552         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4553         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4554         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4555         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4556         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4557         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4558         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4559 }
4560
4561 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4562 {
4563         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4564         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4565         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4566         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4567         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4568         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4569         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4570         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4571         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4572         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4573         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4574         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4575         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4576         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4577         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4578         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4579         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4580         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4581         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4582         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4583         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4584         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4585         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4586         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4587         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4588         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4589         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4590         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4591         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4592         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4593         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4594 }
4595
4596 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4597 {
4598         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4599         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4600         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4601         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4602         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4603                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4604         else
4605                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4606         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4607         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4608         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4609         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4610         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4611         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4612         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4613         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4614         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4615         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4616
4617         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4618         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4619         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4620         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4621         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4622         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4623                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4624         else
4625                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4626         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4627         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4628         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4629         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4630
4631         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4632         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4633         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4634         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4635         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4636         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4637         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4638         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4639         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4640         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4641
4642         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4643                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4644         else
4645                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4646         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4647         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4648         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4649         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4650         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4651         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4652                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4653         else
4654                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4655         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4656         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4657         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4658
4659         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4660         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4661                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4662         else
4663                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4664         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4665         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4666         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4667         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4668         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4669         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4670
4671         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4672         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4673                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4674         else
4675                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4676         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4677         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4678 }
4679
4680 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4681 {
4682         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4683         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4684         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4685         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4686         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4687         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4688         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4689         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4690         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4691         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4692         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4693         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4694         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4695         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4696         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4697         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4698         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4699         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4700         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4701         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4702         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4703         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4704         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4705         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4706         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4707         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4708         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4709         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4710         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4711         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4712         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4713         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4714         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4715         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4716         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4717         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4718         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4719         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4720         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4721         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4722         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4723         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4724         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4725         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4726         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4727         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4728         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4729         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4730         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4731         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4732         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4733         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4734         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4735         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4736         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4737         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4738         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4739         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4740         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4741 }
4742
4743 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
4744 {
4745         u8 reg;
4746         u16 eeprom;
4747
4748         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
4749         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4750         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4751         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4752         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
4753         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4754         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4755         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4756         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4757         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4758         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
4759         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
4760         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
4761         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4762         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4763         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4764         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4765         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4766         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4767         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
4768         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
4769         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4770
4771         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4772         msleep(1);
4773
4774         rt2800_adjust_freq_offset(rt2x00dev);
4775
4776         rt2800_bbp_read(rt2x00dev, 138, &reg);
4777
4778         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
4779         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4780         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4781                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4782         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4783                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4784
4785         rt2800_bbp_write(rt2x00dev, 138, reg);
4786
4787         /* Enable DC filter */
4788         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4789                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4790
4791         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4792         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4793         rt2800_rfcsr_write(rt2x00dev, 38, reg);
4794
4795         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4796         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4797         rt2800_rfcsr_write(rt2x00dev, 39, reg);
4798
4799         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4800
4801         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4802         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4803         rt2800_rfcsr_write(rt2x00dev, 30, reg);
4804 }
4805
4806 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4807 {
4808         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4809         u8 rfcsr;
4810         u8 bbp;
4811         u32 reg;
4812         u16 eeprom;
4813
4814         if (!rt2x00_rt(rt2x00dev, RT3070) &&
4815             !rt2x00_rt(rt2x00dev, RT3071) &&
4816             !rt2x00_rt(rt2x00dev, RT3090) &&
4817             !rt2x00_rt(rt2x00dev, RT3290) &&
4818             !rt2x00_rt(rt2x00dev, RT3352) &&
4819             !rt2x00_rt(rt2x00dev, RT3390) &&
4820             !rt2x00_rt(rt2x00dev, RT3572) &&
4821             !rt2x00_rt(rt2x00dev, RT5390) &&
4822             !rt2x00_rt(rt2x00dev, RT5392) &&
4823             !rt2x00_rt(rt2x00dev, RT5392) &&
4824             !rt2x00_rt(rt2x00dev, RT5592) &&
4825             !rt2800_is_305x_soc(rt2x00dev))
4826                 return 0;
4827
4828         /*
4829          * Init RF calibration.
4830          */
4831
4832         if (rt2x00_rt(rt2x00dev, RT3290) ||
4833             rt2x00_rt(rt2x00dev, RT5390) ||
4834             rt2x00_rt(rt2x00dev, RT5392)) {
4835                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4836                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4837                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4838                 msleep(1);
4839                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4840                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4841         } else {
4842                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4843                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4844                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4845                 msleep(1);
4846                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4847                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4848         }
4849
4850         if (rt2800_is_305x_soc(rt2x00dev)) {
4851                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4852                 return 0;
4853         }
4854
4855         switch (rt2x00dev->chip.rt) {
4856         case RT3070:
4857         case RT3071:
4858         case RT3090:
4859                 rt2800_init_rfcsr_30xx(rt2x00dev);
4860                 break;
4861         case RT3290:
4862                 rt2800_init_rfcsr_3290(rt2x00dev);
4863                 break;
4864         case RT3352:
4865                 rt2800_init_rfcsr_3352(rt2x00dev);
4866                 break;
4867         case RT3390:
4868                 rt2800_init_rfcsr_3390(rt2x00dev);
4869                 break;
4870         case RT3572:
4871                 rt2800_init_rfcsr_3572(rt2x00dev);
4872                 break;
4873         case RT5390:
4874                 rt2800_init_rfcsr_5390(rt2x00dev);
4875                 break;
4876         case RT5392:
4877                 rt2800_init_rfcsr_5392(rt2x00dev);
4878                 break;
4879         case RT5592:
4880                 rt2800_init_rfcsr_5592(rt2x00dev);
4881                 return 0;
4882         }
4883
4884         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4885                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4886                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4887                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4888                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4889         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4890                    rt2x00_rt(rt2x00dev, RT3090)) {
4891                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4892
4893                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4894                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4895                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4896
4897                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4898                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4899                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4900                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4901                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4902                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4903                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4904                         else
4905                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4906                 }
4907                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4908
4909                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4910                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4911                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4912         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4913                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4914                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4915                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4916         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4917                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4918                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4919                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4920
4921                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4922                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4923                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4924                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4925                 msleep(1);
4926                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4927                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4928                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4929                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4930         }
4931
4932         /*
4933          * Set RX Filter calibration for 20MHz and 40MHz
4934          */
4935         if (rt2x00_rt(rt2x00dev, RT3070)) {
4936                 drv_data->calibration_bw20 =
4937                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4938                 drv_data->calibration_bw40 =
4939                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4940         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4941                    rt2x00_rt(rt2x00dev, RT3090) ||
4942                    rt2x00_rt(rt2x00dev, RT3352) ||
4943                    rt2x00_rt(rt2x00dev, RT3390) ||
4944                    rt2x00_rt(rt2x00dev, RT3572)) {
4945                 drv_data->calibration_bw20 =
4946                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4947                 drv_data->calibration_bw40 =
4948                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4949         }
4950
4951         /*
4952          * Save BBP 25 & 26 values for later use in channel switching
4953          */
4954         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4955         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4956
4957         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4958             !rt2x00_rt(rt2x00dev, RT5392)) {
4959                 /*
4960                  * Set back to initial state
4961                  */
4962                 rt2800_bbp_write(rt2x00dev, 24, 0);
4963
4964                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4965                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4966                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4967
4968                 /*
4969                  * Set BBP back to BW20
4970                  */
4971                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4972                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4973                 rt2800_bbp_write(rt2x00dev, 4, bbp);
4974         }
4975
4976         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4977             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4978             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4979             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E) ||
4980             rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
4981                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4982
4983         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4984         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4985         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4986
4987         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4988             !rt2x00_rt(rt2x00dev, RT5392)) {
4989                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4990                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4991                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4992                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4993                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4994                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4995                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4996                                       &rt2x00dev->cap_flags))
4997                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4998                 }
4999                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5000                                   drv_data->txmixer_gain_24g);
5001                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5002         }
5003
5004         if (rt2x00_rt(rt2x00dev, RT3090) ||
5005             rt2x00_rt(rt2x00dev, RT5592)) {
5006                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5007
5008                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5009                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5010                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5011                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5012                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5013                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5014
5015                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5016         }
5017
5018         if (rt2x00_rt(rt2x00dev, RT3071) ||
5019             rt2x00_rt(rt2x00dev, RT3090) ||
5020             rt2x00_rt(rt2x00dev, RT3390)) {
5021                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5022                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5023                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5024                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5025                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5026                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5027                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5028
5029                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5030                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5031                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5032
5033                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5034                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5035                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5036
5037                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5038                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5039                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5040         }
5041
5042         if (rt2x00_rt(rt2x00dev, RT3070)) {
5043                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5044                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5045                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5046                 else
5047                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5048                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5049                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5050                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5051                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5052         }
5053
5054         if (rt2x00_rt(rt2x00dev, RT3290)) {
5055                 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
5056                 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
5057                 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
5058         }
5059
5060         if (rt2x00_rt(rt2x00dev, RT5390) ||
5061             rt2x00_rt(rt2x00dev, RT5392) ||
5062             rt2x00_rt(rt2x00dev, RT5592)) {
5063                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5064                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5065                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5066
5067                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5068                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5069                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5070
5071                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5072                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5073                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5074         }
5075
5076         return 0;
5077 }
5078
5079 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5080 {
5081         u32 reg;
5082         u16 word;
5083
5084         /*
5085          * Initialize all registers.
5086          */
5087         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
5088                      rt2800_init_registers(rt2x00dev)))
5089                 return -EIO;
5090
5091         /*
5092          * Send signal to firmware during boot time.
5093          */
5094         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5095         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5096         if (rt2x00_is_usb(rt2x00dev)) {
5097                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5098                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5099         }
5100         msleep(1);
5101
5102         if (unlikely(rt2800_init_bbp(rt2x00dev) ||
5103                      rt2800_init_rfcsr(rt2x00dev)))
5104                 return -EIO;
5105
5106         if (rt2x00_is_usb(rt2x00dev) &&
5107             (rt2x00_rt(rt2x00dev, RT3070) ||
5108              rt2x00_rt(rt2x00dev, RT3071) ||
5109              rt2x00_rt(rt2x00dev, RT3572))) {
5110                 udelay(200);
5111                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5112                 udelay(10);
5113         }
5114
5115         /*
5116          * Enable RX.
5117          */
5118         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5119         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5120         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5121         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5122
5123         udelay(50);
5124
5125         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5126         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5127         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5128         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5129         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5130         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5131
5132         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5133         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5134         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5135         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5136
5137         /*
5138          * Initialize LED control
5139          */
5140         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
5141         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
5142                            word & 0xff, (word >> 8) & 0xff);
5143
5144         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5145         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
5146                            word & 0xff, (word >> 8) & 0xff);
5147
5148         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5149         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
5150                            word & 0xff, (word >> 8) & 0xff);
5151
5152         return 0;
5153 }
5154 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5155
5156 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5157 {
5158         u32 reg;
5159
5160         rt2800_disable_wpdma(rt2x00dev);
5161
5162         /* Wait for DMA, ignore error */
5163         rt2800_wait_wpdma_ready(rt2x00dev);
5164
5165         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5166         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5167         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5168         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5169 }
5170 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
5171
5172 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5173 {
5174         u32 reg;
5175         u16 efuse_ctrl_reg;
5176
5177         if (rt2x00_rt(rt2x00dev, RT3290))
5178                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5179         else
5180                 efuse_ctrl_reg = EFUSE_CTRL;
5181
5182         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
5183         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5184 }
5185 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5186
5187 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5188 {
5189         u32 reg;
5190         u16 efuse_ctrl_reg;
5191         u16 efuse_data0_reg;
5192         u16 efuse_data1_reg;
5193         u16 efuse_data2_reg;
5194         u16 efuse_data3_reg;
5195
5196         if (rt2x00_rt(rt2x00dev, RT3290)) {
5197                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5198                 efuse_data0_reg = EFUSE_DATA0_3290;
5199                 efuse_data1_reg = EFUSE_DATA1_3290;
5200                 efuse_data2_reg = EFUSE_DATA2_3290;
5201                 efuse_data3_reg = EFUSE_DATA3_3290;
5202         } else {
5203                 efuse_ctrl_reg = EFUSE_CTRL;
5204                 efuse_data0_reg = EFUSE_DATA0;
5205                 efuse_data1_reg = EFUSE_DATA1;
5206                 efuse_data2_reg = EFUSE_DATA2;
5207                 efuse_data3_reg = EFUSE_DATA3;
5208         }
5209         mutex_lock(&rt2x00dev->csr_mutex);
5210
5211         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5212         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5213         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5214         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5215         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5216
5217         /* Wait until the EEPROM has been loaded */
5218         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5219         /* Apparently the data is read from end to start */
5220         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5221         /* The returned value is in CPU order, but eeprom is le */
5222         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5223         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5224         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5225         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5226         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5227         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5228         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5229
5230         mutex_unlock(&rt2x00dev->csr_mutex);
5231 }
5232
5233 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5234 {
5235         unsigned int i;
5236
5237         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5238                 rt2800_efuse_read(rt2x00dev, i);
5239
5240         return 0;
5241 }
5242 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5243
5244 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5245 {
5246         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5247         u16 word;
5248         u8 *mac;
5249         u8 default_lna_gain;
5250         int retval;
5251
5252         /*
5253          * Read the EEPROM.
5254          */
5255         retval = rt2800_read_eeprom(rt2x00dev);
5256         if (retval)
5257                 return retval;
5258
5259         /*
5260          * Start validation of the data that has been read.
5261          */
5262         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5263         if (!is_valid_ether_addr(mac)) {
5264                 eth_random_addr(mac);
5265                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
5266         }
5267
5268         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5269         if (word == 0xffff) {
5270                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5271                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5272                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5273                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5274                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5275         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5276                    rt2x00_rt(rt2x00dev, RT2872)) {
5277                 /*
5278                  * There is a max of 2 RX streams for RT28x0 series
5279                  */
5280                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5281                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5282                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5283         }
5284
5285         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5286         if (word == 0xffff) {
5287                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5288                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5289                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5290                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5291                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5292                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5293                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5294                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5295                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5296                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5297                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5298                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5299                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5300                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5301                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5302                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5303                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
5304         }
5305
5306         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5307         if ((word & 0x00ff) == 0x00ff) {
5308                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5309                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5310                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
5311         }
5312         if ((word & 0xff00) == 0xff00) {
5313                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5314                                    LED_MODE_TXRX_ACTIVITY);
5315                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5316                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5317                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5318                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5319                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5320                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
5321         }
5322
5323         /*
5324          * During the LNA validation we are going to use
5325          * lna0 as correct value. Note that EEPROM_LNA
5326          * is never validated.
5327          */
5328         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5329         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5330
5331         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5332         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5333                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5334         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5335                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5336         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5337
5338         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5339         if ((word & 0x00ff) != 0x00ff) {
5340                 drv_data->txmixer_gain_24g =
5341                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5342         } else {
5343                 drv_data->txmixer_gain_24g = 0;
5344         }
5345
5346         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5347         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5348                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5349         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5350             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5351                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5352                                    default_lna_gain);
5353         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5354
5355         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5356         if ((word & 0x00ff) != 0x00ff) {
5357                 drv_data->txmixer_gain_5g =
5358                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5359         } else {
5360                 drv_data->txmixer_gain_5g = 0;
5361         }
5362
5363         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5364         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5365                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5366         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5367                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5368         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5369
5370         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5371         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5372                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5373         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5374             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5375                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5376                                    default_lna_gain);
5377         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5378
5379         return 0;
5380 }
5381
5382 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5383 {
5384         u32 reg;
5385         u16 value;
5386         u16 eeprom;
5387
5388         /*
5389          * Read EEPROM word for configuration.
5390          */
5391         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5392
5393         /*
5394          * Identify RF chipset by EEPROM value
5395          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5396          * RT53xx: defined in "EEPROM_CHIP_ID" field
5397          */
5398         if (rt2x00_rt(rt2x00dev, RT3290))
5399                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
5400         else
5401                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
5402
5403         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
5404             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
5405             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
5406                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
5407         else
5408                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5409
5410         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
5411                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
5412
5413         switch (rt2x00dev->chip.rt) {
5414         case RT2860:
5415         case RT2872:
5416         case RT2883:
5417         case RT3070:
5418         case RT3071:
5419         case RT3090:
5420         case RT3290:
5421         case RT3352:
5422         case RT3390:
5423         case RT3572:
5424         case RT5390:
5425         case RT5392:
5426         case RT5592:
5427                 break;
5428         default:
5429                 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
5430                 return -ENODEV;
5431         }
5432
5433         switch (rt2x00dev->chip.rf) {
5434         case RF2820:
5435         case RF2850:
5436         case RF2720:
5437         case RF2750:
5438         case RF3020:
5439         case RF2020:
5440         case RF3021:
5441         case RF3022:
5442         case RF3052:
5443         case RF3290:
5444         case RF3320:
5445         case RF3322:
5446         case RF5360:
5447         case RF5370:
5448         case RF5372:
5449         case RF5390:
5450         case RF5392:
5451         case RF5592:
5452                 break;
5453         default:
5454                 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
5455                       rt2x00dev->chip.rf);
5456                 return -ENODEV;
5457         }
5458
5459         /*
5460          * Identify default antenna configuration.
5461          */
5462         rt2x00dev->default_ant.tx_chain_num =
5463             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5464         rt2x00dev->default_ant.rx_chain_num =
5465             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5466
5467         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5468
5469         if (rt2x00_rt(rt2x00dev, RT3070) ||
5470             rt2x00_rt(rt2x00dev, RT3090) ||
5471             rt2x00_rt(rt2x00dev, RT3352) ||
5472             rt2x00_rt(rt2x00dev, RT3390)) {
5473                 value = rt2x00_get_field16(eeprom,
5474                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5475                 switch (value) {
5476                 case 0:
5477                 case 1:
5478                 case 2:
5479                         rt2x00dev->default_ant.tx = ANTENNA_A;
5480                         rt2x00dev->default_ant.rx = ANTENNA_A;
5481                         break;
5482                 case 3:
5483                         rt2x00dev->default_ant.tx = ANTENNA_A;
5484                         rt2x00dev->default_ant.rx = ANTENNA_B;
5485                         break;
5486                 }
5487         } else {
5488                 rt2x00dev->default_ant.tx = ANTENNA_A;
5489                 rt2x00dev->default_ant.rx = ANTENNA_A;
5490         }
5491
5492         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5493                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5494                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5495         }
5496
5497         /*
5498          * Determine external LNA informations.
5499          */
5500         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5501                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5502         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5503                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5504
5505         /*
5506          * Detect if this device has an hardware controlled radio.
5507          */
5508         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5509                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5510
5511         /*
5512          * Detect if this device has Bluetooth co-existence.
5513          */
5514         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5515                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5516
5517         /*
5518          * Read frequency offset and RF programming sequence.
5519          */
5520         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5521         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5522
5523         /*
5524          * Store led settings, for correct led behaviour.
5525          */
5526 #ifdef CONFIG_RT2X00_LIB_LEDS
5527         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5528         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5529         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5530
5531         rt2x00dev->led_mcu_reg = eeprom;
5532 #endif /* CONFIG_RT2X00_LIB_LEDS */
5533
5534         /*
5535          * Check if support EIRP tx power limit feature.
5536          */
5537         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5538
5539         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5540                                         EIRP_MAX_TX_POWER_LIMIT)
5541                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5542
5543         return 0;
5544 }
5545
5546 /*
5547  * RF value list for rt28xx
5548  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5549  */
5550 static const struct rf_channel rf_vals[] = {
5551         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5552         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5553         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5554         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5555         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5556         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5557         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5558         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5559         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5560         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5561         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5562         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5563         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5564         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5565
5566         /* 802.11 UNI / HyperLan 2 */
5567         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5568         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5569         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5570         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5571         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5572         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5573         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5574         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5575         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5576         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5577         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5578         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5579
5580         /* 802.11 HyperLan 2 */
5581         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5582         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5583         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5584         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5585         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5586         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5587         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5588         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5589         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5590         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5591         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5592         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5593         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5594         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5595         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5596         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5597
5598         /* 802.11 UNII */
5599         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5600         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5601         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5602         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5603         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5604         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5605         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5606         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5607         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5608         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5609         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5610
5611         /* 802.11 Japan */
5612         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5613         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5614         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5615         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5616         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5617         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5618         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5619 };
5620
5621 /*
5622  * RF value list for rt3xxx
5623  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5624  */
5625 static const struct rf_channel rf_vals_3x[] = {
5626         {1,  241, 2, 2 },
5627         {2,  241, 2, 7 },
5628         {3,  242, 2, 2 },
5629         {4,  242, 2, 7 },
5630         {5,  243, 2, 2 },
5631         {6,  243, 2, 7 },
5632         {7,  244, 2, 2 },
5633         {8,  244, 2, 7 },
5634         {9,  245, 2, 2 },
5635         {10, 245, 2, 7 },
5636         {11, 246, 2, 2 },
5637         {12, 246, 2, 7 },
5638         {13, 247, 2, 2 },
5639         {14, 248, 2, 4 },
5640
5641         /* 802.11 UNI / HyperLan 2 */
5642         {36, 0x56, 0, 4},
5643         {38, 0x56, 0, 6},
5644         {40, 0x56, 0, 8},
5645         {44, 0x57, 0, 0},
5646         {46, 0x57, 0, 2},
5647         {48, 0x57, 0, 4},
5648         {52, 0x57, 0, 8},
5649         {54, 0x57, 0, 10},
5650         {56, 0x58, 0, 0},
5651         {60, 0x58, 0, 4},
5652         {62, 0x58, 0, 6},
5653         {64, 0x58, 0, 8},
5654
5655         /* 802.11 HyperLan 2 */
5656         {100, 0x5b, 0, 8},
5657         {102, 0x5b, 0, 10},
5658         {104, 0x5c, 0, 0},
5659         {108, 0x5c, 0, 4},
5660         {110, 0x5c, 0, 6},
5661         {112, 0x5c, 0, 8},
5662         {116, 0x5d, 0, 0},
5663         {118, 0x5d, 0, 2},
5664         {120, 0x5d, 0, 4},
5665         {124, 0x5d, 0, 8},
5666         {126, 0x5d, 0, 10},
5667         {128, 0x5e, 0, 0},
5668         {132, 0x5e, 0, 4},
5669         {134, 0x5e, 0, 6},
5670         {136, 0x5e, 0, 8},
5671         {140, 0x5f, 0, 0},
5672
5673         /* 802.11 UNII */
5674         {149, 0x5f, 0, 9},
5675         {151, 0x5f, 0, 11},
5676         {153, 0x60, 0, 1},
5677         {157, 0x60, 0, 5},
5678         {159, 0x60, 0, 7},
5679         {161, 0x60, 0, 9},
5680         {165, 0x61, 0, 1},
5681         {167, 0x61, 0, 3},
5682         {169, 0x61, 0, 5},
5683         {171, 0x61, 0, 7},
5684         {173, 0x61, 0, 9},
5685 };
5686
5687 static const struct rf_channel rf_vals_5592_xtal20[] = {
5688         /* Channel, N, K, mod, R */
5689         {1, 482, 4, 10, 3},
5690         {2, 483, 4, 10, 3},
5691         {3, 484, 4, 10, 3},
5692         {4, 485, 4, 10, 3},
5693         {5, 486, 4, 10, 3},
5694         {6, 487, 4, 10, 3},
5695         {7, 488, 4, 10, 3},
5696         {8, 489, 4, 10, 3},
5697         {9, 490, 4, 10, 3},
5698         {10, 491, 4, 10, 3},
5699         {11, 492, 4, 10, 3},
5700         {12, 493, 4, 10, 3},
5701         {13, 494, 4, 10, 3},
5702         {14, 496, 8, 10, 3},
5703         {36, 172, 8, 12, 1},
5704         {38, 173, 0, 12, 1},
5705         {40, 173, 4, 12, 1},
5706         {42, 173, 8, 12, 1},
5707         {44, 174, 0, 12, 1},
5708         {46, 174, 4, 12, 1},
5709         {48, 174, 8, 12, 1},
5710         {50, 175, 0, 12, 1},
5711         {52, 175, 4, 12, 1},
5712         {54, 175, 8, 12, 1},
5713         {56, 176, 0, 12, 1},
5714         {58, 176, 4, 12, 1},
5715         {60, 176, 8, 12, 1},
5716         {62, 177, 0, 12, 1},
5717         {64, 177, 4, 12, 1},
5718         {100, 183, 4, 12, 1},
5719         {102, 183, 8, 12, 1},
5720         {104, 184, 0, 12, 1},
5721         {106, 184, 4, 12, 1},
5722         {108, 184, 8, 12, 1},
5723         {110, 185, 0, 12, 1},
5724         {112, 185, 4, 12, 1},
5725         {114, 185, 8, 12, 1},
5726         {116, 186, 0, 12, 1},
5727         {118, 186, 4, 12, 1},
5728         {120, 186, 8, 12, 1},
5729         {122, 187, 0, 12, 1},
5730         {124, 187, 4, 12, 1},
5731         {126, 187, 8, 12, 1},
5732         {128, 188, 0, 12, 1},
5733         {130, 188, 4, 12, 1},
5734         {132, 188, 8, 12, 1},
5735         {134, 189, 0, 12, 1},
5736         {136, 189, 4, 12, 1},
5737         {138, 189, 8, 12, 1},
5738         {140, 190, 0, 12, 1},
5739         {149, 191, 6, 12, 1},
5740         {151, 191, 10, 12, 1},
5741         {153, 192, 2, 12, 1},
5742         {155, 192, 6, 12, 1},
5743         {157, 192, 10, 12, 1},
5744         {159, 193, 2, 12, 1},
5745         {161, 193, 6, 12, 1},
5746         {165, 194, 2, 12, 1},
5747         {184, 164, 0, 12, 1},
5748         {188, 164, 4, 12, 1},
5749         {192, 165, 8, 12, 1},
5750         {196, 166, 0, 12, 1},
5751 };
5752
5753 static const struct rf_channel rf_vals_5592_xtal40[] = {
5754         /* Channel, N, K, mod, R */
5755         {1, 241, 2, 10, 3},
5756         {2, 241, 7, 10, 3},
5757         {3, 242, 2, 10, 3},
5758         {4, 242, 7, 10, 3},
5759         {5, 243, 2, 10, 3},
5760         {6, 243, 7, 10, 3},
5761         {7, 244, 2, 10, 3},
5762         {8, 244, 7, 10, 3},
5763         {9, 245, 2, 10, 3},
5764         {10, 245, 7, 10, 3},
5765         {11, 246, 2, 10, 3},
5766         {12, 246, 7, 10, 3},
5767         {13, 247, 2, 10, 3},
5768         {14, 248, 4, 10, 3},
5769         {36, 86, 4, 12, 1},
5770         {38, 86, 6, 12, 1},
5771         {40, 86, 8, 12, 1},
5772         {42, 86, 10, 12, 1},
5773         {44, 87, 0, 12, 1},
5774         {46, 87, 2, 12, 1},
5775         {48, 87, 4, 12, 1},
5776         {50, 87, 6, 12, 1},
5777         {52, 87, 8, 12, 1},
5778         {54, 87, 10, 12, 1},
5779         {56, 88, 0, 12, 1},
5780         {58, 88, 2, 12, 1},
5781         {60, 88, 4, 12, 1},
5782         {62, 88, 6, 12, 1},
5783         {64, 88, 8, 12, 1},
5784         {100, 91, 8, 12, 1},
5785         {102, 91, 10, 12, 1},
5786         {104, 92, 0, 12, 1},
5787         {106, 92, 2, 12, 1},
5788         {108, 92, 4, 12, 1},
5789         {110, 92, 6, 12, 1},
5790         {112, 92, 8, 12, 1},
5791         {114, 92, 10, 12, 1},
5792         {116, 93, 0, 12, 1},
5793         {118, 93, 2, 12, 1},
5794         {120, 93, 4, 12, 1},
5795         {122, 93, 6, 12, 1},
5796         {124, 93, 8, 12, 1},
5797         {126, 93, 10, 12, 1},
5798         {128, 94, 0, 12, 1},
5799         {130, 94, 2, 12, 1},
5800         {132, 94, 4, 12, 1},
5801         {134, 94, 6, 12, 1},
5802         {136, 94, 8, 12, 1},
5803         {138, 94, 10, 12, 1},
5804         {140, 95, 0, 12, 1},
5805         {149, 95, 9, 12, 1},
5806         {151, 95, 11, 12, 1},
5807         {153, 96, 1, 12, 1},
5808         {155, 96, 3, 12, 1},
5809         {157, 96, 5, 12, 1},
5810         {159, 96, 7, 12, 1},
5811         {161, 96, 9, 12, 1},
5812         {165, 97, 1, 12, 1},
5813         {184, 82, 0, 12, 1},
5814         {188, 82, 4, 12, 1},
5815         {192, 82, 8, 12, 1},
5816         {196, 83, 0, 12, 1},
5817 };
5818
5819 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5820 {
5821         struct hw_mode_spec *spec = &rt2x00dev->spec;
5822         struct channel_info *info;
5823         char *default_power1;
5824         char *default_power2;
5825         unsigned int i;
5826         u16 eeprom;
5827         u32 reg;
5828
5829         /*
5830          * Disable powersaving as default on PCI devices.
5831          */
5832         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5833                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5834
5835         /*
5836          * Initialize all hw fields.
5837          */
5838         rt2x00dev->hw->flags =
5839             IEEE80211_HW_SIGNAL_DBM |
5840             IEEE80211_HW_SUPPORTS_PS |
5841             IEEE80211_HW_PS_NULLFUNC_STACK |
5842             IEEE80211_HW_AMPDU_AGGREGATION |
5843             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5844
5845         /*
5846          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5847          * unless we are capable of sending the buffered frames out after the
5848          * DTIM transmission using rt2x00lib_beacondone. This will send out
5849          * multicast and broadcast traffic immediately instead of buffering it
5850          * infinitly and thus dropping it after some time.
5851          */
5852         if (!rt2x00_is_usb(rt2x00dev))
5853                 rt2x00dev->hw->flags |=
5854                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5855
5856         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5857         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5858                                 rt2x00_eeprom_addr(rt2x00dev,
5859                                                    EEPROM_MAC_ADDR_0));
5860
5861         /*
5862          * As rt2800 has a global fallback table we cannot specify
5863          * more then one tx rate per frame but since the hw will
5864          * try several rates (based on the fallback table) we should
5865          * initialize max_report_rates to the maximum number of rates
5866          * we are going to try. Otherwise mac80211 will truncate our
5867          * reported tx rates and the rc algortihm will end up with
5868          * incorrect data.
5869          */
5870         rt2x00dev->hw->max_rates = 1;
5871         rt2x00dev->hw->max_report_rates = 7;
5872         rt2x00dev->hw->max_rate_tries = 1;
5873
5874         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5875
5876         /*
5877          * Initialize hw_mode information.
5878          */
5879         spec->supported_bands = SUPPORT_BAND_2GHZ;
5880         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5881
5882         if (rt2x00_rf(rt2x00dev, RF2820) ||
5883             rt2x00_rf(rt2x00dev, RF2720)) {
5884                 spec->num_channels = 14;
5885                 spec->channels = rf_vals;
5886         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5887                    rt2x00_rf(rt2x00dev, RF2750)) {
5888                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5889                 spec->num_channels = ARRAY_SIZE(rf_vals);
5890                 spec->channels = rf_vals;
5891         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5892                    rt2x00_rf(rt2x00dev, RF2020) ||
5893                    rt2x00_rf(rt2x00dev, RF3021) ||
5894                    rt2x00_rf(rt2x00dev, RF3022) ||
5895                    rt2x00_rf(rt2x00dev, RF3290) ||
5896                    rt2x00_rf(rt2x00dev, RF3320) ||
5897                    rt2x00_rf(rt2x00dev, RF3322) ||
5898                    rt2x00_rf(rt2x00dev, RF5360) ||
5899                    rt2x00_rf(rt2x00dev, RF5370) ||
5900                    rt2x00_rf(rt2x00dev, RF5372) ||
5901                    rt2x00_rf(rt2x00dev, RF5390) ||
5902                    rt2x00_rf(rt2x00dev, RF5392)) {
5903                 spec->num_channels = 14;
5904                 spec->channels = rf_vals_3x;
5905         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5906                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5907                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5908                 spec->channels = rf_vals_3x;
5909         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5910                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5911
5912                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5913                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5914                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5915                         spec->channels = rf_vals_5592_xtal40;
5916                 } else {
5917                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5918                         spec->channels = rf_vals_5592_xtal20;
5919                 }
5920         }
5921
5922         if (WARN_ON_ONCE(!spec->channels))
5923                 return -ENODEV;
5924
5925         /*
5926          * Initialize HT information.
5927          */
5928         if (!rt2x00_rf(rt2x00dev, RF2020))
5929                 spec->ht.ht_supported = true;
5930         else
5931                 spec->ht.ht_supported = false;
5932
5933         spec->ht.cap =
5934             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5935             IEEE80211_HT_CAP_GRN_FLD |
5936             IEEE80211_HT_CAP_SGI_20 |
5937             IEEE80211_HT_CAP_SGI_40;
5938
5939         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5940                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5941
5942         spec->ht.cap |=
5943             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5944                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5945
5946         spec->ht.ampdu_factor = 3;
5947         spec->ht.ampdu_density = 4;
5948         spec->ht.mcs.tx_params =
5949             IEEE80211_HT_MCS_TX_DEFINED |
5950             IEEE80211_HT_MCS_TX_RX_DIFF |
5951             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5952                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5953
5954         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5955         case 3:
5956                 spec->ht.mcs.rx_mask[2] = 0xff;
5957         case 2:
5958                 spec->ht.mcs.rx_mask[1] = 0xff;
5959         case 1:
5960                 spec->ht.mcs.rx_mask[0] = 0xff;
5961                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5962                 break;
5963         }
5964
5965         /*
5966          * Create channel information array
5967          */
5968         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5969         if (!info)
5970                 return -ENOMEM;
5971
5972         spec->channels_info = info;
5973
5974         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5975         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5976
5977         for (i = 0; i < 14; i++) {
5978                 info[i].default_power1 = default_power1[i];
5979                 info[i].default_power2 = default_power2[i];
5980         }
5981
5982         if (spec->num_channels > 14) {
5983                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5984                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5985
5986                 for (i = 14; i < spec->num_channels; i++) {
5987                         info[i].default_power1 = default_power1[i];
5988                         info[i].default_power2 = default_power2[i];
5989                 }
5990         }
5991
5992         switch (rt2x00dev->chip.rf) {
5993         case RF2020:
5994         case RF3020:
5995         case RF3021:
5996         case RF3022:
5997         case RF3320:
5998         case RF3052:
5999         case RF3290:
6000         case RF5360:
6001         case RF5370:
6002         case RF5372:
6003         case RF5390:
6004         case RF5392:
6005                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
6006                 break;
6007         }
6008
6009         return 0;
6010 }
6011
6012 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
6013 {
6014         int retval;
6015         u32 reg;
6016
6017         /*
6018          * Allocate eeprom data.
6019          */
6020         retval = rt2800_validate_eeprom(rt2x00dev);
6021         if (retval)
6022                 return retval;
6023
6024         retval = rt2800_init_eeprom(rt2x00dev);
6025         if (retval)
6026                 return retval;
6027
6028         /*
6029          * Enable rfkill polling by setting GPIO direction of the
6030          * rfkill switch GPIO pin correctly.
6031          */
6032         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6033         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
6034         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6035
6036         /*
6037          * Initialize hw specifications.
6038          */
6039         retval = rt2800_probe_hw_mode(rt2x00dev);
6040         if (retval)
6041                 return retval;
6042
6043         /*
6044          * Set device capabilities.
6045          */
6046         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
6047         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
6048         if (!rt2x00_is_usb(rt2x00dev))
6049                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
6050
6051         /*
6052          * Set device requirements.
6053          */
6054         if (!rt2x00_is_soc(rt2x00dev))
6055                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
6056         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
6057         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
6058         if (!rt2800_hwcrypt_disabled(rt2x00dev))
6059                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
6060         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
6061         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
6062         if (rt2x00_is_usb(rt2x00dev))
6063                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
6064         else {
6065                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
6066                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
6067         }
6068
6069         /*
6070          * Set the rssi offset.
6071          */
6072         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6073
6074         return 0;
6075 }
6076 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
6077
6078 /*
6079  * IEEE80211 stack callback functions.
6080  */
6081 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6082                          u16 *iv16)
6083 {
6084         struct rt2x00_dev *rt2x00dev = hw->priv;
6085         struct mac_iveiv_entry iveiv_entry;
6086         u32 offset;
6087
6088         offset = MAC_IVEIV_ENTRY(hw_key_idx);
6089         rt2800_register_multiread(rt2x00dev, offset,
6090                                       &iveiv_entry, sizeof(iveiv_entry));
6091
6092         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6093         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
6094 }
6095 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
6096
6097 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
6098 {
6099         struct rt2x00_dev *rt2x00dev = hw->priv;
6100         u32 reg;
6101         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6102
6103         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6104         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6105         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6106
6107         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6108         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6109         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6110
6111         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6112         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6113         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6114
6115         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6116         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6117         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6118
6119         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6120         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6121         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6122
6123         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6124         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6125         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6126
6127         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6128         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6129         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6130
6131         return 0;
6132 }
6133 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
6134
6135 int rt2800_conf_tx(struct ieee80211_hw *hw,
6136                    struct ieee80211_vif *vif, u16 queue_idx,
6137                    const struct ieee80211_tx_queue_params *params)
6138 {
6139         struct rt2x00_dev *rt2x00dev = hw->priv;
6140         struct data_queue *queue;
6141         struct rt2x00_field32 field;
6142         int retval;
6143         u32 reg;
6144         u32 offset;
6145
6146         /*
6147          * First pass the configuration through rt2x00lib, that will
6148          * update the queue settings and validate the input. After that
6149          * we are free to update the registers based on the value
6150          * in the queue parameter.
6151          */
6152         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
6153         if (retval)
6154                 return retval;
6155
6156         /*
6157          * We only need to perform additional register initialization
6158          * for WMM queues/
6159          */
6160         if (queue_idx >= 4)
6161                 return 0;
6162
6163         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
6164
6165         /* Update WMM TXOP register */
6166         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6167         field.bit_offset = (queue_idx & 1) * 16;
6168         field.bit_mask = 0xffff << field.bit_offset;
6169
6170         rt2800_register_read(rt2x00dev, offset, &reg);
6171         rt2x00_set_field32(&reg, field, queue->txop);
6172         rt2800_register_write(rt2x00dev, offset, reg);
6173
6174         /* Update WMM registers */
6175         field.bit_offset = queue_idx * 4;
6176         field.bit_mask = 0xf << field.bit_offset;
6177
6178         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6179         rt2x00_set_field32(&reg, field, queue->aifs);
6180         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6181
6182         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6183         rt2x00_set_field32(&reg, field, queue->cw_min);
6184         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6185
6186         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6187         rt2x00_set_field32(&reg, field, queue->cw_max);
6188         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6189
6190         /* Update EDCA registers */
6191         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6192
6193         rt2800_register_read(rt2x00dev, offset, &reg);
6194         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6195         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6196         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6197         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6198         rt2800_register_write(rt2x00dev, offset, reg);
6199
6200         return 0;
6201 }
6202 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6203
6204 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6205 {
6206         struct rt2x00_dev *rt2x00dev = hw->priv;
6207         u64 tsf;
6208         u32 reg;
6209
6210         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6211         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6212         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6213         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6214
6215         return tsf;
6216 }
6217 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6218
6219 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6220                         enum ieee80211_ampdu_mlme_action action,
6221                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6222                         u8 buf_size)
6223 {
6224         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6225         int ret = 0;
6226
6227         /*
6228          * Don't allow aggregation for stations the hardware isn't aware
6229          * of because tx status reports for frames to an unknown station
6230          * always contain wcid=255 and thus we can't distinguish between
6231          * multiple stations which leads to unwanted situations when the
6232          * hw reorders frames due to aggregation.
6233          */
6234         if (sta_priv->wcid < 0)
6235                 return 1;
6236
6237         switch (action) {
6238         case IEEE80211_AMPDU_RX_START:
6239         case IEEE80211_AMPDU_RX_STOP:
6240                 /*
6241                  * The hw itself takes care of setting up BlockAck mechanisms.
6242                  * So, we only have to allow mac80211 to nagotiate a BlockAck
6243                  * agreement. Once that is done, the hw will BlockAck incoming
6244                  * AMPDUs without further setup.
6245                  */
6246                 break;
6247         case IEEE80211_AMPDU_TX_START:
6248                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6249                 break;
6250         case IEEE80211_AMPDU_TX_STOP_CONT:
6251         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6252         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6253                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6254                 break;
6255         case IEEE80211_AMPDU_TX_OPERATIONAL:
6256                 break;
6257         default:
6258                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
6259         }
6260
6261         return ret;
6262 }
6263 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6264
6265 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6266                       struct survey_info *survey)
6267 {
6268         struct rt2x00_dev *rt2x00dev = hw->priv;
6269         struct ieee80211_conf *conf = &hw->conf;
6270         u32 idle, busy, busy_ext;
6271
6272         if (idx != 0)
6273                 return -ENOENT;
6274
6275         survey->channel = conf->channel;
6276
6277         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6278         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6279         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6280
6281         if (idle || busy) {
6282                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6283                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
6284                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6285
6286                 survey->channel_time = (idle + busy) / 1000;
6287                 survey->channel_time_busy = busy / 1000;
6288                 survey->channel_time_ext_busy = busy_ext / 1000;
6289         }
6290
6291         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6292                 survey->filled |= SURVEY_INFO_IN_USE;
6293
6294         return 0;
6295
6296 }
6297 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6298
6299 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6300 MODULE_VERSION(DRV_VERSION);
6301 MODULE_DESCRIPTION("Ralink RT2800 library");
6302 MODULE_LICENSE("GPL");