drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00mmio.h"
  45 #include "rt2x00pci.h"
  46 #include "rt2x00soc.h"
  47 #include "rt2800lib.h"
  48 #include "rt2800.h"
  49 #include "rt2800pci.h"
  50
  51 /*
  52  * Allow hardware encryption to be disabled.
  53  */
  54 static bool modparam_nohwcrypt = false;
  55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  57
  58 static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
  59 {
  60         return modparam_nohwcrypt;
  61 }
  62
  63 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  64 {
  65         unsigned int i;
  66         u32 reg;
  67
  68         /*
  69          * SOC devices don't support MCU requests.
  70          */
  71         if (rt2x00_is_soc(rt2x00dev))
  72                 return;
  73
  74         for (i = 0; i < 200; i++) {
  75                 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  76
  77                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  78                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  79                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  80                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  81                         break;
  82
  83                 udelay(REGISTER_BUSY_DELAY);
  84         }
  85
  86         if (i == 200)
  87                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  88
  89         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  90         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  91 }
  92
  93 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
  94 static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  95 {
  96         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
  97
  98         if (!base_addr)
  99                 return -ENOMEM;
 100
 101         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
 102
 103         iounmap(base_addr);
 104         return 0;
 105 }
 106 #else
 107 static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 108 {
 109         return -ENOMEM;
 110 }
 111 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
 112
 113 #ifdef CONFIG_PCI
 114 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 115 {
 116         struct rt2x00_dev *rt2x00dev = eeprom->data;
 117         u32 reg;
 118
 119         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 120
 121         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 122         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 123         eeprom->reg_data_clock =
 124             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 125         eeprom->reg_chip_select =
 126             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 127 }
 128
 129 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 130 {
 131         struct rt2x00_dev *rt2x00dev = eeprom->data;
 132         u32 reg = 0;
 133
 134         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 135         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 136         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 137                            !!eeprom->reg_data_clock);
 138         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 139                            !!eeprom->reg_chip_select);
 140
 141         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 142 }
 143
 144 static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 145 {
 146         struct eeprom_93cx6 eeprom;
 147         u32 reg;
 148
 149         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 150
 151         eeprom.data = rt2x00dev;
 152         eeprom.register_read = rt2800pci_eepromregister_read;
 153         eeprom.register_write = rt2800pci_eepromregister_write;
 154         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 155         {
 156         case 0:
 157                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 158                 break;
 159         case 1:
 160                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 161                 break;
 162         default:
 163                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 164                 break;
 165         }
 166         eeprom.reg_data_in = 0;
 167         eeprom.reg_data_out = 0;
 168         eeprom.reg_data_clock = 0;
 169         eeprom.reg_chip_select = 0;
 170
 171         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 172                                EEPROM_SIZE / sizeof(u16));
 173
 174         return 0;
 175 }
 176
 177 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 178 {
 179         return rt2800_efuse_detect(rt2x00dev);
 180 }
 181
 182 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 183 {
 184         return rt2800_read_eeprom_efuse(rt2x00dev);
 185 }
 186 #else
 187 static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 188 {
 189         return -EOPNOTSUPP;
 190 }
 191
 192 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 193 {
 194         return 0;
 195 }
 196
 197 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 198 {
 199         return -EOPNOTSUPP;
 200 }
 201 #endif /* CONFIG_PCI */
 202
 203 /*
 204  * Queue handlers.
 205  */
 206 static void rt2800pci_start_queue(struct data_queue *queue)
 207 {
 208         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 209         u32 reg;
 210
 211         switch (queue->qid) {
 212         case QID_RX:
 213                 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 214                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 215                 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 216                 break;
 217         case QID_BEACON:
 218                 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 219                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 220                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 221                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 222                 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 223
 224                 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 225                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
 226                 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
 227                 break;
 228         default:
 229                 break;
 230         }
 231 }
 232
 233 static void rt2800pci_kick_queue(struct data_queue *queue)
 234 {
 235         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 236         struct queue_entry *entry;
 237
 238         switch (queue->qid) {
 239         case QID_AC_VO:
 240         case QID_AC_VI:
 241         case QID_AC_BE:
 242         case QID_AC_BK:
 243                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 244                 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
 245                                          entry->entry_idx);
 246                 break;
 247         case QID_MGMT:
 248                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 249                 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
 250                                          entry->entry_idx);
 251                 break;
 252         default:
 253                 break;
 254         }
 255 }
 256
 257 static void rt2800pci_stop_queue(struct data_queue *queue)
 258 {
 259         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 260         u32 reg;
 261
 262         switch (queue->qid) {
 263         case QID_RX:
 264                 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 265                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 266                 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 267                 break;
 268         case QID_BEACON:
 269                 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 270                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
 271                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
 272                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 273                 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 274
 275                 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 276                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
 277                 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
 278
 279                 /*
 280                  * Wait for current invocation to finish. The tasklet
 281                  * won't be scheduled anymore afterwards since we disabled
 282                  * the TBTT and PRE TBTT timer.
 283                  */
 284                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 285                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 286
 287                 break;
 288         default:
 289                 break;
 290         }
 291 }
 292
 293 /*
 294  * Firmware functions
 295  */
 296 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 297 {
 298         /*
 299          * Chip rt3290 use specific 4KB firmware named rt3290.bin.
 300          */
 301         if (rt2x00_rt(rt2x00dev, RT3290))
 302                 return FIRMWARE_RT3290;
 303         else
 304                 return FIRMWARE_RT2860;
 305 }
 306
 307 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 308                                     const u8 *data, const size_t len)
 309 {
 310         u32 reg;
 311
 312         /*
 313          * enable Host program ram write selection
 314          */
 315         reg = 0;
 316         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 317         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 318
 319         /*
 320          * Write firmware to device.
 321          */
 322         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 323                                       data, len);
 324
 325         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 326         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 327
 328         rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 329         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 330
 331         return 0;
 332 }
 333
 334 /*
 335  * Initialization functions.
 336  */
 337 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 338 {
 339         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 340         u32 word;
 341
 342         if (entry->queue->qid == QID_RX) {
 343                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 344
 345                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 346         } else {
 347                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 348
 349                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 350         }
 351 }
 352
 353 static void rt2800pci_clear_entry(struct queue_entry *entry)
 354 {
 355         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 356         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 357         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 358         u32 word;
 359
 360         if (entry->queue->qid == QID_RX) {
 361                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 362                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 363                 rt2x00_desc_write(entry_priv->desc, 0, word);
 364
 365                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 366                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 367                 rt2x00_desc_write(entry_priv->desc, 1, word);
 368
 369                 /*
 370                  * Set RX IDX in register to inform hardware that we have
 371                  * handled this entry and it is available for reuse again.
 372                  */
 373                 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
 374                                       entry->entry_idx);
 375         } else {
 376                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 377                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 378                 rt2x00_desc_write(entry_priv->desc, 1, word);
 379         }
 380 }
 381
 382 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 383 {
 384         struct queue_entry_priv_pci *entry_priv;
 385
 386         /*
 387          * Initialize registers.
 388          */
 389         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 390         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 391         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
 392                                  rt2x00dev->tx[0].limit);
 393         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 394         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 395
 396         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 397         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 398         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
 399                                  rt2x00dev->tx[1].limit);
 400         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 401         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 402
 403         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 404         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 405         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
 406                                  rt2x00dev->tx[2].limit);
 407         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 408         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 409
 410         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 411         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 412         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
 413                                  rt2x00dev->tx[3].limit);
 414         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 415         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 416
 417         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
 418         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
 419         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
 420         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
 421
 422         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
 423         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
 424         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
 425         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
 426
 427         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 428         rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 429         rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
 430                                  rt2x00dev->rx[0].limit);
 431         rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
 432                                  rt2x00dev->rx[0].limit - 1);
 433         rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
 434
 435         rt2800_disable_wpdma(rt2x00dev);
 436
 437         rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 438
 439         return 0;
 440 }
 441
 442 /*
 443  * Device state switch handlers.
 444  */
 445 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 446                                  enum dev_state state)
 447 {
 448         u32 reg;
 449         unsigned long flags;
 450
 451         /*
 452          * When interrupts are being enabled, the interrupt registers
 453          * should clear the register to assure a clean state.
 454          */
 455         if (state == STATE_RADIO_IRQ_ON) {
 456                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 457                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 458         }
 459
 460         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 461         reg = 0;
 462         if (state == STATE_RADIO_IRQ_ON) {
 463                 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
 464                 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
 465                 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
 466                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 467                 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
 468         }
 469         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 470         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 471
 472         if (state == STATE_RADIO_IRQ_OFF) {
 473                 /*
 474                  * Wait for possibly running tasklets to finish.
 475                  */
 476                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
 477                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
 478                 tasklet_kill(&rt2x00dev->autowake_tasklet);
 479                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 480                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 481         }
 482 }
 483
 484 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 485 {
 486         u32 reg;
 487
 488         /*
 489          * Reset DMA indexes
 490          */
 491         rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 492         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 493         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 494         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 495         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 496         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 497         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 498         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 499         rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 500
 501         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 502         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 503
 504         if (rt2x00_is_pcie(rt2x00dev) &&
 505             (rt2x00_rt(rt2x00dev, RT3572) ||
 506              rt2x00_rt(rt2x00dev, RT5390) ||
 507              rt2x00_rt(rt2x00dev, RT5392))) {
 508                 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
 509                 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 510                 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 511                 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
 512         }
 513
 514         rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 515
 516         reg = 0;
 517         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 518         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 519         rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 520
 521         rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 522
 523         return 0;
 524 }
 525
 526 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 527 {
 528         int retval;
 529
 530         /* Wait for DMA, ignore error until we initialize queues. */
 531         rt2800_wait_wpdma_ready(rt2x00dev);
 532
 533         if (unlikely(rt2800pci_init_queues(rt2x00dev)))
 534                 return -EIO;
 535
 536         retval = rt2800_enable_radio(rt2x00dev);
 537         if (retval)
 538                 return retval;
 539
 540         /* After resume MCU_BOOT_SIGNAL will trash these. */
 541         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
 542         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
 543
 544         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
 545         rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
 546
 547         rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
 548         rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
 549
 550         return retval;
 551 }
 552
 553 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 554 {
 555         if (rt2x00_is_soc(rt2x00dev)) {
 556                 rt2800_disable_radio(rt2x00dev);
 557                 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 558                 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
 559         }
 560 }
 561
 562 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 563                                enum dev_state state)
 564 {
 565         if (state == STATE_AWAKE) {
 566                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
 567                                    0, 0x02);
 568                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
 569         } else if (state == STATE_SLEEP) {
 570                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
 571                                          0xffffffff);
 572                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
 573                                          0xffffffff);
 574                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
 575                                    0xff, 0x01);
 576         }
 577
 578         return 0;
 579 }
 580
 581 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 582                                       enum dev_state state)
 583 {
 584         int retval = 0;
 585
 586         switch (state) {
 587         case STATE_RADIO_ON:
 588                 retval = rt2800pci_enable_radio(rt2x00dev);
 589                 break;
 590         case STATE_RADIO_OFF:
 591                 /*
 592                  * After the radio has been disabled, the device should
 593                  * be put to sleep for powersaving.
 594                  */
 595                 rt2800pci_disable_radio(rt2x00dev);
 596                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 597                 break;
 598         case STATE_RADIO_IRQ_ON:
 599         case STATE_RADIO_IRQ_OFF:
 600                 rt2800pci_toggle_irq(rt2x00dev, state);
 601                 break;
 602         case STATE_DEEP_SLEEP:
 603         case STATE_SLEEP:
 604         case STATE_STANDBY:
 605         case STATE_AWAKE:
 606                 retval = rt2800pci_set_state(rt2x00dev, state);
 607                 break;
 608         default:
 609                 retval = -ENOTSUPP;
 610                 break;
 611         }
 612
 613         if (unlikely(retval))
 614                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 615                       state, retval);
 616
 617         return retval;
 618 }
 619
 620 /*
 621  * TX descriptor initialization
 622  */
 623 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 624 {
 625         return (__le32 *) entry->skb->data;
 626 }
 627
 628 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 629                                     struct txentry_desc *txdesc)
 630 {
 631         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 632         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 633         __le32 *txd = entry_priv->desc;
 634         u32 word;
 635
 636         /*
 637          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 638          * must contains a TXWI structure + 802.11 header + padding + 802.11
 639          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 640          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 641          * data. It means that LAST_SEC0 is always 0.
 642          */
 643
 644         /*
 645          * Initialize TX descriptor
 646          */
 647         word = 0;
 648         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 649         rt2x00_desc_write(txd, 0, word);
 650
 651         word = 0;
 652         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
 653         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 654                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 655         rt2x00_set_field32(&word, TXD_W1_BURST,
 656                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 657         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 658         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 659         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 660         rt2x00_desc_write(txd, 1, word);
 661
 662         word = 0;
 663         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 664                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 665         rt2x00_desc_write(txd, 2, word);
 666
 667         word = 0;
 668         rt2x00_set_field32(&word, TXD_W3_WIV,
 669                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 670         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 671         rt2x00_desc_write(txd, 3, word);
 672
 673         /*
 674          * Register descriptor details in skb frame descriptor.
 675          */
 676         skbdesc->desc = txd;
 677         skbdesc->desc_len = TXD_DESC_SIZE;
 678 }
 679
 680 /*
 681  * RX control handlers
 682  */
 683 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 684                                   struct rxdone_entry_desc *rxdesc)
 685 {
 686         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 687         __le32 *rxd = entry_priv->desc;
 688         u32 word;
 689
 690         rt2x00_desc_read(rxd, 3, &word);
 691
 692         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 693                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 694
 695         /*
 696          * Unfortunately we don't know the cipher type used during
 697          * decryption. This prevents us from correct providing
 698          * correct statistics through debugfs.
 699          */
 700         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 701
 702         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 703                 /*
 704                  * Hardware has stripped IV/EIV data from 802.11 frame during
 705                  * decryption. Unfortunately the descriptor doesn't contain
 706                  * any fields with the EIV/IV data either, so they can't
 707                  * be restored by rt2x00lib.
 708                  */
 709                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 710
 711                 /*
 712                  * The hardware has already checked the Michael Mic and has
 713                  * stripped it from the frame. Signal this to mac80211.
 714                  */
 715                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
 716
 717                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 718                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 719                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 720                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 721         }
 722
 723         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 724                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 725
 726         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 727                 rxdesc->dev_flags |= RXDONE_L2PAD;
 728
 729         /*
 730          * Process the RXWI structure that is at the start of the buffer.
 731          */
 732         rt2800_process_rxwi(entry, rxdesc);
 733 }
 734
 735 /*
 736  * Interrupt functions.
 737  */
 738 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 739 {
 740         struct ieee80211_conf conf = { .flags = 0 };
 741         struct rt2x00lib_conf libconf = { .conf = &conf };
 742
 743         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 744 }
 745
 746 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 747 {
 748         struct data_queue *queue;
 749         struct queue_entry *entry;
 750         u32 status;
 751         u8 qid;
 752         int max_tx_done = 16;
 753
 754         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
 755                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
 756                 if (unlikely(qid >= QID_RX)) {
 757                         /*
 758                          * Unknown queue, this shouldn't happen. Just drop
 759                          * this tx status.
 760                          */
 761                         WARNING(rt2x00dev, "Got TX status report with "
 762                                            "unexpected pid %u, dropping\n", qid);
 763                         break;
 764                 }
 765
 766                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
 767                 if (unlikely(queue == NULL)) {
 768                         /*
 769                          * The queue is NULL, this shouldn't happen. Stop
 770                          * processing here and drop the tx status
 771                          */
 772                         WARNING(rt2x00dev, "Got TX status for an unavailable "
 773                                            "queue %u, dropping\n", qid);
 774                         break;
 775                 }
 776
 777                 if (unlikely(rt2x00queue_empty(queue))) {
 778                         /*
 779                          * The queue is empty. Stop processing here
 780                          * and drop the tx status.
 781                          */
 782                         WARNING(rt2x00dev, "Got TX status for an empty "
 783                                            "queue %u, dropping\n", qid);
 784                         break;
 785                 }
 786
 787                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 788                 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
 789
 790                 if (--max_tx_done == 0)
 791                         break;
 792         }
 793
 794         return !max_tx_done;
 795 }
 796
 797 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
 798                                               struct rt2x00_field32 irq_field)
 799 {
 800         u32 reg;
 801
 802         /*
 803          * Enable a single interrupt. The interrupt mask register
 804          * access needs locking.
 805          */
 806         spin_lock_irq(&rt2x00dev->irqmask_lock);
 807         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 808         rt2x00_set_field32(&reg, irq_field, 1);
 809         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 810         spin_unlock_irq(&rt2x00dev->irqmask_lock);
 811 }
 812
 813 static void rt2800pci_txstatus_tasklet(unsigned long data)
 814 {
 815         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 816         if (rt2800pci_txdone(rt2x00dev))
 817                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 818
 819         /*
 820          * No need to enable the tx status interrupt here as we always
 821          * leave it enabled to minimize the possibility of a tx status
 822          * register overflow. See comment in interrupt handler.
 823          */
 824 }
 825
 826 static void rt2800pci_pretbtt_tasklet(unsigned long data)
 827 {
 828         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 829         rt2x00lib_pretbtt(rt2x00dev);
 830         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 831                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
 832 }
 833
 834 static void rt2800pci_tbtt_tasklet(unsigned long data)
 835 {
 836         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 837         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 838         u32 reg;
 839
 840         rt2x00lib_beacondone(rt2x00dev);
 841
 842         if (rt2x00dev->intf_ap_count) {
 843                 /*
 844                  * The rt2800pci hardware tbtt timer is off by 1us per tbtt
 845                  * causing beacon skew and as a result causing problems with
 846                  * some powersaving clients over time. Shorten the beacon
 847                  * interval every 64 beacons by 64us to mitigate this effect.
 848                  */
 849                 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
 850                         rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 851                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 852                                            (rt2x00dev->beacon_int * 16) - 1);
 853                         rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 854                 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
 855                         rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 856                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 857                                            (rt2x00dev->beacon_int * 16));
 858                         rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 859                 }
 860                 drv_data->tbtt_tick++;
 861                 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
 862         }
 863
 864         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 865                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
 866 }
 867
 868 static void rt2800pci_rxdone_tasklet(unsigned long data)
 869 {
 870         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 871         if (rt2x00pci_rxdone(rt2x00dev))
 872                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 873         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 874                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
 875 }
 876
 877 static void rt2800pci_autowake_tasklet(unsigned long data)
 878 {
 879         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 880         rt2800pci_wakeup(rt2x00dev);
 881         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 882                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
 883 }
 884
 885 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
 886 {
 887         u32 status;
 888         int i;
 889
 890         /*
 891          * The TX_FIFO_STATUS interrupt needs special care. We should
 892          * read TX_STA_FIFO but we should do it immediately as otherwise
 893          * the register can overflow and we would lose status reports.
 894          *
 895          * Hence, read the TX_STA_FIFO register and copy all tx status
 896          * reports into a kernel FIFO which is handled in the txstatus
 897          * tasklet. We use a tasklet to process the tx status reports
 898          * because we can schedule the tasklet multiple times (when the
 899          * interrupt fires again during tx status processing).
 900          *
 901          * Furthermore we don't disable the TX_FIFO_STATUS
 902          * interrupt here but leave it enabled so that the TX_STA_FIFO
 903          * can also be read while the tx status tasklet gets executed.
 904          *
 905          * Since we have only one producer and one consumer we don't
 906          * need to lock the kfifo.
 907          */
 908         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 909                 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
 910
 911                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
 912                         break;
 913
 914                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
 915                         WARNING(rt2x00dev, "TX status FIFO overrun,"
 916                                 "drop tx status report.\n");
 917                         break;
 918                 }
 919         }
 920
 921         /* Schedule the tasklet for processing the tx status. */
 922         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 923 }
 924
 925 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 926 {
 927         struct rt2x00_dev *rt2x00dev = dev_instance;
 928         u32 reg, mask;
 929
 930         /* Read status and ACK all interrupts */
 931         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 932         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 933
 934         if (!reg)
 935                 return IRQ_NONE;
 936
 937         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 938                 return IRQ_HANDLED;
 939
 940         /*
 941          * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
 942          * for interrupts and interrupt masks we can just use the value of
 943          * INT_SOURCE_CSR to create the interrupt mask.
 944          */
 945         mask = ~reg;
 946
 947         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
 948                 rt2800pci_txstatus_interrupt(rt2x00dev);
 949                 /*
 950                  * Never disable the TX_FIFO_STATUS interrupt.
 951                  */
 952                 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 953         }
 954
 955         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 956                 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
 957
 958         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 959                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
 960
 961         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 962                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 963
 964         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 965                 tasklet_schedule(&rt2x00dev->autowake_tasklet);
 966
 967         /*
 968          * Disable all interrupts for which a tasklet was scheduled right now,
 969          * the tasklet will reenable the appropriate interrupts.
 970          */
 971         spin_lock(&rt2x00dev->irqmask_lock);
 972         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 973         reg &= mask;
 974         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 975         spin_unlock(&rt2x00dev->irqmask_lock);
 976
 977         return IRQ_HANDLED;
 978 }
 979
 980 /*
 981  * Device probe functions.
 982  */
 983 static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
 984 {
 985         int retval;
 986
 987         if (rt2x00_is_soc(rt2x00dev))
 988                 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
 989         else if (rt2800pci_efuse_detect(rt2x00dev))
 990                 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
 991         else
 992                 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
 993
 994         return retval;
 995 }
 996
 997 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
 998         .tx                     = rt2x00mac_tx,
 999         .start                  = rt2x00mac_start,
1000         .stop                   = rt2x00mac_stop,
1001         .add_interface          = rt2x00mac_add_interface,
1002         .remove_interface       = rt2x00mac_remove_interface,
1003         .config                 = rt2x00mac_config,
1004         .configure_filter       = rt2x00mac_configure_filter,
1005         .set_key                = rt2x00mac_set_key,
1006         .sw_scan_start          = rt2x00mac_sw_scan_start,
1007         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
1008         .get_stats              = rt2x00mac_get_stats,
1009         .get_tkip_seq           = rt2800_get_tkip_seq,
1010         .set_rts_threshold      = rt2800_set_rts_threshold,
1011         .sta_add                = rt2x00mac_sta_add,
1012         .sta_remove             = rt2x00mac_sta_remove,
1013         .bss_info_changed       = rt2x00mac_bss_info_changed,
1014         .conf_tx                = rt2800_conf_tx,
1015         .get_tsf                = rt2800_get_tsf,
1016         .rfkill_poll            = rt2x00mac_rfkill_poll,
1017         .ampdu_action           = rt2800_ampdu_action,
1018         .flush                  = rt2x00mac_flush,
1019         .get_survey             = rt2800_get_survey,
1020         .get_ringparam          = rt2x00mac_get_ringparam,
1021         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
1022 };
1023
1024 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1025         .register_read          = rt2x00pci_register_read,
1026         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1027         .register_write         = rt2x00pci_register_write,
1028         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1029         .register_multiread     = rt2x00pci_register_multiread,
1030         .register_multiwrite    = rt2x00pci_register_multiwrite,
1031         .regbusy_read           = rt2x00pci_regbusy_read,
1032         .read_eeprom            = rt2800pci_read_eeprom,
1033         .hwcrypt_disabled       = rt2800pci_hwcrypt_disabled,
1034         .drv_write_firmware     = rt2800pci_write_firmware,
1035         .drv_init_registers     = rt2800pci_init_registers,
1036         .drv_get_txwi           = rt2800pci_get_txwi,
1037 };
1038
1039 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1040         .irq_handler            = rt2800pci_interrupt,
1041         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
1042         .pretbtt_tasklet        = rt2800pci_pretbtt_tasklet,
1043         .tbtt_tasklet           = rt2800pci_tbtt_tasklet,
1044         .rxdone_tasklet         = rt2800pci_rxdone_tasklet,
1045         .autowake_tasklet       = rt2800pci_autowake_tasklet,
1046         .probe_hw               = rt2800_probe_hw,
1047         .get_firmware_name      = rt2800pci_get_firmware_name,
1048         .check_firmware         = rt2800_check_firmware,
1049         .load_firmware          = rt2800_load_firmware,
1050         .initialize             = rt2x00pci_initialize,
1051         .uninitialize           = rt2x00pci_uninitialize,
1052         .get_entry_state        = rt2800pci_get_entry_state,
1053         .clear_entry            = rt2800pci_clear_entry,
1054         .set_device_state       = rt2800pci_set_device_state,
1055         .rfkill_poll            = rt2800_rfkill_poll,
1056         .link_stats             = rt2800_link_stats,
1057         .reset_tuner            = rt2800_reset_tuner,
1058         .link_tuner             = rt2800_link_tuner,
1059         .gain_calibration       = rt2800_gain_calibration,
1060         .vco_calibration        = rt2800_vco_calibration,
1061         .start_queue            = rt2800pci_start_queue,
1062         .kick_queue             = rt2800pci_kick_queue,
1063         .stop_queue             = rt2800pci_stop_queue,
1064         .flush_queue            = rt2x00pci_flush_queue,
1065         .write_tx_desc          = rt2800pci_write_tx_desc,
1066         .write_tx_data          = rt2800_write_tx_data,
1067         .write_beacon           = rt2800_write_beacon,
1068         .clear_beacon           = rt2800_clear_beacon,
1069         .fill_rxdone            = rt2800pci_fill_rxdone,
1070         .config_shared_key      = rt2800_config_shared_key,
1071         .config_pairwise_key    = rt2800_config_pairwise_key,
1072         .config_filter          = rt2800_config_filter,
1073         .config_intf            = rt2800_config_intf,
1074         .config_erp             = rt2800_config_erp,
1075         .config_ant             = rt2800_config_ant,
1076         .config                 = rt2800_config,
1077         .sta_add                = rt2800_sta_add,
1078         .sta_remove             = rt2800_sta_remove,
1079 };
1080
1081 static const struct data_queue_desc rt2800pci_queue_rx = {
1082         .entry_num              = 128,
1083         .data_size              = AGGREGATION_SIZE,
1084         .desc_size              = RXD_DESC_SIZE,
1085         .priv_size              = sizeof(struct queue_entry_priv_pci),
1086 };
1087
1088 static const struct data_queue_desc rt2800pci_queue_tx = {
1089         .entry_num              = 64,
1090         .data_size              = AGGREGATION_SIZE,
1091         .desc_size              = TXD_DESC_SIZE,
1092         .priv_size              = sizeof(struct queue_entry_priv_pci),
1093 };
1094
1095 static const struct data_queue_desc rt2800pci_queue_bcn = {
1096         .entry_num              = 8,
1097         .data_size              = 0, /* No DMA required for beacons */
1098         .desc_size              = TXWI_DESC_SIZE,
1099         .priv_size              = sizeof(struct queue_entry_priv_pci),
1100 };
1101
1102 static const struct rt2x00_ops rt2800pci_ops = {
1103         .name                   = KBUILD_MODNAME,
1104         .drv_data_size          = sizeof(struct rt2800_drv_data),
1105         .max_ap_intf            = 8,
1106         .eeprom_size            = EEPROM_SIZE,
1107         .rf_size                = RF_SIZE,
1108         .tx_queues              = NUM_TX_QUEUES,
1109         .extra_tx_headroom      = TXWI_DESC_SIZE,
1110         .rx                     = &rt2800pci_queue_rx,
1111         .tx                     = &rt2800pci_queue_tx,
1112         .bcn                    = &rt2800pci_queue_bcn,
1113         .lib                    = &rt2800pci_rt2x00_ops,
1114         .drv                    = &rt2800pci_rt2800_ops,
1115         .hw                     = &rt2800pci_mac80211_ops,
1116 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1117         .debugfs                = &rt2800_rt2x00debug,
1118 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1119 };
1120
1121 /*
1122  * RT2800pci module information.
1123  */
1124 #ifdef CONFIG_PCI
1125 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1126         { PCI_DEVICE(0x1814, 0x0601) },
1127         { PCI_DEVICE(0x1814, 0x0681) },
1128         { PCI_DEVICE(0x1814, 0x0701) },
1129         { PCI_DEVICE(0x1814, 0x0781) },
1130         { PCI_DEVICE(0x1814, 0x3090) },
1131         { PCI_DEVICE(0x1814, 0x3091) },
1132         { PCI_DEVICE(0x1814, 0x3092) },
1133         { PCI_DEVICE(0x1432, 0x7708) },
1134         { PCI_DEVICE(0x1432, 0x7727) },
1135         { PCI_DEVICE(0x1432, 0x7728) },
1136         { PCI_DEVICE(0x1432, 0x7738) },
1137         { PCI_DEVICE(0x1432, 0x7748) },
1138         { PCI_DEVICE(0x1432, 0x7758) },
1139         { PCI_DEVICE(0x1432, 0x7768) },
1140         { PCI_DEVICE(0x1462, 0x891a) },
1141         { PCI_DEVICE(0x1a3b, 0x1059) },
1142 #ifdef CONFIG_RT2800PCI_RT3290
1143         { PCI_DEVICE(0x1814, 0x3290) },
1144 #endif
1145 #ifdef CONFIG_RT2800PCI_RT33XX
1146         { PCI_DEVICE(0x1814, 0x3390) },
1147 #endif
1148 #ifdef CONFIG_RT2800PCI_RT35XX
1149         { PCI_DEVICE(0x1432, 0x7711) },
1150         { PCI_DEVICE(0x1432, 0x7722) },
1151         { PCI_DEVICE(0x1814, 0x3060) },
1152         { PCI_DEVICE(0x1814, 0x3062) },
1153         { PCI_DEVICE(0x1814, 0x3562) },
1154         { PCI_DEVICE(0x1814, 0x3592) },
1155         { PCI_DEVICE(0x1814, 0x3593) },
1156         { PCI_DEVICE(0x1814, 0x359f) },
1157 #endif
1158 #ifdef CONFIG_RT2800PCI_RT53XX
1159         { PCI_DEVICE(0x1814, 0x5360) },
1160         { PCI_DEVICE(0x1814, 0x5362) },
1161         { PCI_DEVICE(0x1814, 0x5390) },
1162         { PCI_DEVICE(0x1814, 0x5392) },
1163         { PCI_DEVICE(0x1814, 0x539a) },
1164         { PCI_DEVICE(0x1814, 0x539b) },
1165         { PCI_DEVICE(0x1814, 0x539f) },
1166 #endif
1167         { 0, }
1168 };
1169 #endif /* CONFIG_PCI */
1170
1171 MODULE_AUTHOR(DRV_PROJECT);
1172 MODULE_VERSION(DRV_VERSION);
1173 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1174 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1175 #ifdef CONFIG_PCI
1176 MODULE_FIRMWARE(FIRMWARE_RT2860);
1177 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1178 #endif /* CONFIG_PCI */
1179 MODULE_LICENSE("GPL");
1180
1181 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1182 static int rt2800soc_probe(struct platform_device *pdev)
1183 {
1184         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1185 }
1186
1187 static struct platform_driver rt2800soc_driver = {
1188         .driver         = {
1189                 .name           = "rt2800_wmac",
1190                 .owner          = THIS_MODULE,
1191                 .mod_name       = KBUILD_MODNAME,
1192         },
1193         .probe          = rt2800soc_probe,
1194         .remove         = rt2x00soc_remove,
1195         .suspend        = rt2x00soc_suspend,
1196         .resume         = rt2x00soc_resume,
1197 };
1198 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
1199
1200 #ifdef CONFIG_PCI
1201 static int rt2800pci_probe(struct pci_dev *pci_dev,
1202                            const struct pci_device_id *id)
1203 {
1204         return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1205 }
1206
1207 static struct pci_driver rt2800pci_driver = {
1208         .name           = KBUILD_MODNAME,
1209         .id_table       = rt2800pci_device_table,
1210         .probe          = rt2800pci_probe,
1211         .remove         = rt2x00pci_remove,
1212         .suspend        = rt2x00pci_suspend,
1213         .resume         = rt2x00pci_resume,
1214 };
1215 #endif /* CONFIG_PCI */
1216
1217 static int __init rt2800pci_init(void)
1218 {
1219         int ret = 0;
1220
1221 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1222         ret = platform_driver_register(&rt2800soc_driver);
1223         if (ret)
1224                 return ret;
1225 #endif
1226 #ifdef CONFIG_PCI
1227         ret = pci_register_driver(&rt2800pci_driver);
1228         if (ret) {
1229 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1230                 platform_driver_unregister(&rt2800soc_driver);
1231 #endif
1232                 return ret;
1233         }
1234 #endif
1235
1236         return ret;
1237 }
1238
1239 static void __exit rt2800pci_exit(void)
1240 {
1241 #ifdef CONFIG_PCI
1242         pci_unregister_driver(&rt2800pci_driver);
1243 #endif
1244 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1245         platform_driver_unregister(&rt2800soc_driver);
1246 #endif
1247 }
1248
1249 module_init(rt2800pci_init);
1250 module_exit(rt2800pci_exit);