drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800pci
  23         Abstract: rt2800pci device specific routines.
  24         Supported chipsets: RT2800E & RT2800ED.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/eeprom_93cx6.h>
  36
  37 #include "rt2x00.h"
  38 #include "rt2x00pci.h"
  39 #include "rt2x00soc.h"
  40 #include "rt2800lib.h"
  41 #include "rt2800.h"
  42 #include "rt2800pci.h"
  43
  44 #ifdef CONFIG_RT2800PCI_PCI_MODULE
  45 #define CONFIG_RT2800PCI_PCI
  46 #endif
  47
  48 #ifdef CONFIG_RT2800PCI_WISOC_MODULE
  49 #define CONFIG_RT2800PCI_WISOC
  50 #endif
  51
  52 /*
  53  * Allow hardware encryption to be disabled.
  54  */
  55 static int modparam_nohwcrypt = 1;
  56 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  57 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  58
  59 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  60 {
  61         unsigned int i;
  62         u32 reg;
  63
  64         for (i = 0; i < 200; i++) {
  65                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  66
  67                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  68                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  69                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  70                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  71                         break;
  72
  73                 udelay(REGISTER_BUSY_DELAY);
  74         }
  75
  76         if (i == 200)
  77                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  78
  79         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  80         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  81 }
  82
  83 #ifdef CONFIG_RT2800PCI_WISOC
  84 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  85 {
  86         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  87
  88         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  89 }
  90 #else
  91 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  92 {
  93 }
  94 #endif /* CONFIG_RT2800PCI_WISOC */
  95
  96 #ifdef CONFIG_RT2800PCI_PCI
  97 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  98 {
  99         struct rt2x00_dev *rt2x00dev = eeprom->data;
 100         u32 reg;
 101
 102         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 103
 104         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 105         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 106         eeprom->reg_data_clock =
 107             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 108         eeprom->reg_chip_select =
 109             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 110 }
 111
 112 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 113 {
 114         struct rt2x00_dev *rt2x00dev = eeprom->data;
 115         u32 reg = 0;
 116
 117         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 118         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 119         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 120                            !!eeprom->reg_data_clock);
 121         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 122                            !!eeprom->reg_chip_select);
 123
 124         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 125 }
 126
 127 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 128 {
 129         struct eeprom_93cx6 eeprom;
 130         u32 reg;
 131
 132         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 133
 134         eeprom.data = rt2x00dev;
 135         eeprom.register_read = rt2800pci_eepromregister_read;
 136         eeprom.register_write = rt2800pci_eepromregister_write;
 137         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 138             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 139         eeprom.reg_data_in = 0;
 140         eeprom.reg_data_out = 0;
 141         eeprom.reg_data_clock = 0;
 142         eeprom.reg_chip_select = 0;
 143
 144         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 145                                EEPROM_SIZE / sizeof(u16));
 146 }
 147
 148 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 149 {
 150         u32 reg;
 151
 152         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
 153
 154         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
 155 }
 156
 157 static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
 158                                  unsigned int i)
 159 {
 160         u32 reg;
 161
 162         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
 163         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
 164         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
 165         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
 166         rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
 167
 168         /* Wait until the EEPROM has been loaded */
 169         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
 170
 171         /* Apparently the data is read from end to start */
 172         rt2800_register_read(rt2x00dev, EFUSE_DATA3,
 173                                 (u32 *)&rt2x00dev->eeprom[i]);
 174         rt2800_register_read(rt2x00dev, EFUSE_DATA2,
 175                                 (u32 *)&rt2x00dev->eeprom[i + 2]);
 176         rt2800_register_read(rt2x00dev, EFUSE_DATA1,
 177                                 (u32 *)&rt2x00dev->eeprom[i + 4]);
 178         rt2800_register_read(rt2x00dev, EFUSE_DATA0,
 179                                 (u32 *)&rt2x00dev->eeprom[i + 6]);
 180 }
 181
 182 static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 183 {
 184         unsigned int i;
 185
 186         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
 187                 rt2800pci_efuse_read(rt2x00dev, i);
 188 }
 189 #else
 190 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 191 {
 192 }
 193
 194 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 195 {
 196         return 0;
 197 }
 198
 199 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 200 {
 201 }
 202 #endif /* CONFIG_RT2800PCI_PCI */
 203
 204 /*
 205  * Firmware functions
 206  */
 207 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 208 {
 209         return FIRMWARE_RT2860;
 210 }
 211
 212 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
 213                                     const u8 *data, const size_t len)
 214 {
 215         u16 fw_crc;
 216         u16 crc;
 217
 218         /*
 219          * Only support 8kb firmware files.
 220          */
 221         if (len != 8192)
 222                 return FW_BAD_LENGTH;
 223
 224         /*
 225          * The last 2 bytes in the firmware array are the crc checksum itself,
 226          * this means that we should never pass those 2 bytes to the crc
 227          * algorithm.
 228          */
 229         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 230
 231         /*
 232          * Use the crc ccitt algorithm.
 233          * This will return the same value as the legacy driver which
 234          * used bit ordering reversion on the both the firmware bytes
 235          * before input input as well as on the final output.
 236          * Obviously using crc ccitt directly is much more efficient.
 237          */
 238         crc = crc_ccitt(~0, data, len - 2);
 239
 240         /*
 241          * There is a small difference between the crc-itu-t + bitrev and
 242          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 243          * will be swapped, use swab16 to convert the crc to the correct
 244          * value.
 245          */
 246         crc = swab16(crc);
 247
 248         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
 249 }
 250
 251 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
 252                                    const u8 *data, const size_t len)
 253 {
 254         unsigned int i;
 255         u32 reg;
 256
 257         /*
 258          * Wait for stable hardware.
 259          */
 260         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 261                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 262                 if (reg && reg != ~0)
 263                         break;
 264                 msleep(1);
 265         }
 266
 267         if (i == REGISTER_BUSY_COUNT) {
 268                 ERROR(rt2x00dev, "Unstable hardware.\n");
 269                 return -EBUSY;
 270         }
 271
 272         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 273         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 274
 275         /*
 276          * Disable DMA, will be reenabled later when enabling
 277          * the radio.
 278          */
 279         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 280         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 281         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 282         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 283         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 284         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 285         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 286
 287         /*
 288          * enable Host program ram write selection
 289          */
 290         reg = 0;
 291         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 292         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 293
 294         /*
 295          * Write firmware to device.
 296          */
 297         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 298                                       data, len);
 299
 300         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 301         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 302
 303         /*
 304          * Wait for device to stabilize.
 305          */
 306         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 307                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 308                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 309                         break;
 310                 msleep(1);
 311         }
 312
 313         if (i == REGISTER_BUSY_COUNT) {
 314                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 315                 return -EBUSY;
 316         }
 317
 318         /*
 319          * Disable interrupts
 320          */
 321         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
 322
 323         /*
 324          * Initialize BBP R/W access agent
 325          */
 326         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 327         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 328
 329         return 0;
 330 }
 331
 332 /*
 333  * Initialization functions.
 334  */
 335 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 336 {
 337         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 338         u32 word;
 339
 340         if (entry->queue->qid == QID_RX) {
 341                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 342
 343                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 344         } else {
 345                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 346
 347                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 348         }
 349 }
 350
 351 static void rt2800pci_clear_entry(struct queue_entry *entry)
 352 {
 353         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 354         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 355         u32 word;
 356
 357         if (entry->queue->qid == QID_RX) {
 358                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 359                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 360                 rt2x00_desc_write(entry_priv->desc, 0, word);
 361
 362                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 363                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 364                 rt2x00_desc_write(entry_priv->desc, 1, word);
 365         } else {
 366                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 367                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 368                 rt2x00_desc_write(entry_priv->desc, 1, word);
 369         }
 370 }
 371
 372 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 373 {
 374         struct queue_entry_priv_pci *entry_priv;
 375         u32 reg;
 376
 377         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 378         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 379         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 380         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 381         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 382         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 383         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 384         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 385         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 386
 387         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 388         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 389
 390         /*
 391          * Initialize registers.
 392          */
 393         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 394         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 395         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 396         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 397         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 398
 399         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 400         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 401         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 402         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 403         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 404
 405         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 406         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 407         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 408         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 409         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 410
 411         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 412         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 413         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 414         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 415         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 416
 417         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 418         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 419         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 420         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 421         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 422
 423         /*
 424          * Enable global DMA configuration
 425          */
 426         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 427         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 428         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 429         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 430         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 431
 432         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 433
 434         return 0;
 435 }
 436
 437 /*
 438  * Device state switch handlers.
 439  */
 440 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 441                                 enum dev_state state)
 442 {
 443         u32 reg;
 444
 445         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 446         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 447                            (state == STATE_RADIO_RX_ON) ||
 448                            (state == STATE_RADIO_RX_ON_LINK));
 449         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 450 }
 451
 452 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 453                                  enum dev_state state)
 454 {
 455         int mask = (state == STATE_RADIO_IRQ_ON);
 456         u32 reg;
 457
 458         /*
 459          * When interrupts are being enabled, the interrupt registers
 460          * should clear the register to assure a clean state.
 461          */
 462         if (state == STATE_RADIO_IRQ_ON) {
 463                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 464                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 465         }
 466
 467         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 468         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
 469         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
 470         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 471         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
 472         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
 473         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
 474         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
 475         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
 476         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
 477         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
 478         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
 479         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 480         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 481         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 482         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 483         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
 484         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
 485         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
 486         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 487 }
 488
 489 static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 490 {
 491         unsigned int i;
 492         u32 reg;
 493
 494         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 495                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 496                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 497                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 498                         return 0;
 499
 500                 msleep(1);
 501         }
 502
 503         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 504         return -EACCES;
 505 }
 506
 507 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 508 {
 509         u32 reg;
 510         u16 word;
 511
 512         /*
 513          * Initialize all registers.
 514          */
 515         if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
 516                      rt2800pci_init_queues(rt2x00dev) ||
 517                      rt2800_init_registers(rt2x00dev) ||
 518                      rt2800pci_wait_wpdma_ready(rt2x00dev) ||
 519                      rt2800_init_bbp(rt2x00dev) ||
 520                      rt2800_init_rfcsr(rt2x00dev)))
 521                 return -EIO;
 522
 523         /*
 524          * Send signal to firmware during boot time.
 525          */
 526         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
 527
 528         /*
 529          * Enable RX.
 530          */
 531         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 532         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 533         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 534         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 535
 536         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 537         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
 538         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
 539         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
 540         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 541         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 542
 543         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 544         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 545         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 546         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 547
 548         /*
 549          * Initialize LED control
 550          */
 551         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
 552         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
 553                               word & 0xff, (word >> 8) & 0xff);
 554
 555         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
 556         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
 557                               word & 0xff, (word >> 8) & 0xff);
 558
 559         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
 560         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
 561                               word & 0xff, (word >> 8) & 0xff);
 562
 563         return 0;
 564 }
 565
 566 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 567 {
 568         u32 reg;
 569
 570         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 571         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 572         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 573         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 574         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 575         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 576         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 577
 578         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 579         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 580         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 581
 582         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 583
 584         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 585         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 586         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 587         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 588         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 589         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 590         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 591         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 592         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 593
 594         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 595         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 596
 597         /* Wait for DMA, ignore error */
 598         rt2800pci_wait_wpdma_ready(rt2x00dev);
 599 }
 600
 601 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 602                                enum dev_state state)
 603 {
 604         /*
 605          * Always put the device to sleep (even when we intend to wakeup!)
 606          * if the device is booting and wasn't asleep it will return
 607          * failure when attempting to wakeup.
 608          */
 609         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 610
 611         if (state == STATE_AWAKE) {
 612                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 613                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 614         }
 615
 616         return 0;
 617 }
 618
 619 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 620                                       enum dev_state state)
 621 {
 622         int retval = 0;
 623
 624         switch (state) {
 625         case STATE_RADIO_ON:
 626                 /*
 627                  * Before the radio can be enabled, the device first has
 628                  * to be woken up. After that it needs a bit of time
 629                  * to be fully awake and then the radio can be enabled.
 630                  */
 631                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 632                 msleep(1);
 633                 retval = rt2800pci_enable_radio(rt2x00dev);
 634                 break;
 635         case STATE_RADIO_OFF:
 636                 /*
 637                  * After the radio has been disabled, the device should
 638                  * be put to sleep for powersaving.
 639                  */
 640                 rt2800pci_disable_radio(rt2x00dev);
 641                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 642                 break;
 643         case STATE_RADIO_RX_ON:
 644         case STATE_RADIO_RX_ON_LINK:
 645         case STATE_RADIO_RX_OFF:
 646         case STATE_RADIO_RX_OFF_LINK:
 647                 rt2800pci_toggle_rx(rt2x00dev, state);
 648                 break;
 649         case STATE_RADIO_IRQ_ON:
 650         case STATE_RADIO_IRQ_OFF:
 651                 rt2800pci_toggle_irq(rt2x00dev, state);
 652                 break;
 653         case STATE_DEEP_SLEEP:
 654         case STATE_SLEEP:
 655         case STATE_STANDBY:
 656         case STATE_AWAKE:
 657                 retval = rt2800pci_set_state(rt2x00dev, state);
 658                 break;
 659         default:
 660                 retval = -ENOTSUPP;
 661                 break;
 662         }
 663
 664         if (unlikely(retval))
 665                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 666                       state, retval);
 667
 668         return retval;
 669 }
 670
 671 /*
 672  * TX descriptor initialization
 673  */
 674 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 675                                     struct sk_buff *skb,
 676                                     struct txentry_desc *txdesc)
 677 {
 678         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 679         __le32 *txd = skbdesc->desc;
 680         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
 681         u32 word;
 682
 683         /*
 684          * Initialize TX Info descriptor
 685          */
 686         rt2x00_desc_read(txwi, 0, &word);
 687         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 688                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 689         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
 690         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 691         rt2x00_set_field32(&word, TXWI_W0_TS,
 692                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 693         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 694                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 695         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 696         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
 697         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 698         rt2x00_set_field32(&word, TXWI_W0_BW,
 699                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 700         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 701                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 702         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 703         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 704         rt2x00_desc_write(txwi, 0, word);
 705
 706         rt2x00_desc_read(txwi, 1, &word);
 707         rt2x00_set_field32(&word, TXWI_W1_ACK,
 708                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 709         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 710                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 711         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 712         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 713                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 714                            txdesc->key_idx : 0xff);
 715         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 716                            skb->len - txdesc->l2pad);
 717         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
 718                            skbdesc->entry->queue->qid + 1);
 719         rt2x00_desc_write(txwi, 1, word);
 720
 721         /*
 722          * Always write 0 to IV/EIV fields, hardware will insert the IV
 723          * from the IVEIV register when TXD_W3_WIV is set to 0.
 724          * When TXD_W3_WIV is set to 1 it will use the IV data
 725          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 726          * crypto entry in the registers should be used to encrypt the frame.
 727          */
 728         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 729         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 730
 731         /*
 732          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 733          * must contains a TXWI structure + 802.11 header + padding + 802.11
 734          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 735          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 736          * data. It means that LAST_SEC0 is always 0.
 737          */
 738
 739         /*
 740          * Initialize TX descriptor
 741          */
 742         rt2x00_desc_read(txd, 0, &word);
 743         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 744         rt2x00_desc_write(txd, 0, word);
 745
 746         rt2x00_desc_read(txd, 1, &word);
 747         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
 748         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 749                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 750         rt2x00_set_field32(&word, TXD_W1_BURST,
 751                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 752         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
 753                            rt2x00dev->hw->extra_tx_headroom);
 754         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 755         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 756         rt2x00_desc_write(txd, 1, word);
 757
 758         rt2x00_desc_read(txd, 2, &word);
 759         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 760                            skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
 761         rt2x00_desc_write(txd, 2, word);
 762
 763         rt2x00_desc_read(txd, 3, &word);
 764         rt2x00_set_field32(&word, TXD_W3_WIV,
 765                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 766         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 767         rt2x00_desc_write(txd, 3, word);
 768 }
 769
 770 /*
 771  * TX data initialization
 772  */
 773 static void rt2800pci_write_beacon(struct queue_entry *entry)
 774 {
 775         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 776         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 777         unsigned int beacon_base;
 778         u32 reg;
 779
 780         /*
 781          * Disable beaconing while we are reloading the beacon data,
 782          * otherwise we might be sending out invalid data.
 783          */
 784         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 785         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 786         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 787
 788         /*
 789          * Write entire beacon with descriptor to register.
 790          */
 791         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 792         rt2800_register_multiwrite(rt2x00dev,
 793                                       beacon_base,
 794                                       skbdesc->desc, skbdesc->desc_len);
 795         rt2800_register_multiwrite(rt2x00dev,
 796                                       beacon_base + skbdesc->desc_len,
 797                                       entry->skb->data, entry->skb->len);
 798
 799         /*
 800          * Clean up beacon skb.
 801          */
 802         dev_kfree_skb_any(entry->skb);
 803         entry->skb = NULL;
 804 }
 805
 806 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 807                                     const enum data_queue_qid queue_idx)
 808 {
 809         struct data_queue *queue;
 810         unsigned int idx, qidx = 0;
 811         u32 reg;
 812
 813         if (queue_idx == QID_BEACON) {
 814                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 815                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
 816                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 817                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 818                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 819                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 820                 }
 821                 return;
 822         }
 823
 824         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
 825                 return;
 826
 827         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 828         idx = queue->index[Q_INDEX];
 829
 830         if (queue_idx == QID_MGMT)
 831                 qidx = 5;
 832         else
 833                 qidx = queue_idx;
 834
 835         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
 836 }
 837
 838 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
 839                                     const enum data_queue_qid qid)
 840 {
 841         u32 reg;
 842
 843         if (qid == QID_BEACON) {
 844                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 845                 return;
 846         }
 847
 848         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 849         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
 850         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
 851         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
 852         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
 853         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 854 }
 855
 856 /*
 857  * RX control handlers
 858  */
 859 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 860                                   struct rxdone_entry_desc *rxdesc)
 861 {
 862         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 863         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 864         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 865         __le32 *rxd = entry_priv->desc;
 866         __le32 *rxwi = (__le32 *)entry->skb->data;
 867         u32 rxd3;
 868         u32 rxwi0;
 869         u32 rxwi1;
 870         u32 rxwi2;
 871         u32 rxwi3;
 872
 873         rt2x00_desc_read(rxd, 3, &rxd3);
 874         rt2x00_desc_read(rxwi, 0, &rxwi0);
 875         rt2x00_desc_read(rxwi, 1, &rxwi1);
 876         rt2x00_desc_read(rxwi, 2, &rxwi2);
 877         rt2x00_desc_read(rxwi, 3, &rxwi3);
 878
 879         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
 880                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 881
 882         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
 883                 /*
 884                  * Unfortunately we don't know the cipher type used during
 885                  * decryption. This prevents us from correct providing
 886                  * correct statistics through debugfs.
 887                  */
 888                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
 889                 rxdesc->cipher_status =
 890                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
 891         }
 892
 893         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
 894                 /*
 895                  * Hardware has stripped IV/EIV data from 802.11 frame during
 896                  * decryption. Unfortunately the descriptor doesn't contain
 897                  * any fields with the EIV/IV data either, so they can't
 898                  * be restored by rt2x00lib.
 899                  */
 900                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 901
 902                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 903                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 904                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 905                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 906         }
 907
 908         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
 909                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 910
 911         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
 912                 rxdesc->dev_flags |= RXDONE_L2PAD;
 913                 skbdesc->flags |= SKBDESC_L2_PADDED;
 914         }
 915
 916         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
 917                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 918
 919         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
 920                 rxdesc->flags |= RX_FLAG_40MHZ;
 921
 922         /*
 923          * Detect RX rate, always use MCS as signal type.
 924          */
 925         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 926         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
 927         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
 928
 929         /*
 930          * Mask of 0x8 bit to remove the short preamble flag.
 931          */
 932         if (rxdesc->rate_mode == RATE_MODE_CCK)
 933                 rxdesc->signal &= ~0x8;
 934
 935         rxdesc->rssi =
 936             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
 937              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
 938
 939         rxdesc->noise =
 940             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
 941              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
 942
 943         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 944
 945         /*
 946          * Set RX IDX in register to inform hardware that we have handled
 947          * this entry and it is available for reuse again.
 948          */
 949         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 950
 951         /*
 952          * Remove TXWI descriptor from start of buffer.
 953          */
 954         skb_pull(entry->skb, RXWI_DESC_SIZE);
 955         skb_trim(entry->skb, rxdesc->size);
 956 }
 957
 958 /*
 959  * Interrupt functions.
 960  */
 961 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 962 {
 963         struct data_queue *queue;
 964         struct queue_entry *entry;
 965         struct queue_entry *entry_done;
 966         struct queue_entry_priv_pci *entry_priv;
 967         struct txdone_entry_desc txdesc;
 968         u32 word;
 969         u32 reg;
 970         u32 old_reg;
 971         unsigned int type;
 972         unsigned int index;
 973         u16 mcs, real_mcs;
 974
 975         /*
 976          * During each loop we will compare the freshly read
 977          * TX_STA_FIFO register value with the value read from
 978          * the previous loop. If the 2 values are equal then
 979          * we should stop processing because the chance it
 980          * quite big that the device has been unplugged and
 981          * we risk going into an endless loop.
 982          */
 983         old_reg = 0;
 984
 985         while (1) {
 986                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 987                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 988                         break;
 989
 990                 if (old_reg == reg)
 991                         break;
 992                 old_reg = reg;
 993
 994                 /*
 995                  * Skip this entry when it contains an invalid
 996                  * queue identication number.
 997                  */
 998                 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
 999                 if (type >= QID_RX)
1000                         continue;
1001
1002                 queue = rt2x00queue_get_queue(rt2x00dev, type);
1003                 if (unlikely(!queue))
1004                         continue;
1005
1006                 /*
1007                  * Skip this entry when it contains an invalid
1008                  * index number.
1009                  */
1010                 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
1011                 if (unlikely(index >= queue->limit))
1012                         continue;
1013
1014                 entry = &queue->entries[index];
1015                 entry_priv = entry->priv_data;
1016                 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
1017
1018                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1019                 while (entry != entry_done) {
1020                         /*
1021                          * Catch up.
1022                          * Just report any entries we missed as failed.
1023                          */
1024                         WARNING(rt2x00dev,
1025                                 "TX status report missed for entry %d\n",
1026                                 entry_done->entry_idx);
1027
1028                         txdesc.flags = 0;
1029                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1030                         txdesc.retry = 0;
1031
1032                         rt2x00lib_txdone(entry_done, &txdesc);
1033                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1034                 }
1035
1036                 /*
1037                  * Obtain the status about this packet.
1038                  */
1039                 txdesc.flags = 0;
1040                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1041                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1042                 else
1043                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1044
1045                 /*
1046                  * Ralink has a retry mechanism using a global fallback
1047                  * table. We setup this fallback table to try immediate
1048                  * lower rate for all rates. In the TX_STA_FIFO,
1049                  * the MCS field contains the MCS used for the successfull
1050                  * transmission. If the first transmission succeed,
1051                  * we have mcs == tx_mcs. On the second transmission,
1052                  * we have mcs = tx_mcs - 1. So the number of
1053                  * retry is (tx_mcs - mcs).
1054                  */
1055                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1056                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1057                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1058                 txdesc.retry = mcs - min(mcs, real_mcs);
1059
1060                 rt2x00lib_txdone(entry, &txdesc);
1061         }
1062 }
1063
1064 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1065 {
1066         struct rt2x00_dev *rt2x00dev = dev_instance;
1067         u32 reg;
1068
1069         /* Read status and ACK all interrupts */
1070         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1071         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1072
1073         if (!reg)
1074                 return IRQ_NONE;
1075
1076         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1077                 return IRQ_HANDLED;
1078
1079         /*
1080          * 1 - Rx ring done interrupt.
1081          */
1082         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1083                 rt2x00pci_rxdone(rt2x00dev);
1084
1085         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1086                 rt2800pci_txdone(rt2x00dev);
1087
1088         return IRQ_HANDLED;
1089 }
1090
1091 /*
1092  * Device probe functions.
1093  */
1094 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1095 {
1096         /*
1097          * Read EEPROM into buffer
1098          */
1099         switch (rt2x00dev->chip.rt) {
1100         case RT2880:
1101         case RT3052:
1102                 rt2800pci_read_eeprom_soc(rt2x00dev);
1103                 break;
1104         default:
1105                 if (rt2800pci_efuse_detect(rt2x00dev))
1106                         rt2800pci_read_eeprom_efuse(rt2x00dev);
1107                 else
1108                         rt2800pci_read_eeprom_pci(rt2x00dev);
1109                 break;
1110         }
1111
1112         return rt2800_validate_eeprom(rt2x00dev);
1113 }
1114
1115 /*
1116  * RF value list for rt2860
1117  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1118  */
1119 static const struct rf_channel rf_vals[] = {
1120         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1121         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1122         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1123         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1124         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1125         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1126         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1127         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1128         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1129         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1130         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1131         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1132         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1133         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1134
1135         /* 802.11 UNI / HyperLan 2 */
1136         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1137         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1138         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1139         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1140         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1141         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1142         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1143         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1144         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1145         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1146         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1147         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1148
1149         /* 802.11 HyperLan 2 */
1150         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1151         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1152         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1153         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1154         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1155         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1156         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1157         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1158         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1159         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1160         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1161         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1162         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1163         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1164         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1165         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1166
1167         /* 802.11 UNII */
1168         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1169         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1170         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1171         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1172         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1173         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1174         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1175         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
1176         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
1177         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
1178         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
1179
1180         /* 802.11 Japan */
1181         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1182         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1183         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1184         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1185         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1186         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1187         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1188 };
1189
1190 static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1191 {
1192         struct rt2x00_chip *chip = &rt2x00dev->chip;
1193         struct hw_mode_spec *spec = &rt2x00dev->spec;
1194         struct channel_info *info;
1195         char *tx_power1;
1196         char *tx_power2;
1197         unsigned int i;
1198         u16 eeprom;
1199
1200         /*
1201          * Initialize all hw fields.
1202          */
1203         rt2x00dev->hw->flags =
1204             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1205             IEEE80211_HW_SIGNAL_DBM |
1206             IEEE80211_HW_SUPPORTS_PS |
1207             IEEE80211_HW_PS_NULLFUNC_STACK;
1208
1209         if (rt2x00_intf_is_pci(rt2x00dev))
1210                 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
1211
1212         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1213         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1214                                 rt2x00_eeprom_addr(rt2x00dev,
1215                                                    EEPROM_MAC_ADDR_0));
1216
1217         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1218
1219         /*
1220          * Initialize hw_mode information.
1221          */
1222         spec->supported_bands = SUPPORT_BAND_2GHZ;
1223         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1224
1225         if (rt2x00_rf(chip, RF2820) ||
1226             rt2x00_rf(chip, RF2720) ||
1227             (rt2x00_intf_is_pci(rt2x00dev) &&
1228              (rt2x00_rf(chip, RF3020) ||
1229               rt2x00_rf(chip, RF3021) ||
1230               rt2x00_rf(chip, RF3022) ||
1231               rt2x00_rf(chip, RF2020) ||
1232               rt2x00_rf(chip, RF3052)))) {
1233                 spec->num_channels = 14;
1234                 spec->channels = rf_vals;
1235         } else if (rt2x00_rf(chip, RF2850) ||
1236                    rt2x00_rf(chip, RF2750)) {
1237                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1238                 spec->num_channels = ARRAY_SIZE(rf_vals);
1239                 spec->channels = rf_vals;
1240         }
1241
1242         /*
1243          * Initialize HT information.
1244          */
1245         spec->ht.ht_supported = true;
1246         spec->ht.cap =
1247             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1248             IEEE80211_HT_CAP_GRN_FLD |
1249             IEEE80211_HT_CAP_SGI_20 |
1250             IEEE80211_HT_CAP_SGI_40 |
1251             IEEE80211_HT_CAP_TX_STBC |
1252             IEEE80211_HT_CAP_RX_STBC |
1253             IEEE80211_HT_CAP_PSMP_SUPPORT;
1254         spec->ht.ampdu_factor = 3;
1255         spec->ht.ampdu_density = 4;
1256         spec->ht.mcs.tx_params =
1257             IEEE80211_HT_MCS_TX_DEFINED |
1258             IEEE80211_HT_MCS_TX_RX_DIFF |
1259             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
1260                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
1261
1262         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
1263         case 3:
1264                 spec->ht.mcs.rx_mask[2] = 0xff;
1265         case 2:
1266                 spec->ht.mcs.rx_mask[1] = 0xff;
1267         case 1:
1268                 spec->ht.mcs.rx_mask[0] = 0xff;
1269                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
1270                 break;
1271         }
1272
1273         /*
1274          * Create channel information array
1275          */
1276         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1277         if (!info)
1278                 return -ENOMEM;
1279
1280         spec->channels_info = info;
1281
1282         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
1283         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
1284
1285         for (i = 0; i < 14; i++) {
1286                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
1287                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
1288         }
1289
1290         if (spec->num_channels > 14) {
1291                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
1292                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
1293
1294                 for (i = 14; i < spec->num_channels; i++) {
1295                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
1296                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
1297                 }
1298         }
1299
1300         return 0;
1301 }
1302
1303 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1304         .register_read          = rt2x00pci_register_read,
1305         .register_write         = rt2x00pci_register_write,
1306         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1307
1308         .register_multiread     = rt2x00pci_register_multiread,
1309         .register_multiwrite    = rt2x00pci_register_multiwrite,
1310
1311         .regbusy_read           = rt2x00pci_regbusy_read,
1312 };
1313
1314 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1315 {
1316         int retval;
1317
1318         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1319
1320         /*
1321          * Allocate eeprom data.
1322          */
1323         retval = rt2800pci_validate_eeprom(rt2x00dev);
1324         if (retval)
1325                 return retval;
1326
1327         retval = rt2800_init_eeprom(rt2x00dev);
1328         if (retval)
1329                 return retval;
1330
1331         /*
1332          * Initialize hw specifications.
1333          */
1334         retval = rt2800pci_probe_hw_mode(rt2x00dev);
1335         if (retval)
1336                 return retval;
1337
1338         /*
1339          * This device has multiple filters for control frames
1340          * and has a separate filter for PS Poll frames.
1341          */
1342         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1343         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1344
1345         /*
1346          * This device requires firmware.
1347          */
1348         if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1349             !rt2x00_rt(&rt2x00dev->chip, RT3052))
1350                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1351         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1352         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1353         if (!modparam_nohwcrypt)
1354                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1355
1356         /*
1357          * Set the rssi offset.
1358          */
1359         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1360
1361         return 0;
1362 }
1363
1364 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1365         .irq_handler            = rt2800pci_interrupt,
1366         .probe_hw               = rt2800pci_probe_hw,
1367         .get_firmware_name      = rt2800pci_get_firmware_name,
1368         .check_firmware         = rt2800pci_check_firmware,
1369         .load_firmware          = rt2800pci_load_firmware,
1370         .initialize             = rt2x00pci_initialize,
1371         .uninitialize           = rt2x00pci_uninitialize,
1372         .get_entry_state        = rt2800pci_get_entry_state,
1373         .clear_entry            = rt2800pci_clear_entry,
1374         .set_device_state       = rt2800pci_set_device_state,
1375         .rfkill_poll            = rt2800_rfkill_poll,
1376         .link_stats             = rt2800_link_stats,
1377         .reset_tuner            = rt2800_reset_tuner,
1378         .link_tuner             = rt2800_link_tuner,
1379         .write_tx_desc          = rt2800pci_write_tx_desc,
1380         .write_tx_data          = rt2x00pci_write_tx_data,
1381         .write_beacon           = rt2800pci_write_beacon,
1382         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1383         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1384         .fill_rxdone            = rt2800pci_fill_rxdone,
1385         .config_shared_key      = rt2800_config_shared_key,
1386         .config_pairwise_key    = rt2800_config_pairwise_key,
1387         .config_filter          = rt2800_config_filter,
1388         .config_intf            = rt2800_config_intf,
1389         .config_erp             = rt2800_config_erp,
1390         .config_ant             = rt2800_config_ant,
1391         .config                 = rt2800_config,
1392 };
1393
1394 static const struct data_queue_desc rt2800pci_queue_rx = {
1395         .entry_num              = RX_ENTRIES,
1396         .data_size              = AGGREGATION_SIZE,
1397         .desc_size              = RXD_DESC_SIZE,
1398         .priv_size              = sizeof(struct queue_entry_priv_pci),
1399 };
1400
1401 static const struct data_queue_desc rt2800pci_queue_tx = {
1402         .entry_num              = TX_ENTRIES,
1403         .data_size              = AGGREGATION_SIZE,
1404         .desc_size              = TXD_DESC_SIZE,
1405         .priv_size              = sizeof(struct queue_entry_priv_pci),
1406 };
1407
1408 static const struct data_queue_desc rt2800pci_queue_bcn = {
1409         .entry_num              = 8 * BEACON_ENTRIES,
1410         .data_size              = 0, /* No DMA required for beacons */
1411         .desc_size              = TXWI_DESC_SIZE,
1412         .priv_size              = sizeof(struct queue_entry_priv_pci),
1413 };
1414
1415 static const struct rt2x00_ops rt2800pci_ops = {
1416         .name           = KBUILD_MODNAME,
1417         .max_sta_intf   = 1,
1418         .max_ap_intf    = 8,
1419         .eeprom_size    = EEPROM_SIZE,
1420         .rf_size        = RF_SIZE,
1421         .tx_queues      = NUM_TX_QUEUES,
1422         .rx             = &rt2800pci_queue_rx,
1423         .tx             = &rt2800pci_queue_tx,
1424         .bcn            = &rt2800pci_queue_bcn,
1425         .lib            = &rt2800pci_rt2x00_ops,
1426         .hw             = &rt2800_mac80211_ops,
1427 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1428         .debugfs        = &rt2800_rt2x00debug,
1429 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1430 };
1431
1432 /*
1433  * RT2800pci module information.
1434  */
1435 static struct pci_device_id rt2800pci_device_table[] = {
1436         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1437         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1438         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1439         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1440         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1441         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1442         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1443         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1444         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1445         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1446         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1447         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1448         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1449         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1450         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1451         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1452         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1453         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1454         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1455         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1456         { 0, }
1457 };
1458
1459 MODULE_AUTHOR(DRV_PROJECT);
1460 MODULE_VERSION(DRV_VERSION);
1461 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1462 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1463 #ifdef CONFIG_RT2800PCI_PCI
1464 MODULE_FIRMWARE(FIRMWARE_RT2860);
1465 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1466 #endif /* CONFIG_RT2800PCI_PCI */
1467 MODULE_LICENSE("GPL");
1468
1469 #ifdef CONFIG_RT2800PCI_WISOC
1470 #if defined(CONFIG_RALINK_RT288X)
1471 __rt2x00soc_probe(RT2880, &rt2800pci_ops);
1472 #elif defined(CONFIG_RALINK_RT305X)
1473 __rt2x00soc_probe(RT3052, &rt2800pci_ops);
1474 #endif
1475
1476 static struct platform_driver rt2800soc_driver = {
1477         .driver         = {
1478                 .name           = "rt2800_wmac",
1479                 .owner          = THIS_MODULE,
1480                 .mod_name       = KBUILD_MODNAME,
1481         },
1482         .probe          = __rt2x00soc_probe,
1483         .remove         = __devexit_p(rt2x00soc_remove),
1484         .suspend        = rt2x00soc_suspend,
1485         .resume         = rt2x00soc_resume,
1486 };
1487 #endif /* CONFIG_RT2800PCI_WISOC */
1488
1489 #ifdef CONFIG_RT2800PCI_PCI
1490 static struct pci_driver rt2800pci_driver = {
1491         .name           = KBUILD_MODNAME,
1492         .id_table       = rt2800pci_device_table,
1493         .probe          = rt2x00pci_probe,
1494         .remove         = __devexit_p(rt2x00pci_remove),
1495         .suspend        = rt2x00pci_suspend,
1496         .resume         = rt2x00pci_resume,
1497 };
1498 #endif /* CONFIG_RT2800PCI_PCI */
1499
1500 static int __init rt2800pci_init(void)
1501 {
1502         int ret = 0;
1503
1504 #ifdef CONFIG_RT2800PCI_WISOC
1505         ret = platform_driver_register(&rt2800soc_driver);
1506         if (ret)
1507                 return ret;
1508 #endif
1509 #ifdef CONFIG_RT2800PCI_PCI
1510         ret = pci_register_driver(&rt2800pci_driver);
1511         if (ret) {
1512 #ifdef CONFIG_RT2800PCI_WISOC
1513                 platform_driver_unregister(&rt2800soc_driver);
1514 #endif
1515                 return ret;
1516         }
1517 #endif
1518
1519         return ret;
1520 }
1521
1522 static void __exit rt2800pci_exit(void)
1523 {
1524 #ifdef CONFIG_RT2800PCI_PCI
1525         pci_unregister_driver(&rt2800pci_driver);
1526 #endif
1527 #ifdef CONFIG_RT2800PCI_WISOC
1528         platform_driver_unregister(&rt2800soc_driver);
1529 #endif
1530 }
1531
1532 module_init(rt2800pci_init);
1533 module_exit(rt2800pci_exit);