2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static bool modparam_nohwcrypt = false;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57 static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
59 return modparam_nohwcrypt;
62 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
68 * SOC devices don't support MCU requests.
70 if (rt2x00_is_soc(rt2x00dev))
73 for (i = 0; i < 200; i++) {
74 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
76 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
77 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
82 udelay(REGISTER_BUSY_DELAY);
86 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
88 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
89 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
92 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
93 static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
95 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
100 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
106 static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
110 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
113 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
115 struct rt2x00_dev *rt2x00dev = eeprom->data;
118 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
120 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
121 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
122 eeprom->reg_data_clock =
123 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
124 eeprom->reg_chip_select =
125 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
128 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
130 struct rt2x00_dev *rt2x00dev = eeprom->data;
133 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
134 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
135 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
136 !!eeprom->reg_data_clock);
137 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
138 !!eeprom->reg_chip_select);
140 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
143 static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
145 struct eeprom_93cx6 eeprom;
148 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
150 eeprom.data = rt2x00dev;
151 eeprom.register_read = rt2800pci_eepromregister_read;
152 eeprom.register_write = rt2800pci_eepromregister_write;
153 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
156 eeprom.width = PCI_EEPROM_WIDTH_93C46;
159 eeprom.width = PCI_EEPROM_WIDTH_93C66;
162 eeprom.width = PCI_EEPROM_WIDTH_93C86;
165 eeprom.reg_data_in = 0;
166 eeprom.reg_data_out = 0;
167 eeprom.reg_data_clock = 0;
168 eeprom.reg_chip_select = 0;
170 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
171 EEPROM_SIZE / sizeof(u16));
176 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
178 return rt2800_efuse_detect(rt2x00dev);
181 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
183 return rt2800_read_eeprom_efuse(rt2x00dev);
186 static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
191 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
196 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
200 #endif /* CONFIG_PCI */
205 static void rt2800pci_start_queue(struct data_queue *queue)
207 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
210 switch (queue->qid) {
212 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
213 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
214 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
217 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
218 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
219 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
220 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
221 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
223 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
224 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
225 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
232 static void rt2800pci_kick_queue(struct data_queue *queue)
234 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
235 struct queue_entry *entry;
237 switch (queue->qid) {
242 entry = rt2x00queue_get_entry(queue, Q_INDEX);
243 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
247 entry = rt2x00queue_get_entry(queue, Q_INDEX);
248 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
256 static void rt2800pci_stop_queue(struct data_queue *queue)
258 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
261 switch (queue->qid) {
263 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
264 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
265 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
268 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
269 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
270 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
271 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
272 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
274 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
275 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
276 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
279 * Wait for current invocation to finish. The tasklet
280 * won't be scheduled anymore afterwards since we disabled
281 * the TBTT and PRE TBTT timer.
283 tasklet_kill(&rt2x00dev->tbtt_tasklet);
284 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
295 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
298 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
300 if (rt2x00_rt(rt2x00dev, RT3290))
301 return FIRMWARE_RT3290;
303 return FIRMWARE_RT2860;
306 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
307 const u8 *data, const size_t len)
312 * enable Host program ram write selection
315 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
316 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
319 * Write firmware to device.
321 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
324 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
325 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
327 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
328 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
334 * Initialization functions.
336 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
338 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
341 if (entry->queue->qid == QID_RX) {
342 rt2x00_desc_read(entry_priv->desc, 1, &word);
344 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
346 rt2x00_desc_read(entry_priv->desc, 1, &word);
348 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
352 static void rt2800pci_clear_entry(struct queue_entry *entry)
354 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
355 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
356 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
359 if (entry->queue->qid == QID_RX) {
360 rt2x00_desc_read(entry_priv->desc, 0, &word);
361 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
362 rt2x00_desc_write(entry_priv->desc, 0, word);
364 rt2x00_desc_read(entry_priv->desc, 1, &word);
365 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
366 rt2x00_desc_write(entry_priv->desc, 1, word);
369 * Set RX IDX in register to inform hardware that we have
370 * handled this entry and it is available for reuse again.
372 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
375 rt2x00_desc_read(entry_priv->desc, 1, &word);
376 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
377 rt2x00_desc_write(entry_priv->desc, 1, word);
381 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
383 struct queue_entry_priv_pci *entry_priv;
386 * Initialize registers.
388 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
389 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
390 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
391 rt2x00dev->tx[0].limit);
392 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
393 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
395 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
396 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
397 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
398 rt2x00dev->tx[1].limit);
399 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
400 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
402 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
403 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
404 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
405 rt2x00dev->tx[2].limit);
406 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
407 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
409 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
410 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
411 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
412 rt2x00dev->tx[3].limit);
413 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
414 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
416 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
417 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
418 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
419 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
421 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
422 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
423 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
424 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
426 entry_priv = rt2x00dev->rx->entries[0].priv_data;
427 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
428 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
429 rt2x00dev->rx[0].limit);
430 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
431 rt2x00dev->rx[0].limit - 1);
432 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
434 rt2800_disable_wpdma(rt2x00dev);
436 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
442 * Device state switch handlers.
444 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
445 enum dev_state state)
451 * When interrupts are being enabled, the interrupt registers
452 * should clear the register to assure a clean state.
454 if (state == STATE_RADIO_IRQ_ON) {
455 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
456 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
459 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
461 if (state == STATE_RADIO_IRQ_ON) {
462 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1);
463 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
464 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
465 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
466 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
468 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
469 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
471 if (state == STATE_RADIO_IRQ_OFF) {
473 * Wait for possibly running tasklets to finish.
475 tasklet_kill(&rt2x00dev->txstatus_tasklet);
476 tasklet_kill(&rt2x00dev->rxdone_tasklet);
477 tasklet_kill(&rt2x00dev->autowake_tasklet);
478 tasklet_kill(&rt2x00dev->tbtt_tasklet);
479 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
483 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
490 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
491 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
492 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
493 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
494 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
495 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
496 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
497 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
498 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
500 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
503 if (rt2x00_is_pcie(rt2x00dev) &&
504 (rt2x00_rt(rt2x00dev, RT3572) ||
505 rt2x00_rt(rt2x00dev, RT5390) ||
506 rt2x00_rt(rt2x00dev, RT5392))) {
507 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
508 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
509 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
510 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
513 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
516 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
517 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
518 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
520 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
525 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
529 /* Wait for DMA, ignore error until we initialize queues. */
530 rt2800_wait_wpdma_ready(rt2x00dev);
532 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
535 retval = rt2800_enable_radio(rt2x00dev);
539 /* After resume MCU_BOOT_SIGNAL will trash these. */
540 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
541 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
543 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
544 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
546 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
547 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
552 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
554 if (rt2x00_is_soc(rt2x00dev)) {
555 rt2800_disable_radio(rt2x00dev);
556 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
557 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
561 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
562 enum dev_state state)
564 if (state == STATE_AWAKE) {
565 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
567 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
568 } else if (state == STATE_SLEEP) {
569 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
571 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
573 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
580 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
581 enum dev_state state)
587 retval = rt2800pci_enable_radio(rt2x00dev);
589 case STATE_RADIO_OFF:
591 * After the radio has been disabled, the device should
592 * be put to sleep for powersaving.
594 rt2800pci_disable_radio(rt2x00dev);
595 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
597 case STATE_RADIO_IRQ_ON:
598 case STATE_RADIO_IRQ_OFF:
599 rt2800pci_toggle_irq(rt2x00dev, state);
601 case STATE_DEEP_SLEEP:
605 retval = rt2800pci_set_state(rt2x00dev, state);
612 if (unlikely(retval))
613 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
620 * TX descriptor initialization
622 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
624 return (__le32 *) entry->skb->data;
627 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
628 struct txentry_desc *txdesc)
630 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
631 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
632 __le32 *txd = entry_priv->desc;
636 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
637 * must contains a TXWI structure + 802.11 header + padding + 802.11
638 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
639 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
640 * data. It means that LAST_SEC0 is always 0.
644 * Initialize TX descriptor
647 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
648 rt2x00_desc_write(txd, 0, word);
651 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
652 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
653 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
654 rt2x00_set_field32(&word, TXD_W1_BURST,
655 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
656 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
657 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
658 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
659 rt2x00_desc_write(txd, 1, word);
662 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
663 skbdesc->skb_dma + TXWI_DESC_SIZE);
664 rt2x00_desc_write(txd, 2, word);
667 rt2x00_set_field32(&word, TXD_W3_WIV,
668 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
669 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
670 rt2x00_desc_write(txd, 3, word);
673 * Register descriptor details in skb frame descriptor.
676 skbdesc->desc_len = TXD_DESC_SIZE;
680 * RX control handlers
682 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
683 struct rxdone_entry_desc *rxdesc)
685 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
686 __le32 *rxd = entry_priv->desc;
689 rt2x00_desc_read(rxd, 3, &word);
691 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
692 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
695 * Unfortunately we don't know the cipher type used during
696 * decryption. This prevents us from correct providing
697 * correct statistics through debugfs.
699 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
701 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
703 * Hardware has stripped IV/EIV data from 802.11 frame during
704 * decryption. Unfortunately the descriptor doesn't contain
705 * any fields with the EIV/IV data either, so they can't
706 * be restored by rt2x00lib.
708 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
711 * The hardware has already checked the Michael Mic and has
712 * stripped it from the frame. Signal this to mac80211.
714 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
716 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
717 rxdesc->flags |= RX_FLAG_DECRYPTED;
718 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
719 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
722 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
723 rxdesc->dev_flags |= RXDONE_MY_BSS;
725 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
726 rxdesc->dev_flags |= RXDONE_L2PAD;
729 * Process the RXWI structure that is at the start of the buffer.
731 rt2800_process_rxwi(entry, rxdesc);
735 * Interrupt functions.
737 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
739 struct ieee80211_conf conf = { .flags = 0 };
740 struct rt2x00lib_conf libconf = { .conf = &conf };
742 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
745 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
747 struct data_queue *queue;
748 struct queue_entry *entry;
751 int max_tx_done = 16;
753 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
754 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
755 if (unlikely(qid >= QID_RX)) {
757 * Unknown queue, this shouldn't happen. Just drop
760 WARNING(rt2x00dev, "Got TX status report with "
761 "unexpected pid %u, dropping\n", qid);
765 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
766 if (unlikely(queue == NULL)) {
768 * The queue is NULL, this shouldn't happen. Stop
769 * processing here and drop the tx status
771 WARNING(rt2x00dev, "Got TX status for an unavailable "
772 "queue %u, dropping\n", qid);
776 if (unlikely(rt2x00queue_empty(queue))) {
778 * The queue is empty. Stop processing here
779 * and drop the tx status.
781 WARNING(rt2x00dev, "Got TX status for an empty "
782 "queue %u, dropping\n", qid);
786 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
787 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
789 if (--max_tx_done == 0)
796 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
797 struct rt2x00_field32 irq_field)
802 * Enable a single interrupt. The interrupt mask register
803 * access needs locking.
805 spin_lock_irq(&rt2x00dev->irqmask_lock);
806 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
807 rt2x00_set_field32(®, irq_field, 1);
808 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
809 spin_unlock_irq(&rt2x00dev->irqmask_lock);
812 static void rt2800pci_txstatus_tasklet(unsigned long data)
814 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
815 if (rt2800pci_txdone(rt2x00dev))
816 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
819 * No need to enable the tx status interrupt here as we always
820 * leave it enabled to minimize the possibility of a tx status
821 * register overflow. See comment in interrupt handler.
825 static void rt2800pci_pretbtt_tasklet(unsigned long data)
827 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
828 rt2x00lib_pretbtt(rt2x00dev);
829 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
830 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
833 static void rt2800pci_tbtt_tasklet(unsigned long data)
835 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
836 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
839 rt2x00lib_beacondone(rt2x00dev);
841 if (rt2x00dev->intf_ap_count) {
843 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
844 * causing beacon skew and as a result causing problems with
845 * some powersaving clients over time. Shorten the beacon
846 * interval every 64 beacons by 64us to mitigate this effect.
848 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
849 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
850 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
851 (rt2x00dev->beacon_int * 16) - 1);
852 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
853 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
854 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
855 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
856 (rt2x00dev->beacon_int * 16));
857 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
859 drv_data->tbtt_tick++;
860 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
863 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
864 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
867 static void rt2800pci_rxdone_tasklet(unsigned long data)
869 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
870 if (rt2x00pci_rxdone(rt2x00dev))
871 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
872 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
873 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
876 static void rt2800pci_autowake_tasklet(unsigned long data)
878 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
879 rt2800pci_wakeup(rt2x00dev);
880 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
881 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
884 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
890 * The TX_FIFO_STATUS interrupt needs special care. We should
891 * read TX_STA_FIFO but we should do it immediately as otherwise
892 * the register can overflow and we would lose status reports.
894 * Hence, read the TX_STA_FIFO register and copy all tx status
895 * reports into a kernel FIFO which is handled in the txstatus
896 * tasklet. We use a tasklet to process the tx status reports
897 * because we can schedule the tasklet multiple times (when the
898 * interrupt fires again during tx status processing).
900 * Furthermore we don't disable the TX_FIFO_STATUS
901 * interrupt here but leave it enabled so that the TX_STA_FIFO
902 * can also be read while the tx status tasklet gets executed.
904 * Since we have only one producer and one consumer we don't
905 * need to lock the kfifo.
907 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
908 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
910 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
913 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
914 WARNING(rt2x00dev, "TX status FIFO overrun,"
915 "drop tx status report.\n");
920 /* Schedule the tasklet for processing the tx status. */
921 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
924 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
926 struct rt2x00_dev *rt2x00dev = dev_instance;
929 /* Read status and ACK all interrupts */
930 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
931 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
936 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
940 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
941 * for interrupts and interrupt masks we can just use the value of
942 * INT_SOURCE_CSR to create the interrupt mask.
946 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
947 rt2800pci_txstatus_interrupt(rt2x00dev);
949 * Never disable the TX_FIFO_STATUS interrupt.
951 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
954 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
955 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
957 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
958 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
960 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
961 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
963 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
964 tasklet_schedule(&rt2x00dev->autowake_tasklet);
967 * Disable all interrupts for which a tasklet was scheduled right now,
968 * the tasklet will reenable the appropriate interrupts.
970 spin_lock(&rt2x00dev->irqmask_lock);
971 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
973 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
974 spin_unlock(&rt2x00dev->irqmask_lock);
980 * Device probe functions.
982 static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
986 if (rt2x00_is_soc(rt2x00dev))
987 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
988 else if (rt2800pci_efuse_detect(rt2x00dev))
989 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
991 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
996 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
998 .start = rt2x00mac_start,
999 .stop = rt2x00mac_stop,
1000 .add_interface = rt2x00mac_add_interface,
1001 .remove_interface = rt2x00mac_remove_interface,
1002 .config = rt2x00mac_config,
1003 .configure_filter = rt2x00mac_configure_filter,
1004 .set_key = rt2x00mac_set_key,
1005 .sw_scan_start = rt2x00mac_sw_scan_start,
1006 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1007 .get_stats = rt2x00mac_get_stats,
1008 .get_tkip_seq = rt2800_get_tkip_seq,
1009 .set_rts_threshold = rt2800_set_rts_threshold,
1010 .sta_add = rt2x00mac_sta_add,
1011 .sta_remove = rt2x00mac_sta_remove,
1012 .bss_info_changed = rt2x00mac_bss_info_changed,
1013 .conf_tx = rt2800_conf_tx,
1014 .get_tsf = rt2800_get_tsf,
1015 .rfkill_poll = rt2x00mac_rfkill_poll,
1016 .ampdu_action = rt2800_ampdu_action,
1017 .flush = rt2x00mac_flush,
1018 .get_survey = rt2800_get_survey,
1019 .get_ringparam = rt2x00mac_get_ringparam,
1020 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1023 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1024 .register_read = rt2x00pci_register_read,
1025 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1026 .register_write = rt2x00pci_register_write,
1027 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1028 .register_multiread = rt2x00pci_register_multiread,
1029 .register_multiwrite = rt2x00pci_register_multiwrite,
1030 .regbusy_read = rt2x00pci_regbusy_read,
1031 .read_eeprom = rt2800pci_read_eeprom,
1032 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
1033 .drv_write_firmware = rt2800pci_write_firmware,
1034 .drv_init_registers = rt2800pci_init_registers,
1035 .drv_get_txwi = rt2800pci_get_txwi,
1038 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1039 .irq_handler = rt2800pci_interrupt,
1040 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1041 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1042 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1043 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1044 .autowake_tasklet = rt2800pci_autowake_tasklet,
1045 .probe_hw = rt2800_probe_hw,
1046 .get_firmware_name = rt2800pci_get_firmware_name,
1047 .check_firmware = rt2800_check_firmware,
1048 .load_firmware = rt2800_load_firmware,
1049 .initialize = rt2x00pci_initialize,
1050 .uninitialize = rt2x00pci_uninitialize,
1051 .get_entry_state = rt2800pci_get_entry_state,
1052 .clear_entry = rt2800pci_clear_entry,
1053 .set_device_state = rt2800pci_set_device_state,
1054 .rfkill_poll = rt2800_rfkill_poll,
1055 .link_stats = rt2800_link_stats,
1056 .reset_tuner = rt2800_reset_tuner,
1057 .link_tuner = rt2800_link_tuner,
1058 .gain_calibration = rt2800_gain_calibration,
1059 .vco_calibration = rt2800_vco_calibration,
1060 .start_queue = rt2800pci_start_queue,
1061 .kick_queue = rt2800pci_kick_queue,
1062 .stop_queue = rt2800pci_stop_queue,
1063 .flush_queue = rt2x00pci_flush_queue,
1064 .write_tx_desc = rt2800pci_write_tx_desc,
1065 .write_tx_data = rt2800_write_tx_data,
1066 .write_beacon = rt2800_write_beacon,
1067 .clear_beacon = rt2800_clear_beacon,
1068 .fill_rxdone = rt2800pci_fill_rxdone,
1069 .config_shared_key = rt2800_config_shared_key,
1070 .config_pairwise_key = rt2800_config_pairwise_key,
1071 .config_filter = rt2800_config_filter,
1072 .config_intf = rt2800_config_intf,
1073 .config_erp = rt2800_config_erp,
1074 .config_ant = rt2800_config_ant,
1075 .config = rt2800_config,
1076 .sta_add = rt2800_sta_add,
1077 .sta_remove = rt2800_sta_remove,
1080 static const struct data_queue_desc rt2800pci_queue_rx = {
1082 .data_size = AGGREGATION_SIZE,
1083 .desc_size = RXD_DESC_SIZE,
1084 .priv_size = sizeof(struct queue_entry_priv_pci),
1087 static const struct data_queue_desc rt2800pci_queue_tx = {
1089 .data_size = AGGREGATION_SIZE,
1090 .desc_size = TXD_DESC_SIZE,
1091 .priv_size = sizeof(struct queue_entry_priv_pci),
1094 static const struct data_queue_desc rt2800pci_queue_bcn = {
1096 .data_size = 0, /* No DMA required for beacons */
1097 .desc_size = TXWI_DESC_SIZE,
1098 .priv_size = sizeof(struct queue_entry_priv_pci),
1101 static const struct rt2x00_ops rt2800pci_ops = {
1102 .name = KBUILD_MODNAME,
1103 .drv_data_size = sizeof(struct rt2800_drv_data),
1105 .eeprom_size = EEPROM_SIZE,
1107 .tx_queues = NUM_TX_QUEUES,
1108 .extra_tx_headroom = TXWI_DESC_SIZE,
1109 .rx = &rt2800pci_queue_rx,
1110 .tx = &rt2800pci_queue_tx,
1111 .bcn = &rt2800pci_queue_bcn,
1112 .lib = &rt2800pci_rt2x00_ops,
1113 .drv = &rt2800pci_rt2800_ops,
1114 .hw = &rt2800pci_mac80211_ops,
1115 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1116 .debugfs = &rt2800_rt2x00debug,
1117 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1121 * RT2800pci module information.
1124 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1125 { PCI_DEVICE(0x1814, 0x0601) },
1126 { PCI_DEVICE(0x1814, 0x0681) },
1127 { PCI_DEVICE(0x1814, 0x0701) },
1128 { PCI_DEVICE(0x1814, 0x0781) },
1129 { PCI_DEVICE(0x1814, 0x3090) },
1130 { PCI_DEVICE(0x1814, 0x3091) },
1131 { PCI_DEVICE(0x1814, 0x3092) },
1132 { PCI_DEVICE(0x1432, 0x7708) },
1133 { PCI_DEVICE(0x1432, 0x7727) },
1134 { PCI_DEVICE(0x1432, 0x7728) },
1135 { PCI_DEVICE(0x1432, 0x7738) },
1136 { PCI_DEVICE(0x1432, 0x7748) },
1137 { PCI_DEVICE(0x1432, 0x7758) },
1138 { PCI_DEVICE(0x1432, 0x7768) },
1139 { PCI_DEVICE(0x1462, 0x891a) },
1140 { PCI_DEVICE(0x1a3b, 0x1059) },
1141 #ifdef CONFIG_RT2800PCI_RT3290
1142 { PCI_DEVICE(0x1814, 0x3290) },
1144 #ifdef CONFIG_RT2800PCI_RT33XX
1145 { PCI_DEVICE(0x1814, 0x3390) },
1147 #ifdef CONFIG_RT2800PCI_RT35XX
1148 { PCI_DEVICE(0x1432, 0x7711) },
1149 { PCI_DEVICE(0x1432, 0x7722) },
1150 { PCI_DEVICE(0x1814, 0x3060) },
1151 { PCI_DEVICE(0x1814, 0x3062) },
1152 { PCI_DEVICE(0x1814, 0x3562) },
1153 { PCI_DEVICE(0x1814, 0x3592) },
1154 { PCI_DEVICE(0x1814, 0x3593) },
1155 { PCI_DEVICE(0x1814, 0x359f) },
1157 #ifdef CONFIG_RT2800PCI_RT53XX
1158 { PCI_DEVICE(0x1814, 0x5360) },
1159 { PCI_DEVICE(0x1814, 0x5362) },
1160 { PCI_DEVICE(0x1814, 0x5390) },
1161 { PCI_DEVICE(0x1814, 0x5392) },
1162 { PCI_DEVICE(0x1814, 0x539a) },
1163 { PCI_DEVICE(0x1814, 0x539b) },
1164 { PCI_DEVICE(0x1814, 0x539f) },
1168 #endif /* CONFIG_PCI */
1170 MODULE_AUTHOR(DRV_PROJECT);
1171 MODULE_VERSION(DRV_VERSION);
1172 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1173 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1175 MODULE_FIRMWARE(FIRMWARE_RT2860);
1176 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1177 #endif /* CONFIG_PCI */
1178 MODULE_LICENSE("GPL");
1180 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1181 static int rt2800soc_probe(struct platform_device *pdev)
1183 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1186 static struct platform_driver rt2800soc_driver = {
1188 .name = "rt2800_wmac",
1189 .owner = THIS_MODULE,
1190 .mod_name = KBUILD_MODNAME,
1192 .probe = rt2800soc_probe,
1193 .remove = rt2x00soc_remove,
1194 .suspend = rt2x00soc_suspend,
1195 .resume = rt2x00soc_resume,
1197 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
1200 static int rt2800pci_probe(struct pci_dev *pci_dev,
1201 const struct pci_device_id *id)
1203 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1206 static struct pci_driver rt2800pci_driver = {
1207 .name = KBUILD_MODNAME,
1208 .id_table = rt2800pci_device_table,
1209 .probe = rt2800pci_probe,
1210 .remove = rt2x00pci_remove,
1211 .suspend = rt2x00pci_suspend,
1212 .resume = rt2x00pci_resume,
1214 #endif /* CONFIG_PCI */
1216 static int __init rt2800pci_init(void)
1220 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1221 ret = platform_driver_register(&rt2800soc_driver);
1226 ret = pci_register_driver(&rt2800pci_driver);
1228 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1229 platform_driver_unregister(&rt2800soc_driver);
1238 static void __exit rt2800pci_exit(void)
1241 pci_unregister_driver(&rt2800pci_driver);
1243 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1244 platform_driver_unregister(&rt2800soc_driver);
1248 module_init(rt2800pci_init);
1249 module_exit(rt2800pci_exit);