drivers/net/wireless/rt2x00/rt2800usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800usb
  23         Abstract: rt2800usb device specific routines.
  24         Supported chipsets: RT2800U.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt2800usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 1;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  71                                 const unsigned int word, const u8 value)
  72 {
  73         u32 reg;
  74
  75         mutex_lock(&rt2x00dev->csr_mutex);
  76
  77         /*
  78          * Wait until the BBP becomes available, afterwards we
  79          * can safely write the new data into the register.
  80          */
  81         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  82                 reg = 0;
  83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  87
  88                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  89         }
  90
  91         mutex_unlock(&rt2x00dev->csr_mutex);
  92 }
  93
  94 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  95                                const unsigned int word, u8 *value)
  96 {
  97         u32 reg;
  98
  99         mutex_lock(&rt2x00dev->csr_mutex);
 100
 101         /*
 102          * Wait until the BBP becomes available, afterwards we
 103          * can safely write the read request into the register.
 104          * After the data has been written, we wait until hardware
 105          * returns the correct value, if at any time the register
 106          * doesn't become available in time, reg will be 0xffffffff
 107          * which means we return 0xff to the caller.
 108          */
 109         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 110                 reg = 0;
 111                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 114
 115                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 116
 117                 WAIT_FOR_BBP(rt2x00dev, &reg);
 118         }
 119
 120         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 121
 122         mutex_unlock(&rt2x00dev->csr_mutex);
 123 }
 124
 125 static inline void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
 126                                     const unsigned int word, const u8 value)
 127 {
 128         rt2800usb_bbp_write(rt2x00dev, word, value);
 129 }
 130
 131 static inline void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 132                                    const unsigned int word, u8 *value)
 133 {
 134         rt2800usb_bbp_read(rt2x00dev, word, value);
 135 }
 136
 137 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 138                                   const unsigned int word, const u8 value)
 139 {
 140         u32 reg;
 141
 142         mutex_lock(&rt2x00dev->csr_mutex);
 143
 144         /*
 145          * Wait until the RFCSR becomes available, afterwards we
 146          * can safely write the new data into the register.
 147          */
 148         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 149                 reg = 0;
 150                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 154
 155                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 156         }
 157
 158         mutex_unlock(&rt2x00dev->csr_mutex);
 159 }
 160
 161 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 162                                  const unsigned int word, u8 *value)
 163 {
 164         u32 reg;
 165
 166         mutex_lock(&rt2x00dev->csr_mutex);
 167
 168         /*
 169          * Wait until the RFCSR becomes available, afterwards we
 170          * can safely write the read request into the register.
 171          * After the data has been written, we wait until hardware
 172          * returns the correct value, if at any time the register
 173          * doesn't become available in time, reg will be 0xffffffff
 174          * which means we return 0xff to the caller.
 175          */
 176         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 177                 reg = 0;
 178                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 181
 182                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 183
 184                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 185         }
 186
 187         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 188
 189         mutex_unlock(&rt2x00dev->csr_mutex);
 190 }
 191
 192 static inline void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 193                                       const unsigned int word, const u8 value)
 194 {
 195         rt2800usb_rfcsr_write(rt2x00dev, word, value);
 196 }
 197
 198 static inline void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 199                                      const unsigned int word, u8 *value)
 200 {
 201         rt2800usb_rfcsr_read(rt2x00dev, word, value);
 202 }
 203
 204 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 205                                const unsigned int word, const u32 value)
 206 {
 207         u32 reg;
 208
 209         mutex_lock(&rt2x00dev->csr_mutex);
 210
 211         /*
 212          * Wait until the RF becomes available, afterwards we
 213          * can safely write the new data into the register.
 214          */
 215         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 216                 reg = 0;
 217                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 218                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 219                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 220                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 221
 222                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 223                 rt2x00_rf_write(rt2x00dev, word, value);
 224         }
 225
 226         mutex_unlock(&rt2x00dev->csr_mutex);
 227 }
 228
 229 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 230                                   const u8 command, const u8 token,
 231                                   const u8 arg0, const u8 arg1)
 232 {
 233         u32 reg;
 234
 235         mutex_lock(&rt2x00dev->csr_mutex);
 236
 237         /*
 238          * Wait until the MCU becomes available, afterwards we
 239          * can safely write the new data into the register.
 240          */
 241         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 242                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 246                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 247
 248                 reg = 0;
 249                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 250                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 251         }
 252
 253         mutex_unlock(&rt2x00dev->csr_mutex);
 254 }
 255
 256 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 257 static const struct rt2x00debug rt2800usb_rt2x00debug = {
 258         .owner  = THIS_MODULE,
 259         .csr    = {
 260                 .read           = rt2800_register_read,
 261                 .write          = rt2800_register_write,
 262                 .flags          = RT2X00DEBUGFS_OFFSET,
 263                 .word_base      = CSR_REG_BASE,
 264                 .word_size      = sizeof(u32),
 265                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 266         },
 267         .eeprom = {
 268                 .read           = rt2x00_eeprom_read,
 269                 .write          = rt2x00_eeprom_write,
 270                 .word_base      = EEPROM_BASE,
 271                 .word_size      = sizeof(u16),
 272                 .word_count     = EEPROM_SIZE / sizeof(u16),
 273         },
 274         .bbp    = {
 275                 .read           = rt2800_bbp_read,
 276                 .write          = rt2800_bbp_write,
 277                 .word_base      = BBP_BASE,
 278                 .word_size      = sizeof(u8),
 279                 .word_count     = BBP_SIZE / sizeof(u8),
 280         },
 281         .rf     = {
 282                 .read           = rt2x00_rf_read,
 283                 .write          = rt2800usb_rf_write,
 284                 .word_base      = RF_BASE,
 285                 .word_size      = sizeof(u32),
 286                 .word_count     = RF_SIZE / sizeof(u32),
 287         },
 288 };
 289 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 290
 291 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 292 {
 293         u32 reg;
 294
 295         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 296         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 297 }
 298
 299 #ifdef CONFIG_RT2X00_LIB_LEDS
 300 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 301                                      enum led_brightness brightness)
 302 {
 303         struct rt2x00_led *led =
 304             container_of(led_cdev, struct rt2x00_led, led_dev);
 305         unsigned int enabled = brightness != LED_OFF;
 306         unsigned int bg_mode =
 307             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 308         unsigned int polarity =
 309                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 310                                    EEPROM_FREQ_LED_POLARITY);
 311         unsigned int ledmode =
 312                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 313                                    EEPROM_FREQ_LED_MODE);
 314
 315         if (led->type == LED_TYPE_RADIO) {
 316                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 317                                       enabled ? 0x20 : 0);
 318         } else if (led->type == LED_TYPE_ASSOC) {
 319                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 320                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 321         } else if (led->type == LED_TYPE_QUALITY) {
 322                 /*
 323                  * The brightness is divided into 6 levels (0 - 5),
 324                  * The specs tell us the following levels:
 325                  *      0, 1 ,3, 7, 15, 31
 326                  * to determine the level in a simple way we can simply
 327                  * work with bitshifting:
 328                  *      (1 << level) - 1
 329                  */
 330                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 331                                       (1 << brightness / (LED_FULL / 6)) - 1,
 332                                       polarity);
 333         }
 334 }
 335
 336 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 337                                unsigned long *delay_on,
 338                                unsigned long *delay_off)
 339 {
 340         struct rt2x00_led *led =
 341             container_of(led_cdev, struct rt2x00_led, led_dev);
 342         u32 reg;
 343
 344         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 345         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 346         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 347         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 348         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 349         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 350         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 351         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 352         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 353
 354         return 0;
 355 }
 356
 357 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 358                                struct rt2x00_led *led,
 359                                enum led_type type)
 360 {
 361         led->rt2x00dev = rt2x00dev;
 362         led->type = type;
 363         led->led_dev.brightness_set = rt2800usb_brightness_set;
 364         led->led_dev.blink_set = rt2800usb_blink_set;
 365         led->flags = LED_INITIALIZED;
 366 }
 367 #endif /* CONFIG_RT2X00_LIB_LEDS */
 368
 369 /*
 370  * Configuration handlers.
 371  */
 372 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 373                                        struct rt2x00lib_crypto *crypto,
 374                                        struct ieee80211_key_conf *key)
 375 {
 376         struct mac_wcid_entry wcid_entry;
 377         struct mac_iveiv_entry iveiv_entry;
 378         u32 offset;
 379         u32 reg;
 380
 381         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 382
 383         rt2800_register_read(rt2x00dev, offset, &reg);
 384         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 385                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 386         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 387                            (crypto->cmd == SET_KEY) * crypto->cipher);
 388         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 389                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 390         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 391         rt2800_register_write(rt2x00dev, offset, reg);
 392
 393         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 394
 395         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 396         if ((crypto->cipher == CIPHER_TKIP) ||
 397             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 398             (crypto->cipher == CIPHER_AES))
 399                 iveiv_entry.iv[3] |= 0x20;
 400         iveiv_entry.iv[3] |= key->keyidx << 6;
 401         rt2800_register_multiwrite(rt2x00dev, offset,
 402                                       &iveiv_entry, sizeof(iveiv_entry));
 403
 404         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 405
 406         memset(&wcid_entry, 0, sizeof(wcid_entry));
 407         if (crypto->cmd == SET_KEY)
 408                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 409         rt2800_register_multiwrite(rt2x00dev, offset,
 410                                       &wcid_entry, sizeof(wcid_entry));
 411 }
 412
 413 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 414                                        struct rt2x00lib_crypto *crypto,
 415                                        struct ieee80211_key_conf *key)
 416 {
 417         struct hw_key_entry key_entry;
 418         struct rt2x00_field32 field;
 419         u32 offset;
 420         u32 reg;
 421
 422         if (crypto->cmd == SET_KEY) {
 423                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 424
 425                 memcpy(key_entry.key, crypto->key,
 426                        sizeof(key_entry.key));
 427                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 428                        sizeof(key_entry.tx_mic));
 429                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 430                        sizeof(key_entry.rx_mic));
 431
 432                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 433                 rt2800_register_multiwrite(rt2x00dev, offset,
 434                                               &key_entry, sizeof(key_entry));
 435         }
 436
 437         /*
 438          * The cipher types are stored over multiple registers
 439          * starting with SHARED_KEY_MODE_BASE each word will have
 440          * 32 bits and contains the cipher types for 2 bssidx each.
 441          * Using the correct defines correctly will cause overhead,
 442          * so just calculate the correct offset.
 443          */
 444         field.bit_offset = 4 * (key->hw_key_idx % 8);
 445         field.bit_mask = 0x7 << field.bit_offset;
 446
 447         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 448
 449         rt2800_register_read(rt2x00dev, offset, &reg);
 450         rt2x00_set_field32(&reg, field,
 451                            (crypto->cmd == SET_KEY) * crypto->cipher);
 452         rt2800_register_write(rt2x00dev, offset, reg);
 453
 454         /*
 455          * Update WCID information
 456          */
 457         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 458
 459         return 0;
 460 }
 461
 462 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 463                                          struct rt2x00lib_crypto *crypto,
 464                                          struct ieee80211_key_conf *key)
 465 {
 466         struct hw_key_entry key_entry;
 467         u32 offset;
 468
 469         if (crypto->cmd == SET_KEY) {
 470                 /*
 471                  * 1 pairwise key is possible per AID, this means that the AID
 472                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 473                  * last possible shared key entry.
 474                  */
 475                 if (crypto->aid > (256 - 32))
 476                         return -ENOSPC;
 477
 478                 key->hw_key_idx = 32 + crypto->aid;
 479
 480                 memcpy(key_entry.key, crypto->key,
 481                        sizeof(key_entry.key));
 482                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 483                        sizeof(key_entry.tx_mic));
 484                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 485                        sizeof(key_entry.rx_mic));
 486
 487                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 488                 rt2800_register_multiwrite(rt2x00dev, offset,
 489                                               &key_entry, sizeof(key_entry));
 490         }
 491
 492         /*
 493          * Update WCID information
 494          */
 495         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 496
 497         return 0;
 498 }
 499
 500 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 501                                     const unsigned int filter_flags)
 502 {
 503         u32 reg;
 504
 505         /*
 506          * Start configuration steps.
 507          * Note that the version error will always be dropped
 508          * and broadcast frames will always be accepted since
 509          * there is no filter for it at this time.
 510          */
 511         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 513                            !(filter_flags & FIF_FCSFAIL));
 514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 515                            !(filter_flags & FIF_PLCPFAIL));
 516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 517                            !(filter_flags & FIF_PROMISC_IN_BSS));
 518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 519         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 521                            !(filter_flags & FIF_ALLMULTI));
 522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 525                            !(filter_flags & FIF_CONTROL));
 526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 527                            !(filter_flags & FIF_CONTROL));
 528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 529                            !(filter_flags & FIF_CONTROL));
 530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 531                            !(filter_flags & FIF_CONTROL));
 532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 533                            !(filter_flags & FIF_CONTROL));
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 535                            !(filter_flags & FIF_PSPOLL));
 536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 538         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 539                            !(filter_flags & FIF_CONTROL));
 540         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 541 }
 542
 543 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 544                                   struct rt2x00_intf *intf,
 545                                   struct rt2x00intf_conf *conf,
 546                                   const unsigned int flags)
 547 {
 548         unsigned int beacon_base;
 549         u32 reg;
 550
 551         if (flags & CONFIG_UPDATE_TYPE) {
 552                 /*
 553                  * Clear current synchronisation setup.
 554                  * For the Beacon base registers we only need to clear
 555                  * the first byte since that byte contains the VALID and OWNER
 556                  * bits which (when set to 0) will invalidate the entire beacon.
 557                  */
 558                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 559                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 560
 561                 /*
 562                  * Enable synchronisation.
 563                  */
 564                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 565                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 566                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 567                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 568                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 569         }
 570
 571         if (flags & CONFIG_UPDATE_MAC) {
 572                 reg = le32_to_cpu(conf->mac[1]);
 573                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 574                 conf->mac[1] = cpu_to_le32(reg);
 575
 576                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 577                                               conf->mac, sizeof(conf->mac));
 578         }
 579
 580         if (flags & CONFIG_UPDATE_BSSID) {
 581                 reg = le32_to_cpu(conf->bssid[1]);
 582                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 583                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 584                 conf->bssid[1] = cpu_to_le32(reg);
 585
 586                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 587                                               conf->bssid, sizeof(conf->bssid));
 588         }
 589 }
 590
 591 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 592                                  struct rt2x00lib_erp *erp)
 593 {
 594         u32 reg;
 595
 596         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 597         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 598         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 599
 600         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 601         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 602                            !!erp->short_preamble);
 603         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 604                            !!erp->short_preamble);
 605         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 606
 607         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 608         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 609                            erp->cts_protection ? 2 : 0);
 610         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 611
 612         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 613                                  erp->basic_rates);
 614         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 615
 616         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 617         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 618         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 619         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 620
 621         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 622         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 623         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 624         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 625         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 626         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 627         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 628
 629         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 630         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 631                            erp->beacon_int * 16);
 632         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 633 }
 634
 635 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 636                                  struct antenna_setup *ant)
 637 {
 638         u8 r1;
 639         u8 r3;
 640
 641         rt2800_bbp_read(rt2x00dev, 1, &r1);
 642         rt2800_bbp_read(rt2x00dev, 3, &r3);
 643
 644         /*
 645          * Configure the TX antenna.
 646          */
 647         switch ((int)ant->tx) {
 648         case 1:
 649                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 650                 break;
 651         case 2:
 652                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 653                 break;
 654         case 3:
 655                 /* Do nothing */
 656                 break;
 657         }
 658
 659         /*
 660          * Configure the RX antenna.
 661          */
 662         switch ((int)ant->rx) {
 663         case 1:
 664                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 665                 break;
 666         case 2:
 667                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 668                 break;
 669         case 3:
 670                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 671                 break;
 672         }
 673
 674         rt2800_bbp_write(rt2x00dev, 3, r3);
 675         rt2800_bbp_write(rt2x00dev, 1, r1);
 676 }
 677
 678 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 679                                       struct rt2x00lib_conf *libconf)
 680 {
 681         u16 eeprom;
 682         short lna_gain;
 683
 684         if (libconf->rf.channel <= 14) {
 685                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 686                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 687         } else if (libconf->rf.channel <= 64) {
 688                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 689                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 690         } else if (libconf->rf.channel <= 128) {
 691                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 692                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 693         } else {
 694                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 695                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 696         }
 697
 698         rt2x00dev->lna_gain = lna_gain;
 699 }
 700
 701 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 702                                           struct ieee80211_conf *conf,
 703                                           struct rf_channel *rf,
 704                                           struct channel_info *info)
 705 {
 706         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 707
 708         if (rt2x00dev->default_ant.tx == 1)
 709                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 710
 711         if (rt2x00dev->default_ant.rx == 1) {
 712                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 713                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 714         } else if (rt2x00dev->default_ant.rx == 2)
 715                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 716
 717         if (rf->channel > 14) {
 718                 /*
 719                  * When TX power is below 0, we should increase it by 7 to
 720                  * make it a positive value (Minumum value is -7).
 721                  * However this means that values between 0 and 7 have
 722                  * double meaning, and we should set a 7DBm boost flag.
 723                  */
 724                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 725                                    (info->tx_power1 >= 0));
 726
 727                 if (info->tx_power1 < 0)
 728                         info->tx_power1 += 7;
 729
 730                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 731                                    TXPOWER_A_TO_DEV(info->tx_power1));
 732
 733                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 734                                    (info->tx_power2 >= 0));
 735
 736                 if (info->tx_power2 < 0)
 737                         info->tx_power2 += 7;
 738
 739                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 740                                    TXPOWER_A_TO_DEV(info->tx_power2));
 741         } else {
 742                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 743                                    TXPOWER_G_TO_DEV(info->tx_power1));
 744                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 745                                    TXPOWER_G_TO_DEV(info->tx_power2));
 746         }
 747
 748         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 749
 750         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 751         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 752         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 753         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 754
 755         udelay(200);
 756
 757         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 758         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 759         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 760         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 761
 762         udelay(200);
 763
 764         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 765         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 766         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 767         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 768 }
 769
 770 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 771                                           struct ieee80211_conf *conf,
 772                                           struct rf_channel *rf,
 773                                           struct channel_info *info)
 774 {
 775         u8 rfcsr;
 776
 777         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 778         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3);
 779
 780         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 781         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 782         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 783
 784         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 785         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 786                           TXPOWER_G_TO_DEV(info->tx_power1));
 787         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 788
 789         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 790         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 791         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 792
 793         rt2800_rfcsr_write(rt2x00dev, 24,
 794                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 795
 796         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 797         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 798         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 799 }
 800
 801 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 802                                      struct ieee80211_conf *conf,
 803                                      struct rf_channel *rf,
 804                                      struct channel_info *info)
 805 {
 806         u32 reg;
 807         unsigned int tx_pin;
 808         u8 bbp;
 809
 810         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 811                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 812         else
 813                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 814
 815         /*
 816          * Change BBP settings
 817          */
 818         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 819         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 820         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 821         rt2800_bbp_write(rt2x00dev, 86, 0);
 822
 823         if (rf->channel <= 14) {
 824                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 825                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 826                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 827                 } else {
 828                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 829                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 830                 }
 831         } else {
 832                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 833
 834                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 835                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 836                 else
 837                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 838         }
 839
 840         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 841         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 842         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 843         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 844         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 845
 846         tx_pin = 0;
 847
 848         /* Turn on unused PA or LNA when not using 1T or 1R */
 849         if (rt2x00dev->default_ant.tx != 1) {
 850                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 851                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 852         }
 853
 854         /* Turn on unused PA or LNA when not using 1T or 1R */
 855         if (rt2x00dev->default_ant.rx != 1) {
 856                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 857                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 858         }
 859
 860         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 861         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 862         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 863         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 864         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 865         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 866
 867         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 868
 869         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 870         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 871         rt2800_bbp_write(rt2x00dev, 4, bbp);
 872
 873         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 874         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 875         rt2800_bbp_write(rt2x00dev, 3, bbp);
 876
 877         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 878                 if (conf_is_ht40(conf)) {
 879                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 880                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 881                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 882                 } else {
 883                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 884                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 885                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 886                 }
 887         }
 888
 889         msleep(1);
 890 }
 891
 892 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 893                                      const int txpower)
 894 {
 895         u32 reg;
 896         u32 value = TXPOWER_G_TO_DEV(txpower);
 897         u8 r1;
 898
 899         rt2800_bbp_read(rt2x00dev, 1, &r1);
 900         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 901         rt2800_bbp_write(rt2x00dev, 1, r1);
 902
 903         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 904         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 905         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 906         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 907         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 908         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 909         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 910         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 911         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 912         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 913
 914         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 922         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 923         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 924
 925         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 934         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 935
 936         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 945         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 946
 947         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 952         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 953 }
 954
 955 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 956                                          struct rt2x00lib_conf *libconf)
 957 {
 958         u32 reg;
 959
 960         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 961         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 962                            libconf->conf->short_frame_max_tx_count);
 963         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 964                            libconf->conf->long_frame_max_tx_count);
 965         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 966         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 967         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 968         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 969         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 970 }
 971
 972 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
 973                                 struct rt2x00lib_conf *libconf)
 974 {
 975         enum dev_state state =
 976             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 977                 STATE_SLEEP : STATE_AWAKE;
 978         u32 reg;
 979
 980         if (state == STATE_SLEEP) {
 981                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 982
 983                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 984                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 985                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 986                                    libconf->conf->listen_interval - 1);
 987                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 988                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 989
 990                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 991         } else {
 992                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 993
 994                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 995                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 996                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
 997                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
 998                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 999         }
1000 }
1001
1002 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1003                              struct rt2x00lib_conf *libconf,
1004                              const unsigned int flags)
1005 {
1006         /* Always recalculate LNA gain before changing configuration */
1007         rt2800usb_config_lna_gain(rt2x00dev, libconf);
1008
1009         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1010                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
1011                                          &libconf->rf, &libconf->channel);
1012         if (flags & IEEE80211_CONF_CHANGE_POWER)
1013                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1014         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1015                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1016         if (flags & IEEE80211_CONF_CHANGE_PS)
1017                 rt2800usb_config_ps(rt2x00dev, libconf);
1018 }
1019
1020 /*
1021  * Link tuning
1022  */
1023 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1024                                  struct link_qual *qual)
1025 {
1026         u32 reg;
1027
1028         /*
1029          * Update FCS error count from register.
1030          */
1031         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1032         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1033 }
1034
1035 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1036 {
1037         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1038                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1039                         return 0x1c + (2 * rt2x00dev->lna_gain);
1040                 else
1041                         return 0x2e + rt2x00dev->lna_gain;
1042         }
1043
1044         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1045                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1046         else
1047                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1048 }
1049
1050 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1051                                      struct link_qual *qual, u8 vgc_level)
1052 {
1053         if (qual->vgc_level != vgc_level) {
1054                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1055                 qual->vgc_level = vgc_level;
1056                 qual->vgc_level_reg = vgc_level;
1057         }
1058 }
1059
1060 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1061                                   struct link_qual *qual)
1062 {
1063         rt2800usb_set_vgc(rt2x00dev, qual,
1064                           rt2800usb_get_default_vgc(rt2x00dev));
1065 }
1066
1067 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1068                                  struct link_qual *qual, const u32 count)
1069 {
1070         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1071                 return;
1072
1073         /*
1074          * When RSSI is better then -80 increase VGC level with 0x10
1075          */
1076         rt2800usb_set_vgc(rt2x00dev, qual,
1077                           rt2800usb_get_default_vgc(rt2x00dev) +
1078                           ((qual->rssi > -80) * 0x10));
1079 }
1080
1081 /*
1082  * Firmware functions
1083  */
1084 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1085 {
1086         return FIRMWARE_RT2870;
1087 }
1088
1089 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1090 {
1091         u16 fw_crc;
1092         u16 crc;
1093
1094         /*
1095          * The last 2 bytes in the firmware array are the crc checksum itself,
1096          * this means that we should never pass those 2 bytes to the crc
1097          * algorithm.
1098          */
1099         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1100
1101         /*
1102          * Use the crc ccitt algorithm.
1103          * This will return the same value as the legacy driver which
1104          * used bit ordering reversion on the both the firmware bytes
1105          * before input input as well as on the final output.
1106          * Obviously using crc ccitt directly is much more efficient.
1107          */
1108         crc = crc_ccitt(~0, data, len - 2);
1109
1110         /*
1111          * There is a small difference between the crc-itu-t + bitrev and
1112          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1113          * will be swapped, use swab16 to convert the crc to the correct
1114          * value.
1115          */
1116         crc = swab16(crc);
1117
1118         return fw_crc == crc;
1119 }
1120
1121 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1122                                     const u8 *data, const size_t len)
1123 {
1124         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1125         size_t offset = 0;
1126
1127         /*
1128          * Firmware files:
1129          * There are 2 variations of the rt2870 firmware.
1130          * a) size: 4kb
1131          * b) size: 8kb
1132          * Note that (b) contains 2 seperate firmware blobs of 4k
1133          * within the file. The first blob is the same firmware as (a),
1134          * but the second blob is for the additional chipsets.
1135          */
1136         if (len != 4096 && len != 8192)
1137                 return FW_BAD_LENGTH;
1138
1139         /*
1140          * Check if we need the upper 4kb firmware data or not.
1141          */
1142         if ((len == 4096) &&
1143             (chipset != 0x2860) &&
1144             (chipset != 0x2872) &&
1145             (chipset != 0x3070))
1146                 return FW_BAD_VERSION;
1147
1148         /*
1149          * 8kb firmware files must be checked as if it were
1150          * 2 seperate firmware files.
1151          */
1152         while (offset < len) {
1153                 if (!rt2800usb_check_crc(data + offset, 4096))
1154                         return FW_BAD_CRC;
1155
1156                 offset += 4096;
1157         }
1158
1159         return FW_OK;
1160 }
1161
1162 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1163                                    const u8 *data, const size_t len)
1164 {
1165         unsigned int i;
1166         int status;
1167         u32 reg;
1168         u32 offset;
1169         u32 length;
1170         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1171
1172         /*
1173          * Check which section of the firmware we need.
1174          */
1175         if ((chipset == 0x2860) ||
1176             (chipset == 0x2872) ||
1177             (chipset == 0x3070)) {
1178                 offset = 0;
1179                 length = 4096;
1180         } else {
1181                 offset = 4096;
1182                 length = 4096;
1183         }
1184
1185         /*
1186          * Wait for stable hardware.
1187          */
1188         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1189                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1190                 if (reg && reg != ~0)
1191                         break;
1192                 msleep(1);
1193         }
1194
1195         if (i == REGISTER_BUSY_COUNT) {
1196                 ERROR(rt2x00dev, "Unstable hardware.\n");
1197                 return -EBUSY;
1198         }
1199
1200         /*
1201          * Write firmware to device.
1202          */
1203         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1204                                             USB_VENDOR_REQUEST_OUT,
1205                                             FIRMWARE_IMAGE_BASE,
1206                                             data + offset, length,
1207                                             REGISTER_TIMEOUT32(length));
1208
1209         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1210         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1211
1212         /*
1213          * Send firmware request to device to load firmware,
1214          * we need to specify a long timeout time.
1215          */
1216         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1217                                              0, USB_MODE_FIRMWARE,
1218                                              REGISTER_TIMEOUT_FIRMWARE);
1219         if (status < 0) {
1220                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1221                 return status;
1222         }
1223
1224         msleep(10);
1225         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1226
1227         /*
1228          * Send signal to firmware during boot time.
1229          */
1230         rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1231
1232         if ((chipset == 0x3070) ||
1233             (chipset == 0x3071) ||
1234             (chipset == 0x3572)) {
1235                 udelay(200);
1236                 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1237                 udelay(10);
1238         }
1239
1240         /*
1241          * Wait for device to stabilize.
1242          */
1243         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1244                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1245                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1246                         break;
1247                 msleep(1);
1248         }
1249
1250         if (i == REGISTER_BUSY_COUNT) {
1251                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1252                 return -EBUSY;
1253         }
1254
1255         /*
1256          * Initialize firmware.
1257          */
1258         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1259         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1260         msleep(1);
1261
1262         return 0;
1263 }
1264
1265 /*
1266  * Initialization functions.
1267  */
1268 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1269 {
1270         u32 reg;
1271         unsigned int i;
1272
1273         /*
1274          * Wait untill BBP and RF are ready.
1275          */
1276         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1277                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1278                 if (reg && reg != ~0)
1279                         break;
1280                 msleep(1);
1281         }
1282
1283         if (i == REGISTER_BUSY_COUNT) {
1284                 ERROR(rt2x00dev, "Unstable hardware.\n");
1285                 return -EBUSY;
1286         }
1287
1288         rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1289         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1290
1291         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1292         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1293         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1294         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1295
1296         rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1297
1298         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1299                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1300
1301         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1302
1303         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1304         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1305         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1306         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1307         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1308         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1309
1310         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1311         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1312         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1313         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1314         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1315         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1316
1317         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1318         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1319
1320         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1321
1322         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1323         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1324         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1325         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1326         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1327         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1328         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1329         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1330
1331         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1332                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1333                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1334                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1335         } else {
1336                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1337                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1338         }
1339
1340         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1341         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1342         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1343         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1344         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1345         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1346         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1347         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1348         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1349         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1350
1351         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1352         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1353         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1354         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1355
1356         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1357         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1358         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1359             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1360                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1361         else
1362                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1363         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1364         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1365         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1366
1367         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1368
1369         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1370         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1371         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1372         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1373         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1374         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1375         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1376
1377         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1378         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1379         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1380         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1381         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1382         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1383         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1384         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1385         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1386         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1387         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1388
1389         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1390         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1391         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1392         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1393         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1394         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1395         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1396         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1397         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1398         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1399         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1400
1401         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1402         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1403         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1404         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1405         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1406         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1407         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1408         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1409         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1410         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1411         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1412
1413         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1414         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1415         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1416         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1417         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1418         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1419         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1420         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1421         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1422         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1423         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1424
1425         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1426         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1427         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1428         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1429         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1430         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1431         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1432         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1433         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1434         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1435         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1436
1437         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1438         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1439         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1440         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1441         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1442         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1443         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1444         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1445         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1446         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1447         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1448
1449         rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1450
1451         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1452         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1453         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1454         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1455         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1456         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1457         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1458         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1459         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1460         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1461         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1462
1463         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1464         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1465
1466         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1467         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1468         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1469                            IEEE80211_MAX_RTS_THRESHOLD);
1470         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1471         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1472
1473         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1474         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1475
1476         /*
1477          * ASIC will keep garbage value after boot, clear encryption keys.
1478          */
1479         for (i = 0; i < 4; i++)
1480                 rt2800_register_write(rt2x00dev,
1481                                          SHARED_KEY_MODE_ENTRY(i), 0);
1482
1483         for (i = 0; i < 256; i++) {
1484                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1485                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1486                                               wcid, sizeof(wcid));
1487
1488                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1489                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1490         }
1491
1492         /*
1493          * Clear all beacons
1494          * For the Beacon base registers we only need to clear
1495          * the first byte since that byte contains the VALID and OWNER
1496          * bits which (when set to 0) will invalidate the entire beacon.
1497          */
1498         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1499         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1500         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1501         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1502         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1503         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1504         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1505         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1506
1507         rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1508         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1509         rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1510
1511         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1512         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1513         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1514         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1515         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1516         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1517         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1518         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1519         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1520         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1521
1522         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1523         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1524         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1525         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1526         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1527         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1528         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1529         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1530         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1531         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1532
1533         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1534         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1535         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1536         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1537         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1538         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1539         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1540         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1541         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1542         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1543
1544         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1545         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1546         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1547         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1548         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1549         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1550
1551         /*
1552          * We must clear the error counters.
1553          * These registers are cleared on read,
1554          * so we may pass a useless variable to store the value.
1555          */
1556         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1557         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1558         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1559         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1560         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1561         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1562
1563         return 0;
1564 }
1565
1566 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1567 {
1568         unsigned int i;
1569         u32 reg;
1570
1571         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1572                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1573                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1574                         return 0;
1575
1576                 udelay(REGISTER_BUSY_DELAY);
1577         }
1578
1579         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1580         return -EACCES;
1581 }
1582
1583 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1584 {
1585         unsigned int i;
1586         u8 value;
1587
1588         /*
1589          * BBP was enabled after firmware was loaded,
1590          * but we need to reactivate it now.
1591          */
1592         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1593         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1594         msleep(1);
1595
1596         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1597                 rt2800_bbp_read(rt2x00dev, 0, &value);
1598                 if ((value != 0xff) && (value != 0x00))
1599                         return 0;
1600                 udelay(REGISTER_BUSY_DELAY);
1601         }
1602
1603         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1604         return -EACCES;
1605 }
1606
1607 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1608 {
1609         unsigned int i;
1610         u16 eeprom;
1611         u8 reg_id;
1612         u8 value;
1613
1614         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1615                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1616                 return -EACCES;
1617
1618         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1619         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1620         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1621         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1622         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1623         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1624         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1625         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1626         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1627         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1628         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1629         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1630         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1631         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1632
1633         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1634                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1635                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1636         }
1637
1638         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1639                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1640         }
1641
1642         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1643                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1644                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1645                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1646         }
1647
1648         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1649                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1650
1651                 if (eeprom != 0xffff && eeprom != 0x0000) {
1652                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1653                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1654                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1655                 }
1656         }
1657
1658         return 0;
1659 }
1660
1661 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1662                                    bool bw40, u8 rfcsr24, u8 filter_target)
1663 {
1664         unsigned int i;
1665         u8 bbp;
1666         u8 rfcsr;
1667         u8 passband;
1668         u8 stopband;
1669         u8 overtuned = 0;
1670
1671         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1672
1673         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1674         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1675         rt2800_bbp_write(rt2x00dev, 4, bbp);
1676
1677         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1678         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1679         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1680
1681         /*
1682          * Set power & frequency of passband test tone
1683          */
1684         rt2800_bbp_write(rt2x00dev, 24, 0);
1685
1686         for (i = 0; i < 100; i++) {
1687                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1688                 msleep(1);
1689
1690                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1691                 if (passband)
1692                         break;
1693         }
1694
1695         /*
1696          * Set power & frequency of stopband test tone
1697          */
1698         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1699
1700         for (i = 0; i < 100; i++) {
1701                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1702                 msleep(1);
1703
1704                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1705
1706                 if ((passband - stopband) <= filter_target) {
1707                         rfcsr24++;
1708                         overtuned += ((passband - stopband) == filter_target);
1709                 } else
1710                         break;
1711
1712                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1713         }
1714
1715         rfcsr24 -= !!overtuned;
1716
1717         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1718         return rfcsr24;
1719 }
1720
1721 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1722 {
1723         u8 rfcsr;
1724         u8 bbp;
1725
1726         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1727                 return 0;
1728
1729         /*
1730          * Init RF calibration.
1731          */
1732         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1733         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1734         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1735         msleep(1);
1736         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1737         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1738
1739         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1740         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1741         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1742         rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1743         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1744         rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1745         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1746         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1747         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1748         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1749         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1750         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1751         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1752         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1753         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1754         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1755         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1756         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1757         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1758         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1759
1760         /*
1761          * Set RX Filter calibration for 20MHz and 40MHz
1762          */
1763         rt2x00dev->calibration[0] =
1764             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1765         rt2x00dev->calibration[1] =
1766             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1767
1768         /*
1769          * Set back to initial state
1770          */
1771         rt2800_bbp_write(rt2x00dev, 24, 0);
1772
1773         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1774         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1775         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1776
1777         /*
1778          * set BBP back to BW20
1779          */
1780         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1781         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1782         rt2800_bbp_write(rt2x00dev, 4, bbp);
1783
1784         return 0;
1785 }
1786
1787 /*
1788  * Device state switch handlers.
1789  */
1790 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1791                                 enum dev_state state)
1792 {
1793         u32 reg;
1794
1795         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1796         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1797                            (state == STATE_RADIO_RX_ON) ||
1798                            (state == STATE_RADIO_RX_ON_LINK));
1799         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1800 }
1801
1802 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1803 {
1804         unsigned int i;
1805         u32 reg;
1806
1807         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1808                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1809                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1810                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1811                         return 0;
1812
1813                 msleep(1);
1814         }
1815
1816         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1817         return -EACCES;
1818 }
1819
1820 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1821 {
1822         u32 reg;
1823         u16 word;
1824
1825         /*
1826          * Initialize all registers.
1827          */
1828         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1829                      rt2800usb_init_registers(rt2x00dev) ||
1830                      rt2800usb_init_bbp(rt2x00dev) ||
1831                      rt2800usb_init_rfcsr(rt2x00dev)))
1832                 return -EIO;
1833
1834         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1835         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1836         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1837
1838         udelay(50);
1839
1840         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1841         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1842         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1843         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1844         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1845
1846
1847         rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1848         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1849         /* Don't use bulk in aggregation when working with USB 1.1 */
1850         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1851                            (rt2x00dev->rx->usb_maxpacket == 512));
1852         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1853         /*
1854          * Total room for RX frames in kilobytes, PBF might still exceed
1855          * this limit so reduce the number to prevent errors.
1856          */
1857         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1858                            ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1859         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1860         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1861         rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1862
1863         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1864         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1865         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1866         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1867
1868         /*
1869          * Initialize LED control
1870          */
1871         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1872         rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1873                               word & 0xff, (word >> 8) & 0xff);
1874
1875         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1876         rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1877                               word & 0xff, (word >> 8) & 0xff);
1878
1879         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1880         rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1881                               word & 0xff, (word >> 8) & 0xff);
1882
1883         return 0;
1884 }
1885
1886 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1887 {
1888         u32 reg;
1889
1890         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1891         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1892         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1893         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1894
1895         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1896         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1897         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1898
1899         /* Wait for DMA, ignore error */
1900         rt2800usb_wait_wpdma_ready(rt2x00dev);
1901
1902         rt2x00usb_disable_radio(rt2x00dev);
1903 }
1904
1905 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1906                                enum dev_state state)
1907 {
1908         if (state == STATE_AWAKE)
1909                 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1910         else
1911                 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1912
1913         return 0;
1914 }
1915
1916 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1917                                       enum dev_state state)
1918 {
1919         int retval = 0;
1920
1921         switch (state) {
1922         case STATE_RADIO_ON:
1923                 /*
1924                  * Before the radio can be enabled, the device first has
1925                  * to be woken up. After that it needs a bit of time
1926                  * to be fully awake and then the radio can be enabled.
1927                  */
1928                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1929                 msleep(1);
1930                 retval = rt2800usb_enable_radio(rt2x00dev);
1931                 break;
1932         case STATE_RADIO_OFF:
1933                 /*
1934                  * After the radio has been disabled, the device should
1935                  * be put to sleep for powersaving.
1936                  */
1937                 rt2800usb_disable_radio(rt2x00dev);
1938                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1939                 break;
1940         case STATE_RADIO_RX_ON:
1941         case STATE_RADIO_RX_ON_LINK:
1942         case STATE_RADIO_RX_OFF:
1943         case STATE_RADIO_RX_OFF_LINK:
1944                 rt2800usb_toggle_rx(rt2x00dev, state);
1945                 break;
1946         case STATE_RADIO_IRQ_ON:
1947         case STATE_RADIO_IRQ_OFF:
1948                 /* No support, but no error either */
1949                 break;
1950         case STATE_DEEP_SLEEP:
1951         case STATE_SLEEP:
1952         case STATE_STANDBY:
1953         case STATE_AWAKE:
1954                 retval = rt2800usb_set_state(rt2x00dev, state);
1955                 break;
1956         default:
1957                 retval = -ENOTSUPP;
1958                 break;
1959         }
1960
1961         if (unlikely(retval))
1962                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1963                       state, retval);
1964
1965         return retval;
1966 }
1967
1968 /*
1969  * TX descriptor initialization
1970  */
1971 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1972                                     struct sk_buff *skb,
1973                                     struct txentry_desc *txdesc)
1974 {
1975         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1976         __le32 *txi = skbdesc->desc;
1977         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1978         u32 word;
1979
1980         /*
1981          * Initialize TX Info descriptor
1982          */
1983         rt2x00_desc_read(txwi, 0, &word);
1984         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1985                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1986         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1987         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1988         rt2x00_set_field32(&word, TXWI_W0_TS,
1989                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1990         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1991                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1992         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1993         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1994         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1995         rt2x00_set_field32(&word, TXWI_W0_BW,
1996                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1997         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1998                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1999         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2000         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2001         rt2x00_desc_write(txwi, 0, word);
2002
2003         rt2x00_desc_read(txwi, 1, &word);
2004         rt2x00_set_field32(&word, TXWI_W1_ACK,
2005                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2006         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2007                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2008         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2009         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2010                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2011                            txdesc->key_idx : 0xff);
2012         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2013                            skb->len - txdesc->l2pad);
2014         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2015                            skbdesc->entry->queue->qid + 1);
2016         rt2x00_desc_write(txwi, 1, word);
2017
2018         /*
2019          * Always write 0 to IV/EIV fields, hardware will insert the IV
2020          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2021          * When TXINFO_W0_WIV is set to 1 it will use the IV data
2022          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2023          * crypto entry in the registers should be used to encrypt the frame.
2024          */
2025         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2026         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2027
2028         /*
2029          * Initialize TX descriptor
2030          */
2031         rt2x00_desc_read(txi, 0, &word);
2032         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2033                            skb->len + TXWI_DESC_SIZE);
2034         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2035                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2036         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2037         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2038         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2039         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2040                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2041         rt2x00_desc_write(txi, 0, word);
2042 }
2043
2044 /*
2045  * TX data initialization
2046  */
2047 static void rt2800usb_write_beacon(struct queue_entry *entry)
2048 {
2049         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2050         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2051         unsigned int beacon_base;
2052         u32 reg;
2053
2054         /*
2055          * Add the descriptor in front of the skb.
2056          */
2057         skb_push(entry->skb, entry->queue->desc_size);
2058         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2059         skbdesc->desc = entry->skb->data;
2060
2061         /*
2062          * Disable beaconing while we are reloading the beacon data,
2063          * otherwise we might be sending out invalid data.
2064          */
2065         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2066         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2067         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2068
2069         /*
2070          * Write entire beacon with descriptor to register.
2071          */
2072         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2073         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2074                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2075                                             entry->skb->data, entry->skb->len,
2076                                             REGISTER_TIMEOUT32(entry->skb->len));
2077
2078         /*
2079          * Clean up the beacon skb.
2080          */
2081         dev_kfree_skb(entry->skb);
2082         entry->skb = NULL;
2083 }
2084
2085 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2086 {
2087         int length;
2088
2089         /*
2090          * The length _must_ include 4 bytes padding,
2091          * it should always be multiple of 4,
2092          * but it must _not_ be a multiple of the USB packet size.
2093          */
2094         length = roundup(entry->skb->len + 4, 4);
2095         length += (4 * !(length % entry->queue->usb_maxpacket));
2096
2097         return length;
2098 }
2099
2100 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2101                                     const enum data_queue_qid queue)
2102 {
2103         u32 reg;
2104
2105         if (queue != QID_BEACON) {
2106                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2107                 return;
2108         }
2109
2110         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2111         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2112                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2113                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2114                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2115                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2116         }
2117 }
2118
2119 /*
2120  * RX control handlers
2121  */
2122 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2123                                   struct rxdone_entry_desc *rxdesc)
2124 {
2125         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2126         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2127         __le32 *rxd = (__le32 *)entry->skb->data;
2128         __le32 *rxwi;
2129         u32 rxd0;
2130         u32 rxwi0;
2131         u32 rxwi1;
2132         u32 rxwi2;
2133         u32 rxwi3;
2134
2135         /*
2136          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2137          * moving of frame data in rt2x00usb.
2138          */
2139         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2140         rxd = (__le32 *)skbdesc->desc;
2141         rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2142
2143         /*
2144          * It is now safe to read the descriptor on all architectures.
2145          */
2146         rt2x00_desc_read(rxd, 0, &rxd0);
2147         rt2x00_desc_read(rxwi, 0, &rxwi0);
2148         rt2x00_desc_read(rxwi, 1, &rxwi1);
2149         rt2x00_desc_read(rxwi, 2, &rxwi2);
2150         rt2x00_desc_read(rxwi, 3, &rxwi3);
2151
2152         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2153                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2154
2155         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2156                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2157                 rxdesc->cipher_status =
2158                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2159         }
2160
2161         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2162                 /*
2163                  * Hardware has stripped IV/EIV data from 802.11 frame during
2164                  * decryption. Unfortunately the descriptor doesn't contain
2165                  * any fields with the EIV/IV data either, so they can't
2166                  * be restored by rt2x00lib.
2167                  */
2168                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2169
2170                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2171                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2172                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2173                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2174         }
2175
2176         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2177                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2178
2179         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) {
2180                 rxdesc->dev_flags |= RXDONE_L2PAD;
2181                 skbdesc->flags |= SKBDESC_L2_PADDED;
2182         }
2183
2184         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2185                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2186
2187         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2188                 rxdesc->flags |= RX_FLAG_40MHZ;
2189
2190         /*
2191          * Detect RX rate, always use MCS as signal type.
2192          */
2193         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2194         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2195         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2196
2197         /*
2198          * Mask of 0x8 bit to remove the short preamble flag.
2199          */
2200         if (rxdesc->rate_mode == RATE_MODE_CCK)
2201                 rxdesc->signal &= ~0x8;
2202
2203         rxdesc->rssi =
2204             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2205              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2206
2207         rxdesc->noise =
2208             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2209              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2210
2211         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2212
2213         /*
2214          * Remove RXWI descriptor from start of buffer.
2215          */
2216         skb_pull(entry->skb, skbdesc->desc_len);
2217         skb_trim(entry->skb, rxdesc->size);
2218 }
2219
2220 /*
2221  * Device probe functions.
2222  */
2223 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2224 {
2225         u16 word;
2226         u8 *mac;
2227         u8 default_lna_gain;
2228
2229         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2230
2231         /*
2232          * Start validation of the data that has been read.
2233          */
2234         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2235         if (!is_valid_ether_addr(mac)) {
2236                 random_ether_addr(mac);
2237                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2238         }
2239
2240         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2241         if (word == 0xffff) {
2242                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2243                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2244                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2245                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2246                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2247         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2248                 /*
2249                  * There is a max of 2 RX streams for RT2870 series
2250                  */
2251                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2252                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2253                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2254         }
2255
2256         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2257         if (word == 0xffff) {
2258                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2259                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2260                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2261                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2262                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2263                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2264                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2265                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2266                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2267                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2268                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2269                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2270         }
2271
2272         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2273         if ((word & 0x00ff) == 0x00ff) {
2274                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2275                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2276                                    LED_MODE_TXRX_ACTIVITY);
2277                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2278                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2279                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2280                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2281                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2282                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2283         }
2284
2285         /*
2286          * During the LNA validation we are going to use
2287          * lna0 as correct value. Note that EEPROM_LNA
2288          * is never validated.
2289          */
2290         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2291         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2292
2293         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2294         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2295                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2296         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2297                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2298         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2299
2300         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2301         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2302                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2303         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2304             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2305                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2306                                    default_lna_gain);
2307         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2308
2309         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2310         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2311                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2312         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2313                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2314         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2315
2316         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2317         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2318                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2319         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2320             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2321                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2322                                    default_lna_gain);
2323         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2324
2325         return 0;
2326 }
2327
2328 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2329 {
2330         u32 reg;
2331         u16 value;
2332         u16 eeprom;
2333
2334         /*
2335          * Read EEPROM word for configuration.
2336          */
2337         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2338
2339         /*
2340          * Identify RF chipset.
2341          */
2342         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2343         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2344         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2345
2346         /*
2347          * The check for rt2860 is not a typo, some rt2870 hardware
2348          * identifies itself as rt2860 in the CSR register.
2349          */
2350         if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2351             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2352             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2353             !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2354                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2355                 return -ENODEV;
2356         }
2357
2358         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2359             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2360             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2361             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2362             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2363             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2364                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2365                 return -ENODEV;
2366         }
2367
2368         /*
2369          * Identify default antenna configuration.
2370          */
2371         rt2x00dev->default_ant.tx =
2372             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2373         rt2x00dev->default_ant.rx =
2374             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2375
2376         /*
2377          * Read frequency offset and RF programming sequence.
2378          */
2379         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2380         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2381
2382         /*
2383          * Read external LNA informations.
2384          */
2385         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2386
2387         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2388                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2389         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2390                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2391
2392         /*
2393          * Detect if this device has an hardware controlled radio.
2394          */
2395         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2396                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2397
2398         /*
2399          * Store led settings, for correct led behaviour.
2400          */
2401 #ifdef CONFIG_RT2X00_LIB_LEDS
2402         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2403         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2404         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2405
2406         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2407                            &rt2x00dev->led_mcu_reg);
2408 #endif /* CONFIG_RT2X00_LIB_LEDS */
2409
2410         return 0;
2411 }
2412
2413 /*
2414  * RF value list for rt2870
2415  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2416  */
2417 static const struct rf_channel rf_vals[] = {
2418         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2419         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2420         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2421         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2422         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2423         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2424         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2425         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2426         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2427         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2428         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2429         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2430         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2431         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2432
2433         /* 802.11 UNI / HyperLan 2 */
2434         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2435         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2436         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2437         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2438         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2439         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2440         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2441         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2442         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2443         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2444         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2445         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2446
2447         /* 802.11 HyperLan 2 */
2448         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2449         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2450         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2451         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2452         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2453         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2454         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2455         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2456         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2457         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2458         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2459         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2460         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2461         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2462         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2463         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2464
2465         /* 802.11 UNII */
2466         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2467         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2468         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2469         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2470         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2471         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2472         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2473         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2474         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2475         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2476         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2477
2478         /* 802.11 Japan */
2479         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2480         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2481         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2482         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2483         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2484         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2485         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2486 };
2487
2488 /*
2489  * RF value list for rt3070
2490  * Supports: 2.4 GHz
2491  */
2492 static const struct rf_channel rf_vals_3070[] = {
2493         {1,  241, 2, 2 },
2494         {2,  241, 2, 7 },
2495         {3,  242, 2, 2 },
2496         {4,  242, 2, 7 },
2497         {5,  243, 2, 2 },
2498         {6,  243, 2, 7 },
2499         {7,  244, 2, 2 },
2500         {8,  244, 2, 7 },
2501         {9,  245, 2, 2 },
2502         {10, 245, 2, 7 },
2503         {11, 246, 2, 2 },
2504         {12, 246, 2, 7 },
2505         {13, 247, 2, 2 },
2506         {14, 248, 2, 4 },
2507 };
2508
2509 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2510 {
2511         struct hw_mode_spec *spec = &rt2x00dev->spec;
2512         struct channel_info *info;
2513         char *tx_power1;
2514         char *tx_power2;
2515         unsigned int i;
2516         u16 eeprom;
2517
2518         /*
2519          * Initialize all hw fields.
2520          */
2521         rt2x00dev->hw->flags =
2522             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2523             IEEE80211_HW_SIGNAL_DBM |
2524             IEEE80211_HW_SUPPORTS_PS |
2525             IEEE80211_HW_PS_NULLFUNC_STACK;
2526         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2527
2528         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2529         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2530                                 rt2x00_eeprom_addr(rt2x00dev,
2531                                                    EEPROM_MAC_ADDR_0));
2532
2533         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2534
2535         /*
2536          * Initialize HT information.
2537          */
2538         spec->ht.ht_supported = true;
2539         spec->ht.cap =
2540             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2541             IEEE80211_HT_CAP_GRN_FLD |
2542             IEEE80211_HT_CAP_SGI_20 |
2543             IEEE80211_HT_CAP_SGI_40 |
2544             IEEE80211_HT_CAP_TX_STBC |
2545             IEEE80211_HT_CAP_RX_STBC |
2546             IEEE80211_HT_CAP_PSMP_SUPPORT;
2547         spec->ht.ampdu_factor = 3;
2548         spec->ht.ampdu_density = 4;
2549         spec->ht.mcs.tx_params =
2550             IEEE80211_HT_MCS_TX_DEFINED |
2551             IEEE80211_HT_MCS_TX_RX_DIFF |
2552             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2553                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2554
2555         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2556         case 3:
2557                 spec->ht.mcs.rx_mask[2] = 0xff;
2558         case 2:
2559                 spec->ht.mcs.rx_mask[1] = 0xff;
2560         case 1:
2561                 spec->ht.mcs.rx_mask[0] = 0xff;
2562                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2563                 break;
2564         }
2565
2566         /*
2567          * Initialize hw_mode information.
2568          */
2569         spec->supported_bands = SUPPORT_BAND_2GHZ;
2570         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2571
2572         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2573             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2574                 spec->num_channels = 14;
2575                 spec->channels = rf_vals;
2576         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2577                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2578                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2579                 spec->num_channels = ARRAY_SIZE(rf_vals);
2580                 spec->channels = rf_vals;
2581         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2582                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2583                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2584                 spec->channels = rf_vals_3070;
2585         }
2586
2587         /*
2588          * Create channel information array
2589          */
2590         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2591         if (!info)
2592                 return -ENOMEM;
2593
2594         spec->channels_info = info;
2595
2596         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2597         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2598
2599         for (i = 0; i < 14; i++) {
2600                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2601                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2602         }
2603
2604         if (spec->num_channels > 14) {
2605                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2606                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2607
2608                 for (i = 14; i < spec->num_channels; i++) {
2609                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2610                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2611                 }
2612         }
2613
2614         return 0;
2615 }
2616
2617 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2618 {
2619         int retval;
2620
2621         /*
2622          * Allocate eeprom data.
2623          */
2624         retval = rt2800usb_validate_eeprom(rt2x00dev);
2625         if (retval)
2626                 return retval;
2627
2628         retval = rt2800usb_init_eeprom(rt2x00dev);
2629         if (retval)
2630                 return retval;
2631
2632         /*
2633          * Initialize hw specifications.
2634          */
2635         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2636         if (retval)
2637                 return retval;
2638
2639         /*
2640          * This device has multiple filters for control frames
2641          * and has a separate filter for PS Poll frames.
2642          */
2643         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2644         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2645
2646         /*
2647          * This device requires firmware.
2648          */
2649         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2650         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2651         if (!modparam_nohwcrypt)
2652                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2653
2654         /*
2655          * Set the rssi offset.
2656          */
2657         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2658
2659         return 0;
2660 }
2661
2662 /*
2663  * IEEE80211 stack callback functions.
2664  */
2665 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2666                                    u32 *iv32, u16 *iv16)
2667 {
2668         struct rt2x00_dev *rt2x00dev = hw->priv;
2669         struct mac_iveiv_entry iveiv_entry;
2670         u32 offset;
2671
2672         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2673         rt2800_register_multiread(rt2x00dev, offset,
2674                                       &iveiv_entry, sizeof(iveiv_entry));
2675
2676         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2677         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2678 }
2679
2680 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2681 {
2682         struct rt2x00_dev *rt2x00dev = hw->priv;
2683         u32 reg;
2684         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2685
2686         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2687         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2688         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2689
2690         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2691         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2692         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2693
2694         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2695         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2696         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2697
2698         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2699         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2700         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2701
2702         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2703         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2704         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2705
2706         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2707         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2708         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2709
2710         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2711         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2712         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2713
2714         return 0;
2715 }
2716
2717 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2718                              const struct ieee80211_tx_queue_params *params)
2719 {
2720         struct rt2x00_dev *rt2x00dev = hw->priv;
2721         struct data_queue *queue;
2722         struct rt2x00_field32 field;
2723         int retval;
2724         u32 reg;
2725         u32 offset;
2726
2727         /*
2728          * First pass the configuration through rt2x00lib, that will
2729          * update the queue settings and validate the input. After that
2730          * we are free to update the registers based on the value
2731          * in the queue parameter.
2732          */
2733         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2734         if (retval)
2735                 return retval;
2736
2737         /*
2738          * We only need to perform additional register initialization
2739          * for WMM queues/
2740          */
2741         if (queue_idx >= 4)
2742                 return 0;
2743
2744         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2745
2746         /* Update WMM TXOP register */
2747         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2748         field.bit_offset = (queue_idx & 1) * 16;
2749         field.bit_mask = 0xffff << field.bit_offset;
2750
2751         rt2800_register_read(rt2x00dev, offset, &reg);
2752         rt2x00_set_field32(&reg, field, queue->txop);
2753         rt2800_register_write(rt2x00dev, offset, reg);
2754
2755         /* Update WMM registers */
2756         field.bit_offset = queue_idx * 4;
2757         field.bit_mask = 0xf << field.bit_offset;
2758
2759         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2760         rt2x00_set_field32(&reg, field, queue->aifs);
2761         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2762
2763         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2764         rt2x00_set_field32(&reg, field, queue->cw_min);
2765         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2766
2767         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2768         rt2x00_set_field32(&reg, field, queue->cw_max);
2769         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2770
2771         /* Update EDCA registers */
2772         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2773
2774         rt2800_register_read(rt2x00dev, offset, &reg);
2775         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2776         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2777         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2778         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2779         rt2800_register_write(rt2x00dev, offset, reg);
2780
2781         return 0;
2782 }
2783
2784 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2785 {
2786         struct rt2x00_dev *rt2x00dev = hw->priv;
2787         u64 tsf;
2788         u32 reg;
2789
2790         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2791         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2792         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2793         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2794
2795         return tsf;
2796 }
2797
2798 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2799         .tx                     = rt2x00mac_tx,
2800         .start                  = rt2x00mac_start,
2801         .stop                   = rt2x00mac_stop,
2802         .add_interface          = rt2x00mac_add_interface,
2803         .remove_interface       = rt2x00mac_remove_interface,
2804         .config                 = rt2x00mac_config,
2805         .configure_filter       = rt2x00mac_configure_filter,
2806         .set_tim                = rt2x00mac_set_tim,
2807         .set_key                = rt2x00mac_set_key,
2808         .get_stats              = rt2x00mac_get_stats,
2809         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2810         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2811         .bss_info_changed       = rt2x00mac_bss_info_changed,
2812         .conf_tx                = rt2800usb_conf_tx,
2813         .get_tx_stats           = rt2x00mac_get_tx_stats,
2814         .get_tsf                = rt2800usb_get_tsf,
2815         .rfkill_poll            = rt2x00mac_rfkill_poll,
2816 };
2817
2818 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2819         .probe_hw               = rt2800usb_probe_hw,
2820         .get_firmware_name      = rt2800usb_get_firmware_name,
2821         .check_firmware         = rt2800usb_check_firmware,
2822         .load_firmware          = rt2800usb_load_firmware,
2823         .initialize             = rt2x00usb_initialize,
2824         .uninitialize           = rt2x00usb_uninitialize,
2825         .clear_entry            = rt2x00usb_clear_entry,
2826         .set_device_state       = rt2800usb_set_device_state,
2827         .rfkill_poll            = rt2800usb_rfkill_poll,
2828         .link_stats             = rt2800usb_link_stats,
2829         .reset_tuner            = rt2800usb_reset_tuner,
2830         .link_tuner             = rt2800usb_link_tuner,
2831         .write_tx_desc          = rt2800usb_write_tx_desc,
2832         .write_tx_data          = rt2x00usb_write_tx_data,
2833         .write_beacon           = rt2800usb_write_beacon,
2834         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2835         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2836         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2837         .fill_rxdone            = rt2800usb_fill_rxdone,
2838         .config_shared_key      = rt2800usb_config_shared_key,
2839         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2840         .config_filter          = rt2800usb_config_filter,
2841         .config_intf            = rt2800usb_config_intf,
2842         .config_erp             = rt2800usb_config_erp,
2843         .config_ant             = rt2800usb_config_ant,
2844         .config                 = rt2800usb_config,
2845 };
2846
2847 static const struct data_queue_desc rt2800usb_queue_rx = {
2848         .entry_num              = RX_ENTRIES,
2849         .data_size              = AGGREGATION_SIZE,
2850         .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2851         .priv_size              = sizeof(struct queue_entry_priv_usb),
2852 };
2853
2854 static const struct data_queue_desc rt2800usb_queue_tx = {
2855         .entry_num              = TX_ENTRIES,
2856         .data_size              = AGGREGATION_SIZE,
2857         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2858         .priv_size              = sizeof(struct queue_entry_priv_usb),
2859 };
2860
2861 static const struct data_queue_desc rt2800usb_queue_bcn = {
2862         .entry_num              = 8 * BEACON_ENTRIES,
2863         .data_size              = MGMT_FRAME_SIZE,
2864         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2865         .priv_size              = sizeof(struct queue_entry_priv_usb),
2866 };
2867
2868 static const struct rt2x00_ops rt2800usb_ops = {
2869         .name           = KBUILD_MODNAME,
2870         .max_sta_intf   = 1,
2871         .max_ap_intf    = 8,
2872         .eeprom_size    = EEPROM_SIZE,
2873         .rf_size        = RF_SIZE,
2874         .tx_queues      = NUM_TX_QUEUES,
2875         .rx             = &rt2800usb_queue_rx,
2876         .tx             = &rt2800usb_queue_tx,
2877         .bcn            = &rt2800usb_queue_bcn,
2878         .lib            = &rt2800usb_rt2x00_ops,
2879         .hw             = &rt2800usb_mac80211_ops,
2880 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2881         .debugfs        = &rt2800usb_rt2x00debug,
2882 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2883 };
2884
2885 /*
2886  * rt2800usb module information.
2887  */
2888 static struct usb_device_id rt2800usb_device_table[] = {
2889         /* Abocom */
2890         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2891         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2892         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2893         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2894         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2895         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2896         /* AirTies */
2897         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2898         /* Amigo */
2899         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2900         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2901         /* Amit */
2902         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2903         /* ASUS */
2904         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2905         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2906         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2907         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2908         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2909         /* AzureWave */
2910         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2911         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2912         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2913         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2914         /* Belkin */
2915         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2916         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2917         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2918         { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         /* Buffalo */
2920         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2922         /* Conceptronic */
2923         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2924         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2925         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2926         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2928         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2929         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2931         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2933         /* Corega */
2934         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2935         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2936         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2937         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2938         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2939         /* D-Link */
2940         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2941         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2942         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2943         { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2944         { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2947         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2948         /* Edimax */
2949         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2950         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2951         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2952         /* Encore */
2953         { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2954         /* EnGenius */
2955         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2956         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2958         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2959         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2961         /* Gemtek */
2962         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2963         /* Gigabyte */
2964         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2965         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2966         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2967         /* Hawking */
2968         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2969         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2970         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2971         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2972         /* I-O DATA */
2973         { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2974         /* LevelOne */
2975         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2976         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2977         /* Linksys */
2978         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2979         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2980         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2981         /* Logitec */
2982         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2983         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2985         /* Motorola */
2986         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2987         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2988         /* Ovislink */
2989         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2990         /* Pegatron */
2991         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2992         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2993         { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
2994         /* Philips */
2995         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2996         /* Planex */
2997         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2998         { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2999         { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
3000         /* Qcom */
3001         { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
3002         /* Quanta */
3003         { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
3004         /* Ralink */
3005         { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
3006         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
3007         { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
3008         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
3009         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
3010         { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
3011         { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
3012         { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3013         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3014         /* Samsung */
3015         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3016         /* Siemens */
3017         { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3018         /* Sitecom */
3019         { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3020         { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3021         { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3022         { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3023         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3024         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3025         { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3026         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3027         { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3028         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3029         { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3030         { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3031         /* SMC */
3032         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3033         { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3034         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3035         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3036         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3037         { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3038         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3039         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3040         { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3041         /* Sparklan */
3042         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3043         /* Sweex */
3044         { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3045         { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3046         { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3047         /* U-Media*/
3048         { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3049         /* ZCOM */
3050         { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3051         { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3052         /* Zinwell */
3053         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3054         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3055         { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3056         { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
3057         /* Zyxel */
3058         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3059         { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3060         { 0, }
3061 };
3062
3063 MODULE_AUTHOR(DRV_PROJECT);
3064 MODULE_VERSION(DRV_VERSION);
3065 MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3066 MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3067 MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3068 MODULE_FIRMWARE(FIRMWARE_RT2870);
3069 MODULE_LICENSE("GPL");
3070
3071 static struct usb_driver rt2800usb_driver = {
3072         .name           = KBUILD_MODNAME,
3073         .id_table       = rt2800usb_device_table,
3074         .probe          = rt2x00usb_probe,
3075         .disconnect     = rt2x00usb_disconnect,
3076         .suspend        = rt2x00usb_suspend,
3077         .resume         = rt2x00usb_resume,
3078 };
3079
3080 static int __init rt2800usb_init(void)
3081 {
3082         return usb_register(&rt2800usb_driver);
3083 }
3084
3085 static void __exit rt2800usb_exit(void)
3086 {
3087         usb_deregister(&rt2800usb_driver);
3088 }
3089
3090 module_init(rt2800usb_init);
3091 module_exit(rt2800usb_exit);