3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
54 MODULE_DEVICE_TABLE(pci, rtl8180_table);
56 static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
71 static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
88 /* Queues for rtl8180/rtl8185 cards
96 * The complete map for DMA kick reg using all queue is:
97 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
99 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
100 * otherwise QoS can't be done, we use just one.
101 * Beacon queue could be used, but this is not finished yet.
105 * BC | 7 | 1 <- currently not used yet.
106 * HI | 6 | x <- not used
107 * NO | 5 | x <- not used
111 static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
113 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
115 struct rtl8180_priv *priv = dev->priv;
119 buf = (data << 8) | addr;
121 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
123 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
124 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
129 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
131 struct rtl8180_priv *priv = dev->priv;
132 unsigned int count = 32;
137 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
138 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
139 u32 flags = le32_to_cpu(entry->flags);
141 if (flags & RTL818X_RX_DESC_FLAG_OWN)
144 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
145 RTL818X_RX_DESC_FLAG_FOF |
146 RTL818X_RX_DESC_FLAG_RX_ERR)))
149 u32 flags2 = le32_to_cpu(entry->flags2);
150 struct ieee80211_rx_status rx_status = {0};
151 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
153 if (unlikely(!new_skb))
156 mapping = pci_map_single(priv->pdev,
157 skb_tail_pointer(new_skb),
158 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
160 if (pci_dma_mapping_error(priv->pdev, mapping)) {
162 dev_err(&priv->pdev->dev, "RX DMA map error\n");
167 pci_unmap_single(priv->pdev,
168 *((dma_addr_t *)skb->cb),
169 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
170 skb_put(skb, flags & 0xFFF);
172 rx_status.antenna = (flags2 >> 15) & 1;
173 rx_status.rate_idx = (flags >> 20) & 0xF;
174 agc = (flags2 >> 17) & 0x7F;
176 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
177 if (rx_status.rate_idx > 3)
178 signal = 90 - clamp_t(u8, agc, 25, 90);
180 signal = 95 - clamp_t(u8, agc, 30, 95);
183 signal = priv->rf->calc_rssi(agc, sq);
185 rx_status.signal = signal;
186 rx_status.freq = dev->conf.chandef.chan->center_freq;
187 rx_status.band = dev->conf.chandef.chan->band;
188 rx_status.mactime = le64_to_cpu(entry->tsft);
189 rx_status.flag |= RX_FLAG_MACTIME_START;
190 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
191 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
193 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
194 ieee80211_rx_irqsafe(dev, skb);
197 priv->rx_buf[priv->rx_idx] = skb;
198 *((dma_addr_t *) skb->cb) = mapping;
202 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
203 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
205 if (priv->rx_idx == 31)
206 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
207 priv->rx_idx = (priv->rx_idx + 1) % 32;
211 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
213 struct rtl8180_priv *priv = dev->priv;
214 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
216 while (skb_queue_len(&ring->queue)) {
217 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
219 struct ieee80211_tx_info *info;
220 u32 flags = le32_to_cpu(entry->flags);
222 if (flags & RTL818X_TX_DESC_FLAG_OWN)
225 ring->idx = (ring->idx + 1) % ring->entries;
226 skb = __skb_dequeue(&ring->queue);
227 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
228 skb->len, PCI_DMA_TODEVICE);
230 info = IEEE80211_SKB_CB(skb);
231 ieee80211_tx_info_clear_status(info);
233 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
234 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
235 info->flags |= IEEE80211_TX_STAT_ACK;
237 info->status.rates[0].count = (flags & 0xFF) + 1;
238 info->status.rates[1].idx = -1;
240 ieee80211_tx_status_irqsafe(dev, skb);
241 if (ring->entries - skb_queue_len(&ring->queue) == 2)
242 ieee80211_wake_queue(dev, prio);
246 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
248 struct ieee80211_hw *dev = dev_id;
249 struct rtl8180_priv *priv = dev->priv;
252 spin_lock(&priv->lock);
253 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
254 if (unlikely(reg == 0xFFFF)) {
255 spin_unlock(&priv->lock);
259 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
261 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
262 rtl8180_handle_tx(dev, 1);
264 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
265 rtl8180_handle_tx(dev, 0);
267 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
268 rtl8180_handle_rx(dev);
270 spin_unlock(&priv->lock);
275 static void rtl8180_tx(struct ieee80211_hw *dev,
276 struct ieee80211_tx_control *control,
279 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
280 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
281 struct rtl8180_priv *priv = dev->priv;
282 struct rtl8180_tx_ring *ring;
283 struct rtl8180_tx_desc *entry;
285 unsigned int idx, prio, hw_prio;
290 __le16 rts_duration = 0;
292 prio = skb_get_queue_mapping(skb);
293 ring = &priv->tx_ring[prio];
295 mapping = pci_map_single(priv->pdev, skb->data,
296 skb->len, PCI_DMA_TODEVICE);
298 if (pci_dma_mapping_error(priv->pdev, mapping)) {
300 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
305 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
306 RTL818X_TX_DESC_FLAG_LS |
307 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
310 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
311 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
312 RTL818X_TX_DESC_FLAG_NO_ENC;
314 rc_flags = info->control.rates[0].flags;
315 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
316 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
317 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
318 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
319 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
320 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
323 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
324 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
327 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
328 unsigned int remainder;
330 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
331 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
332 remainder = (16 * (skb->len + 4)) %
333 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
338 spin_lock_irqsave(&priv->lock, flags);
340 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
341 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
343 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
344 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
347 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
348 entry = &ring->desc[idx];
350 entry->rts_duration = rts_duration;
351 entry->plcp_len = cpu_to_le16(plcp_len);
352 entry->tx_buf = cpu_to_le32(mapping);
353 entry->frame_len = cpu_to_le32(skb->len);
354 entry->flags2 = info->control.rates[1].idx >= 0 ?
355 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
356 entry->retry_limit = info->control.rates[0].count;
358 /* We must be sure that tx_flags is written last because the HW
359 * looks at it to check if the rest of data is valid or not
362 entry->flags = cpu_to_le32(tx_flags);
363 /* We must be sure this has been written before followings HW
364 * register write, because this write will made the HW attempts
365 * to DMA the just-written data
369 __skb_queue_tail(&ring->queue, skb);
370 if (ring->entries - skb_queue_len(&ring->queue) < 2)
371 ieee80211_stop_queue(dev, prio);
373 spin_unlock_irqrestore(&priv->lock, flags);
375 hw_prio = rtl8180_queues_map[prio];
377 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
378 (1 << hw_prio) | /* ring to poll */
379 (1<<1) | (1<<2));/* stopped rings */
382 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
386 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
387 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
388 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
389 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
390 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
391 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
392 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
393 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
396 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
399 struct rtl8180_priv *priv = dev->priv;
404 max = fls(rates_mask) - 1;
405 min = ffs(rates_mask) - 1;
407 switch (priv->chip_family) {
409 case RTL818X_CHIP_FAMILY_RTL8180:
410 /* in 8180 this is NOT a BITMAP */
411 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
414 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
418 case RTL818X_CHIP_FAMILY_RTL8185:
419 /* in 8185 this is a BITMAP */
420 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
421 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
426 static int rtl8180_init_hw(struct ieee80211_hw *dev)
428 struct rtl8180_priv *priv = dev->priv;
431 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
432 rtl818x_ioread8(priv, &priv->map->CMD);
436 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
437 rtl818x_ioread8(priv, &priv->map->CMD);
439 reg = rtl818x_ioread8(priv, &priv->map->CMD);
441 reg |= RTL818X_CMD_RESET;
442 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
443 rtl818x_ioread8(priv, &priv->map->CMD);
446 /* check success of reset */
447 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
448 wiphy_err(dev->wiphy, "reset timeout!\n");
452 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
453 rtl818x_ioread8(priv, &priv->map->CMD);
456 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
458 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
460 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
461 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
462 reg |= (1 << 15) | (1 << 14) | (1 << 4);
463 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
466 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
468 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
469 rtl8180_set_anaparam(priv, priv->anaparam);
471 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
472 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[1].dma);
473 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
475 /* TODO: necessary? specs indicate not */
476 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
477 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
478 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
479 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
480 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
481 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
483 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
485 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
487 /* TODO: turn off hw wep on rtl8180 */
489 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
491 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
492 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
493 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
495 /* TODO: set ClkRun enable? necessary? */
496 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
497 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
498 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
499 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
500 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
501 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
503 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
505 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
506 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
511 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
512 * otherwise. bitmask 0x3 and 0x01f3 respectively.
513 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
514 * this after rf init.
515 * TODO: try to find out whether RF code really needs to do this..
517 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
518 rtl8180_conf_basic_rates(dev, 0x3);
520 rtl8180_conf_basic_rates(dev, 0x1f3);
525 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
527 struct rtl8180_priv *priv = dev->priv;
528 struct rtl8180_rx_desc *entry;
531 priv->rx_ring = pci_alloc_consistent(priv->pdev,
532 sizeof(*priv->rx_ring) * 32,
535 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
536 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
540 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
543 for (i = 0; i < 32; i++) {
544 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
546 entry = &priv->rx_ring[i];
548 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
551 priv->rx_buf[i] = skb;
552 mapping = (dma_addr_t *)skb->cb;
553 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
554 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
556 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
558 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
562 entry->rx_buf = cpu_to_le32(*mapping);
563 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
566 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
570 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
572 struct rtl8180_priv *priv = dev->priv;
575 for (i = 0; i < 32; i++) {
576 struct sk_buff *skb = priv->rx_buf[i];
580 pci_unmap_single(priv->pdev,
581 *((dma_addr_t *)skb->cb),
582 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
586 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
587 priv->rx_ring, priv->rx_ring_dma);
588 priv->rx_ring = NULL;
591 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
592 unsigned int prio, unsigned int entries)
594 struct rtl8180_priv *priv = dev->priv;
595 struct rtl8180_tx_desc *ring;
599 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
600 if (!ring || (unsigned long)ring & 0xFF) {
601 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
606 memset(ring, 0, sizeof(*ring)*entries);
607 priv->tx_ring[prio].desc = ring;
608 priv->tx_ring[prio].dma = dma;
609 priv->tx_ring[prio].idx = 0;
610 priv->tx_ring[prio].entries = entries;
611 skb_queue_head_init(&priv->tx_ring[prio].queue);
613 for (i = 0; i < entries; i++)
614 ring[i].next_tx_desc =
615 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
620 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
622 struct rtl8180_priv *priv = dev->priv;
623 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
625 while (skb_queue_len(&ring->queue)) {
626 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
627 struct sk_buff *skb = __skb_dequeue(&ring->queue);
629 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
630 skb->len, PCI_DMA_TODEVICE);
632 ring->idx = (ring->idx + 1) % ring->entries;
635 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
636 ring->desc, ring->dma);
640 static int rtl8180_start(struct ieee80211_hw *dev)
642 struct rtl8180_priv *priv = dev->priv;
646 ret = rtl8180_init_rx_ring(dev);
650 for (i = 0; i < (dev->queues + 1); i++)
651 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
654 ret = rtl8180_init_hw(dev);
658 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
659 IRQF_SHARED, KBUILD_MODNAME, dev);
661 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
665 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
667 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
668 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
670 reg = RTL818X_RX_CONF_ONLYERLPKT |
671 RTL818X_RX_CONF_RX_AUTORESETPHY |
672 RTL818X_RX_CONF_MGMT |
673 RTL818X_RX_CONF_DATA |
674 (7 << 8 /* MAX RX DMA */) |
675 RTL818X_RX_CONF_BROADCAST |
676 RTL818X_RX_CONF_NICMAC;
678 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
679 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
681 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
682 ? RTL818X_RX_CONF_CSDM1 : 0;
683 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
684 ? RTL818X_RX_CONF_CSDM2 : 0;
688 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
690 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
691 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
693 /* CW is not on per-packet basis.
694 * in rtl8185 the CW_VALUE reg is used.
696 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
697 /* retry limit IS on per-packet basis.
698 * the short and long retry limit in TX_CONF
701 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
702 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
704 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
705 /* TX antenna and TX gain are not on per-packet basis.
706 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
707 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
709 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
710 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
711 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
712 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
714 /* disable early TX */
715 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
718 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
719 reg |= (6 << 21 /* MAX TX DMA */) |
720 RTL818X_TX_CONF_NO_ICV;
724 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
725 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
727 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
729 reg &= ~RTL818X_TX_CONF_DISCW;
731 /* different meaning, same value on both rtl8185 and rtl8180 */
732 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
734 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
736 reg = rtl818x_ioread8(priv, &priv->map->CMD);
737 reg |= RTL818X_CMD_RX_ENABLE;
738 reg |= RTL818X_CMD_TX_ENABLE;
739 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
744 rtl8180_free_rx_ring(dev);
745 for (i = 0; i < (dev->queues + 1); i++)
746 if (priv->tx_ring[i].desc)
747 rtl8180_free_tx_ring(dev, i);
752 static void rtl8180_stop(struct ieee80211_hw *dev)
754 struct rtl8180_priv *priv = dev->priv;
758 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
760 reg = rtl818x_ioread8(priv, &priv->map->CMD);
761 reg &= ~RTL818X_CMD_TX_ENABLE;
762 reg &= ~RTL818X_CMD_RX_ENABLE;
763 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
767 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
768 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
769 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
770 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
772 free_irq(priv->pdev->irq, dev);
774 rtl8180_free_rx_ring(dev);
775 for (i = 0; i < (dev->queues + 1); i++)
776 rtl8180_free_tx_ring(dev, i);
779 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
780 struct ieee80211_vif *vif)
782 struct rtl8180_priv *priv = dev->priv;
784 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
785 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
788 static void rtl8180_beacon_work(struct work_struct *work)
790 struct rtl8180_vif *vif_priv =
791 container_of(work, struct rtl8180_vif, beacon_work.work);
792 struct ieee80211_vif *vif =
793 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
794 struct ieee80211_hw *dev = vif_priv->dev;
795 struct ieee80211_mgmt *mgmt;
798 /* don't overflow the tx ring */
799 if (ieee80211_queue_stopped(dev, 0))
802 /* grab a fresh beacon */
803 skb = ieee80211_beacon_get(dev, vif);
808 * update beacon timestamp w/ TSF value
809 * TODO: make hardware update beacon timestamp
811 mgmt = (struct ieee80211_mgmt *)skb->data;
812 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
814 /* TODO: use actual beacon queue */
815 skb_set_queue_mapping(skb, 0);
817 rtl8180_tx(dev, NULL, skb);
821 * schedule next beacon
822 * TODO: use hardware support for beacon timing
824 schedule_delayed_work(&vif_priv->beacon_work,
825 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
828 static int rtl8180_add_interface(struct ieee80211_hw *dev,
829 struct ieee80211_vif *vif)
831 struct rtl8180_priv *priv = dev->priv;
832 struct rtl8180_vif *vif_priv;
835 * We only support one active interface at a time.
841 case NL80211_IFTYPE_STATION:
842 case NL80211_IFTYPE_ADHOC:
850 /* Initialize driver private area */
851 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
853 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
854 vif_priv->enable_beacon = false;
856 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
857 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
858 le32_to_cpu(*(__le32 *)vif->addr));
859 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
860 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
861 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
866 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
867 struct ieee80211_vif *vif)
869 struct rtl8180_priv *priv = dev->priv;
873 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
875 struct rtl8180_priv *priv = dev->priv;
876 struct ieee80211_conf *conf = &dev->conf;
878 priv->rf->set_chan(dev, conf);
883 static int rtl8180_conf_tx(struct ieee80211_hw *dev,
884 struct ieee80211_vif *vif, u16 queue,
885 const struct ieee80211_tx_queue_params *params)
887 struct rtl8180_priv *priv = dev->priv;
890 /* nothing to do ? */
891 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
894 cw_min = fls(params->cw_min);
895 cw_max = fls(params->cw_max);
897 rtl818x_iowrite8(priv, &priv->map->CW_VAL, (cw_max << 4) | cw_min);
902 static void rtl8180_conf_erp(struct ieee80211_hw *dev,
903 struct ieee80211_bss_conf *info)
905 struct rtl8180_priv *priv = dev->priv;
910 /* TODO: should we do something ? */
911 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
914 /* I _hope_ this means 10uS for the HW.
915 * In reference code it is 0x22 for
916 * both rtl8187L and rtl8187SE
920 if (info->use_short_slot)
923 priv->slot_time = 20;
925 /* 10 is SIFS time in uS */
926 difs = 10 + 2 * priv->slot_time;
927 eifs = 10 + difs + priv->ack_time;
929 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
930 hw_eifs = DIV_ROUND_UP(eifs, 4);
933 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
934 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
935 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
937 /* from reference code. set ack timeout reg = eifs reg */
938 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
940 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
941 * the HW still wait for DIFS.
942 * HW uses 4uS units for EIFS.
944 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
946 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
949 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
950 struct ieee80211_vif *vif,
951 struct ieee80211_bss_conf *info,
954 struct rtl8180_priv *priv = dev->priv;
955 struct rtl8180_vif *vif_priv;
959 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
961 if (changed & BSS_CHANGED_BSSID) {
962 for (i = 0; i < ETH_ALEN; i++)
963 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
966 if (is_valid_ether_addr(info->bssid)) {
967 if (vif->type == NL80211_IFTYPE_ADHOC)
968 reg = RTL818X_MSR_ADHOC;
970 reg = RTL818X_MSR_INFRA;
972 reg = RTL818X_MSR_NO_LINK;
973 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
976 if (changed & BSS_CHANGED_BASIC_RATES)
977 rtl8180_conf_basic_rates(dev, info->basic_rates);
979 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
981 /* when preamble changes, acktime duration changes, and erp must
982 * be recalculated. ACK time is calculated at lowest rate.
983 * Since mac80211 include SIFS time we remove it (-10)
986 le16_to_cpu(ieee80211_generic_frame_duration(dev,
988 IEEE80211_BAND_2GHZ, 10,
989 &priv->rates[0])) - 10;
991 rtl8180_conf_erp(dev, info);
994 if (changed & BSS_CHANGED_BEACON_ENABLED)
995 vif_priv->enable_beacon = info->enable_beacon;
997 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
998 cancel_delayed_work_sync(&vif_priv->beacon_work);
999 if (vif_priv->enable_beacon)
1000 schedule_work(&vif_priv->beacon_work.work);
1004 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1005 struct netdev_hw_addr_list *mc_list)
1007 return netdev_hw_addr_list_count(mc_list);
1010 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1011 unsigned int changed_flags,
1012 unsigned int *total_flags,
1015 struct rtl8180_priv *priv = dev->priv;
1017 if (changed_flags & FIF_FCSFAIL)
1018 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1019 if (changed_flags & FIF_CONTROL)
1020 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1021 if (changed_flags & FIF_OTHER_BSS)
1022 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1023 if (*total_flags & FIF_ALLMULTI || multicast > 0)
1024 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1026 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1030 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1031 *total_flags |= FIF_FCSFAIL;
1032 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1033 *total_flags |= FIF_CONTROL;
1034 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1035 *total_flags |= FIF_OTHER_BSS;
1036 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1037 *total_flags |= FIF_ALLMULTI;
1039 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1042 static const struct ieee80211_ops rtl8180_ops = {
1044 .start = rtl8180_start,
1045 .stop = rtl8180_stop,
1046 .add_interface = rtl8180_add_interface,
1047 .remove_interface = rtl8180_remove_interface,
1048 .config = rtl8180_config,
1049 .bss_info_changed = rtl8180_bss_info_changed,
1050 .conf_tx = rtl8180_conf_tx,
1051 .prepare_multicast = rtl8180_prepare_multicast,
1052 .configure_filter = rtl8180_configure_filter,
1053 .get_tsf = rtl8180_get_tsf,
1056 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1058 struct rtl8180_priv *priv = eeprom->data;
1059 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1061 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1062 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1063 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1064 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1067 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1069 struct rtl8180_priv *priv = eeprom->data;
1072 if (eeprom->reg_data_in)
1073 reg |= RTL818X_EEPROM_CMD_WRITE;
1074 if (eeprom->reg_data_out)
1075 reg |= RTL818X_EEPROM_CMD_READ;
1076 if (eeprom->reg_data_clock)
1077 reg |= RTL818X_EEPROM_CMD_CK;
1078 if (eeprom->reg_chip_select)
1079 reg |= RTL818X_EEPROM_CMD_CS;
1081 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1082 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1086 static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1088 struct eeprom_93cx6 eeprom;
1089 int eeprom_cck_table_adr;
1094 eeprom.register_read = rtl8180_eeprom_register_read;
1095 eeprom.register_write = rtl8180_eeprom_register_write;
1096 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1097 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1099 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1101 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1102 RTL818X_EEPROM_CMD_PROGRAM);
1103 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1106 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1108 priv->rf_type = eeprom_val;
1110 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1111 priv->csthreshold = eeprom_val >> 8;
1113 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1115 eeprom_cck_table_adr = 0x10;
1118 for (i = 0; i < 14; i += 2) {
1120 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1122 priv->channels[i].hw_value = txpwr & 0xFF;
1123 priv->channels[i + 1].hw_value = txpwr >> 8;
1127 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1128 for (i = 0; i < 14; i += 2) {
1130 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1131 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1132 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1136 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1138 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1139 priv->anaparam = le32_to_cpu(anaparam);
1140 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1143 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1144 RTL818X_EEPROM_CMD_NORMAL);
1147 static int rtl8180_probe(struct pci_dev *pdev,
1148 const struct pci_device_id *id)
1150 struct ieee80211_hw *dev;
1151 struct rtl8180_priv *priv;
1152 unsigned long mem_addr, mem_len;
1153 unsigned int io_addr, io_len;
1155 const char *chip_name, *rf_name = NULL;
1158 err = pci_enable_device(pdev);
1160 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1165 err = pci_request_regions(pdev, KBUILD_MODNAME);
1167 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1172 io_addr = pci_resource_start(pdev, 0);
1173 io_len = pci_resource_len(pdev, 0);
1174 mem_addr = pci_resource_start(pdev, 1);
1175 mem_len = pci_resource_len(pdev, 1);
1177 if (mem_len < sizeof(struct rtl818x_csr) ||
1178 io_len < sizeof(struct rtl818x_csr)) {
1179 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1185 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1186 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1187 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1192 pci_set_master(pdev);
1194 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1196 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1206 SET_IEEE80211_DEV(dev, &pdev->dev);
1207 pci_set_drvdata(pdev, dev);
1209 priv->map = pci_iomap(pdev, 1, mem_len);
1211 priv->map = pci_iomap(pdev, 0, io_len);
1214 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1219 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1220 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1222 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1223 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1225 priv->band.band = IEEE80211_BAND_2GHZ;
1226 priv->band.channels = priv->channels;
1227 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1228 priv->band.bitrates = priv->rates;
1229 priv->band.n_bitrates = 4;
1230 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1232 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1233 IEEE80211_HW_RX_INCLUDES_FCS |
1234 IEEE80211_HW_SIGNAL_UNSPEC;
1235 dev->vif_data_size = sizeof(struct rtl8180_vif);
1236 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1237 BIT(NL80211_IFTYPE_ADHOC);
1238 dev->max_signal = 65;
1240 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1241 reg &= RTL818X_TX_CONF_HWVER_MASK;
1243 case RTL818X_TX_CONF_R8180_ABCD:
1244 chip_name = "RTL8180";
1245 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1248 case RTL818X_TX_CONF_R8180_F:
1249 chip_name = "RTL8180vF";
1250 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1253 case RTL818X_TX_CONF_R8185_ABC:
1254 chip_name = "RTL8185";
1255 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1258 case RTL818X_TX_CONF_R8185_D:
1259 chip_name = "RTL8185vD";
1260 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1263 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1264 pci_name(pdev), reg >> 25);
1268 /* we declare to MAC80211 all the queues except for beacon queue
1269 * that will be eventually handled by DRV.
1270 * TX rings are arranged in such a way that lower is the IDX,
1271 * higher is the priority, in order to achieve direct mapping
1272 * with mac80211, however the beacon queue is an exception and it
1273 * is mapped on the highst tx ring IDX.
1275 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1277 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1278 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1279 pci_try_set_mwi(pdev);
1282 rtl8180_eeprom_read(priv);
1284 switch (priv->rf_type) {
1285 case 1: rf_name = "Intersil";
1287 case 2: rf_name = "RFMD";
1289 case 3: priv->rf = &sa2400_rf_ops;
1291 case 4: priv->rf = &max2820_rf_ops;
1293 case 5: priv->rf = &grf5101_rf_ops;
1295 case 9: priv->rf = rtl8180_detect_rf(dev);
1298 rf_name = "RTL8255";
1301 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1302 pci_name(pdev), priv->rf_type);
1307 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1308 pci_name(pdev), rf_name);
1312 if (!is_valid_ether_addr(priv->mac_addr)) {
1313 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1314 " randomly generated MAC addr\n", pci_name(pdev));
1315 eth_random_addr(priv->mac_addr);
1317 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
1319 spin_lock_init(&priv->lock);
1321 err = ieee80211_register_hw(dev);
1323 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1328 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1329 priv->mac_addr, chip_name, priv->rf->name);
1334 pci_iounmap(pdev, priv->map);
1337 ieee80211_free_hw(dev);
1340 pci_release_regions(pdev);
1341 pci_disable_device(pdev);
1345 static void rtl8180_remove(struct pci_dev *pdev)
1347 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1348 struct rtl8180_priv *priv;
1353 ieee80211_unregister_hw(dev);
1357 pci_iounmap(pdev, priv->map);
1358 pci_release_regions(pdev);
1359 pci_disable_device(pdev);
1360 ieee80211_free_hw(dev);
1364 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1366 pci_save_state(pdev);
1367 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371 static int rtl8180_resume(struct pci_dev *pdev)
1373 pci_set_power_state(pdev, PCI_D0);
1374 pci_restore_state(pdev);
1378 #endif /* CONFIG_PM */
1380 static struct pci_driver rtl8180_driver = {
1381 .name = KBUILD_MODNAME,
1382 .id_table = rtl8180_table,
1383 .probe = rtl8180_probe,
1384 .remove = rtl8180_remove,
1386 .suspend = rtl8180_suspend,
1387 .resume = rtl8180_resume,
1388 #endif /* CONFIG_PM */
1391 module_pci_driver(rtl8180_driver);