3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
32 #include "rtl8225se.h"
34 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
35 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
36 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
37 MODULE_LICENSE("GPL");
39 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
41 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
43 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
46 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
47 { PCI_DEVICE(0x1799, 0x6001) },
48 { PCI_DEVICE(0x1799, 0x6020) },
49 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
50 { PCI_DEVICE(0x1186, 0x3301) },
51 { PCI_DEVICE(0x1432, 0x7106) },
55 MODULE_DEVICE_TABLE(pci, rtl8180_table);
57 static const struct ieee80211_rate rtl818x_rates[] = {
58 { .bitrate = 10, .hw_value = 0, },
59 { .bitrate = 20, .hw_value = 1, },
60 { .bitrate = 55, .hw_value = 2, },
61 { .bitrate = 110, .hw_value = 3, },
62 { .bitrate = 60, .hw_value = 4, },
63 { .bitrate = 90, .hw_value = 5, },
64 { .bitrate = 120, .hw_value = 6, },
65 { .bitrate = 180, .hw_value = 7, },
66 { .bitrate = 240, .hw_value = 8, },
67 { .bitrate = 360, .hw_value = 9, },
68 { .bitrate = 480, .hw_value = 10, },
69 { .bitrate = 540, .hw_value = 11, },
72 static const struct ieee80211_channel rtl818x_channels[] = {
73 { .center_freq = 2412 },
74 { .center_freq = 2417 },
75 { .center_freq = 2422 },
76 { .center_freq = 2427 },
77 { .center_freq = 2432 },
78 { .center_freq = 2437 },
79 { .center_freq = 2442 },
80 { .center_freq = 2447 },
81 { .center_freq = 2452 },
82 { .center_freq = 2457 },
83 { .center_freq = 2462 },
84 { .center_freq = 2467 },
85 { .center_freq = 2472 },
86 { .center_freq = 2484 },
89 /* Queues for rtl8187se card
100 * The complete map for DMA kick reg using use all queue is:
101 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
102 * {1, 6, 5, 4, 3, 2, 7};
104 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
107 * BC | 7 | 4 <- currently not used yet
108 * MG | 1 | x <- Not used
109 * HI | 6 | x <- Not used
115 * Beacon queue could be used, but this is not finished yet.
117 * I thougth about using the other two queues but I decided not to do this:
119 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
122 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
123 * queue but since mac80211 will do not know about it, I will probably gain
124 * some HW priority whenever the VO queue is not empty, but this gain is
125 * limited by the fact that I had to stop the mac80211 queue whenever one of
126 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
129 * - I don't know how to set in the HW the contention window params for MGMT
130 * and HI-prio queues.
133 static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = {5, 4, 3, 2, 7};
135 /* Queues for rtl8180/rtl8185 cards
143 * The complete map for DMA kick reg using all queue is:
144 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
146 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
147 * otherwise QoS can't be done, we use just one.
148 * Beacon queue could be used, but this is not finished yet.
152 * BC | 7 | 1 <- currently not used yet.
153 * HI | 6 | x <- not used
154 * NO | 5 | x <- not used
158 static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
160 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
162 struct rtl8180_priv *priv = dev->priv;
166 buf = (data << 8) | addr;
168 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
170 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
171 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
176 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
178 struct rtl8180_priv *priv = dev->priv;
179 struct rtl818x_rx_cmd_desc *cmd_desc;
180 unsigned int count = 32;
185 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz;
186 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
190 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
191 struct rtl8187se_rx_desc *desc = entry;
193 flags = le32_to_cpu(desc->flags);
194 flags2 = le32_to_cpu(desc->flags2);
195 tsft = le64_to_cpu(desc->tsft);
197 struct rtl8180_rx_desc *desc = entry;
199 flags = le32_to_cpu(desc->flags);
200 flags2 = le32_to_cpu(desc->flags2);
201 tsft = le64_to_cpu(desc->tsft);
204 if (flags & RTL818X_RX_DESC_FLAG_OWN)
207 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
208 RTL818X_RX_DESC_FLAG_FOF |
209 RTL818X_RX_DESC_FLAG_RX_ERR)))
212 struct ieee80211_rx_status rx_status = {0};
213 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
215 if (unlikely(!new_skb))
218 mapping = pci_map_single(priv->pdev,
219 skb_tail_pointer(new_skb),
220 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
222 if (pci_dma_mapping_error(priv->pdev, mapping)) {
224 dev_err(&priv->pdev->dev, "RX DMA map error\n");
229 pci_unmap_single(priv->pdev,
230 *((dma_addr_t *)skb->cb),
231 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
232 skb_put(skb, flags & 0xFFF);
234 rx_status.antenna = (flags2 >> 15) & 1;
235 rx_status.rate_idx = (flags >> 20) & 0xF;
236 agc = (flags2 >> 17) & 0x7F;
238 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
239 if (rx_status.rate_idx > 3)
240 signal = 90 - clamp_t(u8, agc, 25, 90);
242 signal = 95 - clamp_t(u8, agc, 30, 95);
243 } else if (priv->chip_family ==
244 RTL818X_CHIP_FAMILY_RTL8180) {
246 signal = priv->rf->calc_rssi(agc, sq);
248 /* TODO: rtl8187se rssi */
251 rx_status.signal = signal;
252 rx_status.freq = dev->conf.chandef.chan->center_freq;
253 rx_status.band = dev->conf.chandef.chan->band;
254 rx_status.mactime = tsft;
255 rx_status.flag |= RX_FLAG_MACTIME_START;
256 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
257 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
259 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
260 ieee80211_rx_irqsafe(dev, skb);
263 priv->rx_buf[priv->rx_idx] = skb;
264 *((dma_addr_t *) skb->cb) = mapping;
269 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
270 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
272 if (priv->rx_idx == 31)
274 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
275 priv->rx_idx = (priv->rx_idx + 1) % 32;
279 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
281 struct rtl8180_priv *priv = dev->priv;
282 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
284 while (skb_queue_len(&ring->queue)) {
285 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
287 struct ieee80211_tx_info *info;
288 u32 flags = le32_to_cpu(entry->flags);
290 if (flags & RTL818X_TX_DESC_FLAG_OWN)
293 ring->idx = (ring->idx + 1) % ring->entries;
294 skb = __skb_dequeue(&ring->queue);
295 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
296 skb->len, PCI_DMA_TODEVICE);
298 info = IEEE80211_SKB_CB(skb);
299 ieee80211_tx_info_clear_status(info);
301 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
302 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
303 info->flags |= IEEE80211_TX_STAT_ACK;
305 info->status.rates[0].count = (flags & 0xFF) + 1;
306 info->status.rates[1].idx = -1;
308 ieee80211_tx_status_irqsafe(dev, skb);
309 if (ring->entries - skb_queue_len(&ring->queue) == 2)
310 ieee80211_wake_queue(dev, prio);
314 static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id)
316 struct ieee80211_hw *dev = dev_id;
317 struct rtl8180_priv *priv = dev->priv;
322 spin_lock_irqsave(&priv->lock, flags);
323 /* Note: 32-bit interrupt status */
324 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE);
325 if (unlikely(reg == 0xFFFFFFFF)) {
326 spin_unlock_irqrestore(&priv->lock, flags);
330 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg);
332 if (reg & IMR_TIMEOUT1)
333 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
335 if (reg & (IMR_TBDOK | IMR_TBDER))
336 rtl8180_handle_tx(dev, 4);
338 if (reg & (IMR_TVODOK | IMR_TVODER))
339 rtl8180_handle_tx(dev, 0);
341 if (reg & (IMR_TVIDOK | IMR_TVIDER))
342 rtl8180_handle_tx(dev, 1);
344 if (reg & (IMR_TBEDOK | IMR_TBEDER))
345 rtl8180_handle_tx(dev, 2);
347 if (reg & (IMR_TBKDOK | IMR_TBKDER))
348 rtl8180_handle_tx(dev, 3);
350 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK))
351 rtl8180_handle_rx(dev);
352 /* The interface sometimes generates several RX DMA descriptor errors
353 * at startup. Do not report these.
355 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2)
357 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n");
359 spin_unlock_irqrestore(&priv->lock, flags);
363 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
365 struct ieee80211_hw *dev = dev_id;
366 struct rtl8180_priv *priv = dev->priv;
369 spin_lock(&priv->lock);
370 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
371 if (unlikely(reg == 0xFFFF)) {
372 spin_unlock(&priv->lock);
376 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
378 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
379 rtl8180_handle_tx(dev, 1);
381 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
382 rtl8180_handle_tx(dev, 0);
384 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
385 rtl8180_handle_rx(dev);
387 spin_unlock(&priv->lock);
392 static void rtl8180_tx(struct ieee80211_hw *dev,
393 struct ieee80211_tx_control *control,
396 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
397 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
398 struct rtl8180_priv *priv = dev->priv;
399 struct rtl8180_tx_ring *ring;
400 struct rtl8180_tx_desc *entry;
402 unsigned int idx, prio, hw_prio;
407 __le16 rts_duration = 0;
408 /* do arithmetic and then convert to le16 */
409 u16 frame_duration = 0;
411 prio = skb_get_queue_mapping(skb);
412 ring = &priv->tx_ring[prio];
414 mapping = pci_map_single(priv->pdev, skb->data,
415 skb->len, PCI_DMA_TODEVICE);
417 if (pci_dma_mapping_error(priv->pdev, mapping)) {
419 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
423 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
424 RTL818X_TX_DESC_FLAG_LS |
425 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
428 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
429 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
430 RTL818X_TX_DESC_FLAG_NO_ENC;
432 rc_flags = info->control.rates[0].flags;
433 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
434 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
435 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
436 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
437 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
438 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
441 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
442 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
445 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
446 unsigned int remainder;
448 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
449 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
450 remainder = (16 * (skb->len + 4)) %
451 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
456 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
458 /* SIFS time (required by HW) is already included by
459 * ieee80211_generic_frame_duration
461 duration = ieee80211_generic_frame_duration(dev, priv->vif,
462 IEEE80211_BAND_2GHZ, skb->len,
463 ieee80211_get_tx_rate(dev, info));
465 frame_duration = priv->ack_time + le16_to_cpu(duration);
468 spin_lock_irqsave(&priv->lock, flags);
470 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
471 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
473 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
474 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
477 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
478 entry = &ring->desc[idx];
480 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
481 entry->frame_duration = cpu_to_le16(frame_duration);
482 entry->frame_len_se = cpu_to_le16(skb->len);
485 entry->flags3 = cpu_to_le16(1<<4);
487 entry->frame_len = cpu_to_le32(skb->len);
489 entry->rts_duration = rts_duration;
490 entry->plcp_len = cpu_to_le16(plcp_len);
491 entry->tx_buf = cpu_to_le32(mapping);
493 entry->flags2 = info->control.rates[1].idx >= 0 ?
494 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
495 entry->retry_limit = info->control.rates[0].count;
497 /* We must be sure that tx_flags is written last because the HW
498 * looks at it to check if the rest of data is valid or not
501 entry->flags = cpu_to_le32(tx_flags);
502 /* We must be sure this has been written before followings HW
503 * register write, because this write will made the HW attempts
504 * to DMA the just-written data
508 __skb_queue_tail(&ring->queue, skb);
509 if (ring->entries - skb_queue_len(&ring->queue) < 2)
510 ieee80211_stop_queue(dev, prio);
512 spin_unlock_irqrestore(&priv->lock, flags);
514 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
515 /* just poll: rings are stopped with TPPollStop reg */
516 hw_prio = rtl8187se_queues_map[prio];
517 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
520 hw_prio = rtl8180_queues_map[prio];
521 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
522 (1 << hw_prio) | /* ring to poll */
523 (1<<1) | (1<<2));/* stopped rings */
527 static void rtl8180_set_anaparam3(struct rtl8180_priv *priv, u16 anaparam3)
531 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
532 RTL818X_EEPROM_CMD_CONFIG);
534 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
535 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
536 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
538 rtl818x_iowrite16(priv, &priv->map->ANAPARAM3, anaparam3);
540 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
541 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
543 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
544 RTL818X_EEPROM_CMD_NORMAL);
547 void rtl8180_set_anaparam2(struct rtl8180_priv *priv, u32 anaparam2)
551 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
552 RTL818X_EEPROM_CMD_CONFIG);
554 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
555 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
556 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
558 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
560 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
561 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
563 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
564 RTL818X_EEPROM_CMD_NORMAL);
567 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
571 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
572 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
573 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
574 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
575 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
576 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
577 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
578 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
581 static void rtl8187se_mac_config(struct ieee80211_hw *dev)
583 struct rtl8180_priv *priv = dev->priv;
586 rtl818x_iowrite32(priv, REG_ADDR4(0x1F0), 0);
587 rtl818x_ioread32(priv, REG_ADDR4(0x1F0));
588 rtl818x_iowrite32(priv, REG_ADDR4(0x1F4), 0);
589 rtl818x_ioread32(priv, REG_ADDR4(0x1F4));
590 rtl818x_iowrite8(priv, REG_ADDR1(0x1F8), 0);
591 rtl818x_ioread8(priv, REG_ADDR1(0x1F8));
592 /* Enable DA10 TX power saving */
593 reg = rtl818x_ioread8(priv, &priv->map->PHY_PR);
594 rtl818x_iowrite8(priv, &priv->map->PHY_PR, reg | 0x04);
596 rtl818x_iowrite16(priv, PI_DATA_REG, 0x1000);
597 rtl818x_iowrite16(priv, SI_DATA_REG, 0x1000);
598 /* AFE - default to power ON */
599 rtl818x_iowrite16(priv, REG_ADDR2(0x370), 0x0560);
600 rtl818x_iowrite16(priv, REG_ADDR2(0x372), 0x0560);
601 rtl818x_iowrite16(priv, REG_ADDR2(0x374), 0x0DA4);
602 rtl818x_iowrite16(priv, REG_ADDR2(0x376), 0x0DA4);
603 rtl818x_iowrite16(priv, REG_ADDR2(0x378), 0x0560);
604 rtl818x_iowrite16(priv, REG_ADDR2(0x37A), 0x0560);
605 rtl818x_iowrite16(priv, REG_ADDR2(0x37C), 0x00EC);
606 rtl818x_iowrite16(priv, REG_ADDR2(0x37E), 0x00EC);
607 rtl818x_iowrite8(priv, REG_ADDR1(0x24E), 0x01);
608 /* unknown, needed for suspend to RAM resume */
609 rtl818x_iowrite8(priv, REG_ADDR1(0x0A), 0x72);
612 static void rtl8187se_set_antenna_config(struct ieee80211_hw *dev, u8 def_ant,
615 struct rtl8180_priv *priv = dev->priv;
617 rtl8225_write_phy_cck(dev, 0x0C, 0x09);
620 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
621 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
622 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
623 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
624 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
625 } else { /* main antenna */
626 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
627 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
628 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
629 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
630 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
632 } else { /* disable antenna diversity */
634 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
635 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
636 rtl8225_write_phy_cck(dev, 0x01, 0x47);
637 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
638 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
639 } else { /* main antenna */
640 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
641 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
642 rtl8225_write_phy_cck(dev, 0x01, 0x47);
643 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
644 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
647 /* priv->curr_ant = def_ant; */
650 static void rtl8180_int_enable(struct ieee80211_hw *dev)
652 struct rtl8180_priv *priv = dev->priv;
654 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
655 rtl818x_iowrite32(priv, &priv->map->IMR, IMR_TMGDOK |
656 IMR_TBDER | IMR_THPDER |
657 IMR_THPDER | IMR_THPDOK |
658 IMR_TVODER | IMR_TVODOK |
659 IMR_TVIDER | IMR_TVIDOK |
660 IMR_TBEDER | IMR_TBEDOK |
661 IMR_TBKDER | IMR_TBKDOK |
663 IMR_ROK | IMR_RQOSOK);
665 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
669 static void rtl8180_int_disable(struct ieee80211_hw *dev)
671 struct rtl8180_priv *priv = dev->priv;
673 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
674 rtl818x_iowrite32(priv, &priv->map->IMR, 0);
676 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
680 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
683 struct rtl8180_priv *priv = dev->priv;
688 max = fls(rates_mask) - 1;
689 min = ffs(rates_mask) - 1;
691 switch (priv->chip_family) {
693 case RTL818X_CHIP_FAMILY_RTL8180:
694 /* in 8180 this is NOT a BITMAP */
695 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
698 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
701 case RTL818X_CHIP_FAMILY_RTL8185:
702 /* in 8185 this is a BITMAP */
703 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
704 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
707 case RTL818X_CHIP_FAMILY_RTL8187SE:
708 /* in 8187se this is a BITMAP */
709 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, rates_mask);
714 static void rtl8180_config_cardbus(struct ieee80211_hw *dev)
716 struct rtl8180_priv *priv = dev->priv;
720 reg8 = rtl818x_ioread8(priv, &priv->map->CONFIG3);
722 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg8);
724 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
725 rtl818x_iowrite16(priv, FEMR_SE, 0xffff);
727 reg16 = rtl818x_ioread16(priv, &priv->map->FEMR);
728 reg16 |= (1 << 15) | (1 << 14) | (1 << 4);
729 rtl818x_iowrite16(priv, &priv->map->FEMR, reg16);
734 static int rtl8180_init_hw(struct ieee80211_hw *dev)
736 struct rtl8180_priv *priv = dev->priv;
740 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
741 rtl818x_ioread8(priv, &priv->map->CMD);
745 rtl8180_int_disable(dev);
746 rtl818x_ioread8(priv, &priv->map->CMD);
748 reg = rtl818x_ioread8(priv, &priv->map->CMD);
750 reg |= RTL818X_CMD_RESET;
751 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
752 rtl818x_ioread8(priv, &priv->map->CMD);
755 /* check success of reset */
756 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
757 wiphy_err(dev->wiphy, "reset timeout!\n");
761 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
762 rtl818x_ioread8(priv, &priv->map->CMD);
765 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
766 rtl8180_config_cardbus(dev);
769 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
770 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
772 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
774 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
775 rtl8180_set_anaparam(priv, priv->anaparam);
777 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
778 /* mac80211 queue have higher prio for lower index. The last queue
779 * (that mac80211 is not aware of) is reserved for beacons (and have
780 * the highest priority on the NIC)
782 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
783 rtl818x_iowrite32(priv, &priv->map->TBDA,
784 priv->tx_ring[1].dma);
785 rtl818x_iowrite32(priv, &priv->map->TLPDA,
786 priv->tx_ring[0].dma);
788 rtl818x_iowrite32(priv, &priv->map->TBDA,
789 priv->tx_ring[4].dma);
790 rtl818x_iowrite32(priv, &priv->map->TVODA,
791 priv->tx_ring[0].dma);
792 rtl818x_iowrite32(priv, &priv->map->TVIDA,
793 priv->tx_ring[1].dma);
794 rtl818x_iowrite32(priv, &priv->map->TBEDA,
795 priv->tx_ring[2].dma);
796 rtl818x_iowrite32(priv, &priv->map->TBKDA,
797 priv->tx_ring[3].dma);
800 /* TODO: necessary? specs indicate not */
801 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
802 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
803 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
804 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
805 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
806 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
808 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
810 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
812 /* TODO: turn off hw wep on rtl8180 */
814 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
816 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
817 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
818 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
820 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
822 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
823 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
826 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
827 /* TODO: set ClkRun enable? necessary? */
828 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
829 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
830 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
831 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
832 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
833 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
836 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
838 /* the set auto rate fallback bitmask from 1M to 54 Mb/s */
839 rtl818x_iowrite16(priv, ARFR, 0xFFF);
840 rtl818x_ioread16(priv, ARFR);
842 /* stop unused queus (no dma alloc) */
843 rtl818x_iowrite8(priv, &priv->map->TPPOLL_STOP,
844 RTL818x_TPPOLL_STOP_MG | RTL818x_TPPOLL_STOP_HI);
846 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0x00);
847 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
849 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
851 /* some black magic here.. */
852 rtl8187se_mac_config(dev);
854 rtl818x_iowrite16(priv, RFSW_CTRL, 0x569A);
855 rtl818x_ioread16(priv, RFSW_CTRL);
857 rtl8180_set_anaparam(priv, RTL8225SE_ANAPARAM_ON);
858 rtl8180_set_anaparam2(priv, RTL8225SE_ANAPARAM2_ON);
859 rtl8180_set_anaparam3(priv, RTL8225SE_ANAPARAM3);
862 rtl818x_iowrite8(priv, &priv->map->CONFIG5,
863 rtl818x_ioread8(priv, &priv->map->CONFIG5) & 0x7F);
865 /*probably this switch led on */
866 rtl818x_iowrite8(priv, &priv->map->PGSELECT,
867 rtl818x_ioread8(priv, &priv->map->PGSELECT) | 0x08);
869 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
870 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1BFF);
871 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
873 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x4003);
875 /* the reference code mac hardcode table write
876 * this reg by doing byte-wide accesses.
877 * It does it just for lowest and highest byte..
879 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA);
882 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32);
887 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
888 * otherwise. bitmask 0x3 and 0x01f3 respectively.
889 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
890 * this after rf init.
891 * TODO: try to find out whether RF code really needs to do this..
893 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
894 rtl8180_conf_basic_rates(dev, 0x3);
896 rtl8180_conf_basic_rates(dev, 0x1f3);
898 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
899 rtl8187se_set_antenna_config(dev,
900 priv->antenna_diversity_default,
901 priv->antenna_diversity_en);
905 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
907 struct rtl8180_priv *priv = dev->priv;
908 struct rtl818x_rx_cmd_desc *entry;
911 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
912 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc);
914 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc);
916 priv->rx_ring = pci_alloc_consistent(priv->pdev,
917 priv->rx_ring_sz * 32,
920 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
921 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
925 memset(priv->rx_ring, 0, priv->rx_ring_sz * 32);
928 for (i = 0; i < 32; i++) {
929 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
931 entry = priv->rx_ring + priv->rx_ring_sz*i;
933 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
936 priv->rx_buf[i] = skb;
937 mapping = (dma_addr_t *)skb->cb;
938 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
939 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
941 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
943 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
947 entry->rx_buf = cpu_to_le32(*mapping);
948 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
951 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
955 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
957 struct rtl8180_priv *priv = dev->priv;
960 for (i = 0; i < 32; i++) {
961 struct sk_buff *skb = priv->rx_buf[i];
965 pci_unmap_single(priv->pdev,
966 *((dma_addr_t *)skb->cb),
967 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
971 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
972 priv->rx_ring, priv->rx_ring_dma);
973 priv->rx_ring = NULL;
976 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
977 unsigned int prio, unsigned int entries)
979 struct rtl8180_priv *priv = dev->priv;
980 struct rtl8180_tx_desc *ring;
984 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
985 if (!ring || (unsigned long)ring & 0xFF) {
986 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
991 memset(ring, 0, sizeof(*ring)*entries);
992 priv->tx_ring[prio].desc = ring;
993 priv->tx_ring[prio].dma = dma;
994 priv->tx_ring[prio].idx = 0;
995 priv->tx_ring[prio].entries = entries;
996 skb_queue_head_init(&priv->tx_ring[prio].queue);
998 for (i = 0; i < entries; i++)
999 ring[i].next_tx_desc =
1000 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
1005 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
1007 struct rtl8180_priv *priv = dev->priv;
1008 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
1010 while (skb_queue_len(&ring->queue)) {
1011 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
1012 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1014 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
1015 skb->len, PCI_DMA_TODEVICE);
1017 ring->idx = (ring->idx + 1) % ring->entries;
1020 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
1021 ring->desc, ring->dma);
1025 static int rtl8180_start(struct ieee80211_hw *dev)
1027 struct rtl8180_priv *priv = dev->priv;
1031 ret = rtl8180_init_rx_ring(dev);
1035 for (i = 0; i < (dev->queues + 1); i++)
1036 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
1037 goto err_free_rings;
1039 ret = rtl8180_init_hw(dev);
1041 goto err_free_rings;
1043 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1044 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt,
1045 IRQF_SHARED, KBUILD_MODNAME, dev);
1047 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
1048 IRQF_SHARED, KBUILD_MODNAME, dev);
1052 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1053 goto err_free_rings;
1056 rtl8180_int_enable(dev);
1058 /* in rtl8187se at MAR regs offset there is the management
1059 * TX descriptor DMA addres..
1061 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
1062 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
1063 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
1066 reg = RTL818X_RX_CONF_ONLYERLPKT |
1067 RTL818X_RX_CONF_RX_AUTORESETPHY |
1068 RTL818X_RX_CONF_MGMT |
1069 RTL818X_RX_CONF_DATA |
1070 (7 << 8 /* MAX RX DMA */) |
1071 RTL818X_RX_CONF_BROADCAST |
1072 RTL818X_RX_CONF_NICMAC;
1074 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
1075 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
1076 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1077 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
1078 ? RTL818X_RX_CONF_CSDM1 : 0;
1079 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
1080 ? RTL818X_RX_CONF_CSDM2 : 0;
1082 reg &= ~(RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2);
1085 priv->rx_conf = reg;
1086 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
1088 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1089 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
1091 /* CW is not on per-packet basis.
1092 * in rtl8185 the CW_VALUE reg is used.
1094 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
1095 /* retry limit IS on per-packet basis.
1096 * the short and long retry limit in TX_CONF
1099 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
1100 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
1102 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
1103 /* TX antenna and TX gain are not on per-packet basis.
1104 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
1105 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
1107 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
1108 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
1109 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
1110 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
1112 /* disable early TX */
1113 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
1116 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1117 reg |= (6 << 21 /* MAX TX DMA */) |
1118 RTL818X_TX_CONF_NO_ICV;
1120 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1121 reg |= 1<<30; /* "duration procedure mode" */
1123 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
1124 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
1126 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
1128 reg &= ~RTL818X_TX_CONF_DISCW;
1130 /* different meaning, same value on both rtl8185 and rtl8180 */
1131 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
1133 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1135 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1136 reg |= RTL818X_CMD_RX_ENABLE;
1137 reg |= RTL818X_CMD_TX_ENABLE;
1138 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1143 rtl8180_free_rx_ring(dev);
1144 for (i = 0; i < (dev->queues + 1); i++)
1145 if (priv->tx_ring[i].desc)
1146 rtl8180_free_tx_ring(dev, i);
1151 static void rtl8180_stop(struct ieee80211_hw *dev)
1153 struct rtl8180_priv *priv = dev->priv;
1157 rtl8180_int_disable(dev);
1159 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1160 reg &= ~RTL818X_CMD_TX_ENABLE;
1161 reg &= ~RTL818X_CMD_RX_ENABLE;
1162 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1164 priv->rf->stop(dev);
1166 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1167 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1168 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1169 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1171 free_irq(priv->pdev->irq, dev);
1173 rtl8180_free_rx_ring(dev);
1174 for (i = 0; i < (dev->queues + 1); i++)
1175 rtl8180_free_tx_ring(dev, i);
1178 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
1179 struct ieee80211_vif *vif)
1181 struct rtl8180_priv *priv = dev->priv;
1183 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1184 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1187 static void rtl8180_beacon_work(struct work_struct *work)
1189 struct rtl8180_vif *vif_priv =
1190 container_of(work, struct rtl8180_vif, beacon_work.work);
1191 struct ieee80211_vif *vif =
1192 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1193 struct ieee80211_hw *dev = vif_priv->dev;
1194 struct ieee80211_mgmt *mgmt;
1195 struct sk_buff *skb;
1197 /* don't overflow the tx ring */
1198 if (ieee80211_queue_stopped(dev, 0))
1201 /* grab a fresh beacon */
1202 skb = ieee80211_beacon_get(dev, vif);
1207 * update beacon timestamp w/ TSF value
1208 * TODO: make hardware update beacon timestamp
1210 mgmt = (struct ieee80211_mgmt *)skb->data;
1211 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
1213 /* TODO: use actual beacon queue */
1214 skb_set_queue_mapping(skb, 0);
1216 rtl8180_tx(dev, NULL, skb);
1220 * schedule next beacon
1221 * TODO: use hardware support for beacon timing
1223 schedule_delayed_work(&vif_priv->beacon_work,
1224 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1227 static int rtl8180_add_interface(struct ieee80211_hw *dev,
1228 struct ieee80211_vif *vif)
1230 struct rtl8180_priv *priv = dev->priv;
1231 struct rtl8180_vif *vif_priv;
1234 * We only support one active interface at a time.
1239 switch (vif->type) {
1240 case NL80211_IFTYPE_STATION:
1241 case NL80211_IFTYPE_ADHOC:
1249 /* Initialize driver private area */
1250 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1251 vif_priv->dev = dev;
1252 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
1253 vif_priv->enable_beacon = false;
1255 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1256 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1257 le32_to_cpu(*(__le32 *)vif->addr));
1258 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1259 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1260 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1265 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1266 struct ieee80211_vif *vif)
1268 struct rtl8180_priv *priv = dev->priv;
1272 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
1274 struct rtl8180_priv *priv = dev->priv;
1275 struct ieee80211_conf *conf = &dev->conf;
1277 priv->rf->set_chan(dev, conf);
1282 static int rtl8180_conf_tx(struct ieee80211_hw *dev,
1283 struct ieee80211_vif *vif, u16 queue,
1284 const struct ieee80211_tx_queue_params *params)
1286 struct rtl8180_priv *priv = dev->priv;
1289 /* nothing to do ? */
1290 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1293 cw_min = fls(params->cw_min);
1294 cw_max = fls(params->cw_max);
1296 rtl818x_iowrite8(priv, &priv->map->CW_VAL, (cw_max << 4) | cw_min);
1301 static void rtl8180_conf_erp(struct ieee80211_hw *dev,
1302 struct ieee80211_bss_conf *info)
1304 struct rtl8180_priv *priv = dev->priv;
1309 /* TODO: should we do something ? */
1310 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1313 /* I _hope_ this means 10uS for the HW.
1314 * In reference code it is 0x22 for
1315 * both rtl8187L and rtl8187SE
1319 if (info->use_short_slot)
1320 priv->slot_time = 9;
1322 priv->slot_time = 20;
1324 /* 10 is SIFS time in uS */
1325 difs = 10 + 2 * priv->slot_time;
1326 eifs = 10 + difs + priv->ack_time;
1328 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1329 hw_eifs = DIV_ROUND_UP(eifs, 4);
1332 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1333 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
1334 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1336 /* from reference code. set ack timeout reg = eifs reg */
1337 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
1339 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1340 rtl818x_iowrite8(priv, &priv->map->EIFS_8187SE, hw_eifs);
1341 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
1342 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1343 * the HW still wait for DIFS.
1344 * HW uses 4uS units for EIFS.
1346 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
1348 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
1352 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
1353 struct ieee80211_vif *vif,
1354 struct ieee80211_bss_conf *info,
1357 struct rtl8180_priv *priv = dev->priv;
1358 struct rtl8180_vif *vif_priv;
1362 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1364 if (changed & BSS_CHANGED_BSSID) {
1365 for (i = 0; i < ETH_ALEN; i++)
1366 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1369 if (is_valid_ether_addr(info->bssid)) {
1370 if (vif->type == NL80211_IFTYPE_ADHOC)
1371 reg = RTL818X_MSR_ADHOC;
1373 reg = RTL818X_MSR_INFRA;
1375 reg = RTL818X_MSR_NO_LINK;
1377 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1378 reg |= RTL818X_MSR_ENEDCA;
1380 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1383 if (changed & BSS_CHANGED_BASIC_RATES)
1384 rtl8180_conf_basic_rates(dev, info->basic_rates);
1386 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
1388 /* when preamble changes, acktime duration changes, and erp must
1389 * be recalculated. ACK time is calculated at lowest rate.
1390 * Since mac80211 include SIFS time we remove it (-10)
1393 le16_to_cpu(ieee80211_generic_frame_duration(dev,
1395 IEEE80211_BAND_2GHZ, 10,
1396 &priv->rates[0])) - 10;
1398 rtl8180_conf_erp(dev, info);
1401 if (changed & BSS_CHANGED_BEACON_ENABLED)
1402 vif_priv->enable_beacon = info->enable_beacon;
1404 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1405 cancel_delayed_work_sync(&vif_priv->beacon_work);
1406 if (vif_priv->enable_beacon)
1407 schedule_work(&vif_priv->beacon_work.work);
1411 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1412 struct netdev_hw_addr_list *mc_list)
1414 return netdev_hw_addr_list_count(mc_list);
1417 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1418 unsigned int changed_flags,
1419 unsigned int *total_flags,
1422 struct rtl8180_priv *priv = dev->priv;
1424 if (changed_flags & FIF_FCSFAIL)
1425 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1426 if (changed_flags & FIF_CONTROL)
1427 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1428 if (changed_flags & FIF_OTHER_BSS)
1429 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1430 if (*total_flags & FIF_ALLMULTI || multicast > 0)
1431 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1433 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1437 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1438 *total_flags |= FIF_FCSFAIL;
1439 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1440 *total_flags |= FIF_CONTROL;
1441 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1442 *total_flags |= FIF_OTHER_BSS;
1443 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1444 *total_flags |= FIF_ALLMULTI;
1446 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1449 static const struct ieee80211_ops rtl8180_ops = {
1451 .start = rtl8180_start,
1452 .stop = rtl8180_stop,
1453 .add_interface = rtl8180_add_interface,
1454 .remove_interface = rtl8180_remove_interface,
1455 .config = rtl8180_config,
1456 .bss_info_changed = rtl8180_bss_info_changed,
1457 .conf_tx = rtl8180_conf_tx,
1458 .prepare_multicast = rtl8180_prepare_multicast,
1459 .configure_filter = rtl8180_configure_filter,
1460 .get_tsf = rtl8180_get_tsf,
1463 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1465 struct rtl8180_priv *priv = eeprom->data;
1466 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1468 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1469 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1470 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1471 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1474 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1476 struct rtl8180_priv *priv = eeprom->data;
1479 if (eeprom->reg_data_in)
1480 reg |= RTL818X_EEPROM_CMD_WRITE;
1481 if (eeprom->reg_data_out)
1482 reg |= RTL818X_EEPROM_CMD_READ;
1483 if (eeprom->reg_data_clock)
1484 reg |= RTL818X_EEPROM_CMD_CK;
1485 if (eeprom->reg_chip_select)
1486 reg |= RTL818X_EEPROM_CMD_CS;
1488 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1489 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1493 static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1495 struct eeprom_93cx6 eeprom;
1496 int eeprom_cck_table_adr;
1501 eeprom.register_read = rtl8180_eeprom_register_read;
1502 eeprom.register_write = rtl8180_eeprom_register_write;
1503 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1504 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1506 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1508 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1509 RTL818X_EEPROM_CMD_PROGRAM);
1510 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1513 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1515 priv->rf_type = eeprom_val;
1517 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1518 priv->csthreshold = eeprom_val >> 8;
1520 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1522 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1523 eeprom_cck_table_adr = 0x30;
1525 eeprom_cck_table_adr = 0x10;
1528 for (i = 0; i < 14; i += 2) {
1530 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1532 priv->channels[i].hw_value = txpwr & 0xFF;
1533 priv->channels[i + 1].hw_value = txpwr >> 8;
1537 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1538 for (i = 0; i < 14; i += 2) {
1540 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1541 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1542 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1546 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1548 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1549 priv->anaparam = le32_to_cpu(anaparam);
1550 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1553 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1554 eeprom_93cx6_read(&eeprom, 0x3F, &eeprom_val);
1555 priv->antenna_diversity_en = !!(eeprom_val & 0x100);
1556 priv->antenna_diversity_default = (eeprom_val & 0xC00) == 0x400;
1558 eeprom_93cx6_read(&eeprom, 0x7C, &eeprom_val);
1559 priv->xtal_out = eeprom_val & 0xF;
1560 priv->xtal_in = (eeprom_val & 0xF0) >> 4;
1561 priv->xtal_cal = !!(eeprom_val & 0x1000);
1562 priv->thermal_meter_val = (eeprom_val & 0xF00) >> 8;
1563 priv->thermal_meter_en = !!(eeprom_val & 0x2000);
1566 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1567 RTL818X_EEPROM_CMD_NORMAL);
1570 static int rtl8180_probe(struct pci_dev *pdev,
1571 const struct pci_device_id *id)
1573 struct ieee80211_hw *dev;
1574 struct rtl8180_priv *priv;
1575 unsigned long mem_addr, mem_len;
1576 unsigned int io_addr, io_len;
1578 const char *chip_name, *rf_name = NULL;
1581 err = pci_enable_device(pdev);
1583 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1588 err = pci_request_regions(pdev, KBUILD_MODNAME);
1590 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1595 io_addr = pci_resource_start(pdev, 0);
1596 io_len = pci_resource_len(pdev, 0);
1597 mem_addr = pci_resource_start(pdev, 1);
1598 mem_len = pci_resource_len(pdev, 1);
1600 if (mem_len < sizeof(struct rtl818x_csr) ||
1601 io_len < sizeof(struct rtl818x_csr)) {
1602 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1608 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1609 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1610 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1615 pci_set_master(pdev);
1617 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1619 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1629 SET_IEEE80211_DEV(dev, &pdev->dev);
1630 pci_set_drvdata(pdev, dev);
1632 priv->map = pci_iomap(pdev, 1, mem_len);
1634 priv->map = pci_iomap(pdev, 0, io_len);
1637 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1642 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1643 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1645 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1646 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1648 priv->band.band = IEEE80211_BAND_2GHZ;
1649 priv->band.channels = priv->channels;
1650 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1651 priv->band.bitrates = priv->rates;
1652 priv->band.n_bitrates = 4;
1653 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1655 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1656 IEEE80211_HW_RX_INCLUDES_FCS |
1657 IEEE80211_HW_SIGNAL_UNSPEC;
1658 dev->vif_data_size = sizeof(struct rtl8180_vif);
1659 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1660 BIT(NL80211_IFTYPE_ADHOC);
1661 dev->max_signal = 65;
1663 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1664 reg &= RTL818X_TX_CONF_HWVER_MASK;
1666 case RTL818X_TX_CONF_R8180_ABCD:
1667 chip_name = "RTL8180";
1668 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1671 case RTL818X_TX_CONF_R8180_F:
1672 chip_name = "RTL8180vF";
1673 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1676 case RTL818X_TX_CONF_R8185_ABC:
1677 chip_name = "RTL8185";
1678 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1681 case RTL818X_TX_CONF_R8185_D:
1682 chip_name = "RTL8185vD";
1683 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1686 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1687 pci_name(pdev), reg >> 25);
1691 /* we declare to MAC80211 all the queues except for beacon queue
1692 * that will be eventually handled by DRV.
1693 * TX rings are arranged in such a way that lower is the IDX,
1694 * higher is the priority, in order to achieve direct mapping
1695 * with mac80211, however the beacon queue is an exception and it
1696 * is mapped on the highst tx ring IDX.
1698 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1700 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1701 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1702 pci_try_set_mwi(pdev);
1705 rtl8180_eeprom_read(priv);
1707 switch (priv->rf_type) {
1708 case 1: rf_name = "Intersil";
1710 case 2: rf_name = "RFMD";
1712 case 3: priv->rf = &sa2400_rf_ops;
1714 case 4: priv->rf = &max2820_rf_ops;
1716 case 5: priv->rf = &grf5101_rf_ops;
1718 case 9: priv->rf = rtl8180_detect_rf(dev);
1721 rf_name = "RTL8255";
1724 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1725 pci_name(pdev), priv->rf_type);
1730 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1731 pci_name(pdev), rf_name);
1735 if (!is_valid_ether_addr(priv->mac_addr)) {
1736 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1737 " randomly generated MAC addr\n", pci_name(pdev));
1738 eth_random_addr(priv->mac_addr);
1740 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
1742 spin_lock_init(&priv->lock);
1744 err = ieee80211_register_hw(dev);
1746 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1751 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1752 priv->mac_addr, chip_name, priv->rf->name);
1757 pci_iounmap(pdev, priv->map);
1760 ieee80211_free_hw(dev);
1763 pci_release_regions(pdev);
1764 pci_disable_device(pdev);
1768 static void rtl8180_remove(struct pci_dev *pdev)
1770 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1771 struct rtl8180_priv *priv;
1776 ieee80211_unregister_hw(dev);
1780 pci_iounmap(pdev, priv->map);
1781 pci_release_regions(pdev);
1782 pci_disable_device(pdev);
1783 ieee80211_free_hw(dev);
1787 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1789 pci_save_state(pdev);
1790 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1794 static int rtl8180_resume(struct pci_dev *pdev)
1796 pci_set_power_state(pdev, PCI_D0);
1797 pci_restore_state(pdev);
1801 #endif /* CONFIG_PM */
1803 static struct pci_driver rtl8180_driver = {
1804 .name = KBUILD_MODNAME,
1805 .id_table = rtl8180_table,
1806 .probe = rtl8180_probe,
1807 .remove = rtl8180_remove,
1809 .suspend = rtl8180_suspend,
1810 .resume = rtl8180_resume,
1811 #endif /* CONFIG_PM */
1814 module_pci_driver(rtl8180_driver);