3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/etherdevice.h>
24 #include <linux/eeprom_93cx6.h>
25 #include <linux/module.h>
26 #include <net/mac80211.h>
34 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
35 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
36 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
37 MODULE_LICENSE("GPL");
39 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
41 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
43 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
46 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
47 { PCI_DEVICE(0x1799, 0x6001) },
48 { PCI_DEVICE(0x1799, 0x6020) },
49 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
50 { PCI_DEVICE(0x1186, 0x3301) },
51 { PCI_DEVICE(0x1432, 0x7106) },
55 MODULE_DEVICE_TABLE(pci, rtl8180_table);
57 static const struct ieee80211_rate rtl818x_rates[] = {
58 { .bitrate = 10, .hw_value = 0, },
59 { .bitrate = 20, .hw_value = 1, },
60 { .bitrate = 55, .hw_value = 2, },
61 { .bitrate = 110, .hw_value = 3, },
62 { .bitrate = 60, .hw_value = 4, },
63 { .bitrate = 90, .hw_value = 5, },
64 { .bitrate = 120, .hw_value = 6, },
65 { .bitrate = 180, .hw_value = 7, },
66 { .bitrate = 240, .hw_value = 8, },
67 { .bitrate = 360, .hw_value = 9, },
68 { .bitrate = 480, .hw_value = 10, },
69 { .bitrate = 540, .hw_value = 11, },
72 static const struct ieee80211_channel rtl818x_channels[] = {
73 { .center_freq = 2412 },
74 { .center_freq = 2417 },
75 { .center_freq = 2422 },
76 { .center_freq = 2427 },
77 { .center_freq = 2432 },
78 { .center_freq = 2437 },
79 { .center_freq = 2442 },
80 { .center_freq = 2447 },
81 { .center_freq = 2452 },
82 { .center_freq = 2457 },
83 { .center_freq = 2462 },
84 { .center_freq = 2467 },
85 { .center_freq = 2472 },
86 { .center_freq = 2484 },
90 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
92 struct rtl8180_priv *priv = dev->priv;
96 buf = (data << 8) | addr;
98 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
100 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
101 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
106 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
108 struct rtl8180_priv *priv = dev->priv;
109 unsigned int count = 32;
113 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
114 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
115 u32 flags = le32_to_cpu(entry->flags);
117 if (flags & RTL818X_RX_DESC_FLAG_OWN)
120 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
121 RTL818X_RX_DESC_FLAG_FOF |
122 RTL818X_RX_DESC_FLAG_RX_ERR)))
125 u32 flags2 = le32_to_cpu(entry->flags2);
126 struct ieee80211_rx_status rx_status = {0};
127 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
129 if (unlikely(!new_skb))
132 pci_unmap_single(priv->pdev,
133 *((dma_addr_t *)skb->cb),
134 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
135 skb_put(skb, flags & 0xFFF);
137 rx_status.antenna = (flags2 >> 15) & 1;
138 rx_status.rate_idx = (flags >> 20) & 0xF;
139 agc = (flags2 >> 17) & 0x7F;
141 if (rx_status.rate_idx > 3)
142 signal = 90 - clamp_t(u8, agc, 25, 90);
144 signal = 95 - clamp_t(u8, agc, 30, 95);
147 signal = priv->rf->calc_rssi(agc, sq);
149 rx_status.signal = signal;
150 rx_status.freq = dev->conf.channel->center_freq;
151 rx_status.band = dev->conf.channel->band;
152 rx_status.mactime = le64_to_cpu(entry->tsft);
153 rx_status.flag |= RX_FLAG_MACTIME_MPDU;
154 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
155 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
157 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
158 ieee80211_rx_irqsafe(dev, skb);
161 priv->rx_buf[priv->rx_idx] = skb;
162 *((dma_addr_t *) skb->cb) =
163 pci_map_single(priv->pdev, skb_tail_pointer(skb),
164 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
168 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
169 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
171 if (priv->rx_idx == 31)
172 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
173 priv->rx_idx = (priv->rx_idx + 1) % 32;
177 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
179 struct rtl8180_priv *priv = dev->priv;
180 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
182 while (skb_queue_len(&ring->queue)) {
183 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
185 struct ieee80211_tx_info *info;
186 u32 flags = le32_to_cpu(entry->flags);
188 if (flags & RTL818X_TX_DESC_FLAG_OWN)
191 ring->idx = (ring->idx + 1) % ring->entries;
192 skb = __skb_dequeue(&ring->queue);
193 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
194 skb->len, PCI_DMA_TODEVICE);
196 info = IEEE80211_SKB_CB(skb);
197 ieee80211_tx_info_clear_status(info);
199 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
200 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
201 info->flags |= IEEE80211_TX_STAT_ACK;
203 info->status.rates[0].count = (flags & 0xFF) + 1;
204 info->status.rates[1].idx = -1;
206 ieee80211_tx_status_irqsafe(dev, skb);
207 if (ring->entries - skb_queue_len(&ring->queue) == 2)
208 ieee80211_wake_queue(dev, prio);
212 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
214 struct ieee80211_hw *dev = dev_id;
215 struct rtl8180_priv *priv = dev->priv;
218 spin_lock(&priv->lock);
219 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
220 if (unlikely(reg == 0xFFFF)) {
221 spin_unlock(&priv->lock);
225 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
227 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
228 rtl8180_handle_tx(dev, 3);
230 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
231 rtl8180_handle_tx(dev, 2);
233 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
234 rtl8180_handle_tx(dev, 1);
236 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
237 rtl8180_handle_tx(dev, 0);
239 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
240 rtl8180_handle_rx(dev);
242 spin_unlock(&priv->lock);
247 static void rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
249 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
250 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
251 struct rtl8180_priv *priv = dev->priv;
252 struct rtl8180_tx_ring *ring;
253 struct rtl8180_tx_desc *entry;
255 unsigned int idx, prio;
260 __le16 rts_duration = 0;
262 prio = skb_get_queue_mapping(skb);
263 ring = &priv->tx_ring[prio];
265 mapping = pci_map_single(priv->pdev, skb->data,
266 skb->len, PCI_DMA_TODEVICE);
268 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
269 RTL818X_TX_DESC_FLAG_LS |
270 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
274 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
275 RTL818X_TX_DESC_FLAG_NO_ENC;
277 rc_flags = info->control.rates[0].flags;
278 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
279 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
280 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
281 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
282 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
283 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
286 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
287 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
291 unsigned int remainder;
293 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
294 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
295 remainder = (16 * (skb->len + 4)) %
296 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
301 spin_lock_irqsave(&priv->lock, flags);
303 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
304 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
306 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
307 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
310 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
311 entry = &ring->desc[idx];
313 entry->rts_duration = rts_duration;
314 entry->plcp_len = cpu_to_le16(plcp_len);
315 entry->tx_buf = cpu_to_le32(mapping);
316 entry->frame_len = cpu_to_le32(skb->len);
317 entry->flags2 = info->control.rates[1].idx >= 0 ?
318 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
319 entry->retry_limit = info->control.rates[0].count;
320 entry->flags = cpu_to_le32(tx_flags);
321 __skb_queue_tail(&ring->queue, skb);
322 if (ring->entries - skb_queue_len(&ring->queue) < 2)
323 ieee80211_stop_queue(dev, prio);
325 spin_unlock_irqrestore(&priv->lock, flags);
327 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
330 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
334 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
335 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
336 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
337 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
338 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
339 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
340 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
341 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
344 static int rtl8180_init_hw(struct ieee80211_hw *dev)
346 struct rtl8180_priv *priv = dev->priv;
349 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
350 rtl818x_ioread8(priv, &priv->map->CMD);
354 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
355 rtl818x_ioread8(priv, &priv->map->CMD);
357 reg = rtl818x_ioread8(priv, &priv->map->CMD);
359 reg |= RTL818X_CMD_RESET;
360 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
361 rtl818x_ioread8(priv, &priv->map->CMD);
364 /* check success of reset */
365 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
366 wiphy_err(dev->wiphy, "reset timeout!\n");
370 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
371 rtl818x_ioread8(priv, &priv->map->CMD);
374 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
376 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
378 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
379 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
380 reg |= (1 << 15) | (1 << 14) | (1 << 4);
381 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
384 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
387 rtl8180_set_anaparam(priv, priv->anaparam);
389 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
390 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
391 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
392 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
393 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
395 /* TODO: necessary? specs indicate not */
396 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
397 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
398 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
400 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
401 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
403 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
405 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
407 /* TODO: turn off hw wep on rtl8180 */
409 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
412 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
413 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
414 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
416 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
418 /* TODO: set ClkRun enable? necessary? */
419 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
420 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
421 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
422 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
423 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
424 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
426 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
427 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
429 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
430 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
435 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
439 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
441 struct rtl8180_priv *priv = dev->priv;
442 struct rtl8180_rx_desc *entry;
445 priv->rx_ring = pci_alloc_consistent(priv->pdev,
446 sizeof(*priv->rx_ring) * 32,
449 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
450 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
454 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
457 for (i = 0; i < 32; i++) {
458 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
460 entry = &priv->rx_ring[i];
464 priv->rx_buf[i] = skb;
465 mapping = (dma_addr_t *)skb->cb;
466 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
467 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
468 entry->rx_buf = cpu_to_le32(*mapping);
469 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
472 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
476 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
478 struct rtl8180_priv *priv = dev->priv;
481 for (i = 0; i < 32; i++) {
482 struct sk_buff *skb = priv->rx_buf[i];
486 pci_unmap_single(priv->pdev,
487 *((dma_addr_t *)skb->cb),
488 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
492 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
493 priv->rx_ring, priv->rx_ring_dma);
494 priv->rx_ring = NULL;
497 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
498 unsigned int prio, unsigned int entries)
500 struct rtl8180_priv *priv = dev->priv;
501 struct rtl8180_tx_desc *ring;
505 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
506 if (!ring || (unsigned long)ring & 0xFF) {
507 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
512 memset(ring, 0, sizeof(*ring)*entries);
513 priv->tx_ring[prio].desc = ring;
514 priv->tx_ring[prio].dma = dma;
515 priv->tx_ring[prio].idx = 0;
516 priv->tx_ring[prio].entries = entries;
517 skb_queue_head_init(&priv->tx_ring[prio].queue);
519 for (i = 0; i < entries; i++)
520 ring[i].next_tx_desc =
521 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
526 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
528 struct rtl8180_priv *priv = dev->priv;
529 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
531 while (skb_queue_len(&ring->queue)) {
532 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
533 struct sk_buff *skb = __skb_dequeue(&ring->queue);
535 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
536 skb->len, PCI_DMA_TODEVICE);
538 ring->idx = (ring->idx + 1) % ring->entries;
541 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
542 ring->desc, ring->dma);
546 static int rtl8180_start(struct ieee80211_hw *dev)
548 struct rtl8180_priv *priv = dev->priv;
552 ret = rtl8180_init_rx_ring(dev);
556 for (i = 0; i < 4; i++)
557 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
560 ret = rtl8180_init_hw(dev);
564 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
565 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
566 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
567 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
568 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
570 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
571 IRQF_SHARED, KBUILD_MODNAME, dev);
573 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
577 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
579 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
580 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
582 reg = RTL818X_RX_CONF_ONLYERLPKT |
583 RTL818X_RX_CONF_RX_AUTORESETPHY |
584 RTL818X_RX_CONF_MGMT |
585 RTL818X_RX_CONF_DATA |
586 (7 << 8 /* MAX RX DMA */) |
587 RTL818X_RX_CONF_BROADCAST |
588 RTL818X_RX_CONF_NICMAC;
591 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
593 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
594 ? RTL818X_RX_CONF_CSDM1 : 0;
595 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
596 ? RTL818X_RX_CONF_CSDM2 : 0;
600 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
603 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
604 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
605 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
606 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
608 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
609 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
610 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
611 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
612 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
614 /* disable early TX */
615 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
618 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
619 reg |= (6 << 21 /* MAX TX DMA */) |
620 RTL818X_TX_CONF_NO_ICV;
623 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
625 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
627 /* different meaning, same value on both rtl8185 and rtl8180 */
628 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
630 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
632 reg = rtl818x_ioread8(priv, &priv->map->CMD);
633 reg |= RTL818X_CMD_RX_ENABLE;
634 reg |= RTL818X_CMD_TX_ENABLE;
635 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
640 rtl8180_free_rx_ring(dev);
641 for (i = 0; i < 4; i++)
642 if (priv->tx_ring[i].desc)
643 rtl8180_free_tx_ring(dev, i);
648 static void rtl8180_stop(struct ieee80211_hw *dev)
650 struct rtl8180_priv *priv = dev->priv;
654 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
656 reg = rtl818x_ioread8(priv, &priv->map->CMD);
657 reg &= ~RTL818X_CMD_TX_ENABLE;
658 reg &= ~RTL818X_CMD_RX_ENABLE;
659 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
663 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
664 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
665 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
666 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
668 free_irq(priv->pdev->irq, dev);
670 rtl8180_free_rx_ring(dev);
671 for (i = 0; i < 4; i++)
672 rtl8180_free_tx_ring(dev, i);
675 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
676 struct ieee80211_vif *vif)
678 struct rtl8180_priv *priv = dev->priv;
680 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
681 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
684 static void rtl8180_beacon_work(struct work_struct *work)
686 struct rtl8180_vif *vif_priv =
687 container_of(work, struct rtl8180_vif, beacon_work.work);
688 struct ieee80211_vif *vif =
689 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
690 struct ieee80211_hw *dev = vif_priv->dev;
691 struct ieee80211_mgmt *mgmt;
694 /* don't overflow the tx ring */
695 if (ieee80211_queue_stopped(dev, 0))
698 /* grab a fresh beacon */
699 skb = ieee80211_beacon_get(dev, vif);
704 * update beacon timestamp w/ TSF value
705 * TODO: make hardware update beacon timestamp
707 mgmt = (struct ieee80211_mgmt *)skb->data;
708 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
710 /* TODO: use actual beacon queue */
711 skb_set_queue_mapping(skb, 0);
713 rtl8180_tx(dev, skb);
717 * schedule next beacon
718 * TODO: use hardware support for beacon timing
720 schedule_delayed_work(&vif_priv->beacon_work,
721 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
724 static int rtl8180_add_interface(struct ieee80211_hw *dev,
725 struct ieee80211_vif *vif)
727 struct rtl8180_priv *priv = dev->priv;
728 struct rtl8180_vif *vif_priv;
731 * We only support one active interface at a time.
737 case NL80211_IFTYPE_STATION:
738 case NL80211_IFTYPE_ADHOC:
746 /* Initialize driver private area */
747 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
749 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
750 vif_priv->enable_beacon = false;
752 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
753 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
754 le32_to_cpu(*(__le32 *)vif->addr));
755 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
756 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
757 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
762 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
763 struct ieee80211_vif *vif)
765 struct rtl8180_priv *priv = dev->priv;
769 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
771 struct rtl8180_priv *priv = dev->priv;
772 struct ieee80211_conf *conf = &dev->conf;
774 priv->rf->set_chan(dev, conf);
779 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
780 struct ieee80211_vif *vif,
781 struct ieee80211_bss_conf *info,
784 struct rtl8180_priv *priv = dev->priv;
785 struct rtl8180_vif *vif_priv;
789 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
791 if (changed & BSS_CHANGED_BSSID) {
792 for (i = 0; i < ETH_ALEN; i++)
793 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
796 if (is_valid_ether_addr(info->bssid)) {
797 if (vif->type == NL80211_IFTYPE_ADHOC)
798 reg = RTL818X_MSR_ADHOC;
800 reg = RTL818X_MSR_INFRA;
802 reg = RTL818X_MSR_NO_LINK;
803 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
806 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
807 priv->rf->conf_erp(dev, info);
809 if (changed & BSS_CHANGED_BEACON_ENABLED)
810 vif_priv->enable_beacon = info->enable_beacon;
812 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
813 cancel_delayed_work_sync(&vif_priv->beacon_work);
814 if (vif_priv->enable_beacon)
815 schedule_work(&vif_priv->beacon_work.work);
819 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
820 struct netdev_hw_addr_list *mc_list)
822 return netdev_hw_addr_list_count(mc_list);
825 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
826 unsigned int changed_flags,
827 unsigned int *total_flags,
830 struct rtl8180_priv *priv = dev->priv;
832 if (changed_flags & FIF_FCSFAIL)
833 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
834 if (changed_flags & FIF_CONTROL)
835 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
836 if (changed_flags & FIF_OTHER_BSS)
837 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
838 if (*total_flags & FIF_ALLMULTI || multicast > 0)
839 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
841 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
845 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
846 *total_flags |= FIF_FCSFAIL;
847 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
848 *total_flags |= FIF_CONTROL;
849 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
850 *total_flags |= FIF_OTHER_BSS;
851 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
852 *total_flags |= FIF_ALLMULTI;
854 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
857 static const struct ieee80211_ops rtl8180_ops = {
859 .start = rtl8180_start,
860 .stop = rtl8180_stop,
861 .add_interface = rtl8180_add_interface,
862 .remove_interface = rtl8180_remove_interface,
863 .config = rtl8180_config,
864 .bss_info_changed = rtl8180_bss_info_changed,
865 .prepare_multicast = rtl8180_prepare_multicast,
866 .configure_filter = rtl8180_configure_filter,
867 .get_tsf = rtl8180_get_tsf,
870 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
872 struct ieee80211_hw *dev = eeprom->data;
873 struct rtl8180_priv *priv = dev->priv;
874 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
876 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
877 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
878 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
879 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
882 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
884 struct ieee80211_hw *dev = eeprom->data;
885 struct rtl8180_priv *priv = dev->priv;
888 if (eeprom->reg_data_in)
889 reg |= RTL818X_EEPROM_CMD_WRITE;
890 if (eeprom->reg_data_out)
891 reg |= RTL818X_EEPROM_CMD_READ;
892 if (eeprom->reg_data_clock)
893 reg |= RTL818X_EEPROM_CMD_CK;
894 if (eeprom->reg_chip_select)
895 reg |= RTL818X_EEPROM_CMD_CS;
897 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
898 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
902 static int __devinit rtl8180_probe(struct pci_dev *pdev,
903 const struct pci_device_id *id)
905 struct ieee80211_hw *dev;
906 struct rtl8180_priv *priv;
907 unsigned long mem_addr, mem_len;
908 unsigned int io_addr, io_len;
910 struct eeprom_93cx6 eeprom;
911 const char *chip_name, *rf_name = NULL;
914 u8 mac_addr[ETH_ALEN];
916 err = pci_enable_device(pdev);
918 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
923 err = pci_request_regions(pdev, KBUILD_MODNAME);
925 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
930 io_addr = pci_resource_start(pdev, 0);
931 io_len = pci_resource_len(pdev, 0);
932 mem_addr = pci_resource_start(pdev, 1);
933 mem_len = pci_resource_len(pdev, 1);
935 if (mem_len < sizeof(struct rtl818x_csr) ||
936 io_len < sizeof(struct rtl818x_csr)) {
937 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
943 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
944 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
945 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
950 pci_set_master(pdev);
952 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
954 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
964 SET_IEEE80211_DEV(dev, &pdev->dev);
965 pci_set_drvdata(pdev, dev);
967 priv->map = pci_iomap(pdev, 1, mem_len);
969 priv->map = pci_iomap(pdev, 0, io_len);
972 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
977 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
978 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
980 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
981 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
983 priv->band.band = IEEE80211_BAND_2GHZ;
984 priv->band.channels = priv->channels;
985 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
986 priv->band.bitrates = priv->rates;
987 priv->band.n_bitrates = 4;
988 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
990 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
991 IEEE80211_HW_RX_INCLUDES_FCS |
992 IEEE80211_HW_SIGNAL_UNSPEC;
993 dev->vif_data_size = sizeof(struct rtl8180_vif);
994 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
995 BIT(NL80211_IFTYPE_ADHOC);
997 dev->max_signal = 65;
999 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1000 reg &= RTL818X_TX_CONF_HWVER_MASK;
1002 case RTL818X_TX_CONF_R8180_ABCD:
1003 chip_name = "RTL8180";
1005 case RTL818X_TX_CONF_R8180_F:
1006 chip_name = "RTL8180vF";
1008 case RTL818X_TX_CONF_R8185_ABC:
1009 chip_name = "RTL8185";
1011 case RTL818X_TX_CONF_R8185_D:
1012 chip_name = "RTL8185vD";
1015 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1016 pci_name(pdev), reg >> 25);
1020 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1022 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1023 pci_try_set_mwi(pdev);
1027 eeprom.register_read = rtl8180_eeprom_register_read;
1028 eeprom.register_write = rtl8180_eeprom_register_write;
1029 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1030 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1032 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1034 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1035 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1038 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1040 switch (eeprom_val) {
1041 case 1: rf_name = "Intersil";
1043 case 2: rf_name = "RFMD";
1045 case 3: priv->rf = &sa2400_rf_ops;
1047 case 4: priv->rf = &max2820_rf_ops;
1049 case 5: priv->rf = &grf5101_rf_ops;
1051 case 9: priv->rf = rtl8180_detect_rf(dev);
1054 rf_name = "RTL8255";
1057 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1058 pci_name(pdev), eeprom_val);
1063 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1064 pci_name(pdev), rf_name);
1068 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1069 priv->csthreshold = eeprom_val >> 8;
1072 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1073 priv->anaparam = le32_to_cpu(anaparam);
1074 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1077 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1078 if (!is_valid_ether_addr(mac_addr)) {
1079 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1080 " randomly generated MAC addr\n", pci_name(pdev));
1081 random_ether_addr(mac_addr);
1083 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1086 for (i = 0; i < 14; i += 2) {
1088 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1089 priv->channels[i].hw_value = txpwr & 0xFF;
1090 priv->channels[i + 1].hw_value = txpwr >> 8;
1095 for (i = 0; i < 14; i += 2) {
1097 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1098 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1099 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1103 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1105 spin_lock_init(&priv->lock);
1107 err = ieee80211_register_hw(dev);
1109 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1114 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1115 mac_addr, chip_name, priv->rf->name);
1123 pci_set_drvdata(pdev, NULL);
1124 ieee80211_free_hw(dev);
1127 pci_release_regions(pdev);
1128 pci_disable_device(pdev);
1132 static void __devexit rtl8180_remove(struct pci_dev *pdev)
1134 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1135 struct rtl8180_priv *priv;
1140 ieee80211_unregister_hw(dev);
1144 pci_iounmap(pdev, priv->map);
1145 pci_release_regions(pdev);
1146 pci_disable_device(pdev);
1147 ieee80211_free_hw(dev);
1151 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1153 pci_save_state(pdev);
1154 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1158 static int rtl8180_resume(struct pci_dev *pdev)
1160 pci_set_power_state(pdev, PCI_D0);
1161 pci_restore_state(pdev);
1165 #endif /* CONFIG_PM */
1167 static struct pci_driver rtl8180_driver = {
1168 .name = KBUILD_MODNAME,
1169 .id_table = rtl8180_table,
1170 .probe = rtl8180_probe,
1171 .remove = __devexit_p(rtl8180_remove),
1173 .suspend = rtl8180_suspend,
1174 .resume = rtl8180_resume,
1175 #endif /* CONFIG_PM */
1178 module_pci_driver(rtl8180_driver);