drivers/net/wireless/rtl818x/rtl8180/dev.c

   1
   2 /*
   3  * Linux device driver for RTL8180 / RTL8185
   4  *
   5  * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
   6  * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
   7  *
   8  * Based on the r8180 driver, which is:
   9  * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
  10  *
  11  * Thanks to Realtek for their support!
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/eeprom_93cx6.h>
  25 #include <linux/module.h>
  26 #include <net/mac80211.h>
  27
  28 #include "rtl8180.h"
  29 #include "rtl8225.h"
  30 #include "sa2400.h"
  31 #include "max2820.h"
  32 #include "grf5101.h"
  33
  34 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  35 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
  36 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
  37 MODULE_LICENSE("GPL");
  38
  39 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
  40         /* rtl8185 */
  41         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
  42         { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
  43         { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
  44
  45         /* rtl8180 */
  46         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
  47         { PCI_DEVICE(0x1799, 0x6001) },
  48         { PCI_DEVICE(0x1799, 0x6020) },
  49         { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
  50         { }
  51 };
  52
  53 MODULE_DEVICE_TABLE(pci, rtl8180_table);
  54
  55 static const struct ieee80211_rate rtl818x_rates[] = {
  56         { .bitrate = 10, .hw_value = 0, },
  57         { .bitrate = 20, .hw_value = 1, },
  58         { .bitrate = 55, .hw_value = 2, },
  59         { .bitrate = 110, .hw_value = 3, },
  60         { .bitrate = 60, .hw_value = 4, },
  61         { .bitrate = 90, .hw_value = 5, },
  62         { .bitrate = 120, .hw_value = 6, },
  63         { .bitrate = 180, .hw_value = 7, },
  64         { .bitrate = 240, .hw_value = 8, },
  65         { .bitrate = 360, .hw_value = 9, },
  66         { .bitrate = 480, .hw_value = 10, },
  67         { .bitrate = 540, .hw_value = 11, },
  68 };
  69
  70 static const struct ieee80211_channel rtl818x_channels[] = {
  71         { .center_freq = 2412 },
  72         { .center_freq = 2417 },
  73         { .center_freq = 2422 },
  74         { .center_freq = 2427 },
  75         { .center_freq = 2432 },
  76         { .center_freq = 2437 },
  77         { .center_freq = 2442 },
  78         { .center_freq = 2447 },
  79         { .center_freq = 2452 },
  80         { .center_freq = 2457 },
  81         { .center_freq = 2462 },
  82         { .center_freq = 2467 },
  83         { .center_freq = 2472 },
  84         { .center_freq = 2484 },
  85 };
  86
  87
  88 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
  89 {
  90         struct rtl8180_priv *priv = dev->priv;
  91         int i = 10;
  92         u32 buf;
  93
  94         buf = (data << 8) | addr;
  95
  96         rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
  97         while (i--) {
  98                 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
  99                 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
 100                         return;
 101         }
 102 }
 103
 104 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
 105 {
 106         struct rtl8180_priv *priv = dev->priv;
 107         unsigned int count = 32;
 108         u8 signal, agc, sq;
 109
 110         while (count--) {
 111                 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
 112                 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
 113                 u32 flags = le32_to_cpu(entry->flags);
 114
 115                 if (flags & RTL818X_RX_DESC_FLAG_OWN)
 116                         return;
 117
 118                 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
 119                                       RTL818X_RX_DESC_FLAG_FOF |
 120                                       RTL818X_RX_DESC_FLAG_RX_ERR)))
 121                         goto done;
 122                 else {
 123                         u32 flags2 = le32_to_cpu(entry->flags2);
 124                         struct ieee80211_rx_status rx_status = {0};
 125                         struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
 126
 127                         if (unlikely(!new_skb))
 128                                 goto done;
 129
 130                         pci_unmap_single(priv->pdev,
 131                                          *((dma_addr_t *)skb->cb),
 132                                          MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 133                         skb_put(skb, flags & 0xFFF);
 134
 135                         rx_status.antenna = (flags2 >> 15) & 1;
 136                         rx_status.rate_idx = (flags >> 20) & 0xF;
 137                         agc = (flags2 >> 17) & 0x7F;
 138                         if (priv->r8185) {
 139                                 if (rx_status.rate_idx > 3)
 140                                         signal = 90 - clamp_t(u8, agc, 25, 90);
 141                                 else
 142                                         signal = 95 - clamp_t(u8, agc, 30, 95);
 143                         } else {
 144                                 sq = flags2 & 0xff;
 145                                 signal = priv->rf->calc_rssi(agc, sq);
 146                         }
 147                         rx_status.signal = signal;
 148                         rx_status.freq = dev->conf.channel->center_freq;
 149                         rx_status.band = dev->conf.channel->band;
 150                         rx_status.mactime = le64_to_cpu(entry->tsft);
 151                         rx_status.flag |= RX_FLAG_MACTIME_MPDU;
 152                         if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
 153                                 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
 154
 155                         memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 156                         ieee80211_rx_irqsafe(dev, skb);
 157
 158                         skb = new_skb;
 159                         priv->rx_buf[priv->rx_idx] = skb;
 160                         *((dma_addr_t *) skb->cb) =
 161                                 pci_map_single(priv->pdev, skb_tail_pointer(skb),
 162                                                MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 163                 }
 164
 165         done:
 166                 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
 167                 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
 168                                            MAX_RX_SIZE);
 169                 if (priv->rx_idx == 31)
 170                         entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
 171                 priv->rx_idx = (priv->rx_idx + 1) % 32;
 172         }
 173 }
 174
 175 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
 176 {
 177         struct rtl8180_priv *priv = dev->priv;
 178         struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
 179
 180         while (skb_queue_len(&ring->queue)) {
 181                 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
 182                 struct sk_buff *skb;
 183                 struct ieee80211_tx_info *info;
 184                 u32 flags = le32_to_cpu(entry->flags);
 185
 186                 if (flags & RTL818X_TX_DESC_FLAG_OWN)
 187                         return;
 188
 189                 ring->idx = (ring->idx + 1) % ring->entries;
 190                 skb = __skb_dequeue(&ring->queue);
 191                 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
 192                                  skb->len, PCI_DMA_TODEVICE);
 193
 194                 info = IEEE80211_SKB_CB(skb);
 195                 ieee80211_tx_info_clear_status(info);
 196
 197                 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
 198                     (flags & RTL818X_TX_DESC_FLAG_TX_OK))
 199                         info->flags |= IEEE80211_TX_STAT_ACK;
 200
 201                 info->status.rates[0].count = (flags & 0xFF) + 1;
 202                 info->status.rates[1].idx = -1;
 203
 204                 ieee80211_tx_status_irqsafe(dev, skb);
 205                 if (ring->entries - skb_queue_len(&ring->queue) == 2)
 206                         ieee80211_wake_queue(dev, prio);
 207         }
 208 }
 209
 210 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
 211 {
 212         struct ieee80211_hw *dev = dev_id;
 213         struct rtl8180_priv *priv = dev->priv;
 214         u16 reg;
 215
 216         spin_lock(&priv->lock);
 217         reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
 218         if (unlikely(reg == 0xFFFF)) {
 219                 spin_unlock(&priv->lock);
 220                 return IRQ_HANDLED;
 221         }
 222
 223         rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
 224
 225         if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
 226                 rtl8180_handle_tx(dev, 3);
 227
 228         if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
 229                 rtl8180_handle_tx(dev, 2);
 230
 231         if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
 232                 rtl8180_handle_tx(dev, 1);
 233
 234         if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
 235                 rtl8180_handle_tx(dev, 0);
 236
 237         if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
 238                 rtl8180_handle_rx(dev);
 239
 240         spin_unlock(&priv->lock);
 241
 242         return IRQ_HANDLED;
 243 }
 244
 245 static void rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 246 {
 247         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 248         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
 249         struct rtl8180_priv *priv = dev->priv;
 250         struct rtl8180_tx_ring *ring;
 251         struct rtl8180_tx_desc *entry;
 252         unsigned long flags;
 253         unsigned int idx, prio;
 254         dma_addr_t mapping;
 255         u32 tx_flags;
 256         u8 rc_flags;
 257         u16 plcp_len = 0;
 258         __le16 rts_duration = 0;
 259
 260         prio = skb_get_queue_mapping(skb);
 261         ring = &priv->tx_ring[prio];
 262
 263         mapping = pci_map_single(priv->pdev, skb->data,
 264                                  skb->len, PCI_DMA_TODEVICE);
 265
 266         tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
 267                    RTL818X_TX_DESC_FLAG_LS |
 268                    (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
 269                    skb->len;
 270
 271         if (priv->r8185)
 272                 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
 273                             RTL818X_TX_DESC_FLAG_NO_ENC;
 274
 275         rc_flags = info->control.rates[0].flags;
 276         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
 277                 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
 278                 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
 279         } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
 280                 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
 281                 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
 282         }
 283
 284         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
 285                 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
 286                                                       info);
 287
 288         if (!priv->r8185) {
 289                 unsigned int remainder;
 290
 291                 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
 292                                 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
 293                 remainder = (16 * (skb->len + 4)) %
 294                             ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
 295                 if (remainder <= 6)
 296                         plcp_len |= 1 << 15;
 297         }
 298
 299         spin_lock_irqsave(&priv->lock, flags);
 300
 301         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
 302                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
 303                         priv->seqno += 0x10;
 304                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
 305                 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
 306         }
 307
 308         idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
 309         entry = &ring->desc[idx];
 310
 311         entry->rts_duration = rts_duration;
 312         entry->plcp_len = cpu_to_le16(plcp_len);
 313         entry->tx_buf = cpu_to_le32(mapping);
 314         entry->frame_len = cpu_to_le32(skb->len);
 315         entry->flags2 = info->control.rates[1].idx >= 0 ?
 316                 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
 317         entry->retry_limit = info->control.rates[0].count;
 318         entry->flags = cpu_to_le32(tx_flags);
 319         __skb_queue_tail(&ring->queue, skb);
 320         if (ring->entries - skb_queue_len(&ring->queue) < 2)
 321                 ieee80211_stop_queue(dev, prio);
 322
 323         spin_unlock_irqrestore(&priv->lock, flags);
 324
 325         rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
 326 }
 327
 328 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
 329 {
 330         u8 reg;
 331
 332         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 333         reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 334         rtl818x_iowrite8(priv, &priv->map->CONFIG3,
 335                  reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
 336         rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
 337         rtl818x_iowrite8(priv, &priv->map->CONFIG3,
 338                  reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
 339         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 340 }
 341
 342 static int rtl8180_init_hw(struct ieee80211_hw *dev)
 343 {
 344         struct rtl8180_priv *priv = dev->priv;
 345         u16 reg;
 346
 347         rtl818x_iowrite8(priv, &priv->map->CMD, 0);
 348         rtl818x_ioread8(priv, &priv->map->CMD);
 349         msleep(10);
 350
 351         /* reset */
 352         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 353         rtl818x_ioread8(priv, &priv->map->CMD);
 354
 355         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 356         reg &= (1 << 1);
 357         reg |= RTL818X_CMD_RESET;
 358         rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
 359         rtl818x_ioread8(priv, &priv->map->CMD);
 360         msleep(200);
 361
 362         /* check success of reset */
 363         if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
 364                 wiphy_err(dev->wiphy, "reset timeout!\n");
 365                 return -ETIMEDOUT;
 366         }
 367
 368         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
 369         rtl818x_ioread8(priv, &priv->map->CMD);
 370         msleep(200);
 371
 372         if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
 373                 /* For cardbus */
 374                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 375                 reg |= 1 << 1;
 376                 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
 377                 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
 378                 reg |= (1 << 15) | (1 << 14) | (1 << 4);
 379                 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
 380         }
 381
 382         rtl818x_iowrite8(priv, &priv->map->MSR, 0);
 383
 384         if (!priv->r8185)
 385                 rtl8180_set_anaparam(priv, priv->anaparam);
 386
 387         rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
 388         rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
 389         rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
 390         rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
 391         rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
 392
 393         /* TODO: necessary? specs indicate not */
 394         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 395         reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
 396         rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
 397         if (priv->r8185) {
 398                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
 399                 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
 400         }
 401         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 402
 403         /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
 404
 405         /* TODO: turn off hw wep on rtl8180 */
 406
 407         rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
 408
 409         if (priv->r8185) {
 410                 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
 411                 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
 412                 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
 413
 414                 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
 415
 416                 /* TODO: set ClkRun enable? necessary? */
 417                 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
 418                 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
 419                 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 420                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 421                 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
 422                 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 423         } else {
 424                 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
 425                 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
 426
 427                 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
 428                 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
 429         }
 430
 431         priv->rf->init(dev);
 432         if (priv->r8185)
 433                 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
 434         return 0;
 435 }
 436
 437 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
 438 {
 439         struct rtl8180_priv *priv = dev->priv;
 440         struct rtl8180_rx_desc *entry;
 441         int i;
 442
 443         priv->rx_ring = pci_alloc_consistent(priv->pdev,
 444                                              sizeof(*priv->rx_ring) * 32,
 445                                              &priv->rx_ring_dma);
 446
 447         if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
 448                 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
 449                 return -ENOMEM;
 450         }
 451
 452         memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
 453         priv->rx_idx = 0;
 454
 455         for (i = 0; i < 32; i++) {
 456                 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
 457                 dma_addr_t *mapping;
 458                 entry = &priv->rx_ring[i];
 459                 if (!skb)
 460                         return 0;
 461
 462                 priv->rx_buf[i] = skb;
 463                 mapping = (dma_addr_t *)skb->cb;
 464                 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
 465                                           MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 466                 entry->rx_buf = cpu_to_le32(*mapping);
 467                 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
 468                                            MAX_RX_SIZE);
 469         }
 470         entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
 471         return 0;
 472 }
 473
 474 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
 475 {
 476         struct rtl8180_priv *priv = dev->priv;
 477         int i;
 478
 479         for (i = 0; i < 32; i++) {
 480                 struct sk_buff *skb = priv->rx_buf[i];
 481                 if (!skb)
 482                         continue;
 483
 484                 pci_unmap_single(priv->pdev,
 485                                  *((dma_addr_t *)skb->cb),
 486                                  MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 487                 kfree_skb(skb);
 488         }
 489
 490         pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
 491                             priv->rx_ring, priv->rx_ring_dma);
 492         priv->rx_ring = NULL;
 493 }
 494
 495 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
 496                                 unsigned int prio, unsigned int entries)
 497 {
 498         struct rtl8180_priv *priv = dev->priv;
 499         struct rtl8180_tx_desc *ring;
 500         dma_addr_t dma;
 501         int i;
 502
 503         ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
 504         if (!ring || (unsigned long)ring & 0xFF) {
 505                 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
 506                           prio);
 507                 return -ENOMEM;
 508         }
 509
 510         memset(ring, 0, sizeof(*ring)*entries);
 511         priv->tx_ring[prio].desc = ring;
 512         priv->tx_ring[prio].dma = dma;
 513         priv->tx_ring[prio].idx = 0;
 514         priv->tx_ring[prio].entries = entries;
 515         skb_queue_head_init(&priv->tx_ring[prio].queue);
 516
 517         for (i = 0; i < entries; i++)
 518                 ring[i].next_tx_desc =
 519                         cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
 520
 521         return 0;
 522 }
 523
 524 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
 525 {
 526         struct rtl8180_priv *priv = dev->priv;
 527         struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
 528
 529         while (skb_queue_len(&ring->queue)) {
 530                 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
 531                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
 532
 533                 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
 534                                  skb->len, PCI_DMA_TODEVICE);
 535                 kfree_skb(skb);
 536                 ring->idx = (ring->idx + 1) % ring->entries;
 537         }
 538
 539         pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
 540                             ring->desc, ring->dma);
 541         ring->desc = NULL;
 542 }
 543
 544 static int rtl8180_start(struct ieee80211_hw *dev)
 545 {
 546         struct rtl8180_priv *priv = dev->priv;
 547         int ret, i;
 548         u32 reg;
 549
 550         ret = rtl8180_init_rx_ring(dev);
 551         if (ret)
 552                 return ret;
 553
 554         for (i = 0; i < 4; i++)
 555                 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
 556                         goto err_free_rings;
 557
 558         ret = rtl8180_init_hw(dev);
 559         if (ret)
 560                 goto err_free_rings;
 561
 562         rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
 563         rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
 564         rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
 565         rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
 566         rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
 567
 568         ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
 569                           IRQF_SHARED, KBUILD_MODNAME, dev);
 570         if (ret) {
 571                 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
 572                 goto err_free_rings;
 573         }
 574
 575         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
 576
 577         rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
 578         rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
 579
 580         reg = RTL818X_RX_CONF_ONLYERLPKT |
 581               RTL818X_RX_CONF_RX_AUTORESETPHY |
 582               RTL818X_RX_CONF_MGMT |
 583               RTL818X_RX_CONF_DATA |
 584               (7 << 8 /* MAX RX DMA */) |
 585               RTL818X_RX_CONF_BROADCAST |
 586               RTL818X_RX_CONF_NICMAC;
 587
 588         if (priv->r8185)
 589                 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
 590         else {
 591                 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
 592                         ? RTL818X_RX_CONF_CSDM1 : 0;
 593                 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
 594                         ? RTL818X_RX_CONF_CSDM2 : 0;
 595         }
 596
 597         priv->rx_conf = reg;
 598         rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
 599
 600         if (priv->r8185) {
 601                 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
 602                 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
 603                 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
 604                 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
 605
 606                 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
 607                 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
 608                 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
 609                 reg |=  RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
 610                 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
 611
 612                 /* disable early TX */
 613                 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
 614         }
 615
 616         reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
 617         reg |= (6 << 21 /* MAX TX DMA */) |
 618                RTL818X_TX_CONF_NO_ICV;
 619
 620         if (priv->r8185)
 621                 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
 622         else
 623                 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
 624
 625         /* different meaning, same value on both rtl8185 and rtl8180 */
 626         reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
 627
 628         rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
 629
 630         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 631         reg |= RTL818X_CMD_RX_ENABLE;
 632         reg |= RTL818X_CMD_TX_ENABLE;
 633         rtl818x_iowrite8(priv, &priv->map->CMD, reg);
 634
 635         return 0;
 636
 637  err_free_rings:
 638         rtl8180_free_rx_ring(dev);
 639         for (i = 0; i < 4; i++)
 640                 if (priv->tx_ring[i].desc)
 641                         rtl8180_free_tx_ring(dev, i);
 642
 643         return ret;
 644 }
 645
 646 static void rtl8180_stop(struct ieee80211_hw *dev)
 647 {
 648         struct rtl8180_priv *priv = dev->priv;
 649         u8 reg;
 650         int i;
 651
 652         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 653
 654         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 655         reg &= ~RTL818X_CMD_TX_ENABLE;
 656         reg &= ~RTL818X_CMD_RX_ENABLE;
 657         rtl818x_iowrite8(priv, &priv->map->CMD, reg);
 658
 659         priv->rf->stop(dev);
 660
 661         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 662         reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
 663         rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
 664         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 665
 666         free_irq(priv->pdev->irq, dev);
 667
 668         rtl8180_free_rx_ring(dev);
 669         for (i = 0; i < 4; i++)
 670                 rtl8180_free_tx_ring(dev, i);
 671 }
 672
 673 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
 674                            struct ieee80211_vif *vif)
 675 {
 676         struct rtl8180_priv *priv = dev->priv;
 677
 678         return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
 679                (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
 680 }
 681
 682 static void rtl8180_beacon_work(struct work_struct *work)
 683 {
 684         struct rtl8180_vif *vif_priv =
 685                 container_of(work, struct rtl8180_vif, beacon_work.work);
 686         struct ieee80211_vif *vif =
 687                 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
 688         struct ieee80211_hw *dev = vif_priv->dev;
 689         struct ieee80211_mgmt *mgmt;
 690         struct sk_buff *skb;
 691
 692         /* don't overflow the tx ring */
 693         if (ieee80211_queue_stopped(dev, 0))
 694                 goto resched;
 695
 696         /* grab a fresh beacon */
 697         skb = ieee80211_beacon_get(dev, vif);
 698         if (!skb)
 699                 goto resched;
 700
 701         /*
 702          * update beacon timestamp w/ TSF value
 703          * TODO: make hardware update beacon timestamp
 704          */
 705         mgmt = (struct ieee80211_mgmt *)skb->data;
 706         mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
 707
 708         /* TODO: use actual beacon queue */
 709         skb_set_queue_mapping(skb, 0);
 710
 711         rtl8180_tx(dev, skb);
 712
 713 resched:
 714         /*
 715          * schedule next beacon
 716          * TODO: use hardware support for beacon timing
 717          */
 718         schedule_delayed_work(&vif_priv->beacon_work,
 719                         usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
 720 }
 721
 722 static int rtl8180_add_interface(struct ieee80211_hw *dev,
 723                                  struct ieee80211_vif *vif)
 724 {
 725         struct rtl8180_priv *priv = dev->priv;
 726         struct rtl8180_vif *vif_priv;
 727
 728         /*
 729          * We only support one active interface at a time.
 730          */
 731         if (priv->vif)
 732                 return -EBUSY;
 733
 734         switch (vif->type) {
 735         case NL80211_IFTYPE_STATION:
 736         case NL80211_IFTYPE_ADHOC:
 737                 break;
 738         default:
 739                 return -EOPNOTSUPP;
 740         }
 741
 742         priv->vif = vif;
 743
 744         /* Initialize driver private area */
 745         vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
 746         vif_priv->dev = dev;
 747         INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
 748         vif_priv->enable_beacon = false;
 749
 750         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 751         rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
 752                           le32_to_cpu(*(__le32 *)vif->addr));
 753         rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
 754                           le16_to_cpu(*(__le16 *)(vif->addr + 4)));
 755         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 756
 757         return 0;
 758 }
 759
 760 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
 761                                      struct ieee80211_vif *vif)
 762 {
 763         struct rtl8180_priv *priv = dev->priv;
 764         priv->vif = NULL;
 765 }
 766
 767 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
 768 {
 769         struct rtl8180_priv *priv = dev->priv;
 770         struct ieee80211_conf *conf = &dev->conf;
 771
 772         priv->rf->set_chan(dev, conf);
 773
 774         return 0;
 775 }
 776
 777 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
 778                                      struct ieee80211_vif *vif,
 779                                      struct ieee80211_bss_conf *info,
 780                                      u32 changed)
 781 {
 782         struct rtl8180_priv *priv = dev->priv;
 783         struct rtl8180_vif *vif_priv;
 784         int i;
 785         u8 reg;
 786
 787         vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
 788
 789         if (changed & BSS_CHANGED_BSSID) {
 790                 for (i = 0; i < ETH_ALEN; i++)
 791                         rtl818x_iowrite8(priv, &priv->map->BSSID[i],
 792                                          info->bssid[i]);
 793
 794                 if (is_valid_ether_addr(info->bssid)) {
 795                         if (vif->type == NL80211_IFTYPE_ADHOC)
 796                                 reg = RTL818X_MSR_ADHOC;
 797                         else
 798                                 reg = RTL818X_MSR_INFRA;
 799                 } else
 800                         reg = RTL818X_MSR_NO_LINK;
 801                 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
 802         }
 803
 804         if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
 805                 priv->rf->conf_erp(dev, info);
 806
 807         if (changed & BSS_CHANGED_BEACON_ENABLED)
 808                 vif_priv->enable_beacon = info->enable_beacon;
 809
 810         if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
 811                 cancel_delayed_work_sync(&vif_priv->beacon_work);
 812                 if (vif_priv->enable_beacon)
 813                         schedule_work(&vif_priv->beacon_work.work);
 814         }
 815 }
 816
 817 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
 818                                      struct netdev_hw_addr_list *mc_list)
 819 {
 820         return netdev_hw_addr_list_count(mc_list);
 821 }
 822
 823 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
 824                                      unsigned int changed_flags,
 825                                      unsigned int *total_flags,
 826                                      u64 multicast)
 827 {
 828         struct rtl8180_priv *priv = dev->priv;
 829
 830         if (changed_flags & FIF_FCSFAIL)
 831                 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
 832         if (changed_flags & FIF_CONTROL)
 833                 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
 834         if (changed_flags & FIF_OTHER_BSS)
 835                 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
 836         if (*total_flags & FIF_ALLMULTI || multicast > 0)
 837                 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
 838         else
 839                 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
 840
 841         *total_flags = 0;
 842
 843         if (priv->rx_conf & RTL818X_RX_CONF_FCS)
 844                 *total_flags |= FIF_FCSFAIL;
 845         if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
 846                 *total_flags |= FIF_CONTROL;
 847         if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
 848                 *total_flags |= FIF_OTHER_BSS;
 849         if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
 850                 *total_flags |= FIF_ALLMULTI;
 851
 852         rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
 853 }
 854
 855 static const struct ieee80211_ops rtl8180_ops = {
 856         .tx                     = rtl8180_tx,
 857         .start                  = rtl8180_start,
 858         .stop                   = rtl8180_stop,
 859         .add_interface          = rtl8180_add_interface,
 860         .remove_interface       = rtl8180_remove_interface,
 861         .config                 = rtl8180_config,
 862         .bss_info_changed       = rtl8180_bss_info_changed,
 863         .prepare_multicast      = rtl8180_prepare_multicast,
 864         .configure_filter       = rtl8180_configure_filter,
 865         .get_tsf                = rtl8180_get_tsf,
 866 };
 867
 868 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
 869 {
 870         struct ieee80211_hw *dev = eeprom->data;
 871         struct rtl8180_priv *priv = dev->priv;
 872         u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
 873
 874         eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
 875         eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
 876         eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
 877         eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
 878 }
 879
 880 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
 881 {
 882         struct ieee80211_hw *dev = eeprom->data;
 883         struct rtl8180_priv *priv = dev->priv;
 884         u8 reg = 2 << 6;
 885
 886         if (eeprom->reg_data_in)
 887                 reg |= RTL818X_EEPROM_CMD_WRITE;
 888         if (eeprom->reg_data_out)
 889                 reg |= RTL818X_EEPROM_CMD_READ;
 890         if (eeprom->reg_data_clock)
 891                 reg |= RTL818X_EEPROM_CMD_CK;
 892         if (eeprom->reg_chip_select)
 893                 reg |= RTL818X_EEPROM_CMD_CS;
 894
 895         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
 896         rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
 897         udelay(10);
 898 }
 899
 900 static int __devinit rtl8180_probe(struct pci_dev *pdev,
 901                                    const struct pci_device_id *id)
 902 {
 903         struct ieee80211_hw *dev;
 904         struct rtl8180_priv *priv;
 905         unsigned long mem_addr, mem_len;
 906         unsigned int io_addr, io_len;
 907         int err, i;
 908         struct eeprom_93cx6 eeprom;
 909         const char *chip_name, *rf_name = NULL;
 910         u32 reg;
 911         u16 eeprom_val;
 912         u8 mac_addr[ETH_ALEN];
 913
 914         err = pci_enable_device(pdev);
 915         if (err) {
 916                 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
 917                        pci_name(pdev));
 918                 return err;
 919         }
 920
 921         err = pci_request_regions(pdev, KBUILD_MODNAME);
 922         if (err) {
 923                 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
 924                        pci_name(pdev));
 925                 return err;
 926         }
 927
 928         io_addr = pci_resource_start(pdev, 0);
 929         io_len = pci_resource_len(pdev, 0);
 930         mem_addr = pci_resource_start(pdev, 1);
 931         mem_len = pci_resource_len(pdev, 1);
 932
 933         if (mem_len < sizeof(struct rtl818x_csr) ||
 934             io_len < sizeof(struct rtl818x_csr)) {
 935                 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
 936                        pci_name(pdev));
 937                 err = -ENOMEM;
 938                 goto err_free_reg;
 939         }
 940
 941         if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
 942             (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
 943                 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
 944                        pci_name(pdev));
 945                 goto err_free_reg;
 946         }
 947
 948         pci_set_master(pdev);
 949
 950         dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
 951         if (!dev) {
 952                 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
 953                        pci_name(pdev));
 954                 err = -ENOMEM;
 955                 goto err_free_reg;
 956         }
 957
 958         priv = dev->priv;
 959         priv->pdev = pdev;
 960
 961         dev->max_rates = 2;
 962         SET_IEEE80211_DEV(dev, &pdev->dev);
 963         pci_set_drvdata(pdev, dev);
 964
 965         priv->map = pci_iomap(pdev, 1, mem_len);
 966         if (!priv->map)
 967                 priv->map = pci_iomap(pdev, 0, io_len);
 968
 969         if (!priv->map) {
 970                 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
 971                        pci_name(pdev));
 972                 goto err_free_dev;
 973         }
 974
 975         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
 976         BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
 977
 978         memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
 979         memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
 980
 981         priv->band.band = IEEE80211_BAND_2GHZ;
 982         priv->band.channels = priv->channels;
 983         priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
 984         priv->band.bitrates = priv->rates;
 985         priv->band.n_bitrates = 4;
 986         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
 987
 988         dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
 989                      IEEE80211_HW_RX_INCLUDES_FCS |
 990                      IEEE80211_HW_SIGNAL_UNSPEC;
 991         dev->vif_data_size = sizeof(struct rtl8180_vif);
 992         dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
 993                                         BIT(NL80211_IFTYPE_ADHOC);
 994         dev->queues = 1;
 995         dev->max_signal = 65;
 996
 997         reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
 998         reg &= RTL818X_TX_CONF_HWVER_MASK;
 999         switch (reg) {
1000         case RTL818X_TX_CONF_R8180_ABCD:
1001                 chip_name = "RTL8180";
1002                 break;
1003         case RTL818X_TX_CONF_R8180_F:
1004                 chip_name = "RTL8180vF";
1005                 break;
1006         case RTL818X_TX_CONF_R8185_ABC:
1007                 chip_name = "RTL8185";
1008                 break;
1009         case RTL818X_TX_CONF_R8185_D:
1010                 chip_name = "RTL8185vD";
1011                 break;
1012         default:
1013                 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1014                        pci_name(pdev), reg >> 25);
1015                 goto err_iounmap;
1016         }
1017
1018         priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1019         if (priv->r8185) {
1020                 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1021                 pci_try_set_mwi(pdev);
1022         }
1023
1024         eeprom.data = dev;
1025         eeprom.register_read = rtl8180_eeprom_register_read;
1026         eeprom.register_write = rtl8180_eeprom_register_write;
1027         if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1028                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1029         else
1030                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1031
1032         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1033         rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1034         udelay(10);
1035
1036         eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1037         eeprom_val &= 0xFF;
1038         switch (eeprom_val) {
1039         case 1: rf_name = "Intersil";
1040                 break;
1041         case 2: rf_name = "RFMD";
1042                 break;
1043         case 3: priv->rf = &sa2400_rf_ops;
1044                 break;
1045         case 4: priv->rf = &max2820_rf_ops;
1046                 break;
1047         case 5: priv->rf = &grf5101_rf_ops;
1048                 break;
1049         case 9: priv->rf = rtl8180_detect_rf(dev);
1050                 break;
1051         case 10:
1052                 rf_name = "RTL8255";
1053                 break;
1054         default:
1055                 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1056                        pci_name(pdev), eeprom_val);
1057                 goto err_iounmap;
1058         }
1059
1060         if (!priv->rf) {
1061                 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1062                        pci_name(pdev), rf_name);
1063                 goto err_iounmap;
1064         }
1065
1066         eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1067         priv->csthreshold = eeprom_val >> 8;
1068         if (!priv->r8185) {
1069                 __le32 anaparam;
1070                 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1071                 priv->anaparam = le32_to_cpu(anaparam);
1072                 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1073         }
1074
1075         eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1076         if (!is_valid_ether_addr(mac_addr)) {
1077                 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1078                        " randomly generated MAC addr\n", pci_name(pdev));
1079                 random_ether_addr(mac_addr);
1080         }
1081         SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1082
1083         /* CCK TX power */
1084         for (i = 0; i < 14; i += 2) {
1085                 u16 txpwr;
1086                 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1087                 priv->channels[i].hw_value = txpwr & 0xFF;
1088                 priv->channels[i + 1].hw_value = txpwr >> 8;
1089         }
1090
1091         /* OFDM TX power */
1092         if (priv->r8185) {
1093                 for (i = 0; i < 14; i += 2) {
1094                         u16 txpwr;
1095                         eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1096                         priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1097                         priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1098                 }
1099         }
1100
1101         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1102
1103         spin_lock_init(&priv->lock);
1104
1105         err = ieee80211_register_hw(dev);
1106         if (err) {
1107                 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1108                        pci_name(pdev));
1109                 goto err_iounmap;
1110         }
1111
1112         wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1113                    mac_addr, chip_name, priv->rf->name);
1114
1115         return 0;
1116
1117  err_iounmap:
1118         iounmap(priv->map);
1119
1120  err_free_dev:
1121         pci_set_drvdata(pdev, NULL);
1122         ieee80211_free_hw(dev);
1123
1124  err_free_reg:
1125         pci_release_regions(pdev);
1126         pci_disable_device(pdev);
1127         return err;
1128 }
1129
1130 static void __devexit rtl8180_remove(struct pci_dev *pdev)
1131 {
1132         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1133         struct rtl8180_priv *priv;
1134
1135         if (!dev)
1136                 return;
1137
1138         ieee80211_unregister_hw(dev);
1139
1140         priv = dev->priv;
1141
1142         pci_iounmap(pdev, priv->map);
1143         pci_release_regions(pdev);
1144         pci_disable_device(pdev);
1145         ieee80211_free_hw(dev);
1146 }
1147
1148 #ifdef CONFIG_PM
1149 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1150 {
1151         pci_save_state(pdev);
1152         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1153         return 0;
1154 }
1155
1156 static int rtl8180_resume(struct pci_dev *pdev)
1157 {
1158         pci_set_power_state(pdev, PCI_D0);
1159         pci_restore_state(pdev);
1160         return 0;
1161 }
1162
1163 #endif /* CONFIG_PM */
1164
1165 static struct pci_driver rtl8180_driver = {
1166         .name           = KBUILD_MODNAME,
1167         .id_table       = rtl8180_table,
1168         .probe          = rtl8180_probe,
1169         .remove         = __devexit_p(rtl8180_remove),
1170 #ifdef CONFIG_PM
1171         .suspend        = rtl8180_suspend,
1172         .resume         = rtl8180_resume,
1173 #endif /* CONFIG_PM */
1174 };
1175
1176 module_pci_driver(rtl8180_driver);