1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #include <linux/export.h>
38 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
45 static const u8 ac_to_hwq[] = {
52 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
55 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
56 __le16 fc = rtl_get_fc(skb);
57 u8 queue_index = skb_get_queue_mapping(skb);
59 if (unlikely(ieee80211_is_beacon(fc)))
61 if (ieee80211_is_mgmt(fc))
63 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
64 if (ieee80211_is_nullfunc(fc))
67 return ac_to_hwq[queue_index];
70 /* Update PCI dependent default settings*/
71 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
76 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
77 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
80 ppsc->reg_rfps_level = 0;
81 ppsc->support_aspm = false;
83 /*Update PCI ASPM setting */
84 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
85 switch (rtlpci->const_pci_aspm) {
91 /*ASPM dynamically enabled/disable. */
92 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
96 /*ASPM with Clock Req dynamically enabled/disable. */
97 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
98 RT_RF_OFF_LEVL_CLK_REQ);
103 * Always enable ASPM and Clock Req
104 * from initialization to halt.
106 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
107 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
108 RT_RF_OFF_LEVL_CLK_REQ);
113 * Always enable ASPM without Clock Req
114 * from initialization to halt.
116 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
117 RT_RF_OFF_LEVL_CLK_REQ);
118 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
122 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
124 /*Update Radio OFF setting */
125 switch (rtlpci->const_hwsw_rfoff_d3) {
127 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
128 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
142 /*Set HW definition to determine if it supports ASPM. */
143 switch (rtlpci->const_support_pciaspm) {
145 /*Not support ASPM. */
146 bool support_aspm = false;
147 ppsc->support_aspm = support_aspm;
152 bool support_aspm = true;
153 bool support_backdoor = true;
154 ppsc->support_aspm = support_aspm;
156 /*if (priv->oem_id == RT_CID_TOSHIBA &&
157 !priv->ndis_adapter.amd_l1_patch)
158 support_backdoor = false; */
160 ppsc->support_backdoor = support_backdoor;
165 /*ASPM value set by chipset. */
166 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
167 bool support_aspm = true;
168 ppsc->support_aspm = support_aspm;
172 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
173 "switch case not processed\n");
177 /* toshiba aspm issue, toshiba will set aspm selfly
178 * so we should not set aspm in driver */
179 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
180 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
182 ppsc->support_aspm = false;
185 static bool _rtl_pci_platform_switch_device_pci_aspm(
186 struct ieee80211_hw *hw,
189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
195 pci_write_config_byte(rtlpci->pdev, 0x80, value);
200 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
201 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
203 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
204 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
206 pci_write_config_byte(rtlpci->pdev, 0x81, value);
208 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
214 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
215 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
217 struct rtl_priv *rtlpriv = rtl_priv(hw);
218 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
219 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
220 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
221 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
222 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223 /*Retrieve original configuration settings. */
224 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226 pcibridge_linkctrlreg;
230 if (!ppsc->support_aspm)
233 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235 "PCI(Bridge) UNKNOWN\n");
240 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242 _rtl_pci_switch_clk_req(hw, 0x0);
245 /*for promising device will in L0 state after an I/O. */
246 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
256 /*4 Disable Pci Bridge ASPM */
257 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
258 pcibridge_linkctrlreg);
264 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
265 *power saving We should follow the sequence to enable
266 *RTL8192SE first then enable Pci Bridge ASPM
267 *or the system will show bluescreen.
269 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
273 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
275 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
276 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
277 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
278 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
279 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
281 u8 u_pcibridge_aspmsetting;
282 u8 u_device_aspmsetting;
284 if (!ppsc->support_aspm)
287 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
288 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
289 "PCI(Bridge) UNKNOWN\n");
293 /*4 Enable Pci Bridge ASPM */
295 u_pcibridge_aspmsetting =
296 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
297 rtlpci->const_hostpci_aspm_setting;
299 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
300 u_pcibridge_aspmsetting &= ~BIT(0);
302 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
303 u_pcibridge_aspmsetting);
305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
306 "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
307 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
308 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
309 u_pcibridge_aspmsetting);
313 /*Get ASPM level (with/without Clock Req) */
314 aspmlevel = rtlpci->const_devicepci_aspm_setting;
315 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
317 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
318 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
320 u_device_aspmsetting |= aspmlevel;
322 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
324 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
325 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
326 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
327 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
332 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
340 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
342 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
344 if (offset_e0 == 0xA0) {
345 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
346 if (offset_e4 & BIT(23))
353 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
355 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
356 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
357 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
361 num4bbytes = (capabilityoffset + 0x10) / 4;
363 /*Read Link Control Register */
364 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
366 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
369 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
370 struct ieee80211_hw *hw)
372 struct rtl_priv *rtlpriv = rtl_priv(hw);
373 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
379 /*Link Control Register */
380 pos = pci_pcie_cap(pdev);
381 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
382 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
385 pcipriv->ndis_adapter.linkctrl_reg);
387 pci_read_config_byte(pdev, 0x98, &tmp);
389 pci_write_config_byte(pdev, 0x98, tmp);
392 pci_write_config_byte(pdev, 0x70f, tmp);
395 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
397 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
399 _rtl_pci_update_default_setting(hw);
401 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
402 /*Always enable ASPM & Clock Req. */
403 rtl_pci_enable_aspm(hw);
404 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
409 static void _rtl_pci_io_handler_init(struct device *dev,
410 struct ieee80211_hw *hw)
412 struct rtl_priv *rtlpriv = rtl_priv(hw);
414 rtlpriv->io.dev = dev;
416 rtlpriv->io.write8_async = pci_write8_async;
417 rtlpriv->io.write16_async = pci_write16_async;
418 rtlpriv->io.write32_async = pci_write32_async;
420 rtlpriv->io.read8_sync = pci_read8_sync;
421 rtlpriv->io.read16_sync = pci_read16_sync;
422 rtlpriv->io.read32_sync = pci_read32_sync;
426 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
430 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
431 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
433 struct rtl_priv *rtlpriv = rtl_priv(hw);
434 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
435 u8 additionlen = FCS_LEN;
436 struct sk_buff *next_skb;
438 /* here open is 4, wep/tkip is 8, aes is 12*/
439 if (info->control.hw_key)
440 additionlen += info->control.hw_key->icv_len;
442 /* The most skb num is 6 */
443 tcb_desc->empkt_num = 0;
444 spin_lock_bh(&rtlpriv->locks.waitq_lock);
445 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
446 struct ieee80211_tx_info *next_info;
448 next_info = IEEE80211_SKB_CB(next_skb);
449 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
450 tcb_desc->empkt_len[tcb_desc->empkt_num] =
451 next_skb->len + additionlen;
452 tcb_desc->empkt_num++;
457 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
461 if (tcb_desc->empkt_num >= 5)
464 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
469 /* just for early mode now */
470 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
472 struct rtl_priv *rtlpriv = rtl_priv(hw);
473 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
474 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
475 struct sk_buff *skb = NULL;
476 struct ieee80211_tx_info *info = NULL;
479 if (!rtlpriv->rtlhal.earlymode_enable)
482 /* we juse use em for BE/BK/VI/VO */
483 for (tid = 7; tid >= 0; tid--) {
484 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
485 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
486 while (!mac->act_scanning &&
487 rtlpriv->psc.rfpwr_state == ERFON) {
488 struct rtl_tcb_desc tcb_desc;
489 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
491 spin_lock_bh(&rtlpriv->locks.waitq_lock);
492 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
493 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
494 skb = skb_dequeue(&mac->skb_waitq[tid]);
496 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
499 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
501 /* Some macaddr can't do early mode. like
502 * multicast/broadcast/no_qos data */
503 info = IEEE80211_SKB_CB(skb);
504 if (info->flags & IEEE80211_TX_CTL_AMPDU)
505 _rtl_update_earlymode_info(hw, skb,
508 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
514 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
516 struct rtl_priv *rtlpriv = rtl_priv(hw);
517 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
519 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
521 while (skb_queue_len(&ring->queue)) {
522 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
524 struct ieee80211_tx_info *info;
528 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
532 *beacon packet will only use the first
533 *descriptor defautly,and the own may not
534 *be cleared by the hardware
538 ring->idx = (ring->idx + 1) % ring->entries;
540 skb = __skb_dequeue(&ring->queue);
541 pci_unmap_single(rtlpci->pdev,
543 get_desc((u8 *) entry, true,
544 HW_DESC_TXBUFF_ADDR),
545 skb->len, PCI_DMA_TODEVICE);
547 /* remove early mode header */
548 if (rtlpriv->rtlhal.earlymode_enable)
549 skb_pull(skb, EM_HDR_LEN);
551 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
552 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
554 skb_queue_len(&ring->queue),
555 *(u16 *) (skb->data + 22));
557 if (prio == TXCMD_QUEUE) {
563 /* for sw LPS, just after NULL skb send out, we can
564 * sure AP kown we are sleeped, our we should not let
566 fc = rtl_get_fc(skb);
567 if (ieee80211_is_nullfunc(fc)) {
568 if (ieee80211_has_pm(fc)) {
569 rtlpriv->mac80211.offchan_delay = true;
570 rtlpriv->psc.state_inap = true;
572 rtlpriv->psc.state_inap = false;
576 /* update tid tx pkt num */
577 tid = rtl_get_tid(skb);
579 rtlpriv->link_info.tidtx_inperiod[tid]++;
581 info = IEEE80211_SKB_CB(skb);
582 ieee80211_tx_info_clear_status(info);
584 info->flags |= IEEE80211_TX_STAT_ACK;
585 /*info->status.rates[0].count = 1; */
587 ieee80211_tx_status_irqsafe(hw, skb);
589 if ((ring->entries - skb_queue_len(&ring->queue))
592 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
593 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
595 skb_queue_len(&ring->queue));
597 ieee80211_wake_queue(hw,
598 skb_get_queue_mapping
605 if (((rtlpriv->link_info.num_rx_inperiod +
606 rtlpriv->link_info.num_tx_inperiod) > 8) ||
607 (rtlpriv->link_info.num_rx_inperiod > 2)) {
608 schedule_work(&rtlpriv->works.lps_leave_work);
612 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
613 struct ieee80211_rx_status rx_status)
615 struct rtl_priv *rtlpriv = rtl_priv(hw);
616 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
617 __le16 fc = rtl_get_fc(skb);
618 bool unicast = false;
619 struct sk_buff *uskb = NULL;
623 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
625 if (is_broadcast_ether_addr(hdr->addr1)) {
627 } else if (is_multicast_ether_addr(hdr->addr1)) {
631 rtlpriv->stats.rxbytesunicast += skb->len;
634 rtl_is_special_data(hw, skb, false);
636 if (ieee80211_is_data(fc)) {
637 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
640 rtlpriv->link_info.num_rx_inperiod++;
644 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
645 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
646 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
647 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
648 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
651 if (unlikely(!rtl_action_proc(hw, skb, false)))
654 uskb = dev_alloc_skb(skb->len + 128);
655 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
656 pdata = (u8 *)skb_put(uskb, skb->len);
657 memcpy(pdata, skb->data, skb->len);
659 ieee80211_rx_irqsafe(hw, uskb);
662 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
664 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
666 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
668 struct ieee80211_rx_status rx_status = { 0 };
669 unsigned int count = rtlpci->rxringcount;
674 struct rtl_stats stats = {
679 int index = rtlpci->rx_ring[rx_queue_idx].idx;
684 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
687 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
689 struct sk_buff *new_skb = NULL;
691 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
694 /*wait data to be filled by hardware */
698 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
702 if (stats.crc || stats.hwerror)
705 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
706 if (unlikely(!new_skb)) {
707 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
708 "can't alloc skb for rx\n");
712 pci_unmap_single(rtlpci->pdev,
713 *((dma_addr_t *) skb->cb),
714 rtlpci->rxbuffersize,
717 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
719 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
722 * NOTICE This can not be use for mac80211,
723 * this is done in mac80211 code,
724 * if you done here sec DHCP will fail
725 * skb_trim(skb, skb->len - 4);
728 _rtl_receive_one(hw, skb, rx_status);
730 if (((rtlpriv->link_info.num_rx_inperiod +
731 rtlpriv->link_info.num_tx_inperiod) > 8) ||
732 (rtlpriv->link_info.num_rx_inperiod > 2)) {
733 schedule_work(&rtlpriv->works.lps_leave_work);
736 dev_kfree_skb_any(skb);
739 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
740 *((dma_addr_t *) skb->cb) =
741 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
742 rtlpci->rxbuffersize,
746 bufferaddress = (*((dma_addr_t *)skb->cb));
748 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
750 (u8 *)&bufferaddress);
751 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
753 (u8 *)&rtlpci->rxbuffersize);
755 if (index == rtlpci->rxringcount - 1)
756 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
760 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
763 index = (index + 1) % rtlpci->rxringcount;
766 rtlpci->rx_ring[rx_queue_idx].idx = index;
769 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
771 struct ieee80211_hw *hw = dev_id;
772 struct rtl_priv *rtlpriv = rtl_priv(hw);
773 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
777 irqreturn_t ret = IRQ_HANDLED;
779 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
781 /*read ISR: 4/8bytes */
782 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
784 /*Shared IRQ or HW disappared */
785 if (!inta || inta == 0xffff) {
790 /*<1> beacon related */
791 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
792 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
793 "beacon ok interrupt!\n");
796 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
797 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
798 "beacon err interrupt!\n");
801 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
802 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
805 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
806 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
807 "prepare beacon for interrupt!\n");
808 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
812 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
813 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
815 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
816 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
817 "Manage ok interrupt!\n");
818 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
821 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
822 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
823 "HIGH_QUEUE ok interrupt!\n");
824 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
827 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
828 rtlpriv->link_info.num_tx_inperiod++;
830 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
831 "BK Tx OK interrupt!\n");
832 _rtl_pci_tx_isr(hw, BK_QUEUE);
835 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
836 rtlpriv->link_info.num_tx_inperiod++;
838 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
839 "BE TX OK interrupt!\n");
840 _rtl_pci_tx_isr(hw, BE_QUEUE);
843 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
844 rtlpriv->link_info.num_tx_inperiod++;
846 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
847 "VI TX OK interrupt!\n");
848 _rtl_pci_tx_isr(hw, VI_QUEUE);
851 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
852 rtlpriv->link_info.num_tx_inperiod++;
854 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
855 "Vo TX OK interrupt!\n");
856 _rtl_pci_tx_isr(hw, VO_QUEUE);
859 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
860 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
861 rtlpriv->link_info.num_tx_inperiod++;
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
864 "CMD TX OK interrupt!\n");
865 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
870 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
871 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
872 _rtl_pci_rx_interrupt(hw);
875 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
876 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
877 "rx descriptor unavailable!\n");
878 _rtl_pci_rx_interrupt(hw);
881 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
882 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
883 _rtl_pci_rx_interrupt(hw);
886 if (rtlpriv->rtlhal.earlymode_enable)
887 tasklet_schedule(&rtlpriv->works.irq_tasklet);
890 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
894 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
896 _rtl_pci_tx_chk_waitq(hw);
899 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
901 struct rtl_priv *rtlpriv = rtl_priv(hw);
902 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
903 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
904 struct rtl8192_tx_ring *ring = NULL;
905 struct ieee80211_hdr *hdr = NULL;
906 struct ieee80211_tx_info *info = NULL;
907 struct sk_buff *pskb = NULL;
908 struct rtl_tx_desc *pdesc = NULL;
909 struct rtl_tcb_desc tcb_desc;
912 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
913 ring = &rtlpci->tx_ring[BEACON_QUEUE];
914 pskb = __skb_dequeue(&ring->queue);
918 /*NB: the beacon data buffer must be 32-bit aligned. */
919 pskb = ieee80211_beacon_get(hw, mac->vif);
922 hdr = rtl_get_hdr(pskb);
923 info = IEEE80211_SKB_CB(pskb);
924 pdesc = &ring->desc[0];
925 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
926 info, pskb, BEACON_QUEUE, &tcb_desc);
928 __skb_queue_tail(&ring->queue, pskb);
930 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
936 static void rtl_lps_leave_work_callback(struct work_struct *work)
938 struct rtl_works *rtlworks =
939 container_of(work, struct rtl_works, lps_leave_work);
940 struct ieee80211_hw *hw = rtlworks->hw;
945 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
947 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
950 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
951 rtlpci->txringcount[i] = RT_TXDESC_NUM;
954 *we just alloc 2 desc for beacon queue,
955 *because we just need first desc in hw beacon.
957 rtlpci->txringcount[BEACON_QUEUE] = 2;
960 *BE queue need more descriptor for performance
961 *consideration or, No more tx desc will happen,
962 *and may cause mac80211 mem leakage.
964 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
966 rtlpci->rxbuffersize = 9100; /*2048/1024; */
967 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
970 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
971 struct pci_dev *pdev)
973 struct rtl_priv *rtlpriv = rtl_priv(hw);
974 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
975 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
976 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
978 rtlpci->up_first_time = true;
979 rtlpci->being_init_adapter = false;
984 /*Tx/Rx related var */
985 _rtl_pci_init_trx_var(hw);
987 /*IBSS*/ mac->beacon_interval = 100;
990 mac->min_space_cfg = 0;
991 mac->max_mss_density = 0;
992 /*set sane AMPDU defaults */
993 mac->current_ampdu_density = 7;
994 mac->current_ampdu_factor = 3;
997 rtlpci->acm_method = eAcmWay2_SW;
1000 tasklet_init(&rtlpriv->works.irq_tasklet,
1001 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1003 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1004 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1006 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
1009 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1010 unsigned int prio, unsigned int entries)
1012 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1013 struct rtl_priv *rtlpriv = rtl_priv(hw);
1014 struct rtl_tx_desc *ring;
1016 u32 nextdescaddress;
1019 ring = pci_alloc_consistent(rtlpci->pdev,
1020 sizeof(*ring) * entries, &dma);
1022 if (!ring || (unsigned long)ring & 0xFF) {
1023 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1024 "Cannot allocate TX ring (prio = %d)\n", prio);
1028 memset(ring, 0, sizeof(*ring) * entries);
1029 rtlpci->tx_ring[prio].desc = ring;
1030 rtlpci->tx_ring[prio].dma = dma;
1031 rtlpci->tx_ring[prio].idx = 0;
1032 rtlpci->tx_ring[prio].entries = entries;
1033 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1038 for (i = 0; i < entries; i++) {
1039 nextdescaddress = (u32) dma +
1040 ((i + 1) % entries) *
1043 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1044 true, HW_DESC_TX_NEXTDESC_ADDR,
1045 (u8 *)&nextdescaddress);
1051 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1053 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1054 struct rtl_priv *rtlpriv = rtl_priv(hw);
1055 struct rtl_rx_desc *entry = NULL;
1056 int i, rx_queue_idx;
1060 *rx_queue_idx 0:RX_MPDU_QUEUE
1061 *rx_queue_idx 1:RX_CMD_QUEUE
1063 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1065 rtlpci->rx_ring[rx_queue_idx].desc =
1066 pci_alloc_consistent(rtlpci->pdev,
1067 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1068 desc) * rtlpci->rxringcount,
1069 &rtlpci->rx_ring[rx_queue_idx].dma);
1071 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1072 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1073 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1074 "Cannot allocate RX ring\n");
1078 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1079 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1080 rtlpci->rxringcount);
1082 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1084 /* If amsdu_8k is disabled, set buffersize to 4096. This
1085 * change will reduce memory fragmentation.
1087 if (rtlpci->rxbuffersize > 4096 &&
1088 rtlpriv->rtlhal.disable_amsdu_8k)
1089 rtlpci->rxbuffersize = 4096;
1091 for (i = 0; i < rtlpci->rxringcount; i++) {
1092 struct sk_buff *skb =
1093 dev_alloc_skb(rtlpci->rxbuffersize);
1097 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1099 /*skb->dev = dev; */
1101 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1104 *just set skb->cb to mapping addr
1105 *for pci_unmap_single use
1107 *((dma_addr_t *) skb->cb) =
1108 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1109 rtlpci->rxbuffersize,
1110 PCI_DMA_FROMDEVICE);
1112 bufferaddress = (*((dma_addr_t *)skb->cb));
1113 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1114 HW_DESC_RXBUFF_ADDR,
1115 (u8 *)&bufferaddress);
1116 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1120 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1125 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1126 HW_DESC_RXERO, (u8 *)&tmp_one);
1131 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1134 struct rtl_priv *rtlpriv = rtl_priv(hw);
1135 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1136 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1138 while (skb_queue_len(&ring->queue)) {
1139 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1140 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1142 pci_unmap_single(rtlpci->pdev,
1144 ops->get_desc((u8 *) entry, true,
1145 HW_DESC_TXBUFF_ADDR),
1146 skb->len, PCI_DMA_TODEVICE);
1148 ring->idx = (ring->idx + 1) % ring->entries;
1151 pci_free_consistent(rtlpci->pdev,
1152 sizeof(*ring->desc) * ring->entries,
1153 ring->desc, ring->dma);
1157 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1159 int i, rx_queue_idx;
1161 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1162 /*rx_queue_idx 1:RX_CMD_QUEUE */
1163 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1165 for (i = 0; i < rtlpci->rxringcount; i++) {
1166 struct sk_buff *skb =
1167 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1171 pci_unmap_single(rtlpci->pdev,
1172 *((dma_addr_t *) skb->cb),
1173 rtlpci->rxbuffersize,
1174 PCI_DMA_FROMDEVICE);
1178 pci_free_consistent(rtlpci->pdev,
1179 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1180 desc) * rtlpci->rxringcount,
1181 rtlpci->rx_ring[rx_queue_idx].desc,
1182 rtlpci->rx_ring[rx_queue_idx].dma);
1183 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1187 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1193 ret = _rtl_pci_init_rx_ring(hw);
1197 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1198 ret = _rtl_pci_init_tx_ring(hw, i,
1199 rtlpci->txringcount[i]);
1201 goto err_free_rings;
1207 _rtl_pci_free_rx_ring(rtlpci);
1209 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1210 if (rtlpci->tx_ring[i].desc)
1211 _rtl_pci_free_tx_ring(hw, i);
1216 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1218 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1222 _rtl_pci_free_rx_ring(rtlpci);
1225 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1226 _rtl_pci_free_tx_ring(hw, i);
1231 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1233 struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1235 int i, rx_queue_idx;
1236 unsigned long flags;
1239 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1240 /*rx_queue_idx 1:RX_CMD_QUEUE */
1241 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1244 *force the rx_ring[RX_MPDU_QUEUE/
1245 *RX_CMD_QUEUE].idx to the first one
1247 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1248 struct rtl_rx_desc *entry = NULL;
1250 for (i = 0; i < rtlpci->rxringcount; i++) {
1251 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1252 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1257 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1262 *after reset, release previous pending packet,
1263 *and force the tx idx to the first one
1265 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1266 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1267 if (rtlpci->tx_ring[i].desc) {
1268 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1270 while (skb_queue_len(&ring->queue)) {
1271 struct rtl_tx_desc *entry =
1272 &ring->desc[ring->idx];
1273 struct sk_buff *skb =
1274 __skb_dequeue(&ring->queue);
1276 pci_unmap_single(rtlpci->pdev,
1281 HW_DESC_TXBUFF_ADDR),
1282 skb->len, PCI_DMA_TODEVICE);
1284 ring->idx = (ring->idx + 1) % ring->entries;
1290 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1295 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1296 struct sk_buff *skb)
1298 struct rtl_priv *rtlpriv = rtl_priv(hw);
1299 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1300 struct ieee80211_sta *sta = info->control.sta;
1301 struct rtl_sta_info *sta_entry = NULL;
1302 u8 tid = rtl_get_tid(skb);
1306 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1308 if (!rtlpriv->rtlhal.earlymode_enable)
1310 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1312 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1317 /* maybe every tid should be checked */
1318 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1321 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1322 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1323 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1328 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1329 struct rtl_tcb_desc *ptcb_desc)
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
1332 struct rtl_sta_info *sta_entry = NULL;
1333 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1334 struct ieee80211_sta *sta = info->control.sta;
1335 struct rtl8192_tx_ring *ring;
1336 struct rtl_tx_desc *pdesc;
1338 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1339 unsigned long flags;
1340 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1341 __le16 fc = rtl_get_fc(skb);
1342 u8 *pda_addr = hdr->addr1;
1343 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1350 if (ieee80211_is_auth(fc)) {
1351 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n");
1355 if (rtlpriv->psc.sw_ps_enabled) {
1356 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1357 !ieee80211_has_pm(fc))
1358 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1361 rtl_action_proc(hw, skb, true);
1363 if (is_multicast_ether_addr(pda_addr))
1364 rtlpriv->stats.txbytesmulticast += skb->len;
1365 else if (is_broadcast_ether_addr(pda_addr))
1366 rtlpriv->stats.txbytesbroadcast += skb->len;
1368 rtlpriv->stats.txbytesunicast += skb->len;
1370 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1371 ring = &rtlpci->tx_ring[hw_queue];
1372 if (hw_queue != BEACON_QUEUE)
1373 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1378 pdesc = &ring->desc[idx];
1379 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1382 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1383 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1384 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1385 hw_queue, ring->idx, idx,
1386 skb_queue_len(&ring->queue));
1388 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1392 if (ieee80211_is_data_qos(fc)) {
1393 tid = rtl_get_tid(skb);
1395 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1396 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1397 IEEE80211_SCTL_SEQ) >> 4;
1400 if (!ieee80211_has_morefrags(hdr->frame_control))
1401 sta_entry->tids[tid].seq_number = seq_number;
1405 if (ieee80211_is_data(fc))
1406 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1408 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1409 info, skb, hw_queue, ptcb_desc);
1411 __skb_queue_tail(&ring->queue, skb);
1413 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1414 HW_DESC_OWN, (u8 *)&temp_one);
1417 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1418 hw_queue != BEACON_QUEUE) {
1420 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1421 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1422 hw_queue, ring->idx, idx,
1423 skb_queue_len(&ring->queue));
1425 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1428 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1430 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1435 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1437 struct rtl_priv *rtlpriv = rtl_priv(hw);
1438 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1439 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1442 struct rtl8192_tx_ring *ring;
1444 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1446 ring = &pcipriv->dev.tx_ring[queue_id];
1447 queue_len = skb_queue_len(&ring->queue);
1448 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1449 queue_id == TXCMD_QUEUE) {
1457 /* we just wait 1s for all queues */
1458 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1459 is_hal_stop(rtlhal) || i >= 200)
1464 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1466 struct rtl_priv *rtlpriv = rtl_priv(hw);
1467 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1469 _rtl_pci_deinit_trx_ring(hw);
1471 synchronize_irq(rtlpci->pdev->irq);
1472 tasklet_kill(&rtlpriv->works.irq_tasklet);
1473 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1475 flush_workqueue(rtlpriv->works.rtl_wq);
1476 destroy_workqueue(rtlpriv->works.rtl_wq);
1480 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1482 struct rtl_priv *rtlpriv = rtl_priv(hw);
1485 _rtl_pci_init_struct(hw, pdev);
1487 err = _rtl_pci_init_trx_ring(hw);
1489 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1490 "tx ring initialization failed\n");
1497 static int rtl_pci_start(struct ieee80211_hw *hw)
1499 struct rtl_priv *rtlpriv = rtl_priv(hw);
1500 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1501 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1502 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1506 rtl_pci_reset_trx_ring(hw);
1508 rtlpci->driver_is_goingto_unload = false;
1509 err = rtlpriv->cfg->ops->hw_init(hw);
1511 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1512 "Failed to config hardware!\n");
1516 rtlpriv->cfg->ops->enable_interrupt(hw);
1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1519 rtl_init_rx_config(hw);
1521 /*should be after adapter start and interrupt enable. */
1522 set_hal_start(rtlhal);
1524 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1526 rtlpci->up_first_time = false;
1528 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1532 static void rtl_pci_stop(struct ieee80211_hw *hw)
1534 struct rtl_priv *rtlpriv = rtl_priv(hw);
1535 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1536 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1537 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1538 unsigned long flags;
1539 u8 RFInProgressTimeOut = 0;
1542 *should be before disable interrupt&adapter
1543 *and will do it immediately.
1545 set_hal_stop(rtlhal);
1547 rtlpriv->cfg->ops->disable_interrupt(hw);
1548 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1550 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1551 while (ppsc->rfchange_inprogress) {
1552 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1553 if (RFInProgressTimeOut > 100) {
1554 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1558 RFInProgressTimeOut++;
1559 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1561 ppsc->rfchange_inprogress = true;
1562 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1564 rtlpci->driver_is_goingto_unload = true;
1565 rtlpriv->cfg->ops->hw_disable(hw);
1566 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1568 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1569 ppsc->rfchange_inprogress = false;
1570 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1572 rtl_pci_enable_aspm(hw);
1575 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1576 struct ieee80211_hw *hw)
1578 struct rtl_priv *rtlpriv = rtl_priv(hw);
1579 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1580 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1581 struct pci_dev *bridge_pdev = pdev->bus->self;
1588 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1589 venderid = pdev->vendor;
1590 deviceid = pdev->device;
1591 pci_read_config_byte(pdev, 0x8, &revisionid);
1592 pci_read_config_word(pdev, 0x3C, &irqline);
1594 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1595 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1596 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1597 * the correct driver is r8192e_pci, thus this routine should
1600 if (deviceid == RTL_PCI_8192SE_DID &&
1601 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1604 if (deviceid == RTL_PCI_8192_DID ||
1605 deviceid == RTL_PCI_0044_DID ||
1606 deviceid == RTL_PCI_0047_DID ||
1607 deviceid == RTL_PCI_8192SE_DID ||
1608 deviceid == RTL_PCI_8174_DID ||
1609 deviceid == RTL_PCI_8173_DID ||
1610 deviceid == RTL_PCI_8172_DID ||
1611 deviceid == RTL_PCI_8171_DID) {
1612 switch (revisionid) {
1613 case RTL_PCI_REVISION_ID_8192PCIE:
1614 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1615 "8192 PCI-E is found - vid/did=%x/%x\n",
1616 venderid, deviceid);
1617 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1619 case RTL_PCI_REVISION_ID_8192SE:
1620 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1621 "8192SE is found - vid/did=%x/%x\n",
1622 venderid, deviceid);
1623 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1626 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1627 "Err: Unknown device - vid/did=%x/%x\n",
1628 venderid, deviceid);
1629 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1633 } else if (deviceid == RTL_PCI_8192CET_DID ||
1634 deviceid == RTL_PCI_8192CE_DID ||
1635 deviceid == RTL_PCI_8191CE_DID ||
1636 deviceid == RTL_PCI_8188CE_DID) {
1637 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1638 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1639 "8192C PCI-E is found - vid/did=%x/%x\n",
1640 venderid, deviceid);
1641 } else if (deviceid == RTL_PCI_8192DE_DID ||
1642 deviceid == RTL_PCI_8192DE_DID2) {
1643 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1644 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1645 "8192D PCI-E is found - vid/did=%x/%x\n",
1646 venderid, deviceid);
1648 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1649 "Err: Unknown device - vid/did=%x/%x\n",
1650 venderid, deviceid);
1652 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1655 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1656 if (revisionid == 0 || revisionid == 1) {
1657 if (revisionid == 0) {
1658 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1659 "Find 92DE MAC0\n");
1660 rtlhal->interfaceindex = 0;
1661 } else if (revisionid == 1) {
1662 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1663 "Find 92DE MAC1\n");
1664 rtlhal->interfaceindex = 1;
1667 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1668 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1669 venderid, deviceid, revisionid);
1670 rtlhal->interfaceindex = 0;
1674 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1675 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1676 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1679 /*find bridge info if available */
1680 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1681 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1682 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1683 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1684 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1685 "Pci Bridge Vendor is found index: %d\n",
1692 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1693 PCI_BRIDGE_VENDOR_UNKNOWN) {
1694 pcipriv->ndis_adapter.pcibridge_busnum =
1695 bridge_pdev->bus->number;
1696 pcipriv->ndis_adapter.pcibridge_devnum =
1697 PCI_SLOT(bridge_pdev->devfn);
1698 pcipriv->ndis_adapter.pcibridge_funcnum =
1699 PCI_FUNC(bridge_pdev->devfn);
1700 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1701 pci_pcie_cap(bridge_pdev);
1702 pcipriv->ndis_adapter.num4bytes =
1703 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1705 rtl_pci_get_linkcontrol_field(hw);
1707 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1708 PCI_BRIDGE_VENDOR_AMD) {
1709 pcipriv->ndis_adapter.amd_l1_patch =
1710 rtl_pci_get_amd_l1_patch(hw);
1714 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1715 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1716 pcipriv->ndis_adapter.busnumber,
1717 pcipriv->ndis_adapter.devnumber,
1718 pcipriv->ndis_adapter.funcnumber,
1719 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1721 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1722 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1723 pcipriv->ndis_adapter.pcibridge_busnum,
1724 pcipriv->ndis_adapter.pcibridge_devnum,
1725 pcipriv->ndis_adapter.pcibridge_funcnum,
1726 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1727 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1728 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1729 pcipriv->ndis_adapter.amd_l1_patch);
1731 rtl_pci_parse_configuration(pdev, hw);
1736 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1737 const struct pci_device_id *id)
1739 struct ieee80211_hw *hw = NULL;
1741 struct rtl_priv *rtlpriv = NULL;
1742 struct rtl_pci_priv *pcipriv = NULL;
1743 struct rtl_pci *rtlpci;
1744 unsigned long pmem_start, pmem_len, pmem_flags;
1747 err = pci_enable_device(pdev);
1749 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1754 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1755 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1757 "Unable to obtain 32bit DMA for consistent allocations\n");
1758 pci_disable_device(pdev);
1763 pci_set_master(pdev);
1765 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1766 sizeof(struct rtl_priv), &rtl_ops);
1769 "%s : ieee80211 alloc failed\n", pci_name(pdev));
1774 SET_IEEE80211_DEV(hw, &pdev->dev);
1775 pci_set_drvdata(pdev, hw);
1778 pcipriv = (void *)rtlpriv->priv;
1779 pcipriv->dev.pdev = pdev;
1781 /* init cfg & intf_ops */
1782 rtlpriv->rtlhal.interface = INTF_PCI;
1783 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1784 rtlpriv->intf_ops = &rtl_pci_ops;
1787 *init dbgp flags before all
1788 *other functions, because we will
1789 *use it in other funtions like
1790 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1791 *you can not use these macro
1794 rtl_dbgp_flag_init(hw);
1797 err = pci_request_regions(pdev, KBUILD_MODNAME);
1799 RT_ASSERT(false, "Can't obtain PCI resources\n");
1803 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1804 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1805 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1807 /*shared mem start */
1808 rtlpriv->io.pci_mem_start =
1809 (unsigned long)pci_iomap(pdev,
1810 rtlpriv->cfg->bar_id, pmem_len);
1811 if (rtlpriv->io.pci_mem_start == 0) {
1812 RT_ASSERT(false, "Can't map PCI mem\n");
1816 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1817 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1818 pmem_start, pmem_len, pmem_flags,
1819 rtlpriv->io.pci_mem_start);
1821 /* Disable Clk Request */
1822 pci_write_config_byte(pdev, 0x81, 0);
1824 pci_write_config_byte(pdev, 0x44, 0);
1825 pci_write_config_byte(pdev, 0x04, 0x06);
1826 pci_write_config_byte(pdev, 0x04, 0x07);
1829 if (!_rtl_pci_find_adapter(pdev, hw))
1832 /* Init IO handler */
1833 _rtl_pci_io_handler_init(&pdev->dev, hw);
1835 /*like read eeprom and so on */
1836 rtlpriv->cfg->ops->read_eeprom_info(hw);
1838 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1839 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1843 rtlpriv->cfg->ops->init_sw_leds(hw);
1846 rtl_pci_init_aspm(hw);
1848 /* Init mac80211 sw */
1849 err = rtl_init_core(hw);
1851 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1852 "Can't allocate sw for mac80211\n");
1857 err = !rtl_pci_init(hw, pdev);
1859 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
1863 err = ieee80211_register_hw(hw);
1865 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1866 "Can't register mac80211 hw\n");
1869 rtlpriv->mac80211.mac80211_registered = 1;
1872 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1874 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1875 "failed to create sysfs device attributes\n");
1880 rtl_init_rfkill(hw);
1882 rtlpci = rtl_pcidev(pcipriv);
1883 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1884 IRQF_SHARED, KBUILD_MODNAME, hw);
1886 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1887 "%s: failed to register IRQ handler\n",
1888 wiphy_name(hw->wiphy));
1891 rtlpci->irq_alloc = 1;
1894 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1898 pci_set_drvdata(pdev, NULL);
1899 rtl_deinit_core(hw);
1900 _rtl_pci_io_handler_release(hw);
1901 ieee80211_free_hw(hw);
1903 if (rtlpriv->io.pci_mem_start != 0)
1904 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1907 pci_release_regions(pdev);
1911 pci_disable_device(pdev);
1916 EXPORT_SYMBOL(rtl_pci_probe);
1918 void rtl_pci_disconnect(struct pci_dev *pdev)
1920 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1921 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1922 struct rtl_priv *rtlpriv = rtl_priv(hw);
1923 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1924 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1926 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1928 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1930 /*ieee80211_unregister_hw will call ops_stop */
1931 if (rtlmac->mac80211_registered == 1) {
1932 ieee80211_unregister_hw(hw);
1933 rtlmac->mac80211_registered = 0;
1935 rtl_deinit_deferred_work(hw);
1936 rtlpriv->intf_ops->adapter_stop(hw);
1940 rtl_deinit_rfkill(hw);
1943 rtl_deinit_core(hw);
1944 _rtl_pci_io_handler_release(hw);
1945 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1947 if (rtlpci->irq_alloc) {
1948 free_irq(rtlpci->pdev->irq, hw);
1949 rtlpci->irq_alloc = 0;
1952 if (rtlpriv->io.pci_mem_start != 0) {
1953 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1954 pci_release_regions(pdev);
1957 pci_disable_device(pdev);
1959 rtl_pci_disable_aspm(hw);
1961 pci_set_drvdata(pdev, NULL);
1963 ieee80211_free_hw(hw);
1965 EXPORT_SYMBOL(rtl_pci_disconnect);
1967 /***************************************
1968 kernel pci power state define:
1969 PCI_D0 ((pci_power_t __force) 0)
1970 PCI_D1 ((pci_power_t __force) 1)
1971 PCI_D2 ((pci_power_t __force) 2)
1972 PCI_D3hot ((pci_power_t __force) 3)
1973 PCI_D3cold ((pci_power_t __force) 4)
1974 PCI_UNKNOWN ((pci_power_t __force) 5)
1976 This function is called when system
1977 goes into suspend state mac80211 will
1978 call rtl_mac_stop() from the mac80211
1979 suspend function first, So there is
1980 no need to call hw_disable here.
1981 ****************************************/
1982 int rtl_pci_suspend(struct device *dev)
1984 struct pci_dev *pdev = to_pci_dev(dev);
1985 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1986 struct rtl_priv *rtlpriv = rtl_priv(hw);
1988 rtlpriv->cfg->ops->hw_suspend(hw);
1989 rtl_deinit_rfkill(hw);
1993 EXPORT_SYMBOL(rtl_pci_suspend);
1995 int rtl_pci_resume(struct device *dev)
1997 struct pci_dev *pdev = to_pci_dev(dev);
1998 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1999 struct rtl_priv *rtlpriv = rtl_priv(hw);
2001 rtlpriv->cfg->ops->hw_resume(hw);
2002 rtl_init_rfkill(hw);
2005 EXPORT_SYMBOL(rtl_pci_resume);
2007 struct rtl_intf_ops rtl_pci_ops = {
2008 .read_efuse_byte = read_efuse_byte,
2009 .adapter_start = rtl_pci_start,
2010 .adapter_stop = rtl_pci_stop,
2011 .adapter_tx = rtl_pci_tx,
2012 .flush = rtl_pci_flush,
2013 .reset_trx_ring = rtl_pci_reset_trx_ring,
2014 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2016 .disable_aspm = rtl_pci_disable_aspm,
2017 .enable_aspm = rtl_pci_enable_aspm,