drivers/net/wireless/rtlwifi/pci.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "wifi.h"
  31 #include "core.h"
  32 #include "pci.h"
  33 #include "base.h"
  34 #include "ps.h"
  35 #include "efuse.h"
  36 #include <linux/export.h>
  37 #include <linux/kmemleak.h>
  38
  39 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
  40         PCI_VENDOR_ID_INTEL,
  41         PCI_VENDOR_ID_ATI,
  42         PCI_VENDOR_ID_AMD,
  43         PCI_VENDOR_ID_SI
  44 };
  45
  46 static const u8 ac_to_hwq[] = {
  47         VO_QUEUE,
  48         VI_QUEUE,
  49         BE_QUEUE,
  50         BK_QUEUE
  51 };
  52
  53 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
  54                        struct sk_buff *skb)
  55 {
  56         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  57         __le16 fc = rtl_get_fc(skb);
  58         u8 queue_index = skb_get_queue_mapping(skb);
  59
  60         if (unlikely(ieee80211_is_beacon(fc)))
  61                 return BEACON_QUEUE;
  62         if (ieee80211_is_mgmt(fc))
  63                 return MGNT_QUEUE;
  64         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
  65                 if (ieee80211_is_nullfunc(fc))
  66                         return HIGH_QUEUE;
  67
  68         return ac_to_hwq[queue_index];
  69 }
  70
  71 /* Update PCI dependent default settings*/
  72 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
  73 {
  74         struct rtl_priv *rtlpriv = rtl_priv(hw);
  75         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  76         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  77         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  78         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
  79         u8 init_aspm;
  80
  81         ppsc->reg_rfps_level = 0;
  82         ppsc->support_aspm = false;
  83
  84         /*Update PCI ASPM setting */
  85         ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
  86         switch (rtlpci->const_pci_aspm) {
  87         case 0:
  88                 /*No ASPM */
  89                 break;
  90
  91         case 1:
  92                 /*ASPM dynamically enabled/disable. */
  93                 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
  94                 break;
  95
  96         case 2:
  97                 /*ASPM with Clock Req dynamically enabled/disable. */
  98                 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
  99                                          RT_RF_OFF_LEVL_CLK_REQ);
 100                 break;
 101
 102         case 3:
 103                 /*
 104                  * Always enable ASPM and Clock Req
 105                  * from initialization to halt.
 106                  * */
 107                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
 108                 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
 109                                          RT_RF_OFF_LEVL_CLK_REQ);
 110                 break;
 111
 112         case 4:
 113                 /*
 114                  * Always enable ASPM without Clock Req
 115                  * from initialization to halt.
 116                  * */
 117                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
 118                                           RT_RF_OFF_LEVL_CLK_REQ);
 119                 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
 120                 break;
 121         }
 122
 123         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
 124
 125         /*Update Radio OFF setting */
 126         switch (rtlpci->const_hwsw_rfoff_d3) {
 127         case 1:
 128                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 129                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 130                 break;
 131
 132         case 2:
 133                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 134                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 135                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
 136                 break;
 137
 138         case 3:
 139                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
 140                 break;
 141         }
 142
 143         /*Set HW definition to determine if it supports ASPM. */
 144         switch (rtlpci->const_support_pciaspm) {
 145         case 0:{
 146                         /*Not support ASPM. */
 147                         bool support_aspm = false;
 148                         ppsc->support_aspm = support_aspm;
 149                         break;
 150                 }
 151         case 1:{
 152                         /*Support ASPM. */
 153                         bool support_aspm = true;
 154                         bool support_backdoor = true;
 155                         ppsc->support_aspm = support_aspm;
 156
 157                         /*if (priv->oem_id == RT_CID_TOSHIBA &&
 158                            !priv->ndis_adapter.amd_l1_patch)
 159                            support_backdoor = false; */
 160
 161                         ppsc->support_backdoor = support_backdoor;
 162
 163                         break;
 164                 }
 165         case 2:
 166                 /*ASPM value set by chipset. */
 167                 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
 168                         bool support_aspm = true;
 169                         ppsc->support_aspm = support_aspm;
 170                 }
 171                 break;
 172         default:
 173                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 174                          "switch case not processed\n");
 175                 break;
 176         }
 177
 178         /* toshiba aspm issue, toshiba will set aspm selfly
 179          * so we should not set aspm in driver */
 180         pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
 181         if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
 182                 init_aspm == 0x43)
 183                 ppsc->support_aspm = false;
 184 }
 185
 186 static bool _rtl_pci_platform_switch_device_pci_aspm(
 187                         struct ieee80211_hw *hw,
 188                         u8 value)
 189 {
 190         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 191         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 192
 193         if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
 194                 value |= 0x40;
 195
 196         pci_write_config_byte(rtlpci->pdev, 0x80, value);
 197
 198         return false;
 199 }
 200
 201 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
 202 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
 203 {
 204         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 205         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 206
 207         pci_write_config_byte(rtlpci->pdev, 0x81, value);
 208
 209         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 210                 udelay(100);
 211 }
 212
 213 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
 214 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
 215 {
 216         struct rtl_priv *rtlpriv = rtl_priv(hw);
 217         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 218         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 219         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 220         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 221         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 222         /*Retrieve original configuration settings. */
 223         u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
 224         u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
 225                                 pcibridge_linkctrlreg;
 226         u16 aspmlevel = 0;
 227         u8 tmp_u1b = 0;
 228
 229         if (!ppsc->support_aspm)
 230                 return;
 231
 232         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 233                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 234                          "PCI(Bridge) UNKNOWN\n");
 235
 236                 return;
 237         }
 238
 239         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 240                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 241                 _rtl_pci_switch_clk_req(hw, 0x0);
 242         }
 243
 244         /*for promising device will in L0 state after an I/O. */
 245         pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
 246
 247         /*Set corresponding value. */
 248         aspmlevel |= BIT(0) | BIT(1);
 249         linkctrl_reg &= ~aspmlevel;
 250         pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
 251
 252         _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
 253         udelay(50);
 254
 255         /*4 Disable Pci Bridge ASPM */
 256         pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
 257                               pcibridge_linkctrlreg);
 258
 259         udelay(50);
 260 }
 261
 262 /*
 263  *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
 264  *power saving We should follow the sequence to enable
 265  *RTL8192SE first then enable Pci Bridge ASPM
 266  *or the system will show bluescreen.
 267  */
 268 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
 269 {
 270         struct rtl_priv *rtlpriv = rtl_priv(hw);
 271         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 272         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 273         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 274         u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
 275         u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
 276         u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
 277         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 278         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 279         u16 aspmlevel;
 280         u8 u_pcibridge_aspmsetting;
 281         u8 u_device_aspmsetting;
 282
 283         if (!ppsc->support_aspm)
 284                 return;
 285
 286         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 287                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 288                          "PCI(Bridge) UNKNOWN\n");
 289                 return;
 290         }
 291
 292         /*4 Enable Pci Bridge ASPM */
 293
 294         u_pcibridge_aspmsetting =
 295             pcipriv->ndis_adapter.pcibridge_linkctrlreg |
 296             rtlpci->const_hostpci_aspm_setting;
 297
 298         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
 299                 u_pcibridge_aspmsetting &= ~BIT(0);
 300
 301         pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
 302                               u_pcibridge_aspmsetting);
 303
 304         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 305                  "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 306                  pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
 307                  (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
 308                  u_pcibridge_aspmsetting);
 309
 310         udelay(50);
 311
 312         /*Get ASPM level (with/without Clock Req) */
 313         aspmlevel = rtlpci->const_devicepci_aspm_setting;
 314         u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
 315
 316         /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
 317         /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
 318
 319         u_device_aspmsetting |= aspmlevel;
 320
 321         _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
 322
 323         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 324                 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
 325                                              RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
 326                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 327         }
 328         udelay(100);
 329 }
 330
 331 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
 332 {
 333         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 334
 335         bool status = false;
 336         u8 offset_e0;
 337         unsigned offset_e4;
 338
 339         pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
 340
 341         pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
 342
 343         if (offset_e0 == 0xA0) {
 344                 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
 345                 if (offset_e4 & BIT(23))
 346                         status = true;
 347         }
 348
 349         return status;
 350 }
 351
 352 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
 353 {
 354         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 355         struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
 356         u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
 357         u8 linkctrl_reg;
 358         u8 num4bbytes;
 359
 360         num4bbytes = (capabilityoffset + 0x10) / 4;
 361
 362         /*Read  Link Control Register */
 363         pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
 364
 365         pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
 366 }
 367
 368 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
 369                 struct ieee80211_hw *hw)
 370 {
 371         struct rtl_priv *rtlpriv = rtl_priv(hw);
 372         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 373
 374         u8 tmp;
 375         u16 linkctrl_reg;
 376
 377         /*Link Control Register */
 378         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
 379         pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
 380
 381         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
 382                  pcipriv->ndis_adapter.linkctrl_reg);
 383
 384         pci_read_config_byte(pdev, 0x98, &tmp);
 385         tmp |= BIT(4);
 386         pci_write_config_byte(pdev, 0x98, tmp);
 387
 388         tmp = 0x17;
 389         pci_write_config_byte(pdev, 0x70f, tmp);
 390 }
 391
 392 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
 393 {
 394         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 395
 396         _rtl_pci_update_default_setting(hw);
 397
 398         if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
 399                 /*Always enable ASPM & Clock Req. */
 400                 rtl_pci_enable_aspm(hw);
 401                 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
 402         }
 403
 404 }
 405
 406 static void _rtl_pci_io_handler_init(struct device *dev,
 407                                      struct ieee80211_hw *hw)
 408 {
 409         struct rtl_priv *rtlpriv = rtl_priv(hw);
 410
 411         rtlpriv->io.dev = dev;
 412
 413         rtlpriv->io.write8_async = pci_write8_async;
 414         rtlpriv->io.write16_async = pci_write16_async;
 415         rtlpriv->io.write32_async = pci_write32_async;
 416
 417         rtlpriv->io.read8_sync = pci_read8_sync;
 418         rtlpriv->io.read16_sync = pci_read16_sync;
 419         rtlpriv->io.read32_sync = pci_read32_sync;
 420
 421 }
 422
 423 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
 424 {
 425 }
 426
 427 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
 428                 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
 429 {
 430         struct rtl_priv *rtlpriv = rtl_priv(hw);
 431         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 432         u8 additionlen = FCS_LEN;
 433         struct sk_buff *next_skb;
 434
 435         /* here open is 4, wep/tkip is 8, aes is 12*/
 436         if (info->control.hw_key)
 437                 additionlen += info->control.hw_key->icv_len;
 438
 439         /* The most skb num is 6 */
 440         tcb_desc->empkt_num = 0;
 441         spin_lock_bh(&rtlpriv->locks.waitq_lock);
 442         skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
 443                 struct ieee80211_tx_info *next_info;
 444
 445                 next_info = IEEE80211_SKB_CB(next_skb);
 446                 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
 447                         tcb_desc->empkt_len[tcb_desc->empkt_num] =
 448                                 next_skb->len + additionlen;
 449                         tcb_desc->empkt_num++;
 450                 } else {
 451                         break;
 452                 }
 453
 454                 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
 455                                       next_skb))
 456                         break;
 457
 458                 if (tcb_desc->empkt_num >= 5)
 459                         break;
 460         }
 461         spin_unlock_bh(&rtlpriv->locks.waitq_lock);
 462
 463         return true;
 464 }
 465
 466 /* just for early mode now */
 467 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
 468 {
 469         struct rtl_priv *rtlpriv = rtl_priv(hw);
 470         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 471         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 472         struct sk_buff *skb = NULL;
 473         struct ieee80211_tx_info *info = NULL;
 474         int tid;
 475
 476         if (!rtlpriv->rtlhal.earlymode_enable)
 477                 return;
 478
 479         /* we juse use em for BE/BK/VI/VO */
 480         for (tid = 7; tid >= 0; tid--) {
 481                 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
 482                 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
 483                 while (!mac->act_scanning &&
 484                        rtlpriv->psc.rfpwr_state == ERFON) {
 485                         struct rtl_tcb_desc tcb_desc;
 486                         memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
 487
 488                         spin_lock_bh(&rtlpriv->locks.waitq_lock);
 489                         if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
 490                            (ring->entries - skb_queue_len(&ring->queue) > 5)) {
 491                                 skb = skb_dequeue(&mac->skb_waitq[tid]);
 492                         } else {
 493                                 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
 494                                 break;
 495                         }
 496                         spin_unlock_bh(&rtlpriv->locks.waitq_lock);
 497
 498                         /* Some macaddr can't do early mode. like
 499                          * multicast/broadcast/no_qos data */
 500                         info = IEEE80211_SKB_CB(skb);
 501                         if (info->flags & IEEE80211_TX_CTL_AMPDU)
 502                                 _rtl_update_earlymode_info(hw, skb,
 503                                                            &tcb_desc, tid);
 504
 505                         rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
 506                 }
 507         }
 508 }
 509
 510
 511 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
 512 {
 513         struct rtl_priv *rtlpriv = rtl_priv(hw);
 514         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 515
 516         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
 517
 518         while (skb_queue_len(&ring->queue)) {
 519                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
 520                 struct sk_buff *skb;
 521                 struct ieee80211_tx_info *info;
 522                 __le16 fc;
 523                 u8 tid;
 524
 525                 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
 526                                                           HW_DESC_OWN);
 527
 528                 /*
 529                  *beacon packet will only use the first
 530                  *descriptor defautly,and the own may not
 531                  *be cleared by the hardware
 532                  */
 533                 if (own)
 534                         return;
 535                 ring->idx = (ring->idx + 1) % ring->entries;
 536
 537                 skb = __skb_dequeue(&ring->queue);
 538                 pci_unmap_single(rtlpci->pdev,
 539                                  rtlpriv->cfg->ops->
 540                                              get_desc((u8 *) entry, true,
 541                                                       HW_DESC_TXBUFF_ADDR),
 542                                  skb->len, PCI_DMA_TODEVICE);
 543
 544                 /* remove early mode header */
 545                 if (rtlpriv->rtlhal.earlymode_enable)
 546                         skb_pull(skb, EM_HDR_LEN);
 547
 548                 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
 549                          "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
 550                          ring->idx,
 551                          skb_queue_len(&ring->queue),
 552                          *(u16 *) (skb->data + 22));
 553
 554                 if (prio == TXCMD_QUEUE) {
 555                         dev_kfree_skb(skb);
 556                         goto tx_status_ok;
 557
 558                 }
 559
 560                 /* for sw LPS, just after NULL skb send out, we can
 561                  * sure AP kown we are sleeped, our we should not let
 562                  * rf to sleep*/
 563                 fc = rtl_get_fc(skb);
 564                 if (ieee80211_is_nullfunc(fc)) {
 565                         if (ieee80211_has_pm(fc)) {
 566                                 rtlpriv->mac80211.offchan_delay = true;
 567                                 rtlpriv->psc.state_inap = true;
 568                         } else {
 569                                 rtlpriv->psc.state_inap = false;
 570                         }
 571                 }
 572
 573                 /* update tid tx pkt num */
 574                 tid = rtl_get_tid(skb);
 575                 if (tid <= 7)
 576                         rtlpriv->link_info.tidtx_inperiod[tid]++;
 577
 578                 info = IEEE80211_SKB_CB(skb);
 579                 ieee80211_tx_info_clear_status(info);
 580
 581                 info->flags |= IEEE80211_TX_STAT_ACK;
 582                 /*info->status.rates[0].count = 1; */
 583
 584                 ieee80211_tx_status_irqsafe(hw, skb);
 585
 586                 if ((ring->entries - skb_queue_len(&ring->queue))
 587                                 == 2) {
 588
 589                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 590                                  "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
 591                                  prio, ring->idx,
 592                                  skb_queue_len(&ring->queue));
 593
 594                         ieee80211_wake_queue(hw,
 595                                         skb_get_queue_mapping
 596                                         (skb));
 597                 }
 598 tx_status_ok:
 599                 skb = NULL;
 600         }
 601
 602         if (((rtlpriv->link_info.num_rx_inperiod +
 603                 rtlpriv->link_info.num_tx_inperiod) > 8) ||
 604                 (rtlpriv->link_info.num_rx_inperiod > 2)) {
 605                 schedule_work(&rtlpriv->works.lps_leave_work);
 606         }
 607 }
 608
 609 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
 610                              struct ieee80211_rx_status rx_status)
 611 {
 612         struct rtl_priv *rtlpriv = rtl_priv(hw);
 613         struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
 614         __le16 fc = rtl_get_fc(skb);
 615         bool unicast = false;
 616         struct sk_buff *uskb = NULL;
 617         u8 *pdata;
 618
 619
 620         memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 621
 622         if (is_broadcast_ether_addr(hdr->addr1)) {
 623                 ;/*TODO*/
 624         } else if (is_multicast_ether_addr(hdr->addr1)) {
 625                 ;/*TODO*/
 626         } else {
 627                 unicast = true;
 628                 rtlpriv->stats.rxbytesunicast += skb->len;
 629         }
 630
 631         rtl_is_special_data(hw, skb, false);
 632
 633         if (ieee80211_is_data(fc)) {
 634                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
 635
 636                 if (unicast)
 637                         rtlpriv->link_info.num_rx_inperiod++;
 638         }
 639
 640         /* for sw lps */
 641         rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
 642         rtl_recognize_peer(hw, (void *)skb->data, skb->len);
 643         if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
 644             (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
 645              (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
 646                 return;
 647
 648         if (unlikely(!rtl_action_proc(hw, skb, false)))
 649                 return;
 650
 651         uskb = dev_alloc_skb(skb->len + 128);
 652         if (!uskb)
 653                 return;         /* exit if allocation failed */
 654         memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
 655         pdata = (u8 *)skb_put(uskb, skb->len);
 656         memcpy(pdata, skb->data, skb->len);
 657
 658         ieee80211_rx_irqsafe(hw, uskb);
 659 }
 660
 661 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
 662 {
 663         struct rtl_priv *rtlpriv = rtl_priv(hw);
 664         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 665         int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
 666
 667         struct ieee80211_rx_status rx_status = { 0 };
 668         unsigned int count = rtlpci->rxringcount;
 669         u8 own;
 670         u8 tmp_one;
 671         u32 bufferaddress;
 672
 673         struct rtl_stats stats = {
 674                 .signal = 0,
 675                 .noise = -98,
 676                 .rate = 0,
 677         };
 678         int index = rtlpci->rx_ring[rx_queue_idx].idx;
 679
 680         /*RX NORMAL PKT */
 681         while (count--) {
 682                 /*rx descriptor */
 683                 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
 684                                 index];
 685                 /*rx pkt */
 686                 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
 687                                 index];
 688                 struct sk_buff *new_skb = NULL;
 689
 690                 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
 691                                                        false, HW_DESC_OWN);
 692
 693                 /*wait data to be filled by hardware */
 694                 if (own)
 695                         break;
 696
 697                 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
 698                                                  &rx_status,
 699                                                  (u8 *) pdesc, skb);
 700
 701                 if (stats.crc || stats.hwerror)
 702                         goto done;
 703
 704                 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
 705                 if (unlikely(!new_skb)) {
 706                         RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
 707                                  "can't alloc skb for rx\n");
 708                         goto done;
 709                 }
 710
 711                 pci_unmap_single(rtlpci->pdev,
 712                                  *((dma_addr_t *) skb->cb),
 713                                  rtlpci->rxbuffersize,
 714                                  PCI_DMA_FROMDEVICE);
 715
 716                 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
 717                         HW_DESC_RXPKT_LEN));
 718                 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
 719
 720                 /*
 721                  * NOTICE This can not be use for mac80211,
 722                  * this is done in mac80211 code,
 723                  * if you done here sec DHCP will fail
 724                  * skb_trim(skb, skb->len - 4);
 725                  */
 726
 727                 _rtl_receive_one(hw, skb, rx_status);
 728
 729                 if (((rtlpriv->link_info.num_rx_inperiod +
 730                         rtlpriv->link_info.num_tx_inperiod) > 8) ||
 731                         (rtlpriv->link_info.num_rx_inperiod > 2)) {
 732                         schedule_work(&rtlpriv->works.lps_leave_work);
 733                 }
 734
 735                 dev_kfree_skb_any(skb);
 736                 skb = new_skb;
 737
 738                 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
 739                 *((dma_addr_t *) skb->cb) =
 740                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
 741                                            rtlpci->rxbuffersize,
 742                                            PCI_DMA_FROMDEVICE);
 743
 744 done:
 745                 bufferaddress = (*((dma_addr_t *)skb->cb));
 746                 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
 747                         return;
 748                 tmp_one = 1;
 749                 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
 750                                             HW_DESC_RXBUFF_ADDR,
 751                                             (u8 *)&bufferaddress);
 752                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 753                                             HW_DESC_RXPKT_LEN,
 754                                             (u8 *)&rtlpci->rxbuffersize);
 755
 756                 if (index == rtlpci->rxringcount - 1)
 757                         rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 758                                                     HW_DESC_RXERO,
 759                                                     &tmp_one);
 760
 761                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
 762                                             &tmp_one);
 763
 764                 index = (index + 1) % rtlpci->rxringcount;
 765         }
 766
 767         rtlpci->rx_ring[rx_queue_idx].idx = index;
 768 }
 769
 770 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
 771 {
 772         struct ieee80211_hw *hw = dev_id;
 773         struct rtl_priv *rtlpriv = rtl_priv(hw);
 774         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 775         unsigned long flags;
 776         u32 inta = 0;
 777         u32 intb = 0;
 778         irqreturn_t ret = IRQ_HANDLED;
 779
 780         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
 781
 782         /*read ISR: 4/8bytes */
 783         rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
 784
 785         /*Shared IRQ or HW disappared */
 786         if (!inta || inta == 0xffff) {
 787                 ret = IRQ_NONE;
 788                 goto done;
 789         }
 790
 791         /*<1> beacon related */
 792         if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
 793                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 794                          "beacon ok interrupt!\n");
 795         }
 796
 797         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
 798                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 799                          "beacon err interrupt!\n");
 800         }
 801
 802         if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
 803                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
 804         }
 805
 806         if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
 807                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 808                          "prepare beacon for interrupt!\n");
 809                 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
 810         }
 811
 812         /*<3> Tx related */
 813         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
 814                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
 815
 816         if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
 817                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 818                          "Manage ok interrupt!\n");
 819                 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
 820         }
 821
 822         if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
 823                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 824                          "HIGH_QUEUE ok interrupt!\n");
 825                 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
 826         }
 827
 828         if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
 829                 rtlpriv->link_info.num_tx_inperiod++;
 830
 831                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 832                          "BK Tx OK interrupt!\n");
 833                 _rtl_pci_tx_isr(hw, BK_QUEUE);
 834         }
 835
 836         if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
 837                 rtlpriv->link_info.num_tx_inperiod++;
 838
 839                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 840                          "BE TX OK interrupt!\n");
 841                 _rtl_pci_tx_isr(hw, BE_QUEUE);
 842         }
 843
 844         if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
 845                 rtlpriv->link_info.num_tx_inperiod++;
 846
 847                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 848                          "VI TX OK interrupt!\n");
 849                 _rtl_pci_tx_isr(hw, VI_QUEUE);
 850         }
 851
 852         if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
 853                 rtlpriv->link_info.num_tx_inperiod++;
 854
 855                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 856                          "Vo TX OK interrupt!\n");
 857                 _rtl_pci_tx_isr(hw, VO_QUEUE);
 858         }
 859
 860         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
 861                 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
 862                         rtlpriv->link_info.num_tx_inperiod++;
 863
 864                         RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 865                                  "CMD TX OK interrupt!\n");
 866                         _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
 867                 }
 868         }
 869
 870         /*<2> Rx related */
 871         if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
 872                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
 873                 _rtl_pci_rx_interrupt(hw);
 874         }
 875
 876         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
 877                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 878                          "rx descriptor unavailable!\n");
 879                 _rtl_pci_rx_interrupt(hw);
 880         }
 881
 882         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
 883                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
 884                 _rtl_pci_rx_interrupt(hw);
 885         }
 886
 887         if (rtlpriv->rtlhal.earlymode_enable)
 888                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 889
 890 done:
 891         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 892         return ret;
 893 }
 894
 895 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
 896 {
 897         _rtl_pci_tx_chk_waitq(hw);
 898 }
 899
 900 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
 901 {
 902         struct rtl_priv *rtlpriv = rtl_priv(hw);
 903         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 904         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 905         struct rtl8192_tx_ring *ring = NULL;
 906         struct ieee80211_hdr *hdr = NULL;
 907         struct ieee80211_tx_info *info = NULL;
 908         struct sk_buff *pskb = NULL;
 909         struct rtl_tx_desc *pdesc = NULL;
 910         struct rtl_tcb_desc tcb_desc;
 911         u8 temp_one = 1;
 912
 913         memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
 914         ring = &rtlpci->tx_ring[BEACON_QUEUE];
 915         pskb = __skb_dequeue(&ring->queue);
 916         if (pskb) {
 917                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
 918                 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
 919                                  (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
 920                                  pskb->len, PCI_DMA_TODEVICE);
 921                 kfree_skb(pskb);
 922         }
 923
 924         /*NB: the beacon data buffer must be 32-bit aligned. */
 925         pskb = ieee80211_beacon_get(hw, mac->vif);
 926         if (pskb == NULL)
 927                 return;
 928         hdr = rtl_get_hdr(pskb);
 929         info = IEEE80211_SKB_CB(pskb);
 930         pdesc = &ring->desc[0];
 931         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
 932                 info, NULL, pskb, BEACON_QUEUE, &tcb_desc);
 933
 934         __skb_queue_tail(&ring->queue, pskb);
 935
 936         rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
 937                                     &temp_one);
 938
 939         return;
 940 }
 941
 942 static void rtl_lps_leave_work_callback(struct work_struct *work)
 943 {
 944         struct rtl_works *rtlworks =
 945             container_of(work, struct rtl_works, lps_leave_work);
 946         struct ieee80211_hw *hw = rtlworks->hw;
 947
 948         rtl_lps_leave(hw);
 949 }
 950
 951 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
 952 {
 953         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 954         u8 i;
 955
 956         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
 957                 rtlpci->txringcount[i] = RT_TXDESC_NUM;
 958
 959         /*
 960          *we just alloc 2 desc for beacon queue,
 961          *because we just need first desc in hw beacon.
 962          */
 963         rtlpci->txringcount[BEACON_QUEUE] = 2;
 964
 965         /*
 966          *BE queue need more descriptor for performance
 967          *consideration or, No more tx desc will happen,
 968          *and may cause mac80211 mem leakage.
 969          */
 970         rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
 971
 972         rtlpci->rxbuffersize = 9100;    /*2048/1024; */
 973         rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;     /*64; */
 974 }
 975
 976 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
 977                 struct pci_dev *pdev)
 978 {
 979         struct rtl_priv *rtlpriv = rtl_priv(hw);
 980         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 981         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 982         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 983
 984         rtlpci->up_first_time = true;
 985         rtlpci->being_init_adapter = false;
 986
 987         rtlhal->hw = hw;
 988         rtlpci->pdev = pdev;
 989
 990         /*Tx/Rx related var */
 991         _rtl_pci_init_trx_var(hw);
 992
 993         /*IBSS*/ mac->beacon_interval = 100;
 994
 995         /*AMPDU*/
 996         mac->min_space_cfg = 0;
 997         mac->max_mss_density = 0;
 998         /*set sane AMPDU defaults */
 999         mac->current_ampdu_density = 7;
1000         mac->current_ampdu_factor = 3;
1001
1002         /*QOS*/
1003         rtlpci->acm_method = eAcmWay2_SW;
1004
1005         /*task */
1006         tasklet_init(&rtlpriv->works.irq_tasklet,
1007                      (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1008                      (unsigned long)hw);
1009         tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1010                      (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1011                      (unsigned long)hw);
1012         INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
1013 }
1014
1015 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1016                                  unsigned int prio, unsigned int entries)
1017 {
1018         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1019         struct rtl_priv *rtlpriv = rtl_priv(hw);
1020         struct rtl_tx_desc *ring;
1021         dma_addr_t dma;
1022         u32 nextdescaddress;
1023         int i;
1024
1025         ring = pci_alloc_consistent(rtlpci->pdev,
1026                                     sizeof(*ring) * entries, &dma);
1027
1028         if (!ring || (unsigned long)ring & 0xFF) {
1029                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1030                          "Cannot allocate TX ring (prio = %d)\n", prio);
1031                 return -ENOMEM;
1032         }
1033
1034         memset(ring, 0, sizeof(*ring) * entries);
1035         rtlpci->tx_ring[prio].desc = ring;
1036         rtlpci->tx_ring[prio].dma = dma;
1037         rtlpci->tx_ring[prio].idx = 0;
1038         rtlpci->tx_ring[prio].entries = entries;
1039         skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1040
1041         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1042                  prio, ring);
1043
1044         for (i = 0; i < entries; i++) {
1045                 nextdescaddress = (u32) dma +
1046                                               ((i + 1) % entries) *
1047                                               sizeof(*ring);
1048
1049                 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1050                                             true, HW_DESC_TX_NEXTDESC_ADDR,
1051                                             (u8 *)&nextdescaddress);
1052         }
1053
1054         return 0;
1055 }
1056
1057 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1058 {
1059         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1060         struct rtl_priv *rtlpriv = rtl_priv(hw);
1061         struct rtl_rx_desc *entry = NULL;
1062         int i, rx_queue_idx;
1063         u8 tmp_one = 1;
1064
1065         /*
1066          *rx_queue_idx 0:RX_MPDU_QUEUE
1067          *rx_queue_idx 1:RX_CMD_QUEUE
1068          */
1069         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1070              rx_queue_idx++) {
1071                 rtlpci->rx_ring[rx_queue_idx].desc =
1072                     pci_alloc_consistent(rtlpci->pdev,
1073                                          sizeof(*rtlpci->rx_ring[rx_queue_idx].
1074                                                 desc) * rtlpci->rxringcount,
1075                                          &rtlpci->rx_ring[rx_queue_idx].dma);
1076
1077                 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1078                     (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1079                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1080                                  "Cannot allocate RX ring\n");
1081                         return -ENOMEM;
1082                 }
1083
1084                 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1085                        sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1086                        rtlpci->rxringcount);
1087
1088                 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1089
1090                 /* If amsdu_8k is disabled, set buffersize to 4096. This
1091                  * change will reduce memory fragmentation.
1092                  */
1093                 if (rtlpci->rxbuffersize > 4096 &&
1094                     rtlpriv->rtlhal.disable_amsdu_8k)
1095                         rtlpci->rxbuffersize = 4096;
1096
1097                 for (i = 0; i < rtlpci->rxringcount; i++) {
1098                         struct sk_buff *skb =
1099                             dev_alloc_skb(rtlpci->rxbuffersize);
1100                         u32 bufferaddress;
1101                         if (!skb)
1102                                 return 0;
1103                         kmemleak_not_leak(skb);
1104                         entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1105
1106                         /*skb->dev = dev; */
1107
1108                         rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1109
1110                         /*
1111                          *just set skb->cb to mapping addr
1112                          *for pci_unmap_single use
1113                          */
1114                         *((dma_addr_t *) skb->cb) =
1115                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1116                                            rtlpci->rxbuffersize,
1117                                            PCI_DMA_FROMDEVICE);
1118
1119                         bufferaddress = (*((dma_addr_t *)skb->cb));
1120                         if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) {
1121                                 dev_kfree_skb_any(skb);
1122                                 return 1;
1123                         }
1124                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1125                                                     HW_DESC_RXBUFF_ADDR,
1126                                                     (u8 *)&bufferaddress);
1127                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1128                                                     HW_DESC_RXPKT_LEN,
1129                                                     (u8 *)&rtlpci->
1130                                                     rxbuffersize);
1131                         rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1132                                                     HW_DESC_RXOWN,
1133                                                     &tmp_one);
1134                 }
1135
1136                 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1137                                             HW_DESC_RXERO, &tmp_one);
1138         }
1139         return 0;
1140 }
1141
1142 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1143                 unsigned int prio)
1144 {
1145         struct rtl_priv *rtlpriv = rtl_priv(hw);
1146         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1147         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1148
1149         while (skb_queue_len(&ring->queue)) {
1150                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1151                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1152
1153                 pci_unmap_single(rtlpci->pdev,
1154                                  rtlpriv->cfg->
1155                                              ops->get_desc((u8 *) entry, true,
1156                                                    HW_DESC_TXBUFF_ADDR),
1157                                  skb->len, PCI_DMA_TODEVICE);
1158                 kfree_skb(skb);
1159                 ring->idx = (ring->idx + 1) % ring->entries;
1160         }
1161
1162         if (ring->desc) {
1163                 pci_free_consistent(rtlpci->pdev,
1164                                     sizeof(*ring->desc) * ring->entries,
1165                                     ring->desc, ring->dma);
1166                 ring->desc = NULL;
1167         }
1168 }
1169
1170 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1171 {
1172         int i, rx_queue_idx;
1173
1174         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1175         /*rx_queue_idx 1:RX_CMD_QUEUE */
1176         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1177              rx_queue_idx++) {
1178                 for (i = 0; i < rtlpci->rxringcount; i++) {
1179                         struct sk_buff *skb =
1180                             rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1181                         if (!skb)
1182                                 continue;
1183
1184                         pci_unmap_single(rtlpci->pdev,
1185                                          *((dma_addr_t *) skb->cb),
1186                                          rtlpci->rxbuffersize,
1187                                          PCI_DMA_FROMDEVICE);
1188                         kfree_skb(skb);
1189                 }
1190
1191                 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1192                         pci_free_consistent(rtlpci->pdev,
1193                                     sizeof(*rtlpci->rx_ring[rx_queue_idx].
1194                                            desc) * rtlpci->rxringcount,
1195                                     rtlpci->rx_ring[rx_queue_idx].desc,
1196                                     rtlpci->rx_ring[rx_queue_idx].dma);
1197                         rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1198                 }
1199         }
1200 }
1201
1202 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1203 {
1204         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1205         int ret;
1206         int i;
1207
1208         ret = _rtl_pci_init_rx_ring(hw);
1209         if (ret)
1210                 return ret;
1211
1212         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1213                 ret = _rtl_pci_init_tx_ring(hw, i,
1214                                  rtlpci->txringcount[i]);
1215                 if (ret)
1216                         goto err_free_rings;
1217         }
1218
1219         return 0;
1220
1221 err_free_rings:
1222         _rtl_pci_free_rx_ring(rtlpci);
1223
1224         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1225                 if (rtlpci->tx_ring[i].desc)
1226                         _rtl_pci_free_tx_ring(hw, i);
1227
1228         return 1;
1229 }
1230
1231 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1232 {
1233         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1234         u32 i;
1235
1236         /*free rx rings */
1237         _rtl_pci_free_rx_ring(rtlpci);
1238
1239         /*free tx rings */
1240         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1241                 _rtl_pci_free_tx_ring(hw, i);
1242
1243         return 0;
1244 }
1245
1246 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1247 {
1248         struct rtl_priv *rtlpriv = rtl_priv(hw);
1249         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1250         int i, rx_queue_idx;
1251         unsigned long flags;
1252         u8 tmp_one = 1;
1253
1254         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1255         /*rx_queue_idx 1:RX_CMD_QUEUE */
1256         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1257              rx_queue_idx++) {
1258                 /*
1259                  *force the rx_ring[RX_MPDU_QUEUE/
1260                  *RX_CMD_QUEUE].idx to the first one
1261                  */
1262                 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1263                         struct rtl_rx_desc *entry = NULL;
1264
1265                         for (i = 0; i < rtlpci->rxringcount; i++) {
1266                                 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1267                                 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1268                                                             false,
1269                                                             HW_DESC_RXOWN,
1270                                                             &tmp_one);
1271                         }
1272                         rtlpci->rx_ring[rx_queue_idx].idx = 0;
1273                 }
1274         }
1275
1276         /*
1277          *after reset, release previous pending packet,
1278          *and force the  tx idx to the first one
1279          */
1280         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1281                 if (rtlpci->tx_ring[i].desc) {
1282                         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1283
1284                         while (skb_queue_len(&ring->queue)) {
1285                                 struct rtl_tx_desc *entry;
1286                                 struct sk_buff *skb;
1287
1288                                 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1289                                                   flags);
1290                                 entry = &ring->desc[ring->idx];
1291                                 skb = __skb_dequeue(&ring->queue);
1292                                 pci_unmap_single(rtlpci->pdev,
1293                                                  rtlpriv->cfg->ops->
1294                                                          get_desc((u8 *)
1295                                                          entry,
1296                                                          true,
1297                                                          HW_DESC_TXBUFF_ADDR),
1298                                                  skb->len, PCI_DMA_TODEVICE);
1299                                 ring->idx = (ring->idx + 1) % ring->entries;
1300                                 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1301                                                   flags);
1302                                 kfree_skb(skb);
1303                         }
1304                         ring->idx = 0;
1305                 }
1306         }
1307
1308         return 0;
1309 }
1310
1311 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1312                                         struct ieee80211_sta *sta,
1313                                         struct sk_buff *skb)
1314 {
1315         struct rtl_priv *rtlpriv = rtl_priv(hw);
1316         struct rtl_sta_info *sta_entry = NULL;
1317         u8 tid = rtl_get_tid(skb);
1318         __le16 fc = rtl_get_fc(skb);
1319
1320         if (!sta)
1321                 return false;
1322         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1323
1324         if (!rtlpriv->rtlhal.earlymode_enable)
1325                 return false;
1326         if (ieee80211_is_nullfunc(fc))
1327                 return false;
1328         if (ieee80211_is_qos_nullfunc(fc))
1329                 return false;
1330         if (ieee80211_is_pspoll(fc))
1331                 return false;
1332         if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1333                 return false;
1334         if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1335                 return false;
1336         if (tid > 7)
1337                 return false;
1338
1339         /* maybe every tid should be checked */
1340         if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1341                 return false;
1342
1343         spin_lock_bh(&rtlpriv->locks.waitq_lock);
1344         skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1345         spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1346
1347         return true;
1348 }
1349
1350 static int rtl_pci_tx(struct ieee80211_hw *hw,
1351                       struct ieee80211_sta *sta,
1352                       struct sk_buff *skb,
1353                       struct rtl_tcb_desc *ptcb_desc)
1354 {
1355         struct rtl_priv *rtlpriv = rtl_priv(hw);
1356         struct rtl_sta_info *sta_entry = NULL;
1357         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1358         struct rtl8192_tx_ring *ring;
1359         struct rtl_tx_desc *pdesc;
1360         u8 idx;
1361         u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1362         unsigned long flags;
1363         struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1364         __le16 fc = rtl_get_fc(skb);
1365         u8 *pda_addr = hdr->addr1;
1366         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1367         /*ssn */
1368         u8 tid = 0;
1369         u16 seq_number = 0;
1370         u8 own;
1371         u8 temp_one = 1;
1372
1373         if (ieee80211_is_mgmt(fc))
1374                 rtl_tx_mgmt_proc(hw, skb);
1375
1376         if (rtlpriv->psc.sw_ps_enabled) {
1377                 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1378                         !ieee80211_has_pm(fc))
1379                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1380         }
1381
1382         rtl_action_proc(hw, skb, true);
1383
1384         if (is_multicast_ether_addr(pda_addr))
1385                 rtlpriv->stats.txbytesmulticast += skb->len;
1386         else if (is_broadcast_ether_addr(pda_addr))
1387                 rtlpriv->stats.txbytesbroadcast += skb->len;
1388         else
1389                 rtlpriv->stats.txbytesunicast += skb->len;
1390
1391         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1392         ring = &rtlpci->tx_ring[hw_queue];
1393         if (hw_queue != BEACON_QUEUE)
1394                 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1395                                 ring->entries;
1396         else
1397                 idx = 0;
1398
1399         pdesc = &ring->desc[idx];
1400         own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1401                         true, HW_DESC_OWN);
1402
1403         if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1404                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1405                          "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1406                          hw_queue, ring->idx, idx,
1407                          skb_queue_len(&ring->queue));
1408
1409                 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1410                 return skb->len;
1411         }
1412
1413         if (ieee80211_is_data_qos(fc)) {
1414                 tid = rtl_get_tid(skb);
1415                 if (sta) {
1416                         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1417                         seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1418                                       IEEE80211_SCTL_SEQ) >> 4;
1419                         seq_number += 1;
1420
1421                         if (!ieee80211_has_morefrags(hdr->frame_control))
1422                                 sta_entry->tids[tid].seq_number = seq_number;
1423                 }
1424         }
1425
1426         if (ieee80211_is_data(fc))
1427                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1428
1429         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1430                         info, sta, skb, hw_queue, ptcb_desc);
1431
1432         __skb_queue_tail(&ring->queue, skb);
1433
1434         rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1435                                     HW_DESC_OWN, &temp_one);
1436
1437
1438         if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1439             hw_queue != BEACON_QUEUE) {
1440
1441                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1442                          "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1443                          hw_queue, ring->idx, idx,
1444                          skb_queue_len(&ring->queue));
1445
1446                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1447         }
1448
1449         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1450
1451         rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1452
1453         return 0;
1454 }
1455
1456 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1457 {
1458         struct rtl_priv *rtlpriv = rtl_priv(hw);
1459         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1460         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1461         u16 i = 0;
1462         int queue_id;
1463         struct rtl8192_tx_ring *ring;
1464
1465         for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1466                 u32 queue_len;
1467                 ring = &pcipriv->dev.tx_ring[queue_id];
1468                 queue_len = skb_queue_len(&ring->queue);
1469                 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1470                         queue_id == TXCMD_QUEUE) {
1471                         queue_id--;
1472                         continue;
1473                 } else {
1474                         msleep(20);
1475                         i++;
1476                 }
1477
1478                 /* we just wait 1s for all queues */
1479                 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1480                         is_hal_stop(rtlhal) || i >= 200)
1481                         return;
1482         }
1483 }
1484
1485 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1486 {
1487         struct rtl_priv *rtlpriv = rtl_priv(hw);
1488         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1489
1490         _rtl_pci_deinit_trx_ring(hw);
1491
1492         synchronize_irq(rtlpci->pdev->irq);
1493         tasklet_kill(&rtlpriv->works.irq_tasklet);
1494         cancel_work_sync(&rtlpriv->works.lps_leave_work);
1495
1496         flush_workqueue(rtlpriv->works.rtl_wq);
1497         destroy_workqueue(rtlpriv->works.rtl_wq);
1498
1499 }
1500
1501 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1502 {
1503         struct rtl_priv *rtlpriv = rtl_priv(hw);
1504         int err;
1505
1506         _rtl_pci_init_struct(hw, pdev);
1507
1508         err = _rtl_pci_init_trx_ring(hw);
1509         if (err) {
1510                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1511                          "tx ring initialization failed\n");
1512                 return err;
1513         }
1514
1515         return 0;
1516 }
1517
1518 static int rtl_pci_start(struct ieee80211_hw *hw)
1519 {
1520         struct rtl_priv *rtlpriv = rtl_priv(hw);
1521         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1522         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1523         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1524
1525         int err;
1526
1527         rtl_pci_reset_trx_ring(hw);
1528
1529         rtlpci->driver_is_goingto_unload = false;
1530         err = rtlpriv->cfg->ops->hw_init(hw);
1531         if (err) {
1532                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1533                          "Failed to config hardware!\n");
1534                 return err;
1535         }
1536
1537         rtlpriv->cfg->ops->enable_interrupt(hw);
1538         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1539
1540         rtl_init_rx_config(hw);
1541
1542         /*should be after adapter start and interrupt enable. */
1543         set_hal_start(rtlhal);
1544
1545         RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1546
1547         rtlpci->up_first_time = false;
1548
1549         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1550         return 0;
1551 }
1552
1553 static void rtl_pci_stop(struct ieee80211_hw *hw)
1554 {
1555         struct rtl_priv *rtlpriv = rtl_priv(hw);
1556         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1557         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1558         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1559         unsigned long flags;
1560         u8 RFInProgressTimeOut = 0;
1561
1562         /*
1563          *should be before disable interrupt&adapter
1564          *and will do it immediately.
1565          */
1566         set_hal_stop(rtlhal);
1567
1568         rtlpriv->cfg->ops->disable_interrupt(hw);
1569         cancel_work_sync(&rtlpriv->works.lps_leave_work);
1570
1571         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1572         while (ppsc->rfchange_inprogress) {
1573                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1574                 if (RFInProgressTimeOut > 100) {
1575                         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1576                         break;
1577                 }
1578                 mdelay(1);
1579                 RFInProgressTimeOut++;
1580                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1581         }
1582         ppsc->rfchange_inprogress = true;
1583         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1584
1585         rtlpci->driver_is_goingto_unload = true;
1586         rtlpriv->cfg->ops->hw_disable(hw);
1587         /* some things are not needed if firmware not available */
1588         if (!rtlpriv->max_fw_size)
1589                 return;
1590         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1591
1592         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1593         ppsc->rfchange_inprogress = false;
1594         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1595
1596         rtl_pci_enable_aspm(hw);
1597 }
1598
1599 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1600                 struct ieee80211_hw *hw)
1601 {
1602         struct rtl_priv *rtlpriv = rtl_priv(hw);
1603         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1604         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1605         struct pci_dev *bridge_pdev = pdev->bus->self;
1606         u16 venderid;
1607         u16 deviceid;
1608         u8 revisionid;
1609         u16 irqline;
1610         u8 tmp;
1611
1612         pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1613         venderid = pdev->vendor;
1614         deviceid = pdev->device;
1615         pci_read_config_byte(pdev, 0x8, &revisionid);
1616         pci_read_config_word(pdev, 0x3C, &irqline);
1617
1618         /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1619          * r8192e_pci, and RTL8192SE, which uses this driver. If the
1620          * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1621          * the correct driver is r8192e_pci, thus this routine should
1622          * return false.
1623          */
1624         if (deviceid == RTL_PCI_8192SE_DID &&
1625             revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1626                 return false;
1627
1628         if (deviceid == RTL_PCI_8192_DID ||
1629             deviceid == RTL_PCI_0044_DID ||
1630             deviceid == RTL_PCI_0047_DID ||
1631             deviceid == RTL_PCI_8192SE_DID ||
1632             deviceid == RTL_PCI_8174_DID ||
1633             deviceid == RTL_PCI_8173_DID ||
1634             deviceid == RTL_PCI_8172_DID ||
1635             deviceid == RTL_PCI_8171_DID) {
1636                 switch (revisionid) {
1637                 case RTL_PCI_REVISION_ID_8192PCIE:
1638                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1639                                  "8192 PCI-E is found - vid/did=%x/%x\n",
1640                                  venderid, deviceid);
1641                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1642                         return false;
1643                 case RTL_PCI_REVISION_ID_8192SE:
1644                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1645                                  "8192SE is found - vid/did=%x/%x\n",
1646                                  venderid, deviceid);
1647                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1648                         break;
1649                 default:
1650                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1651                                  "Err: Unknown device - vid/did=%x/%x\n",
1652                                  venderid, deviceid);
1653                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1654                         break;
1655
1656                 }
1657         } else if (deviceid == RTL_PCI_8723AE_DID) {
1658                 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1659                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1660                          "8723AE PCI-E is found - "
1661                          "vid/did=%x/%x\n", venderid, deviceid);
1662         } else if (deviceid == RTL_PCI_8192CET_DID ||
1663                    deviceid == RTL_PCI_8192CE_DID ||
1664                    deviceid == RTL_PCI_8191CE_DID ||
1665                    deviceid == RTL_PCI_8188CE_DID) {
1666                 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1667                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1668                          "8192C PCI-E is found - vid/did=%x/%x\n",
1669                          venderid, deviceid);
1670         } else if (deviceid == RTL_PCI_8192DE_DID ||
1671                    deviceid == RTL_PCI_8192DE_DID2) {
1672                 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1673                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1674                          "8192D PCI-E is found - vid/did=%x/%x\n",
1675                          venderid, deviceid);
1676         } else {
1677                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1678                          "Err: Unknown device - vid/did=%x/%x\n",
1679                          venderid, deviceid);
1680
1681                 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1682         }
1683
1684         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1685                 if (revisionid == 0 || revisionid == 1) {
1686                         if (revisionid == 0) {
1687                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1688                                          "Find 92DE MAC0\n");
1689                                 rtlhal->interfaceindex = 0;
1690                         } else if (revisionid == 1) {
1691                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1692                                          "Find 92DE MAC1\n");
1693                                 rtlhal->interfaceindex = 1;
1694                         }
1695                 } else {
1696                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1697                                  "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1698                                  venderid, deviceid, revisionid);
1699                         rtlhal->interfaceindex = 0;
1700                 }
1701         }
1702         /*find bus info */
1703         pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1704         pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1705         pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1706
1707         if (bridge_pdev) {
1708                 /*find bridge info if available */
1709                 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1710                 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1711                         if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1712                                 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1713                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1714                                          "Pci Bridge Vendor is found index: %d\n",
1715                                          tmp);
1716                                 break;
1717                         }
1718                 }
1719         }
1720
1721         if (pcipriv->ndis_adapter.pcibridge_vendor !=
1722                 PCI_BRIDGE_VENDOR_UNKNOWN) {
1723                 pcipriv->ndis_adapter.pcibridge_busnum =
1724                     bridge_pdev->bus->number;
1725                 pcipriv->ndis_adapter.pcibridge_devnum =
1726                     PCI_SLOT(bridge_pdev->devfn);
1727                 pcipriv->ndis_adapter.pcibridge_funcnum =
1728                     PCI_FUNC(bridge_pdev->devfn);
1729                 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1730                     pci_pcie_cap(bridge_pdev);
1731                 pcipriv->ndis_adapter.num4bytes =
1732                     (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1733
1734                 rtl_pci_get_linkcontrol_field(hw);
1735
1736                 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1737                     PCI_BRIDGE_VENDOR_AMD) {
1738                         pcipriv->ndis_adapter.amd_l1_patch =
1739                             rtl_pci_get_amd_l1_patch(hw);
1740                 }
1741         }
1742
1743         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1744                  "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1745                  pcipriv->ndis_adapter.busnumber,
1746                  pcipriv->ndis_adapter.devnumber,
1747                  pcipriv->ndis_adapter.funcnumber,
1748                  pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1749
1750         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1751                  "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1752                  pcipriv->ndis_adapter.pcibridge_busnum,
1753                  pcipriv->ndis_adapter.pcibridge_devnum,
1754                  pcipriv->ndis_adapter.pcibridge_funcnum,
1755                  pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1756                  pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1757                  pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1758                  pcipriv->ndis_adapter.amd_l1_patch);
1759
1760         rtl_pci_parse_configuration(pdev, hw);
1761
1762         return true;
1763 }
1764
1765 int rtl_pci_probe(struct pci_dev *pdev,
1766                             const struct pci_device_id *id)
1767 {
1768         struct ieee80211_hw *hw = NULL;
1769
1770         struct rtl_priv *rtlpriv = NULL;
1771         struct rtl_pci_priv *pcipriv = NULL;
1772         struct rtl_pci *rtlpci;
1773         unsigned long pmem_start, pmem_len, pmem_flags;
1774         int err;
1775
1776         err = pci_enable_device(pdev);
1777         if (err) {
1778                 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1779                           pci_name(pdev));
1780                 return err;
1781         }
1782
1783         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1784                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1785                         RT_ASSERT(false,
1786                                   "Unable to obtain 32bit DMA for consistent allocations\n");
1787                         err = -ENOMEM;
1788                         goto fail1;
1789                 }
1790         }
1791
1792         pci_set_master(pdev);
1793
1794         hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1795                                 sizeof(struct rtl_priv), &rtl_ops);
1796         if (!hw) {
1797                 RT_ASSERT(false,
1798                           "%s : ieee80211 alloc failed\n", pci_name(pdev));
1799                 err = -ENOMEM;
1800                 goto fail1;
1801         }
1802
1803         SET_IEEE80211_DEV(hw, &pdev->dev);
1804         pci_set_drvdata(pdev, hw);
1805
1806         rtlpriv = hw->priv;
1807         pcipriv = (void *)rtlpriv->priv;
1808         pcipriv->dev.pdev = pdev;
1809         init_completion(&rtlpriv->firmware_loading_complete);
1810
1811         /* init cfg & intf_ops */
1812         rtlpriv->rtlhal.interface = INTF_PCI;
1813         rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1814         rtlpriv->intf_ops = &rtl_pci_ops;
1815
1816         /*
1817          *init dbgp flags before all
1818          *other functions, because we will
1819          *use it in other funtions like
1820          *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1821          *you can not use these macro
1822          *before this
1823          */
1824         rtl_dbgp_flag_init(hw);
1825
1826         /* MEM map */
1827         err = pci_request_regions(pdev, KBUILD_MODNAME);
1828         if (err) {
1829                 RT_ASSERT(false, "Can't obtain PCI resources\n");
1830                 goto fail1;
1831         }
1832
1833         pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1834         pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1835         pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1836
1837         /*shared mem start */
1838         rtlpriv->io.pci_mem_start =
1839                         (unsigned long)pci_iomap(pdev,
1840                         rtlpriv->cfg->bar_id, pmem_len);
1841         if (rtlpriv->io.pci_mem_start == 0) {
1842                 RT_ASSERT(false, "Can't map PCI mem\n");
1843                 err = -ENOMEM;
1844                 goto fail2;
1845         }
1846
1847         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1848                  "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1849                  pmem_start, pmem_len, pmem_flags,
1850                  rtlpriv->io.pci_mem_start);
1851
1852         /* Disable Clk Request */
1853         pci_write_config_byte(pdev, 0x81, 0);
1854         /* leave D3 mode */
1855         pci_write_config_byte(pdev, 0x44, 0);
1856         pci_write_config_byte(pdev, 0x04, 0x06);
1857         pci_write_config_byte(pdev, 0x04, 0x07);
1858
1859         /* find adapter */
1860         if (!_rtl_pci_find_adapter(pdev, hw)) {
1861                 err = -ENODEV;
1862                 goto fail3;
1863         }
1864
1865         /* Init IO handler */
1866         _rtl_pci_io_handler_init(&pdev->dev, hw);
1867
1868         /*like read eeprom and so on */
1869         rtlpriv->cfg->ops->read_eeprom_info(hw);
1870
1871         /*aspm */
1872         rtl_pci_init_aspm(hw);
1873
1874         /* Init mac80211 sw */
1875         err = rtl_init_core(hw);
1876         if (err) {
1877                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1878                          "Can't allocate sw for mac80211\n");
1879                 goto fail3;
1880         }
1881
1882         /* Init PCI sw */
1883         err = rtl_pci_init(hw, pdev);
1884         if (err) {
1885                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
1886                 goto fail3;
1887         }
1888
1889         if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1890                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1891                 err = -ENODEV;
1892                 goto fail3;
1893         }
1894
1895         rtlpriv->cfg->ops->init_sw_leds(hw);
1896
1897         err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1898         if (err) {
1899                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1900                          "failed to create sysfs device attributes\n");
1901                 goto fail3;
1902         }
1903
1904         rtlpci = rtl_pcidev(pcipriv);
1905         err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1906                           IRQF_SHARED, KBUILD_MODNAME, hw);
1907         if (err) {
1908                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1909                          "%s: failed to register IRQ handler\n",
1910                          wiphy_name(hw->wiphy));
1911                 goto fail3;
1912         }
1913         rtlpci->irq_alloc = 1;
1914
1915         return 0;
1916
1917 fail3:
1918         rtl_deinit_core(hw);
1919         _rtl_pci_io_handler_release(hw);
1920
1921         if (rtlpriv->io.pci_mem_start != 0)
1922                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1923
1924 fail2:
1925         pci_release_regions(pdev);
1926         complete(&rtlpriv->firmware_loading_complete);
1927
1928 fail1:
1929         if (hw)
1930                 ieee80211_free_hw(hw);
1931         pci_set_drvdata(pdev, NULL);
1932         pci_disable_device(pdev);
1933
1934         return err;
1935
1936 }
1937 EXPORT_SYMBOL(rtl_pci_probe);
1938
1939 void rtl_pci_disconnect(struct pci_dev *pdev)
1940 {
1941         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1942         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1943         struct rtl_priv *rtlpriv = rtl_priv(hw);
1944         struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1945         struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1946
1947         /* just in case driver is removed before firmware callback */
1948         wait_for_completion(&rtlpriv->firmware_loading_complete);
1949         clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1950
1951         sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1952
1953         /*ieee80211_unregister_hw will call ops_stop */
1954         if (rtlmac->mac80211_registered == 1) {
1955                 ieee80211_unregister_hw(hw);
1956                 rtlmac->mac80211_registered = 0;
1957         } else {
1958                 rtl_deinit_deferred_work(hw);
1959                 rtlpriv->intf_ops->adapter_stop(hw);
1960         }
1961         rtlpriv->cfg->ops->disable_interrupt(hw);
1962
1963         /*deinit rfkill */
1964         rtl_deinit_rfkill(hw);
1965
1966         rtl_pci_deinit(hw);
1967         rtl_deinit_core(hw);
1968         _rtl_pci_io_handler_release(hw);
1969         rtlpriv->cfg->ops->deinit_sw_vars(hw);
1970
1971         if (rtlpci->irq_alloc) {
1972                 free_irq(rtlpci->pdev->irq, hw);
1973                 rtlpci->irq_alloc = 0;
1974         }
1975
1976         if (rtlpriv->io.pci_mem_start != 0) {
1977                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1978                 pci_release_regions(pdev);
1979         }
1980
1981         pci_disable_device(pdev);
1982
1983         rtl_pci_disable_aspm(hw);
1984
1985         pci_set_drvdata(pdev, NULL);
1986
1987         ieee80211_free_hw(hw);
1988 }
1989 EXPORT_SYMBOL(rtl_pci_disconnect);
1990
1991 #ifdef CONFIG_PM_SLEEP
1992 /***************************************
1993 kernel pci power state define:
1994 PCI_D0         ((pci_power_t __force) 0)
1995 PCI_D1         ((pci_power_t __force) 1)
1996 PCI_D2         ((pci_power_t __force) 2)
1997 PCI_D3hot      ((pci_power_t __force) 3)
1998 PCI_D3cold     ((pci_power_t __force) 4)
1999 PCI_UNKNOWN    ((pci_power_t __force) 5)
2000
2001 This function is called when system
2002 goes into suspend state mac80211 will
2003 call rtl_mac_stop() from the mac80211
2004 suspend function first, So there is
2005 no need to call hw_disable here.
2006 ****************************************/
2007 int rtl_pci_suspend(struct device *dev)
2008 {
2009         struct pci_dev *pdev = to_pci_dev(dev);
2010         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2011         struct rtl_priv *rtlpriv = rtl_priv(hw);
2012
2013         rtlpriv->cfg->ops->hw_suspend(hw);
2014         rtl_deinit_rfkill(hw);
2015
2016         return 0;
2017 }
2018 EXPORT_SYMBOL(rtl_pci_suspend);
2019
2020 int rtl_pci_resume(struct device *dev)
2021 {
2022         struct pci_dev *pdev = to_pci_dev(dev);
2023         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2024         struct rtl_priv *rtlpriv = rtl_priv(hw);
2025
2026         rtlpriv->cfg->ops->hw_resume(hw);
2027         rtl_init_rfkill(hw);
2028         return 0;
2029 }
2030 EXPORT_SYMBOL(rtl_pci_resume);
2031 #endif /* CONFIG_PM_SLEEP */
2032
2033 struct rtl_intf_ops rtl_pci_ops = {
2034         .read_efuse_byte = read_efuse_byte,
2035         .adapter_start = rtl_pci_start,
2036         .adapter_stop = rtl_pci_stop,
2037         .adapter_tx = rtl_pci_tx,
2038         .flush = rtl_pci_flush,
2039         .reset_trx_ring = rtl_pci_reset_trx_ring,
2040         .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2041
2042         .disable_aspm = rtl_pci_disable_aspm,
2043         .enable_aspm = rtl_pci_enable_aspm,
2044 };