drivers/net/wireless/rtlwifi/rtl8188ee/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL92C_DEF_H__
  31 #define __RTL92C_DEF_H__
  32
  33 #define HAL_RETRY_LIMIT_INFRA                           48
  34 #define HAL_RETRY_LIMIT_AP_ADHOC                        7
  35
  36 #define RESET_DELAY_8185                                20
  37
  38 #define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
  39 #define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
  40
  41 #define NUM_OF_FIRMWARE_QUEUE                           10
  42 #define NUM_OF_PAGES_IN_FW                              0x100
  43 #define NUM_OF_PAGE_IN_FW_QUEUE_BK                      0x07
  44 #define NUM_OF_PAGE_IN_FW_QUEUE_BE                      0x07
  45 #define NUM_OF_PAGE_IN_FW_QUEUE_VI                      0x07
  46 #define NUM_OF_PAGE_IN_FW_QUEUE_VO                      0x07
  47 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                    0x0
  48 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD                     0x0
  49 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                    0x02
  50 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                    0x02
  51 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN                     0x2
  52 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB                     0xA1
  53
  54 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                  0x026
  55 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                  0x048
  56 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                  0x048
  57 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                  0x026
  58 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                 0x00
  59
  60 #define MAX_LINES_HWCONFIG_TXT                          1000
  61 #define MAX_BYTES_LINE_HWCONFIG_TXT                     256
  62
  63 #define SW_THREE_WIRE                                   0
  64 #define HW_THREE_WIRE                                   2
  65
  66 #define BT_DEMO_BOARD                                   0
  67 #define BT_QA_BOARD                                     1
  68 #define BT_FPGA                                         2
  69
  70 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                 0
  71 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
  72 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
  73
  74 #define MAX_H2C_QUEUE_NUM                               10
  75
  76 #define RX_MPDU_QUEUE                                   0
  77 #define RX_CMD_QUEUE                                    1
  78 #define RX_MAX_QUEUE                                    2
  79 #define AC2QUEUEID(_AC)                                 (_AC)
  80
  81 #define C2H_RX_CMD_HDR_LEN                              8
  82 #define GET_C2H_CMD_CMD_LEN(__prxhdr)                   \
  83         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
  84 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)                \
  85         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
  86 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)                   \
  87         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
  88 #define GET_C2H_CMD_CONTINUE(__prxhdr)                  \
  89         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
  90 #define GET_C2H_CMD_CONTENT(__prxhdr)                   \
  91         ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
  92
  93 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
  94         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
  95 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)       \
  96         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
  97 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
  98         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
  99 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
 100         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
 101 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)     \
 102         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
 103 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 104         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 105 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)       \
 106         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 107 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)      \
 108         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 109 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)       \
 110         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 111
 112 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 113
 114
 115 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
 116  * [7] Manufacturer: TSMC=0, UMC=1
 117  * [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
 118  * [3] Chip type: TEST=0, NORMAL=1
 119  * [2:0] IC type: 81xxC=0, 8723=1, 92D=2
 120  */
 121 #define CHIP_8723                       BIT(0)
 122 #define CHIP_92D                        BIT(1)
 123 #define NORMAL_CHIP                     BIT(3)
 124 #define RF_TYPE_1T1R                    (~(BIT(4)|BIT(5)|BIT(6)))
 125 #define RF_TYPE_1T2R                    BIT(4)
 126 #define RF_TYPE_2T2R                    BIT(5)
 127 #define CHIP_VENDOR_UMC                 BIT(7)
 128 #define B_CUT_VERSION                   BIT(12)
 129 #define C_CUT_VERSION                   BIT(13)
 130 #define D_CUT_VERSION                   ((BIT(12)|BIT(13)))
 131 #define E_CUT_VERSION                   BIT(14)
 132
 133
 134 /* MASK */
 135 #define IC_TYPE_MASK                    (BIT(0)|BIT(1)|BIT(2))
 136 #define CHIP_TYPE_MASK                  BIT(3)
 137 #define RF_TYPE_MASK                    (BIT(4)|BIT(5)|BIT(6))
 138 #define MANUFACTUER_MASK                BIT(7)
 139 #define ROM_VERSION_MASK                (BIT(11)|BIT(10)|BIT(9)|BIT(8))
 140 #define CUT_VERSION_MASK                (BIT(15)|BIT(14)|BIT(13)|BIT(12))
 141
 142 /* Get element */
 143 #define GET_CVID_IC_TYPE(version)       ((version) & IC_TYPE_MASK)
 144 #define GET_CVID_CHIP_TYPE(version)     ((version) & CHIP_TYPE_MASK)
 145 #define GET_CVID_RF_TYPE(version)       ((version) & RF_TYPE_MASK)
 146 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
 147 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
 148 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
 149
 150
 151 #define IS_81XXC(version)                                               \
 152         ((GET_CVID_IC_TYPE(version) == 0) ? true : false)
 153 #define IS_8723_SERIES(version)                                         \
 154         ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false)
 155 #define IS_92D(version)                                                 \
 156         ((GET_CVID_IC_TYPE(version) == CHIP_92D) ? true : false)
 157
 158 #define IS_NORMAL_CHIP(version)                                         \
 159         ((GET_CVID_CHIP_TYPE(version)) ? true : false)
 160 #define IS_NORMAL_CHIP92D(version)                                      \
 161         ((GET_CVID_CHIP_TYPE(version)) ? true : false)
 162
 163 #define IS_1T1R(version)                                                \
 164         ((GET_CVID_RF_TYPE(version)) ? false : true)
 165 #define IS_1T2R(version)                                                \
 166         ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false)
 167 #define IS_2T2R(version)                                                \
 168         ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false)
 169 #define IS_CHIP_VENDOR_UMC(version)                                     \
 170         ((GET_CVID_MANUFACTUER(version)) ? true : false)
 171
 172 #define IS_92C_SERIAL(version)                                          \
 173         ((IS_81XXC(version) && IS_2T2R(version)) ? true : false)
 174 #define IS_81xxC_VENDOR_UMC_A_CUT(version)                              \
 175         (IS_81XXC(version) ? ((IS_CHIP_VENDOR_UMC(version)) ?           \
 176          ((GET_CVID_CUT_VERSION(version)) ? false : true) : false) : false)
 177 #define IS_81xxC_VENDOR_UMC_B_CUT(version)                              \
 178         (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ?             \
 179         ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true        \
 180         : false) : false) : false)
 181
 182 enum version_8188e {
 183         VERSION_TEST_CHIP_88E = 0x00,
 184         VERSION_NORMAL_CHIP_88E = 0x01,
 185         VERSION_UNKNOWN = 0xFF,
 186 };
 187
 188 enum rx_packet_type {
 189         NORMAL_RX,
 190         TX_REPORT1,
 191         TX_REPORT2,
 192         HIS_REPORT,
 193 };
 194
 195 enum rtl819x_loopback_e {
 196         RTL819X_NO_LOOPBACK = 0,
 197         RTL819X_MAC_LOOPBACK = 1,
 198         RTL819X_DMA_LOOPBACK = 2,
 199         RTL819X_CCK_LOOPBACK = 3,
 200 };
 201
 202 enum rf_optype {
 203         RF_OP_BY_SW_3WIRE = 0,
 204         RF_OP_BY_FW,
 205         RF_OP_MAX
 206 };
 207
 208 enum rf_power_state {
 209         RF_ON,
 210         RF_OFF,
 211         RF_SLEEP,
 212         RF_SHUT_DOWN,
 213 };
 214
 215 enum power_save_mode {
 216         POWER_SAVE_MODE_ACTIVE,
 217         POWER_SAVE_MODE_SAVE,
 218 };
 219
 220 enum power_polocy_config {
 221         POWERCFG_MAX_POWER_SAVINGS,
 222         POWERCFG_GLOBAL_POWER_SAVINGS,
 223         POWERCFG_LOCAL_POWER_SAVINGS,
 224         POWERCFG_LENOVO,
 225 };
 226
 227 enum interface_select_pci {
 228         INTF_SEL1_MINICARD,
 229         INTF_SEL0_PCIE,
 230         INTF_SEL2_RSV,
 231         INTF_SEL3_RSV,
 232 };
 233
 234 enum hal_fw_c2h_cmd_id {
 235         HAL_FW_C2H_CMD_Read_MACREG,
 236         HAL_FW_C2H_CMD_Read_BBREG,
 237         HAL_FW_C2H_CMD_Read_RFREG,
 238         HAL_FW_C2H_CMD_Read_EEPROM,
 239         HAL_FW_C2H_CMD_Read_EFUSE,
 240         HAL_FW_C2H_CMD_Read_CAM,
 241         HAL_FW_C2H_CMD_Get_BasicRate,
 242         HAL_FW_C2H_CMD_Get_DataRate,
 243         HAL_FW_C2H_CMD_Survey,
 244         HAL_FW_C2H_CMD_SurveyDone,
 245         HAL_FW_C2H_CMD_JoinBss,
 246         HAL_FW_C2H_CMD_AddSTA,
 247         HAL_FW_C2H_CMD_DelSTA,
 248         HAL_FW_C2H_CMD_AtimDone,
 249         HAL_FW_C2H_CMD_TX_Report,
 250         HAL_FW_C2H_CMD_CCX_Report,
 251         HAL_FW_C2H_CMD_DTM_Report,
 252         HAL_FW_C2H_CMD_TX_Rate_Statistics,
 253         HAL_FW_C2H_CMD_C2HLBK,
 254         HAL_FW_C2H_CMD_C2HDBG,
 255         HAL_FW_C2H_CMD_C2HFEEDBACK,
 256         HAL_FW_C2H_CMD_MAX
 257 };
 258
 259 enum wake_on_wlan_mode {
 260         ewowlandisable,
 261         ewakeonmagicpacketonly,
 262         ewakeonpatternmatchonly,
 263         ewakeonbothtypepacket
 264 };
 265
 266 enum rtl_desc_qsel {
 267         QSLT_BK = 0x2,
 268         QSLT_BE = 0x0,
 269         QSLT_VI = 0x5,
 270         QSLT_VO = 0x7,
 271         QSLT_BEACON = 0x10,
 272         QSLT_HIGH = 0x11,
 273         QSLT_MGNT = 0x12,
 274         QSLT_CMD = 0x13,
 275 };
 276
 277 enum rtl_desc92c_rate {
 278         DESC92C_RATE1M = 0x00,
 279         DESC92C_RATE2M = 0x01,
 280         DESC92C_RATE5_5M = 0x02,
 281         DESC92C_RATE11M = 0x03,
 282
 283         DESC92C_RATE6M = 0x04,
 284         DESC92C_RATE9M = 0x05,
 285         DESC92C_RATE12M = 0x06,
 286         DESC92C_RATE18M = 0x07,
 287         DESC92C_RATE24M = 0x08,
 288         DESC92C_RATE36M = 0x09,
 289         DESC92C_RATE48M = 0x0a,
 290         DESC92C_RATE54M = 0x0b,
 291
 292         DESC92C_RATEMCS0 = 0x0c,
 293         DESC92C_RATEMCS1 = 0x0d,
 294         DESC92C_RATEMCS2 = 0x0e,
 295         DESC92C_RATEMCS3 = 0x0f,
 296         DESC92C_RATEMCS4 = 0x10,
 297         DESC92C_RATEMCS5 = 0x11,
 298         DESC92C_RATEMCS6 = 0x12,
 299         DESC92C_RATEMCS7 = 0x13,
 300         DESC92C_RATEMCS8 = 0x14,
 301         DESC92C_RATEMCS9 = 0x15,
 302         DESC92C_RATEMCS10 = 0x16,
 303         DESC92C_RATEMCS11 = 0x17,
 304         DESC92C_RATEMCS12 = 0x18,
 305         DESC92C_RATEMCS13 = 0x19,
 306         DESC92C_RATEMCS14 = 0x1a,
 307         DESC92C_RATEMCS15 = 0x1b,
 308         DESC92C_RATEMCS15_SG = 0x1c,
 309         DESC92C_RATEMCS32 = 0x20,
 310 };
 311
 312 struct phy_sts_cck_8192s_t {
 313         u8 adc_pwdb_X[4];
 314         u8 sq_rpt;
 315         u8 cck_agc_rpt;
 316 };
 317
 318 struct h2c_cmd_8192c {
 319         u8 element_id;
 320         u32 cmd_len;
 321         u8 *p_cmdbuffer;
 322 };
 323
 324 #endif