drivers/net/wireless/rtlwifi/rtl8188ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "pwrseq.h"
  41
  42 #define LLT_CONFIG              5
  43
  44 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  45                                       u8 set_bits, u8 clear_bits)
  46 {
  47         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49
  50         rtlpci->reg_bcn_ctrl_val |= set_bits;
  51         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  52
  53         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  54 }
  55
  56 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
  57 {
  58         struct rtl_priv *rtlpriv = rtl_priv(hw);
  59         u8 tmp1byte;
  60
  61         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  62         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  63         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  64         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  65         tmp1byte &= ~(BIT(0));
  66         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  67 }
  68
  69 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
  70 {
  71         struct rtl_priv *rtlpriv = rtl_priv(hw);
  72         u8 tmp1byte;
  73
  74         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  75         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  76         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  77         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  78         tmp1byte |= BIT(0);
  79         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  80 }
  81
  82 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  83 {
  84         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  85 }
  86
  87 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  88 {
  89         struct rtl_priv *rtlpriv = rtl_priv(hw);
  90         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  91         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  92         unsigned long flags;
  93
  94         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  95         while (skb_queue_len(&ring->queue)) {
  96                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  97                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  98
  99                 pci_unmap_single(rtlpci->pdev,
 100                                  rtlpriv->cfg->ops->get_desc(
 101                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 102                                  skb->len, PCI_DMA_TODEVICE);
 103                 kfree_skb(skb);
 104                 ring->idx = (ring->idx + 1) % ring->entries;
 105         }
 106         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 107 }
 108
 109 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 110 {
 111         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 112 }
 113
 114 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
 115                                      u8 rpwm_val, bool b_need_turn_off_ckk)
 116 {
 117         struct rtl_priv *rtlpriv = rtl_priv(hw);
 118         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 119         bool b_support_remote_wake_up;
 120         u32 count = 0, isr_regaddr, content;
 121         bool schedule_timer = b_need_turn_off_ckk;
 122         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 123                                         (u8 *)(&b_support_remote_wake_up));
 124
 125         if (!rtlhal->fw_ready)
 126                 return;
 127         if (!rtlpriv->psc.fw_current_inpsmode)
 128                 return;
 129
 130         while (1) {
 131                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 132                 if (rtlhal->fw_clk_change_in_progress) {
 133                         while (rtlhal->fw_clk_change_in_progress) {
 134                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 135                                 count++;
 136                                 udelay(100);
 137                                 if (count > 1000)
 138                                         return;
 139                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 140                         }
 141                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 142                 } else {
 143                         rtlhal->fw_clk_change_in_progress = false;
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                         break;
 146                 }
 147         }
 148
 149         if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
 150                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 151                 if (FW_PS_IS_ACK(rpwm_val)) {
 152                         isr_regaddr = REG_HISR;
 153                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 154                         while (!(content & IMR_CPWM) && (count < 500)) {
 155                                 udelay(50);
 156                                 count++;
 157                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         }
 159
 160                         if (content & IMR_CPWM) {
 161                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 162                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
 163                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 164                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 165                                          rtlhal->fw_ps_state);
 166                         }
 167                 }
 168
 169                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 170                 rtlhal->fw_clk_change_in_progress = false;
 171                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 172                 if (schedule_timer) {
 173                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 174                                   jiffies + MSECS(10));
 175                 }
 176
 177         } else  {
 178                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 179                 rtlhal->fw_clk_change_in_progress = false;
 180                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 181         }
 182 }
 183
 184 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
 185                                       u8 rpwm_val)
 186 {
 187         struct rtl_priv *rtlpriv = rtl_priv(hw);
 188         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 189         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 190         struct rtl8192_tx_ring *ring;
 191         enum rf_pwrstate rtstate;
 192         bool schedule_timer = false;
 193         u8 queue;
 194
 195         if (!rtlhal->fw_ready)
 196                 return;
 197         if (!rtlpriv->psc.fw_current_inpsmode)
 198                 return;
 199         if (!rtlhal->allow_sw_to_change_hwclc)
 200                 return;
 201         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 202         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 203                 return;
 204
 205         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 206                 ring = &rtlpci->tx_ring[queue];
 207                 if (skb_queue_len(&ring->queue)) {
 208                         schedule_timer = true;
 209                         break;
 210                 }
 211         }
 212
 213         if (schedule_timer) {
 214                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 215                           jiffies + MSECS(10));
 216                 return;
 217         }
 218
 219         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 220             FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
 221                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 222                 if (!rtlhal->fw_clk_change_in_progress) {
 223                         rtlhal->fw_clk_change_in_progress = true;
 224                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 225                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 226                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 227                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 228                                                       &rpwm_val);
 229                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 230                         rtlhal->fw_clk_change_in_progress = false;
 231                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 232                 } else {
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 235                                   jiffies + MSECS(10));
 236                 }
 237         }
 238 }
 239
 240 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 241 {
 242         u8 rpwm_val = 0;
 243
 244         rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
 245         _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
 246 }
 247
 248 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 249 {
 250         u8 rpwm_val = 0;
 251         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
 252         _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 253 }
 254 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
 255 {
 256         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 257
 258         _rtl88ee_set_fw_ps_rf_off_low_power(hw);
 259 }
 260
 261 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
 262 {
 263         struct rtl_priv *rtlpriv = rtl_priv(hw);
 264         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 265         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 266         bool fw_current_inps = false;
 267         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 268
 269         if (ppsc->low_power_enable) {
 270                 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
 271                 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
 272                 rtlhal->allow_sw_to_change_hwclc = false;
 273                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 274                                               &fw_pwrmode);
 275                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 276                                               (u8 *)(&fw_current_inps));
 277         } else {
 278                 rpwm_val = FW_PS_STATE_ALL_ON_88E;      /* RF on */
 279                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 280                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 281                                               &fw_pwrmode);
 282                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 283                                               (u8 *)(&fw_current_inps));
 284         }
 285 }
 286
 287 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
 288 {
 289         struct rtl_priv *rtlpriv = rtl_priv(hw);
 290         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 291         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 292         bool fw_current_inps = true;
 293         u8 rpwm_val;
 294
 295         if (ppsc->low_power_enable) {
 296                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;      /* RF off */
 297                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 298                                               (u8 *)(&fw_current_inps));
 299                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 300                                               &ppsc->fwctrl_psmode);
 301                 rtlhal->allow_sw_to_change_hwclc = true;
 302                 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 303         } else {
 304                 rpwm_val = FW_PS_STATE_RF_OFF_88E;      /* RF off */
 305                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 306                                               (u8 *)(&fw_current_inps));
 307                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 308                                               &ppsc->fwctrl_psmode);
 309                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 310         }
 311 }
 312
 313 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 314 {
 315         struct rtl_priv *rtlpriv = rtl_priv(hw);
 316         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 317         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 318
 319         switch (variable) {
 320         case HW_VAR_RCR:
 321                 *((u32 *)(val)) = rtlpci->receive_config;
 322                 break;
 323         case HW_VAR_RF_STATE:
 324                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 325                 break;
 326         case HW_VAR_FWLPS_RF_ON:{
 327                 enum rf_pwrstate rfstate;
 328                 u32 val_rcr;
 329
 330                 rtlpriv->cfg->ops->get_hw_reg(hw,
 331                                               HW_VAR_RF_STATE,
 332                                               (u8 *)(&rfstate));
 333                 if (rfstate == ERFOFF) {
 334                         *((bool *)(val)) = true;
 335                 } else {
 336                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 337                         val_rcr &= 0x00070000;
 338                         if (val_rcr)
 339                                 *((bool *)(val)) = false;
 340                         else
 341                                 *((bool *)(val)) = true;
 342                 }
 343                 break; }
 344         case HW_VAR_FW_PSMODE_STATUS:
 345                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 346                 break;
 347         case HW_VAR_CORRECT_TSF:{
 348                 u64 tsf;
 349                 u32 *ptsf_low = (u32 *)&tsf;
 350                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 351
 352                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 353                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 354
 355                 *((u64 *)(val)) = tsf;
 356                 break; }
 357         default:
 358                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 359                          "switch case not process %x\n", variable);
 360                 break;
 361         }
 362 }
 363
 364 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 365 {
 366         struct rtl_priv *rtlpriv = rtl_priv(hw);
 367         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 368         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 369         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 370         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 371         u8 idx;
 372
 373         switch (variable) {
 374         case HW_VAR_ETHER_ADDR:
 375                 for (idx = 0; idx < ETH_ALEN; idx++) {
 376                         rtl_write_byte(rtlpriv, (REG_MACID + idx),
 377                                        val[idx]);
 378                 }
 379                 break;
 380         case HW_VAR_BASIC_RATE:{
 381                 u16 b_rate_cfg = ((u16 *)val)[0];
 382                 u8 rate_index = 0;
 383                 b_rate_cfg = b_rate_cfg & 0x15f;
 384                 b_rate_cfg |= 0x01;
 385                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 386                 rtl_write_byte(rtlpriv, REG_RRSR + 1,
 387                                (b_rate_cfg >> 8) & 0xff);
 388                 while (b_rate_cfg > 0x1) {
 389                         b_rate_cfg = (b_rate_cfg >> 1);
 390                         rate_index++;
 391                 }
 392                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 393                                rate_index);
 394                 break;
 395                 }
 396         case HW_VAR_BSSID:
 397                 for (idx = 0; idx < ETH_ALEN; idx++) {
 398                         rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 399                                        val[idx]);
 400                 }
 401                 break;
 402         case HW_VAR_SIFS:
 403                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 404                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 405
 406                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 407                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 408
 409                 if (!mac->ht_enable)
 410                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 411                                        0x0e0e);
 412                 else
 413                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 414                                        *((u16 *)val));
 415                 break;
 416         case HW_VAR_SLOT_TIME:{
 417                 u8 e_aci;
 418
 419                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 420                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 421
 422                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 423
 424                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 425                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 426                                                       &e_aci);
 427                 }
 428                 break;
 429                 }
 430         case HW_VAR_ACK_PREAMBLE:{
 431                 u8 reg_tmp;
 432                 u8 short_preamble = (bool)*val;
 433                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 434                 if (short_preamble) {
 435                         reg_tmp |= 0x02;
 436                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 437                                        2, reg_tmp);
 438                 } else {
 439                         reg_tmp |= 0xFD;
 440                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 441                                        2, reg_tmp);
 442                 }
 443                 break; }
 444         case HW_VAR_WPA_CONFIG:
 445                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 446                 break;
 447         case HW_VAR_AMPDU_MIN_SPACE:{
 448                 u8 min_spacing_to_set;
 449                 u8 sec_min_space;
 450
 451                 min_spacing_to_set = *val;
 452                 if (min_spacing_to_set <= 7) {
 453                         sec_min_space = 0;
 454
 455                         if (min_spacing_to_set < sec_min_space)
 456                                 min_spacing_to_set = sec_min_space;
 457
 458                         mac->min_space_cfg = ((mac->min_space_cfg &
 459                                                0xf8) |
 460                                               min_spacing_to_set);
 461
 462                         *val = min_spacing_to_set;
 463
 464                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 465                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 466                                   mac->min_space_cfg);
 467
 468                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 469                                        mac->min_space_cfg);
 470                 }
 471                 break; }
 472         case HW_VAR_SHORTGI_DENSITY:{
 473                 u8 density_to_set;
 474
 475                 density_to_set = *val;
 476                 mac->min_space_cfg |= (density_to_set << 3);
 477
 478                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 479                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 480                           mac->min_space_cfg);
 481
 482                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 483                                mac->min_space_cfg);
 484                 break;
 485                 }
 486         case HW_VAR_AMPDU_FACTOR:{
 487                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 488                 u8 factor_toset;
 489                 u8 *p_regtoset = NULL;
 490                 u8 index = 0;
 491
 492                 p_regtoset = regtoset_normal;
 493
 494                 factor_toset = *val;
 495                 if (factor_toset <= 3) {
 496                         factor_toset = (1 << (factor_toset + 2));
 497                         if (factor_toset > 0xf)
 498                                 factor_toset = 0xf;
 499
 500                         for (index = 0; index < 4; index++) {
 501                                 if ((p_regtoset[index] & 0xf0) >
 502                                     (factor_toset << 4))
 503                                         p_regtoset[index] =
 504                                             (p_regtoset[index] & 0x0f) |
 505                                             (factor_toset << 4);
 506
 507                                 if ((p_regtoset[index] & 0x0f) >
 508                                     factor_toset)
 509                                         p_regtoset[index] =
 510                                             (p_regtoset[index] & 0xf0) |
 511                                             (factor_toset);
 512
 513                                 rtl_write_byte(rtlpriv,
 514                                                (REG_AGGLEN_LMT + index),
 515                                                p_regtoset[index]);
 516
 517                         }
 518
 519                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 520                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 521                                   factor_toset);
 522                 }
 523                 break; }
 524         case HW_VAR_AC_PARAM:{
 525                 u8 e_aci = *val;
 526                 rtl88e_dm_init_edca_turbo(hw);
 527
 528                 if (rtlpci->acm_method != EACMWAY2_SW)
 529                         rtlpriv->cfg->ops->set_hw_reg(hw,
 530                                                       HW_VAR_ACM_CTRL,
 531                                                       &e_aci);
 532                 break; }
 533         case HW_VAR_ACM_CTRL:{
 534                 u8 e_aci = *val;
 535                 union aci_aifsn *p_aci_aifsn =
 536                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 537                 u8 acm = p_aci_aifsn->f.acm;
 538                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 539
 540                 acm_ctrl = acm_ctrl |
 541                            ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 542
 543                 if (acm) {
 544                         switch (e_aci) {
 545                         case AC0_BE:
 546                                 acm_ctrl |= ACMHW_BEQEN;
 547                                 break;
 548                         case AC2_VI:
 549                                 acm_ctrl |= ACMHW_VIQEN;
 550                                 break;
 551                         case AC3_VO:
 552                                 acm_ctrl |= ACMHW_VOQEN;
 553                                 break;
 554                         default:
 555                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 556                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 557                                          acm);
 558                                 break;
 559                         }
 560                 } else {
 561                         switch (e_aci) {
 562                         case AC0_BE:
 563                                 acm_ctrl &= (~ACMHW_BEQEN);
 564                                 break;
 565                         case AC2_VI:
 566                                 acm_ctrl &= (~ACMHW_VIQEN);
 567                                 break;
 568                         case AC3_VO:
 569                                 acm_ctrl &= (~ACMHW_BEQEN);
 570                                 break;
 571                         default:
 572                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 573                                          "switch case not process\n");
 574                                 break;
 575                         }
 576                 }
 577
 578                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 579                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 580                          acm_ctrl);
 581                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 582                 break; }
 583         case HW_VAR_RCR:
 584                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 585                 rtlpci->receive_config = ((u32 *)(val))[0];
 586                 break;
 587         case HW_VAR_RETRY_LIMIT:{
 588                 u8 retry_limit = *val;
 589
 590                 rtl_write_word(rtlpriv, REG_RL,
 591                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 592                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 593                 break; }
 594         case HW_VAR_DUAL_TSF_RST:
 595                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 596                 break;
 597         case HW_VAR_EFUSE_BYTES:
 598                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 599                 break;
 600         case HW_VAR_EFUSE_USAGE:
 601                 rtlefuse->efuse_usedpercentage = *val;
 602                 break;
 603         case HW_VAR_IO_CMD:
 604                 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 605                 break;
 606         case HW_VAR_SET_RPWM:{
 607                 u8 rpwm_val;
 608
 609                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 610                 udelay(1);
 611
 612                 if (rpwm_val & BIT(7)) {
 613                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 614                 } else {
 615                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
 616                 }
 617                 break; }
 618         case HW_VAR_H2C_FW_PWRMODE:
 619                 rtl88e_set_fw_pwrmode_cmd(hw, *val);
 620                 break;
 621         case HW_VAR_FW_PSMODE_STATUS:
 622                 ppsc->fw_current_inpsmode = *((bool *)val);
 623                 break;
 624         case HW_VAR_RESUME_CLK_ON:
 625                 _rtl88ee_set_fw_ps_rf_on(hw);
 626                 break;
 627         case HW_VAR_FW_LPS_ACTION:{
 628                 bool enter_fwlps = *((bool *)val);
 629
 630                 if (enter_fwlps)
 631                         _rtl88ee_fwlps_enter(hw);
 632                  else
 633                         _rtl88ee_fwlps_leave(hw);
 634
 635                  break; }
 636         case HW_VAR_H2C_FW_JOINBSSRPT:{
 637                 u8 mstatus = *val;
 638                 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 639                 u8 count = 0, dlbcn_count = 0;
 640                 bool b_recover = false;
 641
 642                 if (mstatus == RT_MEDIA_CONNECT) {
 643                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 644                                                       NULL);
 645
 646                         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 647                         rtl_write_byte(rtlpriv, REG_CR + 1,
 648                                        (tmp_regcr | BIT(0)));
 649
 650                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 651                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 652
 653                         tmp_reg422 =
 654                             rtl_read_byte(rtlpriv,
 655                                           REG_FWHW_TXQ_CTRL + 2);
 656                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 657                                        tmp_reg422 & (~BIT(6)));
 658                         if (tmp_reg422 & BIT(6))
 659                                 b_recover = true;
 660
 661                         do {
 662                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 663                                                              REG_TDECTRL+2);
 664                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
 665                                                (bcnvalid_reg | BIT(0)));
 666                                 _rtl88ee_return_beacon_queue_skb(hw);
 667
 668                                 rtl88e_set_fw_rsvdpagepkt(hw, 0);
 669                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 670                                                              REG_TDECTRL+2);
 671                                 count = 0;
 672                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 673                                         count++;
 674                                         udelay(10);
 675                                         bcnvalid_reg =
 676                                           rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 677                                 }
 678                                 dlbcn_count++;
 679                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 680
 681                         if (bcnvalid_reg & BIT(0))
 682                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 683
 684                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 685                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 686
 687                         if (b_recover) {
 688                                 rtl_write_byte(rtlpriv,
 689                                                REG_FWHW_TXQ_CTRL + 2,
 690                                                tmp_reg422);
 691                         }
 692
 693                         rtl_write_byte(rtlpriv, REG_CR + 1,
 694                                        (tmp_regcr & ~(BIT(0))));
 695                 }
 696                 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 697                 break; }
 698         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 699                 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
 700                 break;
 701         case HW_VAR_AID:{
 702                 u16 u2btmp;
 703
 704                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 705                 u2btmp &= 0xC000;
 706                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 707                                mac->assoc_id));
 708                 break; }
 709         case HW_VAR_CORRECT_TSF:{
 710                 u8 btype_ibss = *val;
 711
 712                 if (btype_ibss)
 713                         _rtl88ee_stop_tx_beacon(hw);
 714
 715                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 716
 717                 rtl_write_dword(rtlpriv, REG_TSFTR,
 718                                 (u32)(mac->tsf & 0xffffffff));
 719                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 720                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 721
 722                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 723
 724                 if (btype_ibss)
 725                         _rtl88ee_resume_tx_beacon(hw);
 726                 break; }
 727         case HW_VAR_KEEP_ALIVE: {
 728                 u8 array[2];
 729
 730                 array[0] = 0xff;
 731                 array[1] = *((u8 *)val);
 732                 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
 733                                     2, array);
 734                 break; }
 735         default:
 736                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 737                          "switch case not process %x\n", variable);
 738                 break;
 739         }
 740 }
 741
 742 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 743 {
 744         struct rtl_priv *rtlpriv = rtl_priv(hw);
 745         bool status = true;
 746         long count = 0;
 747         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 748                     _LLT_OP(_LLT_WRITE_ACCESS);
 749
 750         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 751
 752         do {
 753                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 754                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 755                         break;
 756
 757                 if (count > POLLING_LLT_THRESHOLD) {
 758                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 759                                  "Failed to polling write LLT done at address %d!\n",
 760                                  address);
 761                         status = false;
 762                         break;
 763                 }
 764         } while (++count);
 765
 766         return status;
 767 }
 768
 769 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
 770 {
 771         struct rtl_priv *rtlpriv = rtl_priv(hw);
 772         unsigned short i;
 773         u8 txpktbuf_bndy;
 774         u8 maxpage;
 775         bool status;
 776
 777         maxpage = 0xAF;
 778         txpktbuf_bndy = 0xAB;
 779
 780         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
 781         rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
 782
 783         /*0x2600   MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
 784         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
 785         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 786
 787         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 788         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 789
 790         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 791         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 792         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 793
 794         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 795                 status = _rtl88ee_llt_write(hw, i, i + 1);
 796                 if (true != status)
 797                         return status;
 798         }
 799
 800         status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 801         if (true != status)
 802                 return status;
 803
 804         for (i = txpktbuf_bndy; i < maxpage; i++) {
 805                 status = _rtl88ee_llt_write(hw, i, (i + 1));
 806                 if (true != status)
 807                         return status;
 808         }
 809
 810         status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
 811         if (true != status)
 812                 return status;
 813
 814         return true;
 815 }
 816
 817 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 818 {
 819         struct rtl_priv *rtlpriv = rtl_priv(hw);
 820         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 821         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 822         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 823
 824         if (rtlpriv->rtlhal.up_first_time)
 825                 return;
 826
 827         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 828                 rtl88ee_sw_led_on(hw, pLed0);
 829         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 830                 rtl88ee_sw_led_on(hw, pLed0);
 831         else
 832                 rtl88ee_sw_led_off(hw, pLed0);
 833 }
 834
 835 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
 836 {
 837         struct rtl_priv *rtlpriv = rtl_priv(hw);
 838         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 839         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 840
 841         u8 bytetmp;
 842         u16 wordtmp;
 843
 844         /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
 845         bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
 846         rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
 847         /*Auto Power Down to CHIP-off State*/
 848         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 849         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 850
 851         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 852         /* HW Power on sequence */
 853         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 854                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 855                                       RTL8188EE_NIC_ENABLE_FLOW)) {
 856                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 857                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 858                 return false;
 859         }
 860
 861         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 862         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 863
 864         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 865         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
 866
 867         bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
 868         rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
 869
 870         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
 871         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
 872
 873         bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
 874         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
 875         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
 876         rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
 877
 878         /*Add for wake up online*/
 879         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 880
 881         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
 882         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
 883         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
 884         rtl_write_byte(rtlpriv, 0x367, 0x80);
 885
 886         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 887         rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
 888         rtl_write_byte(rtlpriv, REG_CR+2, 0x00);
 889
 890         if (!rtlhal->mac_func_enable) {
 891                 if (_rtl88ee_llt_table_init(hw) == false) {
 892                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 893                                  "LLT table init fail\n");
 894                         return false;
 895                 }
 896         }
 897         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 898         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 899
 900         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 901         wordtmp &= 0xf;
 902         wordtmp |= 0xE771;
 903         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 904
 905         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 906         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 907         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 908
 909         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 910                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 911                         DMA_BIT_MASK(32));
 912         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 913                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 914                         DMA_BIT_MASK(32));
 915         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 916                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 917         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 918                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 919         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 920                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 921         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 922                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 923         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 924                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 925                         DMA_BIT_MASK(32));
 926         rtl_write_dword(rtlpriv, REG_RX_DESA,
 927                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 928                         DMA_BIT_MASK(32));
 929
 930         /* if we want to support 64 bit DMA, we should set it here,
 931          * but now we do not support 64 bit DMA
 932          */
 933         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 934
 935         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 936         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
 937
 938         if (rtlhal->earlymode_enable) {/*Early mode enable*/
 939                 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
 940                 bytetmp |= 0x1f;
 941                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
 942                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
 943         }
 944         _rtl88ee_gen_refresh_led_state(hw);
 945         return true;
 946 }
 947
 948 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
 949 {
 950         struct rtl_priv *rtlpriv = rtl_priv(hw);
 951         u8 reg_bw_opmode;
 952         u32 reg_ratr, reg_prsr;
 953
 954         reg_bw_opmode = BW_OPMODE_20MHZ;
 955         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 956             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 957         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 958
 959         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 960         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 961 }
 962
 963 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
 964 {
 965         struct rtl_priv *rtlpriv = rtl_priv(hw);
 966         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 967         u8 tmp1byte = 0;
 968         u32 tmp4byte = 0, count = 0;
 969
 970         rtl_write_word(rtlpriv, 0x354, 0x8104);
 971         rtl_write_word(rtlpriv, 0x358, 0x24);
 972
 973         rtl_write_word(rtlpriv, 0x350, 0x70c);
 974         rtl_write_byte(rtlpriv, 0x352, 0x2);
 975         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 976         count = 0;
 977         while (tmp1byte && count < 20) {
 978                 udelay(10);
 979                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 980                 count++;
 981         }
 982         if (0 == tmp1byte) {
 983                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
 984                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
 985                 rtl_write_word(rtlpriv, 0x350, 0xf70c);
 986                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 987         }
 988
 989         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 990         count = 0;
 991         while (tmp1byte && count < 20) {
 992                 udelay(10);
 993                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 994                 count++;
 995         }
 996
 997         rtl_write_word(rtlpriv, 0x350, 0x718);
 998         rtl_write_byte(rtlpriv, 0x352, 0x2);
 999         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1000         count = 0;
1001         while (tmp1byte && count < 20) {
1002                 udelay(10);
1003                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1004                 count++;
1005         }
1006
1007         if (ppsc->support_backdoor || (0 == tmp1byte)) {
1008                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1009                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
1010                 rtl_write_word(rtlpriv, 0x350, 0xf718);
1011                 rtl_write_byte(rtlpriv, 0x352, 0x1);
1012         }
1013
1014         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1015         count = 0;
1016         while (tmp1byte && count < 20) {
1017                 udelay(10);
1018                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1019                 count++;
1020         }
1021 }
1022
1023 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1024 {
1025         struct rtl_priv *rtlpriv = rtl_priv(hw);
1026         u8 sec_reg_value;
1027
1028         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1029                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1030                   rtlpriv->sec.pairwise_enc_algorithm,
1031                   rtlpriv->sec.group_enc_algorithm);
1032
1033         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1034                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1035                          "not open hw encryption\n");
1036                 return;
1037         }
1038
1039         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1040
1041         if (rtlpriv->sec.use_defaultkey) {
1042                 sec_reg_value |= SCR_TXUSEDK;
1043                 sec_reg_value |= SCR_RXUSEDK;
1044         }
1045
1046         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1047
1048         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1049
1050         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1051                  "The SECR-value %x\n", sec_reg_value);
1052
1053         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1054 }
1055
1056 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1057 {
1058         struct rtl_priv *rtlpriv = rtl_priv(hw);
1059         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1060         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1061         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1062         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1063         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1064         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1065         bool rtstatus = true;
1066         int err = 0;
1067         u8 tmp_u1b, u1byte;
1068         unsigned long flags;
1069
1070         rtlpriv->rtlhal.being_init_adapter = true;
1071         /* As this function can take a very long time (up to 350 ms)
1072          * and can be called with irqs disabled, reenable the irqs
1073          * to let the other devices continue being serviced.
1074          *
1075          * It is safe doing so since our own interrupts will only be enabled
1076          * in a subsequent step.
1077          */
1078         local_save_flags(flags);
1079         local_irq_enable();
1080         rtlhal->fw_ready = false;
1081
1082         rtlpriv->intf_ops->disable_aspm(hw);
1083
1084         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1085         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1086         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1087                 rtlhal->mac_func_enable = true;
1088         } else {
1089                 rtlhal->mac_func_enable = false;
1090                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1091         }
1092
1093         rtstatus = _rtl88ee_init_mac(hw);
1094         if (rtstatus != true) {
1095                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1096                 err = 1;
1097                 goto exit;
1098         }
1099
1100         err = rtl88e_download_fw(hw, false);
1101         if (err) {
1102                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1103                          "Failed to download FW. Init HW without FW now..\n");
1104                 err = 1;
1105                 goto exit;
1106         }
1107         rtlhal->fw_ready = true;
1108         /*fw related variable initialize */
1109         rtlhal->last_hmeboxnum = 0;
1110         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1111         rtlhal->fw_clk_change_in_progress = false;
1112         rtlhal->allow_sw_to_change_hwclc = false;
1113         ppsc->fw_current_inpsmode = false;
1114
1115         rtl88e_phy_mac_config(hw);
1116         /* because last function modify RCR, so we update
1117          * rcr var here, or TP will unstable for receive_config
1118          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1119          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1120          */
1121         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1122         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1123
1124         rtl88e_phy_bb_config(hw);
1125         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1126         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1127
1128         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1129         rtl88e_phy_rf_config(hw);
1130
1131         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1132                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1133         rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1134
1135         _rtl88ee_hw_configure(hw);
1136         rtl_cam_reset_all_entry(hw);
1137         rtl88ee_enable_hw_security_config(hw);
1138
1139         rtlhal->mac_func_enable = true;
1140         ppsc->rfpwr_state = ERFON;
1141
1142         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1143         _rtl88ee_enable_aspm_back_door(hw);
1144         rtlpriv->intf_ops->enable_aspm(hw);
1145
1146         if (ppsc->rfpwr_state == ERFON) {
1147                 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1148                     ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1149                      (rtlhal->oem_id == RT_CID_819X_HP))) {
1150                         rtl88e_phy_set_rfpath_switch(hw, true);
1151                         rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1152                 } else {
1153                         rtl88e_phy_set_rfpath_switch(hw, false);
1154                         rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1155                 }
1156                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1157                          (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1158                          ("MAIN_ANT") : ("AUX_ANT"));
1159
1160                 if (rtlphy->iqk_initialized) {
1161                         rtl88e_phy_iq_calibrate(hw, true);
1162                 } else {
1163                         rtl88e_phy_iq_calibrate(hw, false);
1164                         rtlphy->iqk_initialized = true;
1165                 }
1166
1167                 rtl88e_dm_check_txpower_tracking(hw);
1168                 rtl88e_phy_lc_calibrate(hw);
1169         }
1170
1171         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1172         if (!(tmp_u1b & BIT(0))) {
1173                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1174                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1175         }
1176
1177         if (!(tmp_u1b & BIT(4))) {
1178                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1179                 tmp_u1b &= 0x0F;
1180                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1181                 udelay(10);
1182                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1183                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1184         }
1185         rtl_write_byte(rtlpriv, REG_NAV_CTRL+2,  ((30000+127)/128));
1186         rtl88e_dm_init(hw);
1187 exit:
1188         local_irq_restore(flags);
1189         rtlpriv->rtlhal.being_init_adapter = false;
1190         return err;
1191 }
1192
1193 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1194 {
1195         struct rtl_priv *rtlpriv = rtl_priv(hw);
1196         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1197         enum version_8188e version = VERSION_UNKNOWN;
1198         u32 value32;
1199
1200         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1201         if (value32 & TRP_VAUX_EN) {
1202                 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1203         } else {
1204                 version = NORMAL_CHIP;
1205                 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1206                 version = version | ((value32 & VENDOR_ID) ?
1207                           CHIP_VENDOR_UMC : 0);
1208         }
1209
1210         rtlphy->rf_type = RF_1T1R;
1211         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1212                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1213                  "RF_2T2R" : "RF_1T1R");
1214
1215         return version;
1216 }
1217
1218 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1219                                      enum nl80211_iftype type)
1220 {
1221         struct rtl_priv *rtlpriv = rtl_priv(hw);
1222         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1223         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1224         u8 mode = MSR_NOLINK;
1225
1226         switch (type) {
1227         case NL80211_IFTYPE_UNSPECIFIED:
1228                 mode = MSR_NOLINK;
1229                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1230                          "Set Network type to NO LINK!\n");
1231                 break;
1232         case NL80211_IFTYPE_ADHOC:
1233         case NL80211_IFTYPE_MESH_POINT:
1234                 mode = MSR_ADHOC;
1235                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1236                          "Set Network type to Ad Hoc!\n");
1237                 break;
1238         case NL80211_IFTYPE_STATION:
1239                 mode = MSR_INFRA;
1240                 ledaction = LED_CTL_LINK;
1241                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1242                          "Set Network type to STA!\n");
1243                 break;
1244         case NL80211_IFTYPE_AP:
1245                 mode = MSR_AP;
1246                 ledaction = LED_CTL_LINK;
1247                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1248                          "Set Network type to AP!\n");
1249                 break;
1250         default:
1251                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1252                          "Network type %d not support!\n", type);
1253                 return 1;
1254                 break;
1255         }
1256
1257         /* MSR_INFRA == Link in infrastructure network;
1258          * MSR_ADHOC == Link in ad hoc network;
1259          * Therefore, check link state is necessary.
1260          *
1261          * MSR_AP == AP mode; link state is not cared here.
1262          */
1263         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1264                 mode = MSR_NOLINK;
1265                 ledaction = LED_CTL_NO_LINK;
1266         }
1267
1268         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1269                 _rtl88ee_stop_tx_beacon(hw);
1270                 _rtl88ee_enable_bcn_sub_func(hw);
1271         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1272                 _rtl88ee_resume_tx_beacon(hw);
1273                 _rtl88ee_disable_bcn_sub_func(hw);
1274         } else {
1275                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1276                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1277                          mode);
1278         }
1279
1280         rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1281         rtlpriv->cfg->ops->led_control(hw, ledaction);
1282         if (mode == MSR_AP)
1283                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1284         else
1285                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1286         return 0;
1287 }
1288
1289 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1290 {
1291         struct rtl_priv *rtlpriv = rtl_priv(hw);
1292         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1293         u32 reg_rcr = rtlpci->receive_config;
1294
1295         if (rtlpriv->psc.rfpwr_state != ERFON)
1296                 return;
1297
1298         if (check_bssid == true) {
1299                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1301                                               (u8 *)(&reg_rcr));
1302                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1303         } else if (check_bssid == false) {
1304                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1305                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1306                 rtlpriv->cfg->ops->set_hw_reg(hw,
1307                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1308         }
1309
1310 }
1311
1312 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1313                              enum nl80211_iftype type)
1314 {
1315         struct rtl_priv *rtlpriv = rtl_priv(hw);
1316
1317         if (_rtl88ee_set_media_status(hw, type))
1318                 return -EOPNOTSUPP;
1319
1320         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1321                 if (type != NL80211_IFTYPE_AP &&
1322                     type != NL80211_IFTYPE_MESH_POINT)
1323                         rtl88ee_set_check_bssid(hw, true);
1324         } else {
1325                 rtl88ee_set_check_bssid(hw, false);
1326         }
1327
1328         return 0;
1329 }
1330
1331 /* don't set REG_EDCA_BE_PARAM here
1332  * because mac80211 will send pkt when scan
1333  */
1334 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1335 {
1336         struct rtl_priv *rtlpriv = rtl_priv(hw);
1337         rtl88e_dm_init_edca_turbo(hw);
1338         switch (aci) {
1339         case AC1_BK:
1340                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1341                 break;
1342         case AC0_BE:
1343                 break;
1344         case AC2_VI:
1345                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1346                 break;
1347         case AC3_VO:
1348                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1349                 break;
1350         default:
1351                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1352                 break;
1353         }
1354 }
1355
1356 static void rtl88ee_clear_interrupt(struct ieee80211_hw *hw)
1357 {
1358         struct rtl_priv *rtlpriv = rtl_priv(hw);
1359         u32 tmp;
1360
1361         tmp = rtl_read_dword(rtlpriv, REG_HISR);
1362         rtl_write_dword(rtlpriv, REG_HISR, tmp);
1363
1364         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1365         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1366
1367         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1368         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1369 }
1370
1371 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1372 {
1373         struct rtl_priv *rtlpriv = rtl_priv(hw);
1374         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1375
1376         rtl88ee_clear_interrupt(hw);/*clear it here first*/
1377         rtl_write_dword(rtlpriv, REG_HIMR,
1378                         rtlpci->irq_mask[0] & 0xFFFFFFFF);
1379         rtl_write_dword(rtlpriv, REG_HIMRE,
1380                         rtlpci->irq_mask[1] & 0xFFFFFFFF);
1381         rtlpci->irq_enabled = true;
1382         /* there are some C2H CMDs have been sent
1383          * before system interrupt is enabled, e.g., C2H, CPWM.
1384          * So we need to clear all C2H events that FW has notified,
1385          * otherwise FW won't schedule any commands anymore.
1386          */
1387         rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1388         /*enable system interrupt*/
1389         rtl_write_dword(rtlpriv, REG_HSIMR,
1390                         rtlpci->sys_irq_mask & 0xFFFFFFFF);
1391 }
1392
1393 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1394 {
1395         struct rtl_priv *rtlpriv = rtl_priv(hw);
1396         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1397
1398         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1399         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1400         rtlpci->irq_enabled = false;
1401         /*synchronize_irq(rtlpci->pdev->irq);*/
1402 }
1403
1404 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1405 {
1406         struct rtl_priv *rtlpriv = rtl_priv(hw);
1407         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1408         u8 u1b_tmp;
1409         u32 count = 0;
1410         rtlhal->mac_func_enable = false;
1411         rtlpriv->intf_ops->enable_aspm(hw);
1412
1413         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1414         u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1415         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1416
1417         u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1418         while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1419                 udelay(10);
1420                 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1421                 count++;
1422         }
1423         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1424
1425         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1426                                  PWR_INTF_PCI_MSK,
1427                                  RTL8188EE_NIC_LPS_ENTER_FLOW);
1428
1429         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1430
1431         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1432                 rtl88e_firmware_selfreset(hw);
1433
1434         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1435         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1436         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1437
1438         u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1439         rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1440
1441         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1442                                  PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1443
1444         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1445         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1446         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1447         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1448
1449         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1450
1451         u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1452         rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1453         rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1454
1455         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1456         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1457         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1458         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1459
1460         rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1461 }
1462
1463 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1464 {
1465         struct rtl_priv *rtlpriv = rtl_priv(hw);
1466         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1467         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1468         enum nl80211_iftype opmode;
1469
1470         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1471
1472         mac->link_state = MAC80211_NOLINK;
1473         opmode = NL80211_IFTYPE_UNSPECIFIED;
1474
1475         _rtl88ee_set_media_status(hw, opmode);
1476
1477         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1478             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1479                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1480
1481         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1482         _rtl88ee_poweroff_adapter(hw);
1483
1484         /* after power off we should do iqk again */
1485         rtlpriv->phy.iqk_initialized = false;
1486 }
1487
1488 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1489                                   u32 *p_inta, u32 *p_intb)
1490 {
1491         struct rtl_priv *rtlpriv = rtl_priv(hw);
1492         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1493
1494         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1495         rtl_write_dword(rtlpriv, ISR, *p_inta);
1496
1497         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1498         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1499
1500 }
1501
1502 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1503 {
1504         struct rtl_priv *rtlpriv = rtl_priv(hw);
1505         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1506         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1507         u16 bcn_interval, atim_window;
1508
1509         bcn_interval = mac->beacon_interval;
1510         atim_window = 2;        /*FIX MERGE */
1511         rtl88ee_disable_interrupt(hw);
1512         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1513         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1514         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1515         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1516         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1517         rtl_write_byte(rtlpriv, 0x606, 0x30);
1518         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1519         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1520         /*rtl88ee_enable_interrupt(hw);*/
1521 }
1522
1523 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1524 {
1525         struct rtl_priv *rtlpriv = rtl_priv(hw);
1526         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1527         u16 bcn_interval = mac->beacon_interval;
1528
1529         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1530                  "beacon_interval:%d\n", bcn_interval);
1531         /*rtl88ee_disable_interrupt(hw);*/
1532         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1533         /*rtl88ee_enable_interrupt(hw);*/
1534 }
1535
1536 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1537                                    u32 add_msr, u32 rm_msr)
1538 {
1539         struct rtl_priv *rtlpriv = rtl_priv(hw);
1540         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1541
1542         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1543                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1544
1545         if (add_msr)
1546                 rtlpci->irq_mask[0] |= add_msr;
1547         if (rm_msr)
1548                 rtlpci->irq_mask[0] &= (~rm_msr);
1549         rtl88ee_disable_interrupt(hw);
1550         rtl88ee_enable_interrupt(hw);
1551 }
1552
1553 static u8 _rtl88e_get_chnl_group(u8 chnl)
1554 {
1555         u8 group = 0;
1556
1557         if (chnl < 3)
1558                 group = 0;
1559         else if (chnl < 6)
1560                 group = 1;
1561         else if (chnl < 9)
1562                 group = 2;
1563         else if (chnl < 12)
1564                 group = 3;
1565         else if (chnl < 14)
1566                 group = 4;
1567         else if (chnl == 14)
1568                 group = 5;
1569
1570         return group;
1571 }
1572
1573 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1574 {
1575         int group, txcnt;
1576
1577         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1578                 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1579                 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1580         }
1581         for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1582                 if (txcnt == 0) {
1583                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1584                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1585                 } else {
1586                         pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1587                         pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1588                         pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1589                         pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1590                 }
1591         }
1592 }
1593
1594 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1595                                       struct txpower_info_2g *pwrinfo24g,
1596                                       struct txpower_info_5g *pwrinfo5g,
1597                                       bool autoload_fail, u8 *hwinfo)
1598 {
1599         struct rtl_priv *rtlpriv = rtl_priv(hw);
1600         u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1601
1602         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1603                  "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1604                  (eeaddr+1), hwinfo[eeaddr+1]);
1605         if (0xFF == hwinfo[eeaddr+1])  /*YJ,add,120316*/
1606                 autoload_fail = true;
1607
1608         if (autoload_fail) {
1609                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1610                          "auto load fail : Use Default value!\n");
1611                 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1612                         /* 2.4G default value */
1613                         set_24g_base(pwrinfo24g, rfpath);
1614                 }
1615                 return;
1616         }
1617
1618         for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1619                 /*2.4G default value*/
1620                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1621                         pwrinfo24g->index_cck_base[rfpath][group] =
1622                           hwinfo[eeaddr++];
1623                         if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1624                                 pwrinfo24g->index_cck_base[rfpath][group] =
1625                                   0x2D;
1626                 }
1627                 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1628                         pwrinfo24g->index_bw40_base[rfpath][group] =
1629                                 hwinfo[eeaddr++];
1630                         if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1631                                 pwrinfo24g->index_bw40_base[rfpath][group] =
1632                                         0x2D;
1633                 }
1634                 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1635                 if (hwinfo[eeaddr] == 0xFF) {
1636                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1637                 } else {
1638                         pwrinfo24g->bw20_diff[rfpath][0] =
1639                                 (hwinfo[eeaddr]&0xf0)>>4;
1640                         /*bit sign number to 8 bit sign number*/
1641                         if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1642                                 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1643                 }
1644
1645                 if (hwinfo[eeaddr] == 0xFF) {
1646                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1647                 } else {
1648                         pwrinfo24g->ofdm_diff[rfpath][0] =
1649                                 (hwinfo[eeaddr]&0x0f);
1650                                 /*bit sign number to 8 bit sign number*/
1651                         if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1652                                 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1653                 }
1654                 pwrinfo24g->cck_diff[rfpath][0] = 0;
1655                 eeaddr++;
1656                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1657                         if (hwinfo[eeaddr] == 0xFF) {
1658                                 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1659                         } else {
1660                                 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1661                                   (hwinfo[eeaddr]&0xf0)>>4;
1662                                 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1663                                     BIT(3))
1664                                         pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1665                                           0xF0;
1666                         }
1667
1668                         if (hwinfo[eeaddr] == 0xFF) {
1669                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1670                                         0xFE;
1671                         } else {
1672                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1673                                   (hwinfo[eeaddr]&0x0f);
1674                                 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1675                                     BIT(3))
1676                                         pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1677                                           0xF0;
1678                         }
1679                         eeaddr++;
1680
1681                         if (hwinfo[eeaddr] == 0xFF) {
1682                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1683                         } else {
1684                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1685                                   (hwinfo[eeaddr]&0xf0)>>4;
1686                                 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1687                                     BIT(3))
1688                                         pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1689                                           0xF0;
1690                         }
1691
1692                         if (hwinfo[eeaddr] == 0xFF) {
1693                                 pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1694                         } else {
1695                                 pwrinfo24g->cck_diff[rfpath][txcnt] =
1696                                   (hwinfo[eeaddr]&0x0f);
1697                                 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1698                                     BIT(3))
1699                                         pwrinfo24g->cck_diff[rfpath][txcnt] |=
1700                                           0xF0;
1701                         }
1702                         eeaddr++;
1703                 }
1704
1705                 /*5G default value*/
1706                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1707                         pwrinfo5g->index_bw40_base[rfpath][group] =
1708                                 hwinfo[eeaddr++];
1709                         if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1710                                 pwrinfo5g->index_bw40_base[rfpath][group] =
1711                                   0xFE;
1712                 }
1713
1714                 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1715
1716                 if (hwinfo[eeaddr] == 0xFF) {
1717                         pwrinfo5g->bw20_diff[rfpath][0] = 0;
1718                 } else {
1719                         pwrinfo5g->bw20_diff[rfpath][0] =
1720                           (hwinfo[eeaddr]&0xf0)>>4;
1721                         if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1722                                 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1723                 }
1724
1725                 if (hwinfo[eeaddr] == 0xFF) {
1726                         pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1727                 } else {
1728                         pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1729                         if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1730                                 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1731                 }
1732                 eeaddr++;
1733                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1734                         if (hwinfo[eeaddr] == 0xFF) {
1735                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =   0xFE;
1736                         } else {
1737                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1738                                   (hwinfo[eeaddr]&0xf0)>>4;
1739                                 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1740                                     BIT(3))
1741                                         pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1742                                           0xF0;
1743                         }
1744
1745                         if (hwinfo[eeaddr] == 0xFF) {
1746                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =   0xFE;
1747                         } else {
1748                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1749                                   (hwinfo[eeaddr]&0x0f);
1750                                 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1751                                     BIT(3))
1752                                         pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1753                                           0xF0;
1754                         }
1755                         eeaddr++;
1756                 }
1757
1758                 if (hwinfo[eeaddr] == 0xFF) {
1759                         pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1760                         pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1761                 } else {
1762                         pwrinfo5g->ofdm_diff[rfpath][1] =
1763                                         (hwinfo[eeaddr]&0xf0)>>4;
1764                         pwrinfo5g->ofdm_diff[rfpath][2] =
1765                                         (hwinfo[eeaddr]&0x0f);
1766                 }
1767                 eeaddr++;
1768
1769                 if (hwinfo[eeaddr] == 0xFF)
1770                         pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1771                 else
1772                         pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1773                 eeaddr++;
1774
1775                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1776                         if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1777                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] =   0xFE;
1778                         else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1779                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1780                 }
1781         }
1782 }
1783
1784 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1785                                                  bool autoload_fail,
1786                                                  u8 *hwinfo)
1787 {
1788         struct rtl_priv *rtlpriv = rtl_priv(hw);
1789         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1790         struct txpower_info_2g pwrinfo24g;
1791         struct txpower_info_5g pwrinfo5g;
1792         u8 rf_path, index;
1793         u8 i;
1794
1795         read_power_value_fromprom(hw, &pwrinfo24g,
1796                                   &pwrinfo5g, autoload_fail, hwinfo);
1797
1798         for (rf_path = 0; rf_path < 2; rf_path++) {
1799                 for (i = 0; i < 14; i++) {
1800                         index = _rtl88e_get_chnl_group(i+1);
1801
1802                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1803                                 pwrinfo24g.index_cck_base[rf_path][index];
1804                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1805                                 pwrinfo24g.index_bw40_base[rf_path][index];
1806                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1807                                 pwrinfo24g.bw20_diff[rf_path][0];
1808                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1809                                 pwrinfo24g.ofdm_diff[rf_path][0];
1810                 }
1811
1812                 for (i = 0; i < 14; i++) {
1813                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1814                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1815                                 rf_path, i,
1816                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1817                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1818                 }
1819         }
1820
1821         if (!autoload_fail)
1822                 rtlefuse->eeprom_thermalmeter =
1823                         hwinfo[EEPROM_THERMAL_METER_88E];
1824         else
1825                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1826
1827         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1828                 rtlefuse->apk_thermalmeterignore = true;
1829                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1830         }
1831
1832         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1833         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1834                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1835
1836         if (!autoload_fail) {
1837                 rtlefuse->eeprom_regulatory =
1838                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1839                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1840                         rtlefuse->eeprom_regulatory = 0;
1841         } else {
1842                 rtlefuse->eeprom_regulatory = 0;
1843         }
1844         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1845                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1846 }
1847
1848 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1849 {
1850         struct rtl_priv *rtlpriv = rtl_priv(hw);
1851         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1852         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1853         u16 i, usvalue;
1854         u8 hwinfo[HWSET_MAX_SIZE];
1855         u16 eeprom_id;
1856
1857         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1858                 rtl_efuse_shadow_map_update(hw);
1859
1860                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1861                        HWSET_MAX_SIZE);
1862         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1863                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1864                          "RTL819X Not boot from eeprom, check it !!");
1865                 return;
1866         } else {
1867                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1868                          "boot from neither eeprom nor efuse, check it !!");
1869                 return;
1870         }
1871
1872         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
1873                       hwinfo, HWSET_MAX_SIZE);
1874
1875         eeprom_id = *((u16 *)&hwinfo[0]);
1876         if (eeprom_id != RTL8188E_EEPROM_ID) {
1877                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1878                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1879                 rtlefuse->autoload_failflag = true;
1880         } else {
1881                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1882                 rtlefuse->autoload_failflag = false;
1883         }
1884
1885         if (rtlefuse->autoload_failflag == true)
1886                 return;
1887         /*VID DID SVID SDID*/
1888         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1889         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1890         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1891         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1892         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1893                  "EEPROMId = 0x%4x\n", eeprom_id);
1894         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1895                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1896         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1897                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1898         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1899                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1900         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1901                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1902         /*customer ID*/
1903         rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
1904         if (rtlefuse->eeprom_oemid == 0xFF)
1905                 rtlefuse->eeprom_oemid =        0;
1906
1907         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1908                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1909         /*EEPROM version*/
1910         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1911         /*mac address*/
1912         for (i = 0; i < 6; i += 2) {
1913                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1914                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1915         }
1916
1917         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1918                  "dev_addr: %pM\n", rtlefuse->dev_addr);
1919         /*channel plan */
1920         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1921         /* set channel paln to world wide 13 */
1922         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1923         /*tx power*/
1924         _rtl88ee_read_txpower_info_from_hwpg(hw,
1925                                              rtlefuse->autoload_failflag,
1926                                              hwinfo);
1927         rtlefuse->txpwr_fromeprom = true;
1928
1929         rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1930                                                  rtlefuse->autoload_failflag,
1931                                                  hwinfo);
1932
1933         /*board type*/
1934         rtlefuse->board_type =
1935                 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1936         rtlhal->board_type = rtlefuse->board_type;
1937         /*Wake on wlan*/
1938         rtlefuse->wowlan_enable =
1939                 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1940         /*parse xtal*/
1941         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1942         if (hwinfo[EEPROM_XTAL_88E])
1943                 rtlefuse->crystalcap = 0x20;
1944         /*antenna diversity*/
1945         rtlefuse->antenna_div_cfg =
1946                 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1947         if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1948                 rtlefuse->antenna_div_cfg = 0;
1949         if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1950             rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1951                 rtlefuse->antenna_div_cfg = 0;
1952
1953         rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1954         if (rtlefuse->antenna_div_type == 0xFF)
1955                 rtlefuse->antenna_div_type = 0x01;
1956         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1957                 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1958                 rtlefuse->antenna_div_cfg = 1;
1959
1960         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1961                 switch (rtlefuse->eeprom_oemid) {
1962                 case EEPROM_CID_DEFAULT:
1963                         if (rtlefuse->eeprom_did == 0x8179) {
1964                                 if (rtlefuse->eeprom_svid == 0x1025) {
1965                                         rtlhal->oem_id = RT_CID_819X_ACER;
1966                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1967                                      rtlefuse->eeprom_smid == 0x0179) ||
1968                                      (rtlefuse->eeprom_svid == 0x17AA &&
1969                                      rtlefuse->eeprom_smid == 0x0179)) {
1970                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
1971                                 } else if (rtlefuse->eeprom_svid == 0x103c &&
1972                                            rtlefuse->eeprom_smid == 0x197d) {
1973                                         rtlhal->oem_id = RT_CID_819X_HP;
1974                                 } else {
1975                                         rtlhal->oem_id = RT_CID_DEFAULT;
1976                                 }
1977                         } else {
1978                                 rtlhal->oem_id = RT_CID_DEFAULT;
1979                         }
1980                         break;
1981                 case EEPROM_CID_TOSHIBA:
1982                         rtlhal->oem_id = RT_CID_TOSHIBA;
1983                         break;
1984                 case EEPROM_CID_QMI:
1985                         rtlhal->oem_id = RT_CID_819X_QMI;
1986                         break;
1987                 case EEPROM_CID_WHQL:
1988                 default:
1989                         rtlhal->oem_id = RT_CID_DEFAULT;
1990                         break;
1991
1992                 }
1993         }
1994 }
1995
1996 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1997 {
1998         struct rtl_priv *rtlpriv = rtl_priv(hw);
1999         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2000         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2001
2002         pcipriv->ledctl.led_opendrain = true;
2003
2004         switch (rtlhal->oem_id) {
2005         case RT_CID_819X_HP:
2006                 pcipriv->ledctl.led_opendrain = true;
2007                 break;
2008         case RT_CID_819X_LENOVO:
2009         case RT_CID_DEFAULT:
2010         case RT_CID_TOSHIBA:
2011         case RT_CID_CCX:
2012         case RT_CID_819X_ACER:
2013         case RT_CID_WHQL:
2014         default:
2015                 break;
2016         }
2017         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2018                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2019 }
2020
2021 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
2022 {
2023         struct rtl_priv *rtlpriv = rtl_priv(hw);
2024         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2025         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2026         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2027         u8 tmp_u1b;
2028
2029         rtlhal->version = _rtl88ee_read_chip_version(hw);
2030         if (get_rf_type(rtlphy) == RF_1T1R)
2031                 rtlpriv->dm.rfpath_rxenable[0] = true;
2032         else
2033                 rtlpriv->dm.rfpath_rxenable[0] =
2034                     rtlpriv->dm.rfpath_rxenable[1] = true;
2035         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2036                                                 rtlhal->version);
2037         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2038         if (tmp_u1b & BIT(4)) {
2039                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2040                 rtlefuse->epromtype = EEPROM_93C46;
2041         } else {
2042                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2043                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2044         }
2045         if (tmp_u1b & BIT(5)) {
2046                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2047                 rtlefuse->autoload_failflag = false;
2048                 _rtl88ee_read_adapter_info(hw);
2049         } else {
2050                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2051         }
2052         _rtl88ee_hal_customized_behavior(hw);
2053 }
2054
2055 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
2056                 struct ieee80211_sta *sta)
2057 {
2058         struct rtl_priv *rtlpriv = rtl_priv(hw);
2059         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2060         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2061         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2062         u32 ratr_value;
2063         u8 ratr_index = 0;
2064         u8 b_nmode = mac->ht_enable;
2065         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2066         u16 shortgi_rate;
2067         u32 tmp_ratr_value;
2068         u8 curtxbw_40mhz = mac->bw_40;
2069         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2070                                 1 : 0;
2071         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2072                                 1 : 0;
2073         enum wireless_mode wirelessmode = mac->mode;
2074         u32 ratr_mask;
2075
2076         if (rtlhal->current_bandtype == BAND_ON_5G)
2077                 ratr_value = sta->supp_rates[1] << 4;
2078         else
2079                 ratr_value = sta->supp_rates[0];
2080         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2081                 ratr_value = 0xfff;
2082         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2083                        sta->ht_cap.mcs.rx_mask[0] << 12);
2084         switch (wirelessmode) {
2085         case WIRELESS_MODE_B:
2086                 if (ratr_value & 0x0000000c)
2087                         ratr_value &= 0x0000000d;
2088                 else
2089                         ratr_value &= 0x0000000f;
2090                 break;
2091         case WIRELESS_MODE_G:
2092                 ratr_value &= 0x00000FF5;
2093                 break;
2094         case WIRELESS_MODE_N_24G:
2095         case WIRELESS_MODE_N_5G:
2096                 b_nmode = 1;
2097                 if (get_rf_type(rtlphy) == RF_1T2R ||
2098                     get_rf_type(rtlphy) == RF_1T1R)
2099                         ratr_mask = 0x000ff005;
2100                 else
2101                         ratr_mask = 0x0f0ff005;
2102
2103                 ratr_value &= ratr_mask;
2104                 break;
2105         default:
2106                 if (rtlphy->rf_type == RF_1T2R)
2107                         ratr_value &= 0x000ff0ff;
2108                 else
2109                         ratr_value &= 0x0f0ff0ff;
2110
2111                 break;
2112         }
2113
2114         if ((rtlpriv->btcoexist.bt_coexistence) &&
2115             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2116             (rtlpriv->btcoexist.bt_cur_state) &&
2117             (rtlpriv->btcoexist.bt_ant_isolation) &&
2118             ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2119              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2120                 ratr_value &= 0x0fffcfc0;
2121         else
2122                 ratr_value &= 0x0FFFFFFF;
2123
2124         if (b_nmode &&
2125             ((curtxbw_40mhz && curshortgi_40mhz) ||
2126              (!curtxbw_40mhz && curshortgi_20mhz))) {
2127                 ratr_value |= 0x10000000;
2128                 tmp_ratr_value = (ratr_value >> 12);
2129
2130                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2131                         if ((1 << shortgi_rate) & tmp_ratr_value)
2132                                 break;
2133                 }
2134
2135                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2136                     (shortgi_rate << 4) | (shortgi_rate);
2137         }
2138
2139         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2140
2141         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2142                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2143 }
2144
2145 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2146                 struct ieee80211_sta *sta, u8 rssi_level)
2147 {
2148         struct rtl_priv *rtlpriv = rtl_priv(hw);
2149         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2150         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2151         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2152         struct rtl_sta_info *sta_entry = NULL;
2153         u32 ratr_bitmap;
2154         u8 ratr_index;
2155         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2156                                 ? 1 : 0;
2157         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2158                                 1 : 0;
2159         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2160                                 1 : 0;
2161         enum wireless_mode wirelessmode = 0;
2162         bool b_shortgi = false;
2163         u8 rate_mask[5];
2164         u8 macid = 0;
2165         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2166
2167         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2168         wirelessmode = sta_entry->wireless_mode;
2169         if (mac->opmode == NL80211_IFTYPE_STATION ||
2170                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2171                 curtxbw_40mhz = mac->bw_40;
2172         else if (mac->opmode == NL80211_IFTYPE_AP ||
2173                 mac->opmode == NL80211_IFTYPE_ADHOC)
2174                 macid = sta->aid + 1;
2175
2176         if (rtlhal->current_bandtype == BAND_ON_5G)
2177                 ratr_bitmap = sta->supp_rates[1] << 4;
2178         else
2179                 ratr_bitmap = sta->supp_rates[0];
2180         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2181                 ratr_bitmap = 0xfff;
2182         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2183                         sta->ht_cap.mcs.rx_mask[0] << 12);
2184         switch (wirelessmode) {
2185         case WIRELESS_MODE_B:
2186                 ratr_index = RATR_INX_WIRELESS_B;
2187                 if (ratr_bitmap & 0x0000000c)
2188                         ratr_bitmap &= 0x0000000d;
2189                 else
2190                         ratr_bitmap &= 0x0000000f;
2191                 break;
2192         case WIRELESS_MODE_G:
2193                 ratr_index = RATR_INX_WIRELESS_GB;
2194
2195                 if (rssi_level == 1)
2196                         ratr_bitmap &= 0x00000f00;
2197                 else if (rssi_level == 2)
2198                         ratr_bitmap &= 0x00000ff0;
2199                 else
2200                         ratr_bitmap &= 0x00000ff5;
2201                 break;
2202         case WIRELESS_MODE_N_24G:
2203         case WIRELESS_MODE_N_5G:
2204                 ratr_index = RATR_INX_WIRELESS_NGB;
2205                 if (rtlphy->rf_type == RF_1T2R ||
2206                     rtlphy->rf_type == RF_1T1R) {
2207                         if (curtxbw_40mhz) {
2208                                 if (rssi_level == 1)
2209                                         ratr_bitmap &= 0x000f0000;
2210                                 else if (rssi_level == 2)
2211                                         ratr_bitmap &= 0x000ff000;
2212                                 else
2213                                         ratr_bitmap &= 0x000ff015;
2214                         } else {
2215                                 if (rssi_level == 1)
2216                                         ratr_bitmap &= 0x000f0000;
2217                                 else if (rssi_level == 2)
2218                                         ratr_bitmap &= 0x000ff000;
2219                                 else
2220                                         ratr_bitmap &= 0x000ff005;
2221                         }
2222                 } else {
2223                         if (curtxbw_40mhz) {
2224                                 if (rssi_level == 1)
2225                                         ratr_bitmap &= 0x0f8f0000;
2226                                 else if (rssi_level == 2)
2227                                         ratr_bitmap &= 0x0f8ff000;
2228                                 else
2229                                         ratr_bitmap &= 0x0f8ff015;
2230                         } else {
2231                                 if (rssi_level == 1)
2232                                         ratr_bitmap &= 0x0f8f0000;
2233                                 else if (rssi_level == 2)
2234                                         ratr_bitmap &= 0x0f8ff000;
2235                                 else
2236                                         ratr_bitmap &= 0x0f8ff005;
2237                         }
2238                 }
2239                 /*}*/
2240
2241                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2242                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2243
2244                         if (macid == 0)
2245                                 b_shortgi = true;
2246                         else if (macid == 1)
2247                                 b_shortgi = false;
2248                 }
2249                 break;
2250         default:
2251                 ratr_index = RATR_INX_WIRELESS_NGB;
2252
2253                 if (rtlphy->rf_type == RF_1T2R)
2254                         ratr_bitmap &= 0x000ff0ff;
2255                 else
2256                         ratr_bitmap &= 0x0f0ff0ff;
2257                 break;
2258         }
2259         sta_entry->ratr_index = ratr_index;
2260
2261         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2262                  "ratr_bitmap :%x\n", ratr_bitmap);
2263         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2264                              (ratr_index << 28);
2265         rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2266         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2267                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2268                  ratr_index, ratr_bitmap,
2269                  rate_mask[0], rate_mask[1],
2270                  rate_mask[2], rate_mask[3],
2271                  rate_mask[4]);
2272         rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2273         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2274 }
2275
2276 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2277                 struct ieee80211_sta *sta, u8 rssi_level)
2278 {
2279         struct rtl_priv *rtlpriv = rtl_priv(hw);
2280
2281         if (rtlpriv->dm.useramask)
2282                 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level);
2283         else
2284                 rtl88ee_update_hal_rate_table(hw, sta);
2285 }
2286
2287 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2288 {
2289         struct rtl_priv *rtlpriv = rtl_priv(hw);
2290         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2291         u16 sifs_timer;
2292
2293         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2294         if (!mac->ht_enable)
2295                 sifs_timer = 0x0a0a;
2296         else
2297                 sifs_timer = 0x0e0e;
2298         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2299 }
2300
2301 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2302 {
2303         struct rtl_priv *rtlpriv = rtl_priv(hw);
2304         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2305         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2306         u32 u4tmp;
2307         bool b_actuallyset = false;
2308
2309         if (rtlpriv->rtlhal.being_init_adapter)
2310                 return false;
2311
2312         if (ppsc->swrf_processing)
2313                 return false;
2314
2315         spin_lock(&rtlpriv->locks.rf_ps_lock);
2316         if (ppsc->rfchange_inprogress) {
2317                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2318                 return false;
2319         } else {
2320                 ppsc->rfchange_inprogress = true;
2321                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2322         }
2323
2324         cur_rfstate = ppsc->rfpwr_state;
2325
2326         u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2327         e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2328
2329         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2330                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2331                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2332
2333                 e_rfpowerstate_toset = ERFON;
2334                 ppsc->hwradiooff = false;
2335                 b_actuallyset = true;
2336         } else if ((!ppsc->hwradiooff) &&
2337                    (e_rfpowerstate_toset == ERFOFF)) {
2338                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2339                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2340
2341                 e_rfpowerstate_toset = ERFOFF;
2342                 ppsc->hwradiooff = true;
2343                 b_actuallyset = true;
2344         }
2345
2346         if (b_actuallyset) {
2347                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2348                 ppsc->rfchange_inprogress = false;
2349                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2350         } else {
2351                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2352                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2353
2354                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2355                 ppsc->rfchange_inprogress = false;
2356                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2357         }
2358
2359         *valid = 1;
2360         return !ppsc->hwradiooff;
2361
2362 }
2363
2364 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2365                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2366                      bool is_wepkey, bool clear_all)
2367 {
2368         struct rtl_priv *rtlpriv = rtl_priv(hw);
2369         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2370         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2371         u8 *macaddr = p_macaddr;
2372         u32 entry_id = 0;
2373         bool is_pairwise = false;
2374         static u8 cam_const_addr[4][6] = {
2375                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2376                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2377                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2378                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2379         };
2380         static u8 cam_const_broad[] = {
2381                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2382         };
2383
2384         if (clear_all) {
2385                 u8 idx = 0;
2386                 u8 cam_offset = 0;
2387                 u8 clear_number = 5;
2388
2389                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2390
2391                 for (idx = 0; idx < clear_number; idx++) {
2392                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2393                         rtl_cam_empty_entry(hw, cam_offset + idx);
2394
2395                         if (idx < 5) {
2396                                 memset(rtlpriv->sec.key_buf[idx], 0,
2397                                        MAX_KEY_LEN);
2398                                 rtlpriv->sec.key_len[idx] = 0;
2399                         }
2400                 }
2401
2402         } else {
2403                 switch (enc_algo) {
2404                 case WEP40_ENCRYPTION:
2405                         enc_algo = CAM_WEP40;
2406                         break;
2407                 case WEP104_ENCRYPTION:
2408                         enc_algo = CAM_WEP104;
2409                         break;
2410                 case TKIP_ENCRYPTION:
2411                         enc_algo = CAM_TKIP;
2412                         break;
2413                 case AESCCMP_ENCRYPTION:
2414                         enc_algo = CAM_AES;
2415                         break;
2416                 default:
2417                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2418                                  "switch case not process\n");
2419                         enc_algo = CAM_TKIP;
2420                         break;
2421                 }
2422
2423                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2424                         macaddr = cam_const_addr[key_index];
2425                         entry_id = key_index;
2426                 } else {
2427                         if (is_group) {
2428                                 macaddr = cam_const_broad;
2429                                 entry_id = key_index;
2430                         } else {
2431                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2432                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2433                                         entry_id =
2434                                           rtl_cam_get_free_entry(hw, p_macaddr);
2435                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2436                                                 RT_TRACE(rtlpriv, COMP_SEC,
2437                                                          DBG_EMERG,
2438                                                          "Can not find free hw security cam entry\n");
2439                                                 return;
2440                                         }
2441                                 } else {
2442                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2443                                 }
2444                                 key_index = PAIRWISE_KEYIDX;
2445                                 is_pairwise = true;
2446                         }
2447                 }
2448
2449                 if (rtlpriv->sec.key_len[key_index] == 0) {
2450                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2451                                  "delete one entry, entry_id is %d\n",
2452                                  entry_id);
2453                         if (mac->opmode == NL80211_IFTYPE_AP ||
2454                                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2455                                 rtl_cam_del_entry(hw, p_macaddr);
2456                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2457                 } else {
2458                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2459                                  "add one entry\n");
2460                         if (is_pairwise) {
2461                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2462                                          "set Pairwise key\n");
2463
2464                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2465                                                       entry_id, enc_algo,
2466                                                       CAM_CONFIG_NO_USEDK,
2467                                                       rtlpriv->sec.key_buf[key_index]);
2468                         } else {
2469                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2470                                          "set group key\n");
2471
2472                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2473                                         rtl_cam_add_one_entry(hw,
2474                                                         rtlefuse->dev_addr,
2475                                                         PAIRWISE_KEYIDX,
2476                                                         CAM_PAIRWISE_KEY_POSITION,
2477                                                         enc_algo,
2478                                                         CAM_CONFIG_NO_USEDK,
2479                                                         rtlpriv->sec.key_buf
2480                                                         [entry_id]);
2481                                 }
2482
2483                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2484                                                       entry_id, enc_algo,
2485                                                       CAM_CONFIG_NO_USEDK,
2486                                                       rtlpriv->sec.key_buf[entry_id]);
2487                         }
2488
2489                 }
2490         }
2491 }
2492
2493 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2494 {
2495         struct rtl_priv *rtlpriv = rtl_priv(hw);
2496
2497         rtlpriv->btcoexist.bt_coexistence =
2498                 rtlpriv->btcoexist.eeprom_bt_coexist;
2499         rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2500         rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2501
2502         if (rtlpriv->btcoexist.reg_bt_iso == 2)
2503                 rtlpriv->btcoexist.bt_ant_isolation =
2504                                 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2505         else
2506                 rtlpriv->btcoexist.bt_ant_isolation =
2507                                 rtlpriv->btcoexist.reg_bt_iso;
2508
2509         rtlpriv->btcoexist.bt_radio_shared_type =
2510                 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2511
2512         if (rtlpriv->btcoexist.bt_coexistence) {
2513                 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2514                         rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2515                 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2516                         rtlpriv->btcoexist.bt_service = BT_SCO;
2517                 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2518                         rtlpriv->btcoexist.bt_service = BT_BUSY;
2519                 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2520                         rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2521                 else
2522                         rtlpriv->btcoexist.bt_service = BT_IDLE;
2523
2524                 rtlpriv->btcoexist.bt_edca_ul = 0;
2525                 rtlpriv->btcoexist.bt_edca_dl = 0;
2526                 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2527         }
2528 }
2529
2530 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2531                                               bool auto_load_fail, u8 *hwinfo)
2532 {
2533         struct rtl_priv *rtlpriv = rtl_priv(hw);
2534         u8 value;
2535
2536         if (!auto_load_fail) {
2537                 rtlpriv->btcoexist.eeprom_bt_coexist =
2538                         ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2539                 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2540                         rtlpriv->btcoexist.eeprom_bt_coexist  = 0;
2541                 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2542                 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2543                 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2544                 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2545                 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2546                                  ((value & 0x20) >> 5);
2547         } else {
2548                 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2549                 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2550                 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2551                 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2552                 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2553         }
2554
2555         rtl8188ee_bt_var_init(hw);
2556 }
2557
2558 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2559 {
2560         struct rtl_priv *rtlpriv = rtl_priv(hw);
2561
2562         /* 0:Low, 1:High, 2:From Efuse. */
2563         rtlpriv->btcoexist.reg_bt_iso = 2;
2564         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2565         rtlpriv->btcoexist.reg_bt_sco = 3;
2566         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2567         rtlpriv->btcoexist.reg_bt_sco = 0;
2568 }
2569
2570 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2571 {
2572         struct rtl_priv *rtlpriv = rtl_priv(hw);
2573         struct rtl_phy *rtlphy = &rtlpriv->phy;
2574         u8 u1_tmp;
2575
2576         if (rtlpriv->btcoexist.bt_coexistence &&
2577             ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2578               rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2579                 if (rtlpriv->btcoexist.bt_ant_isolation)
2580                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2581
2582                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2583                          BIT_OFFSET_LEN_MASK_32(0, 1);
2584                 u1_tmp = u1_tmp |
2585                          ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2586                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2587                          ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2588                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2589                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2590
2591                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2592                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2593                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2594
2595                 /* Config to 1T1R. */
2596                 if (rtlphy->rf_type == RF_1T1R) {
2597                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2598                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2599                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2600
2601                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2602                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2603                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2604                 }
2605         }
2606 }
2607
2608 void rtl88ee_suspend(struct ieee80211_hw *hw)
2609 {
2610 }
2611
2612 void rtl88ee_resume(struct ieee80211_hw *hw)
2613 {
2614 }