drivers/net/wireless/rtlwifi/rtl8188ee/rf.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "reg.h"
  32 #include "def.h"
  33 #include "phy.h"
  34 #include "rf.h"
  35 #include "dm.h"
  36
  37 void rtl88e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
  38 {
  39         struct rtl_priv *rtlpriv = rtl_priv(hw);
  40         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  41
  42         switch (bandwidth) {
  43         case HT_CHANNEL_WIDTH_20:
  44                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  45                                              0xfffff3ff) | BIT(10) | BIT(11));
  46                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  47                               rtlphy->rfreg_chnlval[0]);
  48                 break;
  49         case HT_CHANNEL_WIDTH_20_40:
  50                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  51                                              0xfffff3ff) | BIT(10));
  52                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  53                               rtlphy->rfreg_chnlval[0]);
  54                 break;
  55         default:
  56                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  57                          "unknown bandwidth: %#X\n", bandwidth);
  58                 break;
  59         }
  60 }
  61
  62 void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
  63                                        u8 *plevel)
  64 {
  65         struct rtl_priv *rtlpriv = rtl_priv(hw);
  66         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  67         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  68         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  69         u32 tx_agc[2] = {0, 0}, tmpval;
  70         bool turbo_scanoff = false;
  71         u8 idx1, idx2;
  72         u8 *ptr;
  73         u8 direction;
  74         u32 pwrtrac_value;
  75
  76         if (rtlefuse->eeprom_regulatory != 0)
  77                 turbo_scanoff = true;
  78
  79         if (mac->act_scanning == true) {
  80                 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
  81                 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
  82
  83                 if (turbo_scanoff) {
  84                         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  85                                 tx_agc[idx1] = plevel[idx1] |
  86                                                (plevel[idx1] << 8) |
  87                                                (plevel[idx1] << 16) |
  88                                                (plevel[idx1] << 24);
  89                         }
  90                 }
  91         } else {
  92                 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  93                         tx_agc[idx1] = plevel[idx1] | (plevel[idx1] << 8) |
  94                                        (plevel[idx1] << 16) |
  95                                        (plevel[idx1] << 24);
  96                 }
  97
  98                 if (rtlefuse->eeprom_regulatory == 0) {
  99                         tmpval = (rtlphy->mcs_offset[0][6]) +
 100                                  (rtlphy->mcs_offset[0][7] << 8);
 101                         tx_agc[RF90_PATH_A] += tmpval;
 102
 103                         tmpval = (rtlphy->mcs_offset[0][14]) +
 104                                  (rtlphy->mcs_offset[0][15] << 24);
 105                         tx_agc[RF90_PATH_B] += tmpval;
 106                 }
 107         }
 108
 109         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
 110                 ptr = (u8 *)(&(tx_agc[idx1]));
 111                 for (idx2 = 0; idx2 < 4; idx2++) {
 112                         if (*ptr > RF6052_MAX_TX_PWR)
 113                                 *ptr = RF6052_MAX_TX_PWR;
 114                         ptr++;
 115                 }
 116         }
 117         rtl88e_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
 118         if (direction == 1) {
 119                 tx_agc[0] += pwrtrac_value;
 120                 tx_agc[1] += pwrtrac_value;
 121         } else if (direction == 2) {
 122                 tx_agc[0] -= pwrtrac_value;
 123                 tx_agc[1] -= pwrtrac_value;
 124         }
 125         tmpval = tx_agc[RF90_PATH_A] & 0xff;
 126         rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
 127
 128         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 129                 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 130                 RTXAGC_A_CCK1_MCS32);
 131
 132         tmpval = tx_agc[RF90_PATH_A] >> 8;
 133
 134         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 135
 136         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 137                 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 138                  RTXAGC_B_CCK11_A_CCK2_11);
 139
 140         tmpval = tx_agc[RF90_PATH_B] >> 24;
 141         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
 142
 143         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 144                 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 145                  RTXAGC_B_CCK11_A_CCK2_11);
 146
 147         tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
 148         rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
 149
 150         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 151                 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 152                  RTXAGC_B_CCK1_55_MCS32);
 153 }
 154
 155 static void rtl88e_phy_get_power_base(struct ieee80211_hw *hw,
 156                                       u8 *pwrlvlofdm, u8 *pwrlvlbw20,
 157                                       u8 *pwrlvlbw40, u8 channel,
 158                                       u32 *ofdmbase, u32 *mcsbase)
 159 {
 160         struct rtl_priv *rtlpriv = rtl_priv(hw);
 161         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 162         u32 base0, base1;
 163         u8 i, powerlevel[2];
 164
 165         for (i = 0; i < 2; i++) {
 166                 base0 = pwrlvlofdm[i];
 167
 168                 base0 = (base0 << 24) | (base0 << 16) |
 169                              (base0 << 8) | base0;
 170                 *(ofdmbase + i) = base0;
 171                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 172                         "[OFDM power base index rf(%c) = 0x%x]\n",
 173                         ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
 174         }
 175
 176         for (i = 0; i < 2; i++) {
 177                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
 178                         powerlevel[i] = pwrlvlbw20[i];
 179                 else
 180                         powerlevel[i] = pwrlvlbw40[i];
 181                 base1 = powerlevel[i];
 182                 base1 = (base1 << 24) |
 183                     (base1 << 16) | (base1 << 8) | base1;
 184
 185                 *(mcsbase + i) = base1;
 186
 187                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 188                         "[MCS power base index rf(%c) = 0x%x]\n",
 189                         ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
 190         }
 191 }
 192
 193 static void get_txpwr_by_reg(struct ieee80211_hw *hw, u8 chan, u8 index,
 194                              u32 *base0, u32 *base1, u32 *outval)
 195 {
 196         struct rtl_priv *rtlpriv = rtl_priv(hw);
 197         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 198         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 199         u8 i, chg = 0, pwr_lim[4], pwr_diff = 0, cust_pwr_dif;
 200         u32 writeval, cust_lim, rf, tmp;
 201         u8 ch = chan - 1;
 202         u8 j;
 203
 204         for (rf = 0; rf < 2; rf++) {
 205                 j = index + (rf ? 8 : 0);
 206                 tmp = ((index < 2) ? base0[rf] : base1[rf]);
 207                 switch (rtlefuse->eeprom_regulatory) {
 208                 case 0:
 209                         chg = 0;
 210
 211                         writeval = rtlphy->mcs_offset[chg][j] + tmp;
 212
 213                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 214                                 "RTK better performance, "
 215                                 "writeval(%c) = 0x%x\n",
 216                                 ((rf == 0) ? 'A' : 'B'), writeval);
 217                         break;
 218                 case 1:
 219                         if (rtlphy->pwrgroup_cnt == 1) {
 220                                 chg = 0;
 221                         } else {
 222                                 chg = chan / 3;
 223                                 if (chan == 14)
 224                                         chg = 5;
 225                         }
 226                         writeval = rtlphy->mcs_offset[chg][j] + tmp;
 227
 228                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 229                                 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
 230                                  ((rf == 0) ? 'A' : 'B'), writeval);
 231                         break;
 232                 case 2:
 233                         writeval = ((index < 2) ? base0[rf] : base1[rf]);
 234
 235                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 236                                 "Better regulatory, writeval(%c) = 0x%x\n",
 237                                  ((rf == 0) ? 'A' : 'B'), writeval);
 238                         break;
 239                 case 3:
 240                         chg = 0;
 241
 242                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
 243                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 244                                         "customer's limit, 40MHz rf(%c) = 0x%x\n",
 245                                          ((rf == 0) ? 'A' : 'B'),
 246                                          rtlefuse->pwrgroup_ht40[rf][ch]);
 247                         } else {
 248                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 249                                         "customer's limit, 20MHz rf(%c) = 0x%x\n",
 250                                          ((rf == 0) ? 'A' : 'B'),
 251                                          rtlefuse->pwrgroup_ht20[rf][ch]);
 252                         }
 253
 254                         if (index < 2)
 255                                 pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][ch];
 256                         else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
 257                                 pwr_diff = rtlefuse->txpwr_ht20diff[rf][ch];
 258
 259                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
 260                                 cust_pwr_dif = rtlefuse->pwrgroup_ht40[rf][ch];
 261                         else
 262                                 cust_pwr_dif = rtlefuse->pwrgroup_ht20[rf][ch];
 263
 264                         if (pwr_diff > cust_pwr_dif)
 265                                 pwr_diff = 0;
 266                         else
 267                                 pwr_diff = cust_pwr_dif - pwr_diff;
 268
 269                         for (i = 0; i < 4; i++) {
 270                                 pwr_lim[i] = (u8)((rtlphy->mcs_offset[chg][j] &
 271                                              (0x7f << (i * 8))) >> (i * 8));
 272
 273                                 if (pwr_lim[i] > pwr_diff)
 274                                         pwr_lim[i] = pwr_diff;
 275                         }
 276
 277                         cust_lim = (pwr_lim[3] << 24) | (pwr_lim[2] << 16) |
 278                                    (pwr_lim[1] << 8) | (pwr_lim[0]);
 279
 280                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 281                                 "Customer's limit rf(%c) = 0x%x\n",
 282                                 ((rf == 0) ? 'A' : 'B'), cust_lim);
 283
 284                         writeval = cust_lim + tmp;
 285
 286                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 287                                 "Customer, writeval rf(%c) = 0x%x\n",
 288                                 ((rf == 0) ? 'A' : 'B'), writeval);
 289                         break;
 290                 default:
 291                         chg = 0;
 292                         writeval = rtlphy->mcs_offset[chg][j] + tmp;
 293
 294                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 295                                 "RTK better performance, writeval "
 296                                 "rf(%c) = 0x%x\n",
 297                                 ((rf == 0) ? 'A' : 'B'), writeval);
 298                         break;
 299                 }
 300
 301                 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
 302                         writeval = writeval - 0x06060606;
 303                 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 304                          TXHIGHPWRLEVEL_BT2)
 305                         writeval -= 0x0c0c0c0c;
 306                 *(outval + rf) = writeval;
 307         }
 308 }
 309
 310 static void write_ofdm_pwr(struct ieee80211_hw *hw, u8 index, u32 *pvalue)
 311 {
 312         struct rtl_priv *rtlpriv = rtl_priv(hw);
 313         u16 regoffset_a[6] = {
 314                 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
 315                 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
 316                 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
 317         };
 318         u16 regoffset_b[6] = {
 319                 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
 320                 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
 321                 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
 322         };
 323         u8 i, rf, pwr_val[4];
 324         u32 writeval;
 325         u16 regoffset;
 326
 327         for (rf = 0; rf < 2; rf++) {
 328                 writeval = pvalue[rf];
 329                 for (i = 0; i < 4; i++) {
 330                         pwr_val[i] = (u8) ((writeval & (0x7f <<
 331                                      (i * 8))) >> (i * 8));
 332
 333                         if (pwr_val[i] > RF6052_MAX_TX_PWR)
 334                                 pwr_val[i] = RF6052_MAX_TX_PWR;
 335                 }
 336                 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
 337                            (pwr_val[1] << 8) | pwr_val[0];
 338
 339                 if (rf == 0)
 340                         regoffset = regoffset_a[index];
 341                 else
 342                         regoffset = regoffset_b[index];
 343                 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
 344
 345                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 346                         "Set 0x%x = %08x\n", regoffset, writeval);
 347         }
 348 }
 349
 350 void rtl88e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
 351                                         u8 *pwrlvlofdm,
 352                                         u8 *pwrlvlbw20,
 353                                         u8 *pwrlvlbw40, u8 chan)
 354 {
 355         u32 writeval[2], base0[2], base1[2];
 356         u8 index;
 357         u8 direction;
 358         u32 pwrtrac_value;
 359
 360         rtl88e_phy_get_power_base(hw, pwrlvlofdm, pwrlvlbw20,
 361                                   pwrlvlbw40, chan, &base0[0],
 362                                   &base1[0]);
 363
 364         rtl88e_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
 365
 366         for (index = 0; index < 6; index++) {
 367                 get_txpwr_by_reg(hw, chan, index, &base0[0], &base1[0],
 368                                  &writeval[0]);
 369                 if (direction == 1) {
 370                         writeval[0] += pwrtrac_value;
 371                         writeval[1] += pwrtrac_value;
 372                 } else if (direction == 2) {
 373                         writeval[0] -= pwrtrac_value;
 374                         writeval[1] -= pwrtrac_value;
 375                 }
 376                 write_ofdm_pwr(hw, index, &writeval[0]);
 377         }
 378 }
 379
 380 static bool rf6052_conf_para(struct ieee80211_hw *hw)
 381 {
 382         struct rtl_priv *rtlpriv = rtl_priv(hw);
 383         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 384         u32 u4val = 0;
 385         u8 rfpath;
 386         bool rtstatus = true;
 387         struct bb_reg_def *pphyreg;
 388
 389         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
 390                 pphyreg = &rtlphy->phyreg_def[rfpath];
 391
 392                 switch (rfpath) {
 393                 case RF90_PATH_A:
 394                 case RF90_PATH_C:
 395                         u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
 396                                                     BRFSI_RFENV);
 397                         break;
 398                 case RF90_PATH_B:
 399                 case RF90_PATH_D:
 400                         u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
 401                                                     BRFSI_RFENV << 16);
 402                         break;
 403                 }
 404
 405                 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
 406                 udelay(1);
 407
 408                 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
 409                 udelay(1);
 410
 411                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
 412                               B3WIREADDREAALENGTH, 0x0);
 413                 udelay(1);
 414
 415                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
 416                 udelay(1);
 417
 418                 switch (rfpath) {
 419                 case RF90_PATH_A:
 420                         rtstatus = rtl88e_phy_config_rf_with_headerfile(hw,
 421                                         (enum radio_path)rfpath);
 422                         break;
 423                 case RF90_PATH_B:
 424                         rtstatus = rtl88e_phy_config_rf_with_headerfile(hw,
 425                                         (enum radio_path)rfpath);
 426                         break;
 427                 case RF90_PATH_C:
 428                         break;
 429                 case RF90_PATH_D:
 430                         break;
 431                 }
 432
 433                 switch (rfpath) {
 434                 case RF90_PATH_A:
 435                 case RF90_PATH_C:
 436                         rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, u4val);
 437                         break;
 438                 case RF90_PATH_B:
 439                 case RF90_PATH_D:
 440                         rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
 441                                       u4val);
 442                         break;
 443                 }
 444
 445                 if (rtstatus != true) {
 446                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 447                                  "Radio[%d] Fail!!", rfpath);
 448                         return false;
 449                 }
 450         }
 451
 452         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
 453         return rtstatus;
 454 }
 455
 456 bool rtl88e_phy_rf6052_config(struct ieee80211_hw *hw)
 457 {
 458         struct rtl_priv *rtlpriv = rtl_priv(hw);
 459         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 460
 461         if (rtlphy->rf_type == RF_1T1R)
 462                 rtlphy->num_total_rfpath = 1;
 463         else
 464                 rtlphy->num_total_rfpath = 2;
 465
 466         return rf6052_conf_para(hw);
 467 }