drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8192c/fw_common.h"
  41 #include "dm.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 #define LLT_CONFIG      5
  46
  47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  48                                       u8 set_bits, u8 clear_bits)
  49 {
  50         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52
  53         rtlpci->reg_bcn_ctrl_val |= set_bits;
  54         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  55
  56         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  57 }
  58
  59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62         u8 tmp1byte;
  63
  64         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  65         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  66         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  67         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  68         tmp1byte &= ~(BIT(0));
  69         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  70 }
  71
  72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  73 {
  74         struct rtl_priv *rtlpriv = rtl_priv(hw);
  75         u8 tmp1byte;
  76
  77         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  78         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  79         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  80         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  81         tmp1byte |= BIT(0);
  82         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  83 }
  84
  85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  86 {
  87         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  88 }
  89
  90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  91 {
  92         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  93 }
  94
  95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  96 {
  97         struct rtl_priv *rtlpriv = rtl_priv(hw);
  98         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  99         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 100
 101         switch (variable) {
 102         case HW_VAR_RCR:
 103                 *((u32 *) (val)) = rtlpci->receive_config;
 104                 break;
 105         case HW_VAR_RF_STATE:
 106                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 107                 break;
 108         case HW_VAR_FWLPS_RF_ON:{
 109                         enum rf_pwrstate rfState;
 110                         u32 val_rcr;
 111
 112                         rtlpriv->cfg->ops->get_hw_reg(hw,
 113                                                       HW_VAR_RF_STATE,
 114                                                       (u8 *) (&rfState));
 115                         if (rfState == ERFOFF) {
 116                                 *((bool *) (val)) = true;
 117                         } else {
 118                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 119                                 val_rcr &= 0x00070000;
 120                                 if (val_rcr)
 121                                         *((bool *) (val)) = false;
 122                                 else
 123                                         *((bool *) (val)) = true;
 124                         }
 125                         break;
 126                 }
 127         case HW_VAR_FW_PSMODE_STATUS:
 128                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 129                 break;
 130         case HW_VAR_CORRECT_TSF:{
 131                 u64 tsf;
 132                 u32 *ptsf_low = (u32 *)&tsf;
 133                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 134
 135                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 136                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 137
 138                 *((u64 *) (val)) = tsf;
 139
 140                 break;
 141                 }
 142         default:
 143                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 144                          "switch case not processed\n");
 145                 break;
 146         }
 147 }
 148
 149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 150 {
 151         struct rtl_priv *rtlpriv = rtl_priv(hw);
 152         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 153         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 154         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 155         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 156         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 157         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 158         u8 idx;
 159
 160         switch (variable) {
 161         case HW_VAR_ETHER_ADDR:{
 162                         for (idx = 0; idx < ETH_ALEN; idx++) {
 163                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 164                                                val[idx]);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_BASIC_RATE:{
 169                         u16 rate_cfg = ((u16 *) val)[0];
 170                         u8 rate_index = 0;
 171                         rate_cfg &= 0x15f;
 172                         rate_cfg |= 0x01;
 173                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 174                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 175                                        (rate_cfg >> 8) & 0xff);
 176                         while (rate_cfg > 0x1) {
 177                                 rate_cfg = (rate_cfg >> 1);
 178                                 rate_index++;
 179                         }
 180                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 181                                        rate_index);
 182                         break;
 183                 }
 184         case HW_VAR_BSSID:{
 185                         for (idx = 0; idx < ETH_ALEN; idx++) {
 186                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 187                                                val[idx]);
 188                         }
 189                         break;
 190                 }
 191         case HW_VAR_SIFS:{
 192                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 193                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 194
 195                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 196                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 197
 198                         if (!mac->ht_enable)
 199                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 200                                                0x0e0e);
 201                         else
 202                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 203                                                *((u16 *) val));
 204                         break;
 205                 }
 206         case HW_VAR_SLOT_TIME:{
 207                         u8 e_aci;
 208
 209                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 210                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 211
 212                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 213
 214                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 215                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 216                                                               HW_VAR_AC_PARAM,
 217                                                               (u8 *) (&e_aci));
 218                         }
 219                         break;
 220                 }
 221         case HW_VAR_ACK_PREAMBLE:{
 222                         u8 reg_tmp;
 223                         u8 short_preamble = (bool) (*(u8 *) val);
 224                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 225                         if (short_preamble)
 226                                 reg_tmp |= 0x80;
 227
 228                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 229                         break;
 230                 }
 231         case HW_VAR_AMPDU_MIN_SPACE:{
 232                         u8 min_spacing_to_set;
 233                         u8 sec_min_space;
 234
 235                         min_spacing_to_set = *((u8 *) val);
 236                         if (min_spacing_to_set <= 7) {
 237                                 sec_min_space = 0;
 238
 239                                 if (min_spacing_to_set < sec_min_space)
 240                                         min_spacing_to_set = sec_min_space;
 241
 242                                 mac->min_space_cfg = ((mac->min_space_cfg &
 243                                                        0xf8) |
 244                                                       min_spacing_to_set);
 245
 246                                 *val = min_spacing_to_set;
 247
 248                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 249                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 250                                          mac->min_space_cfg);
 251
 252                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 253                                                mac->min_space_cfg);
 254                         }
 255                         break;
 256                 }
 257         case HW_VAR_SHORTGI_DENSITY:{
 258                         u8 density_to_set;
 259
 260                         density_to_set = *((u8 *) val);
 261                         mac->min_space_cfg |= (density_to_set << 3);
 262
 263                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 264                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 265                                  mac->min_space_cfg);
 266
 267                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 268                                        mac->min_space_cfg);
 269
 270                         break;
 271                 }
 272         case HW_VAR_AMPDU_FACTOR:{
 273                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 274                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 275
 276                         u8 factor_toset;
 277                         u8 *p_regtoset = NULL;
 278                         u8 index = 0;
 279
 280                         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 281                             (rtlpcipriv->bt_coexist.bt_coexist_type ==
 282                             BT_CSR_BC4))
 283                                 p_regtoset = regtoset_bt;
 284                         else
 285                                 p_regtoset = regtoset_normal;
 286
 287                         factor_toset = *((u8 *) val);
 288                         if (factor_toset <= 3) {
 289                                 factor_toset = (1 << (factor_toset + 2));
 290                                 if (factor_toset > 0xf)
 291                                         factor_toset = 0xf;
 292
 293                                 for (index = 0; index < 4; index++) {
 294                                         if ((p_regtoset[index] & 0xf0) >
 295                                             (factor_toset << 4))
 296                                                 p_regtoset[index] =
 297                                                     (p_regtoset[index] & 0x0f) |
 298                                                     (factor_toset << 4);
 299
 300                                         if ((p_regtoset[index] & 0x0f) >
 301                                             factor_toset)
 302                                                 p_regtoset[index] =
 303                                                     (p_regtoset[index] & 0xf0) |
 304                                                     (factor_toset);
 305
 306                                         rtl_write_byte(rtlpriv,
 307                                                        (REG_AGGLEN_LMT + index),
 308                                                        p_regtoset[index]);
 309
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                          factor_toset);
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *((u8 *) val);
 320                         rtl92c_dm_init_edca_turbo(hw);
 321
 322                         if (rtlpci->acm_method != eAcmWay2_SW)
 323                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 324                                                               HW_VAR_ACM_CTRL,
 325                                                               (u8 *) (&e_aci));
 326                         break;
 327                 }
 328         case HW_VAR_ACM_CTRL:{
 329                         u8 e_aci = *((u8 *) val);
 330                         union aci_aifsn *p_aci_aifsn =
 331                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 332                         u8 acm = p_aci_aifsn->f.acm;
 333                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 334
 335                         acm_ctrl =
 336                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 337
 338                         if (acm) {
 339                                 switch (e_aci) {
 340                                 case AC0_BE:
 341                                         acm_ctrl |= AcmHw_BeqEn;
 342                                         break;
 343                                 case AC2_VI:
 344                                         acm_ctrl |= AcmHw_ViqEn;
 345                                         break;
 346                                 case AC3_VO:
 347                                         acm_ctrl |= AcmHw_VoqEn;
 348                                         break;
 349                                 default:
 350                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 351                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 352                                                  acm);
 353                                         break;
 354                                 }
 355                         } else {
 356                                 switch (e_aci) {
 357                                 case AC0_BE:
 358                                         acm_ctrl &= (~AcmHw_BeqEn);
 359                                         break;
 360                                 case AC2_VI:
 361                                         acm_ctrl &= (~AcmHw_ViqEn);
 362                                         break;
 363                                 case AC3_VO:
 364                                         acm_ctrl &= (~AcmHw_BeqEn);
 365                                         break;
 366                                 default:
 367                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 368                                                  "switch case not processed\n");
 369                                         break;
 370                                 }
 371                         }
 372
 373                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 374                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 375                                  acm_ctrl);
 376                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 377                         break;
 378                 }
 379         case HW_VAR_RCR:{
 380                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 381                         rtlpci->receive_config = ((u32 *) (val))[0];
 382                         break;
 383                 }
 384         case HW_VAR_RETRY_LIMIT:{
 385                         u8 retry_limit = ((u8 *) (val))[0];
 386
 387                         rtl_write_word(rtlpriv, REG_RL,
 388                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 389                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 390                         break;
 391                 }
 392         case HW_VAR_DUAL_TSF_RST:
 393                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 394                 break;
 395         case HW_VAR_EFUSE_BYTES:
 396                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 397                 break;
 398         case HW_VAR_EFUSE_USAGE:
 399                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 400                 break;
 401         case HW_VAR_IO_CMD:
 402                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 403                 break;
 404         case HW_VAR_WPA_CONFIG:
 405                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 406                 break;
 407         case HW_VAR_SET_RPWM:{
 408                         u8 rpwm_val;
 409
 410                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 411                         udelay(1);
 412
 413                         if (rpwm_val & BIT(7)) {
 414                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 415                                                (*(u8 *) val));
 416                         } else {
 417                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 418                                                ((*(u8 *) val) | BIT(7)));
 419                         }
 420
 421                         break;
 422                 }
 423         case HW_VAR_H2C_FW_PWRMODE:{
 424                         u8 psmode = (*(u8 *) val);
 425
 426                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 427                             (!IS_92C_SERIAL(rtlhal->version))) {
 428                                 rtl92c_dm_rf_saving(hw, true);
 429                         }
 430
 431                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 432                         break;
 433                 }
 434         case HW_VAR_FW_PSMODE_STATUS:
 435                 ppsc->fw_current_inpsmode = *((bool *) val);
 436                 break;
 437         case HW_VAR_H2C_FW_JOINBSSRPT:{
 438                         u8 mstatus = (*(u8 *) val);
 439                         u8 tmp_regcr, tmp_reg422;
 440                         bool recover = false;
 441
 442                         if (mstatus == RT_MEDIA_CONNECT) {
 443                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 444                                                               NULL);
 445
 446                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 447                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 448                                                (tmp_regcr | BIT(0)));
 449
 450                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 451                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 452
 453                                 tmp_reg422 =
 454                                     rtl_read_byte(rtlpriv,
 455                                                   REG_FWHW_TXQ_CTRL + 2);
 456                                 if (tmp_reg422 & BIT(6))
 457                                         recover = true;
 458                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 459                                                tmp_reg422 & (~BIT(6)));
 460
 461                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 462
 463                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 464                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 465
 466                                 if (recover) {
 467                                         rtl_write_byte(rtlpriv,
 468                                                        REG_FWHW_TXQ_CTRL + 2,
 469                                                        tmp_reg422);
 470                                 }
 471
 472                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 473                                                (tmp_regcr & ~(BIT(0))));
 474                         }
 475                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 476
 477                         break;
 478                 }
 479         case HW_VAR_AID:{
 480                         u16 u2btmp;
 481                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 482                         u2btmp &= 0xC000;
 483                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 484                                                 mac->assoc_id));
 485
 486                         break;
 487                 }
 488         case HW_VAR_CORRECT_TSF:{
 489                         u8 btype_ibss = ((u8 *) (val))[0];
 490
 491                         if (btype_ibss)
 492                                 _rtl92ce_stop_tx_beacon(hw);
 493
 494                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 495
 496                         rtl_write_dword(rtlpriv, REG_TSFTR,
 497                                         (u32) (mac->tsf & 0xffffffff));
 498                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 499                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 500
 501                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 502
 503                         if (btype_ibss)
 504                                 _rtl92ce_resume_tx_beacon(hw);
 505
 506                         break;
 507
 508                 }
 509         default:
 510                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 511                          "switch case not processed\n");
 512                 break;
 513         }
 514 }
 515
 516 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 517 {
 518         struct rtl_priv *rtlpriv = rtl_priv(hw);
 519         bool status = true;
 520         long count = 0;
 521         u32 value = _LLT_INIT_ADDR(address) |
 522             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 523
 524         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 525
 526         do {
 527                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 528                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 529                         break;
 530
 531                 if (count > POLLING_LLT_THRESHOLD) {
 532                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 533                                  "Failed to polling write LLT done at address %d!\n",
 534                                  address);
 535                         status = false;
 536                         break;
 537                 }
 538         } while (++count);
 539
 540         return status;
 541 }
 542
 543 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 544 {
 545         struct rtl_priv *rtlpriv = rtl_priv(hw);
 546         unsigned short i;
 547         u8 txpktbuf_bndy;
 548         u8 maxPage;
 549         bool status;
 550
 551 #if LLT_CONFIG == 1
 552         maxPage = 255;
 553         txpktbuf_bndy = 252;
 554 #elif LLT_CONFIG == 2
 555         maxPage = 127;
 556         txpktbuf_bndy = 124;
 557 #elif LLT_CONFIG == 3
 558         maxPage = 255;
 559         txpktbuf_bndy = 174;
 560 #elif LLT_CONFIG == 4
 561         maxPage = 255;
 562         txpktbuf_bndy = 246;
 563 #elif LLT_CONFIG == 5
 564         maxPage = 255;
 565         txpktbuf_bndy = 246;
 566 #endif
 567
 568 #if LLT_CONFIG == 1
 569         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 570         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 571 #elif LLT_CONFIG == 2
 572         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 573 #elif LLT_CONFIG == 3
 574         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 575 #elif LLT_CONFIG == 4
 576         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 577 #elif LLT_CONFIG == 5
 578         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 579
 580         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 581 #endif
 582
 583         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 584         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 585
 586         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 587         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 588
 589         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 590         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 591         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 592
 593         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 594                 status = _rtl92ce_llt_write(hw, i, i + 1);
 595                 if (true != status)
 596                         return status;
 597         }
 598
 599         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 600         if (true != status)
 601                 return status;
 602
 603         for (i = txpktbuf_bndy; i < maxPage; i++) {
 604                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 605                 if (true != status)
 606                         return status;
 607         }
 608
 609         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 610         if (true != status)
 611                 return status;
 612
 613         return true;
 614 }
 615
 616 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 617 {
 618         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 619         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 620         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 621         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 622
 623         if (rtlpci->up_first_time)
 624                 return;
 625
 626         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 627                 rtl92ce_sw_led_on(hw, pLed0);
 628         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 629                 rtl92ce_sw_led_on(hw, pLed0);
 630         else
 631                 rtl92ce_sw_led_off(hw, pLed0);
 632 }
 633
 634 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 635 {
 636         struct rtl_priv *rtlpriv = rtl_priv(hw);
 637         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 638         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 639         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 640
 641         unsigned char bytetmp;
 642         unsigned short wordtmp;
 643         u16 retry;
 644
 645         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 646         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 647                 u32 value32;
 648                 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
 649                 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
 650                 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
 651         }
 652         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 653         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 654
 655         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 656                 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
 657
 658                 u4b_tmp &= (~0x00024800);
 659                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
 660         }
 661
 662         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 663         udelay(2);
 664
 665         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 666         udelay(2);
 667
 668         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 669         udelay(2);
 670
 671         retry = 0;
 672         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 673                  rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 674
 675         while ((bytetmp & BIT(0)) && retry < 1000) {
 676                 retry++;
 677                 udelay(50);
 678                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 679                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 680                          rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 681                 udelay(50);
 682         }
 683
 684         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 685
 686         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 687         udelay(2);
 688
 689         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 690                 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
 691                 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
 692         }
 693
 694         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 695
 696         if (_rtl92ce_llt_table_init(hw) == false)
 697                 return false;
 698
 699         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 700         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 701
 702         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 703
 704         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 705         wordtmp &= 0xf;
 706         wordtmp |= 0xF771;
 707         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 708
 709         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 710         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 711         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 712
 713         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 714
 715         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 716                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 717                         DMA_BIT_MASK(32));
 718         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 719                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 720                         DMA_BIT_MASK(32));
 721         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 722                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 723         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 724                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 725         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 726                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 727         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 728                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 729         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 730                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 731                         DMA_BIT_MASK(32));
 732         rtl_write_dword(rtlpriv, REG_RX_DESA,
 733                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 734                         DMA_BIT_MASK(32));
 735
 736         if (IS_92C_SERIAL(rtlhal->version))
 737                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 738         else
 739                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 740
 741         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 742
 743         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 744         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 745         do {
 746                 retry++;
 747                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 748         } while ((retry < 200) && (bytetmp & BIT(7)));
 749
 750         _rtl92ce_gen_refresh_led_state(hw);
 751
 752         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 753
 754         return true;
 755 }
 756
 757 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 758 {
 759         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 760         struct rtl_priv *rtlpriv = rtl_priv(hw);
 761         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 762         u8 reg_bw_opmode;
 763         u32 reg_prsr;
 764
 765         reg_bw_opmode = BW_OPMODE_20MHZ;
 766         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 767
 768         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 769
 770         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 771
 772         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 773
 774         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 775
 776         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 777
 778         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 779
 780         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 781
 782         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 783
 784         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 785
 786         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 787         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 788         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 789         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 790
 791         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 792             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 793                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 794         else
 795                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 796
 797         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 798
 799         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 800
 801         rtlpci->reg_bcn_ctrl_val = 0x1f;
 802         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 803
 804         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 805
 806         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 807
 808         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 809         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 810
 811         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 812             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
 813                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 814                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 815         } else {
 816                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 817                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 818         }
 819
 820         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 821              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 822                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 823         else
 824                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 825
 826         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 827
 828         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 829         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 830
 831         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 832
 833         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 834
 835         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 836         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 837
 838 }
 839
 840 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 841 {
 842         struct rtl_priv *rtlpriv = rtl_priv(hw);
 843         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 844
 845         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 846         rtl_write_word(rtlpriv, 0x350, 0x870c);
 847         rtl_write_byte(rtlpriv, 0x352, 0x1);
 848
 849         if (ppsc->support_backdoor)
 850                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 851         else
 852                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 853
 854         rtl_write_word(rtlpriv, 0x350, 0x2718);
 855         rtl_write_byte(rtlpriv, 0x352, 0x1);
 856 }
 857
 858 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 859 {
 860         struct rtl_priv *rtlpriv = rtl_priv(hw);
 861         u8 sec_reg_value;
 862
 863         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 864                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 865                  rtlpriv->sec.pairwise_enc_algorithm,
 866                  rtlpriv->sec.group_enc_algorithm);
 867
 868         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 869                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 870                          "not open hw encryption\n");
 871                 return;
 872         }
 873
 874         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 875
 876         if (rtlpriv->sec.use_defaultkey) {
 877                 sec_reg_value |= SCR_TxUseDK;
 878                 sec_reg_value |= SCR_RxUseDK;
 879         }
 880
 881         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 882
 883         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 884
 885         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 886                  "The SECR-value %x\n", sec_reg_value);
 887
 888         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 889
 890 }
 891
 892 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 893 {
 894         struct rtl_priv *rtlpriv = rtl_priv(hw);
 895         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 896         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 897         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 898         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 899         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 900         static bool iqk_initialized; /* initialized to false */
 901         bool rtstatus = true;
 902         bool is92c;
 903         int err;
 904         u8 tmp_u1b;
 905
 906         rtlpci->being_init_adapter = true;
 907         rtlpriv->intf_ops->disable_aspm(hw);
 908         rtstatus = _rtl92ce_init_mac(hw);
 909         if (rtstatus != true) {
 910                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
 911                 err = 1;
 912                 return err;
 913         }
 914
 915         err = rtl92c_download_fw(hw);
 916         if (err) {
 917                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 918                          "Failed to download FW. Init HW without FW now..\n");
 919                 err = 1;
 920                 rtlhal->fw_ready = false;
 921                 return err;
 922         } else {
 923                 rtlhal->fw_ready = true;
 924         }
 925
 926         rtlhal->last_hmeboxnum = 0;
 927         rtl92c_phy_mac_config(hw);
 928         rtl92c_phy_bb_config(hw);
 929         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 930         rtl92c_phy_rf_config(hw);
 931         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 932                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 933         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 934                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 935         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 936         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 937         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 938         _rtl92ce_hw_configure(hw);
 939         rtl_cam_reset_all_entry(hw);
 940         rtl92ce_enable_hw_security_config(hw);
 941
 942         ppsc->rfpwr_state = ERFON;
 943
 944         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 945         _rtl92ce_enable_aspm_back_door(hw);
 946         rtlpriv->intf_ops->enable_aspm(hw);
 947
 948         rtl8192ce_bt_hw_init(hw);
 949
 950         if (ppsc->rfpwr_state == ERFON) {
 951                 rtl92c_phy_set_rfpath_switch(hw, 1);
 952                 if (iqk_initialized) {
 953                         rtl92c_phy_iq_calibrate(hw, true);
 954                 } else {
 955                         rtl92c_phy_iq_calibrate(hw, false);
 956                         iqk_initialized = true;
 957                 }
 958
 959                 rtl92c_dm_check_txpower_tracking(hw);
 960                 rtl92c_phy_lc_calibrate(hw);
 961         }
 962
 963         is92c = IS_92C_SERIAL(rtlhal->version);
 964         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 965         if (!(tmp_u1b & BIT(0))) {
 966                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 967                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
 968         }
 969
 970         if (!(tmp_u1b & BIT(1)) && is92c) {
 971                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 972                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
 973         }
 974
 975         if (!(tmp_u1b & BIT(4))) {
 976                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 977                 tmp_u1b &= 0x0F;
 978                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 979                 udelay(10);
 980                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
 981                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
 982         }
 983         rtl92c_dm_init(hw);
 984         rtlpci->being_init_adapter = false;
 985         return err;
 986 }
 987
 988 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
 989 {
 990         struct rtl_priv *rtlpriv = rtl_priv(hw);
 991         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 992         enum version_8192c version = VERSION_UNKNOWN;
 993         u32 value32;
 994
 995         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
 996         if (value32 & TRP_VAUX_EN) {
 997                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
 998                            VERSION_A_CHIP_88C;
 999         } else {
1000                 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1001                            VERSION_B_CHIP_88C;
1002         }
1003
1004         switch (version) {
1005         case VERSION_B_CHIP_92C:
1006                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1007                          "Chip Version ID: VERSION_B_CHIP_92C\n");
1008                 break;
1009         case VERSION_B_CHIP_88C:
1010                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1011                          "Chip Version ID: VERSION_B_CHIP_88C\n");
1012                 break;
1013         case VERSION_A_CHIP_92C:
1014                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1015                          "Chip Version ID: VERSION_A_CHIP_92C\n");
1016                 break;
1017         case VERSION_A_CHIP_88C:
1018                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1019                          "Chip Version ID: VERSION_A_CHIP_88C\n");
1020                 break;
1021         default:
1022                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1023                          "Chip Version ID: Unknown. Bug?\n");
1024                 break;
1025         }
1026
1027         switch (version & 0x3) {
1028         case CHIP_88C:
1029                 rtlphy->rf_type = RF_1T1R;
1030                 break;
1031         case CHIP_92C:
1032                 rtlphy->rf_type = RF_2T2R;
1033                 break;
1034         case CHIP_92C_1T2R:
1035                 rtlphy->rf_type = RF_1T2R;
1036                 break;
1037         default:
1038                 rtlphy->rf_type = RF_1T1R;
1039                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1040                          "ERROR RF_Type is set!!\n");
1041                 break;
1042         }
1043
1044         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1045                  rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1046
1047         return version;
1048 }
1049
1050 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1051                                      enum nl80211_iftype type)
1052 {
1053         struct rtl_priv *rtlpriv = rtl_priv(hw);
1054         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1055         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1056         bt_msr &= 0xfc;
1057
1058         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1059             type == NL80211_IFTYPE_STATION) {
1060                 _rtl92ce_stop_tx_beacon(hw);
1061                 _rtl92ce_enable_bcn_sub_func(hw);
1062         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1063                 _rtl92ce_resume_tx_beacon(hw);
1064                 _rtl92ce_disable_bcn_sub_func(hw);
1065         } else {
1066                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1067                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1068                          type);
1069         }
1070
1071         switch (type) {
1072         case NL80211_IFTYPE_UNSPECIFIED:
1073                 bt_msr |= MSR_NOLINK;
1074                 ledaction = LED_CTL_LINK;
1075                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1076                          "Set Network type to NO LINK!\n");
1077                 break;
1078         case NL80211_IFTYPE_ADHOC:
1079                 bt_msr |= MSR_ADHOC;
1080                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1081                          "Set Network type to Ad Hoc!\n");
1082                 break;
1083         case NL80211_IFTYPE_STATION:
1084                 bt_msr |= MSR_INFRA;
1085                 ledaction = LED_CTL_LINK;
1086                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1087                          "Set Network type to STA!\n");
1088                 break;
1089         case NL80211_IFTYPE_AP:
1090                 bt_msr |= MSR_AP;
1091                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1092                          "Set Network type to AP!\n");
1093                 break;
1094         default:
1095                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1096                          "Network type %d not supported!\n", type);
1097                 return 1;
1098                 break;
1099
1100         }
1101
1102         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1103         rtlpriv->cfg->ops->led_control(hw, ledaction);
1104         if ((bt_msr & 0xfc) == MSR_AP)
1105                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1106         else
1107                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1108         return 0;
1109 }
1110
1111 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1112 {
1113         struct rtl_priv *rtlpriv = rtl_priv(hw);
1114         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1115
1116         if (rtlpriv->psc.rfpwr_state != ERFON)
1117                 return;
1118
1119         if (check_bssid) {
1120                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1121                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1122                                               (u8 *) (&reg_rcr));
1123                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1124         } else if (check_bssid == false) {
1125                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1126                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1127                 rtlpriv->cfg->ops->set_hw_reg(hw,
1128                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1129         }
1130
1131 }
1132
1133 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1134 {
1135         struct rtl_priv *rtlpriv = rtl_priv(hw);
1136
1137         if (_rtl92ce_set_media_status(hw, type))
1138                 return -EOPNOTSUPP;
1139
1140         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1141                 if (type != NL80211_IFTYPE_AP)
1142                         rtl92ce_set_check_bssid(hw, true);
1143         } else {
1144                 rtl92ce_set_check_bssid(hw, false);
1145         }
1146
1147         return 0;
1148 }
1149
1150 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1151 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1152 {
1153         struct rtl_priv *rtlpriv = rtl_priv(hw);
1154         rtl92c_dm_init_edca_turbo(hw);
1155         switch (aci) {
1156         case AC1_BK:
1157                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1158                 break;
1159         case AC0_BE:
1160                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1161                 break;
1162         case AC2_VI:
1163                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1164                 break;
1165         case AC3_VO:
1166                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1167                 break;
1168         default:
1169                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1170                 break;
1171         }
1172 }
1173
1174 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1175 {
1176         struct rtl_priv *rtlpriv = rtl_priv(hw);
1177         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1178
1179         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1180         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1181 }
1182
1183 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1184 {
1185         struct rtl_priv *rtlpriv = rtl_priv(hw);
1186         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1187
1188         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1189         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1190         synchronize_irq(rtlpci->pdev->irq);
1191 }
1192
1193 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1194 {
1195         struct rtl_priv *rtlpriv = rtl_priv(hw);
1196         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1197         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1198         u8 u1b_tmp;
1199         u32 u4b_tmp;
1200
1201         rtlpriv->intf_ops->enable_aspm(hw);
1202         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1203         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1204         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1205         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1206         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1207         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1208         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1209                 rtl92c_firmware_selfreset(hw);
1210         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1211         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1212         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1213         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1214         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1215              ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1216              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1217                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1218                                 (u1b_tmp << 8));
1219         } else {
1220                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1221                                 (u1b_tmp << 8));
1222         }
1223         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1224         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1225         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1226         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1227         if (rtlpcipriv->bt_coexist.bt_coexistence) {
1228                 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1229                 u4b_tmp |= 0x03824800;
1230                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1231         } else {
1232                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1233         }
1234
1235         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1236         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1237 }
1238
1239 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1240 {
1241         struct rtl_priv *rtlpriv = rtl_priv(hw);
1242         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1243         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1244         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1245         enum nl80211_iftype opmode;
1246
1247         mac->link_state = MAC80211_NOLINK;
1248         opmode = NL80211_IFTYPE_UNSPECIFIED;
1249         _rtl92ce_set_media_status(hw, opmode);
1250         if (rtlpci->driver_is_goingto_unload ||
1251             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1252                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1253         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1254         _rtl92ce_poweroff_adapter(hw);
1255 }
1256
1257 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1258                                   u32 *p_inta, u32 *p_intb)
1259 {
1260         struct rtl_priv *rtlpriv = rtl_priv(hw);
1261         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1262
1263         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1264         rtl_write_dword(rtlpriv, ISR, *p_inta);
1265
1266         /*
1267          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1268          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1269          */
1270 }
1271
1272 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1273 {
1274
1275         struct rtl_priv *rtlpriv = rtl_priv(hw);
1276         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1277         u16 bcn_interval, atim_window;
1278
1279         bcn_interval = mac->beacon_interval;
1280         atim_window = 2;        /*FIX MERGE */
1281         rtl92ce_disable_interrupt(hw);
1282         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1283         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1284         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1285         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1286         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1287         rtl_write_byte(rtlpriv, 0x606, 0x30);
1288         rtl92ce_enable_interrupt(hw);
1289 }
1290
1291 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1292 {
1293         struct rtl_priv *rtlpriv = rtl_priv(hw);
1294         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1295         u16 bcn_interval = mac->beacon_interval;
1296
1297         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1298                  "beacon_interval:%d\n", bcn_interval);
1299         rtl92ce_disable_interrupt(hw);
1300         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1301         rtl92ce_enable_interrupt(hw);
1302 }
1303
1304 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1305                                    u32 add_msr, u32 rm_msr)
1306 {
1307         struct rtl_priv *rtlpriv = rtl_priv(hw);
1308         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1309
1310         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1311                  add_msr, rm_msr);
1312
1313         if (add_msr)
1314                 rtlpci->irq_mask[0] |= add_msr;
1315         if (rm_msr)
1316                 rtlpci->irq_mask[0] &= (~rm_msr);
1317         rtl92ce_disable_interrupt(hw);
1318         rtl92ce_enable_interrupt(hw);
1319 }
1320
1321 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1322                                                  bool autoload_fail,
1323                                                  u8 *hwinfo)
1324 {
1325         struct rtl_priv *rtlpriv = rtl_priv(hw);
1326         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1327         u8 rf_path, index, tempval;
1328         u16 i;
1329
1330         for (rf_path = 0; rf_path < 2; rf_path++) {
1331                 for (i = 0; i < 3; i++) {
1332                         if (!autoload_fail) {
1333                                 rtlefuse->
1334                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1335                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1336                                 rtlefuse->
1337                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1338                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1339                                            i];
1340                         } else {
1341                                 rtlefuse->
1342                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1343                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1344                                 rtlefuse->
1345                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1346                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1347                         }
1348                 }
1349         }
1350
1351         for (i = 0; i < 3; i++) {
1352                 if (!autoload_fail)
1353                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1354                 else
1355                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1356                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1357                     (tempval & 0xf);
1358                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1359                     ((tempval & 0xf0) >> 4);
1360         }
1361
1362         for (rf_path = 0; rf_path < 2; rf_path++)
1363                 for (i = 0; i < 3; i++)
1364                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1365                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1366                                 rf_path, i,
1367                                 rtlefuse->
1368                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1369         for (rf_path = 0; rf_path < 2; rf_path++)
1370                 for (i = 0; i < 3; i++)
1371                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1372                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1373                                 rf_path, i,
1374                                 rtlefuse->
1375                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1376         for (rf_path = 0; rf_path < 2; rf_path++)
1377                 for (i = 0; i < 3; i++)
1378                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1379                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1380                                 rf_path, i,
1381                                 rtlefuse->
1382                                 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]);
1383
1384         for (rf_path = 0; rf_path < 2; rf_path++) {
1385                 for (i = 0; i < 14; i++) {
1386                         index = _rtl92c_get_chnl_group((u8) i);
1387
1388                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1389                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1390                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1391                             rtlefuse->
1392                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1393
1394                         if ((rtlefuse->
1395                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1396                              rtlefuse->
1397                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1398                             > 0) {
1399                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1400                                     rtlefuse->
1401                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1402                                     [index] -
1403                                     rtlefuse->
1404                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1405                                     [index];
1406                         } else {
1407                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1408                         }
1409                 }
1410
1411                 for (i = 0; i < 14; i++) {
1412                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1413                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1414                                 rf_path, i,
1415                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1416                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1417                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1418                 }
1419         }
1420
1421         for (i = 0; i < 3; i++) {
1422                 if (!autoload_fail) {
1423                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1424                             hwinfo[EEPROM_TXPWR_GROUP + i];
1425                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1426                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1427                 } else {
1428                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1429                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1430                 }
1431         }
1432
1433         for (rf_path = 0; rf_path < 2; rf_path++) {
1434                 for (i = 0; i < 14; i++) {
1435                         index = _rtl92c_get_chnl_group((u8) i);
1436
1437                         if (rf_path == RF90_PATH_A) {
1438                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1439                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1440                                      & 0xf);
1441                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1442                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1443                                      & 0xf);
1444                         } else if (rf_path == RF90_PATH_B) {
1445                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1446                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1447                                       & 0xf0) >> 4);
1448                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1449                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1450                                       & 0xf0) >> 4);
1451                         }
1452
1453                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1454                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1455                                 rf_path, i,
1456                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1457                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1458                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1459                                 rf_path, i,
1460                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1461                 }
1462         }
1463
1464         for (i = 0; i < 14; i++) {
1465                 index = _rtl92c_get_chnl_group((u8) i);
1466
1467                 if (!autoload_fail)
1468                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1469                 else
1470                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1471
1472                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1473                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1474                     ((tempval >> 4) & 0xF);
1475
1476                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1477                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1478
1479                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1480                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1481
1482                 index = _rtl92c_get_chnl_group((u8) i);
1483
1484                 if (!autoload_fail)
1485                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1486                 else
1487                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1488
1489                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1490                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1491                     ((tempval >> 4) & 0xF);
1492         }
1493
1494         rtlefuse->legacy_ht_txpowerdiff =
1495             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1496
1497         for (i = 0; i < 14; i++)
1498                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1499                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1500                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1501         for (i = 0; i < 14; i++)
1502                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1503                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1504                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1505         for (i = 0; i < 14; i++)
1506                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1507                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1508                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1509         for (i = 0; i < 14; i++)
1510                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1511                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1512                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1513
1514         if (!autoload_fail)
1515                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1516         else
1517                 rtlefuse->eeprom_regulatory = 0;
1518         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1519                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1520
1521         if (!autoload_fail) {
1522                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1523                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1524         } else {
1525                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1526                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1527         }
1528         RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1529                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1530                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1531
1532         if (!autoload_fail)
1533                 tempval = hwinfo[EEPROM_THERMAL_METER];
1534         else
1535                 tempval = EEPROM_DEFAULT_THERMALMETER;
1536         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1537
1538         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1539                 rtlefuse->apk_thermalmeterignore = true;
1540
1541         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1542         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1543                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1544 }
1545
1546 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1547 {
1548         struct rtl_priv *rtlpriv = rtl_priv(hw);
1549         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1550         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1551         u16 i, usvalue;
1552         u8 hwinfo[HWSET_MAX_SIZE];
1553         u16 eeprom_id;
1554
1555         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1556                 rtl_efuse_shadow_map_update(hw);
1557
1558                 memcpy((void *)hwinfo,
1559                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1560                        HWSET_MAX_SIZE);
1561         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1562                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1563                          "RTL819X Not boot from eeprom, check it !!");
1564         }
1565
1566         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1567                       hwinfo, HWSET_MAX_SIZE);
1568
1569         eeprom_id = *((u16 *)&hwinfo[0]);
1570         if (eeprom_id != RTL8190_EEPROM_ID) {
1571                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1572                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1573                 rtlefuse->autoload_failflag = true;
1574         } else {
1575                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1576                 rtlefuse->autoload_failflag = false;
1577         }
1578
1579         if (rtlefuse->autoload_failflag)
1580                 return;
1581
1582         for (i = 0; i < 6; i += 2) {
1583                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1584                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1585         }
1586
1587         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1588
1589         _rtl92ce_read_txpower_info_from_hwpg(hw,
1590                                              rtlefuse->autoload_failflag,
1591                                              hwinfo);
1592
1593         rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1594                                                  rtlefuse->autoload_failflag,
1595                                                  hwinfo);
1596
1597         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1598         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1599         rtlefuse->txpwr_fromeprom = true;
1600         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1601
1602         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1603                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1604
1605         /* set channel paln to world wide 13 */
1606         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1607
1608         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1609                 switch (rtlefuse->eeprom_oemid) {
1610                 case EEPROM_CID_DEFAULT:
1611                         if (rtlefuse->eeprom_did == 0x8176) {
1612                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1613                                      rtlefuse->eeprom_smid == 0x1629))
1614                                         rtlhal->oem_id = RT_CID_819x_HP;
1615                                 else
1616                                         rtlhal->oem_id = RT_CID_DEFAULT;
1617                         } else {
1618                                 rtlhal->oem_id = RT_CID_DEFAULT;
1619                         }
1620                         break;
1621                 case EEPROM_CID_TOSHIBA:
1622                         rtlhal->oem_id = RT_CID_TOSHIBA;
1623                         break;
1624                 case EEPROM_CID_QMI:
1625                         rtlhal->oem_id = RT_CID_819x_QMI;
1626                         break;
1627                 case EEPROM_CID_WHQL:
1628                 default:
1629                         rtlhal->oem_id = RT_CID_DEFAULT;
1630                         break;
1631
1632                 }
1633         }
1634
1635 }
1636
1637 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1638 {
1639         struct rtl_priv *rtlpriv = rtl_priv(hw);
1640         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1641         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1642
1643         switch (rtlhal->oem_id) {
1644         case RT_CID_819x_HP:
1645                 pcipriv->ledctl.led_opendrain = true;
1646                 break;
1647         case RT_CID_819x_Lenovo:
1648         case RT_CID_DEFAULT:
1649         case RT_CID_TOSHIBA:
1650         case RT_CID_CCX:
1651         case RT_CID_819x_Acer:
1652         case RT_CID_WHQL:
1653         default:
1654                 break;
1655         }
1656         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1657                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1658 }
1659
1660 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1661 {
1662         struct rtl_priv *rtlpriv = rtl_priv(hw);
1663         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1664         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1665         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1666         u8 tmp_u1b;
1667
1668         rtlhal->version = _rtl92ce_read_chip_version(hw);
1669         if (get_rf_type(rtlphy) == RF_1T1R)
1670                 rtlpriv->dm.rfpath_rxenable[0] = true;
1671         else
1672                 rtlpriv->dm.rfpath_rxenable[0] =
1673                     rtlpriv->dm.rfpath_rxenable[1] = true;
1674         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1675                  rtlhal->version);
1676         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1677         if (tmp_u1b & BIT(4)) {
1678                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1679                 rtlefuse->epromtype = EEPROM_93C46;
1680         } else {
1681                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1682                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1683         }
1684         if (tmp_u1b & BIT(5)) {
1685                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1686                 rtlefuse->autoload_failflag = false;
1687                 _rtl92ce_read_adapter_info(hw);
1688         } else {
1689                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1690         }
1691         _rtl92ce_hal_customized_behavior(hw);
1692 }
1693
1694 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1695                 struct ieee80211_sta *sta)
1696 {
1697         struct rtl_priv *rtlpriv = rtl_priv(hw);
1698         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1699         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1700         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1701         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1702         u32 ratr_value;
1703         u8 ratr_index = 0;
1704         u8 nmode = mac->ht_enable;
1705         u8 mimo_ps = IEEE80211_SMPS_OFF;
1706         u16 shortgi_rate;
1707         u32 tmp_ratr_value;
1708         u8 curtxbw_40mhz = mac->bw_40;
1709         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1710                                1 : 0;
1711         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1712                                1 : 0;
1713         enum wireless_mode wirelessmode = mac->mode;
1714
1715         if (rtlhal->current_bandtype == BAND_ON_5G)
1716                 ratr_value = sta->supp_rates[1] << 4;
1717         else
1718                 ratr_value = sta->supp_rates[0];
1719         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1720                         sta->ht_cap.mcs.rx_mask[0] << 12);
1721         switch (wirelessmode) {
1722         case WIRELESS_MODE_B:
1723                 if (ratr_value & 0x0000000c)
1724                         ratr_value &= 0x0000000d;
1725                 else
1726                         ratr_value &= 0x0000000f;
1727                 break;
1728         case WIRELESS_MODE_G:
1729                 ratr_value &= 0x00000FF5;
1730                 break;
1731         case WIRELESS_MODE_N_24G:
1732         case WIRELESS_MODE_N_5G:
1733                 nmode = 1;
1734                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1735                         ratr_value &= 0x0007F005;
1736                 } else {
1737                         u32 ratr_mask;
1738
1739                         if (get_rf_type(rtlphy) == RF_1T2R ||
1740                             get_rf_type(rtlphy) == RF_1T1R)
1741                                 ratr_mask = 0x000ff005;
1742                         else
1743                                 ratr_mask = 0x0f0ff005;
1744
1745                         ratr_value &= ratr_mask;
1746                 }
1747                 break;
1748         default:
1749                 if (rtlphy->rf_type == RF_1T2R)
1750                         ratr_value &= 0x000ff0ff;
1751                 else
1752                         ratr_value &= 0x0f0ff0ff;
1753
1754                 break;
1755         }
1756
1757         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1758             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1759             (rtlpcipriv->bt_coexist.bt_cur_state) &&
1760             (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1761             ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1762             (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1763                 ratr_value &= 0x0fffcfc0;
1764         else
1765                 ratr_value &= 0x0FFFFFFF;
1766
1767         if (nmode && ((curtxbw_40mhz &&
1768                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1769                                                curshortgi_20mhz))) {
1770
1771                 ratr_value |= 0x10000000;
1772                 tmp_ratr_value = (ratr_value >> 12);
1773
1774                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1775                         if ((1 << shortgi_rate) & tmp_ratr_value)
1776                                 break;
1777                 }
1778
1779                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1780                     (shortgi_rate << 4) | (shortgi_rate);
1781         }
1782
1783         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1784
1785         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1786                  rtl_read_dword(rtlpriv, REG_ARFR0));
1787 }
1788
1789 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1790                 struct ieee80211_sta *sta, u8 rssi_level)
1791 {
1792         struct rtl_priv *rtlpriv = rtl_priv(hw);
1793         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1794         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1795         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1796         struct rtl_sta_info *sta_entry = NULL;
1797         u32 ratr_bitmap;
1798         u8 ratr_index;
1799         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1800                                 ? 1 : 0;
1801         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1802                                 1 : 0;
1803         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1804                                 1 : 0;
1805         enum wireless_mode wirelessmode = 0;
1806         bool shortgi = false;
1807         u8 rate_mask[5];
1808         u8 macid = 0;
1809         u8 mimo_ps = IEEE80211_SMPS_OFF;
1810
1811         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1812         wirelessmode = sta_entry->wireless_mode;
1813         if (mac->opmode == NL80211_IFTYPE_STATION)
1814                 curtxbw_40mhz = mac->bw_40;
1815         else if (mac->opmode == NL80211_IFTYPE_AP ||
1816                 mac->opmode == NL80211_IFTYPE_ADHOC)
1817                 macid = sta->aid + 1;
1818
1819         if (rtlhal->current_bandtype == BAND_ON_5G)
1820                 ratr_bitmap = sta->supp_rates[1] << 4;
1821         else
1822                 ratr_bitmap = sta->supp_rates[0];
1823         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1824                         sta->ht_cap.mcs.rx_mask[0] << 12);
1825         switch (wirelessmode) {
1826         case WIRELESS_MODE_B:
1827                 ratr_index = RATR_INX_WIRELESS_B;
1828                 if (ratr_bitmap & 0x0000000c)
1829                         ratr_bitmap &= 0x0000000d;
1830                 else
1831                         ratr_bitmap &= 0x0000000f;
1832                 break;
1833         case WIRELESS_MODE_G:
1834                 ratr_index = RATR_INX_WIRELESS_GB;
1835
1836                 if (rssi_level == 1)
1837                         ratr_bitmap &= 0x00000f00;
1838                 else if (rssi_level == 2)
1839                         ratr_bitmap &= 0x00000ff0;
1840                 else
1841                         ratr_bitmap &= 0x00000ff5;
1842                 break;
1843         case WIRELESS_MODE_A:
1844                 ratr_index = RATR_INX_WIRELESS_A;
1845                 ratr_bitmap &= 0x00000ff0;
1846                 break;
1847         case WIRELESS_MODE_N_24G:
1848         case WIRELESS_MODE_N_5G:
1849                 ratr_index = RATR_INX_WIRELESS_NGB;
1850
1851                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1852                         if (rssi_level == 1)
1853                                 ratr_bitmap &= 0x00070000;
1854                         else if (rssi_level == 2)
1855                                 ratr_bitmap &= 0x0007f000;
1856                         else
1857                                 ratr_bitmap &= 0x0007f005;
1858                 } else {
1859                         if (rtlphy->rf_type == RF_1T2R ||
1860                             rtlphy->rf_type == RF_1T1R) {
1861                                 if (curtxbw_40mhz) {
1862                                         if (rssi_level == 1)
1863                                                 ratr_bitmap &= 0x000f0000;
1864                                         else if (rssi_level == 2)
1865                                                 ratr_bitmap &= 0x000ff000;
1866                                         else
1867                                                 ratr_bitmap &= 0x000ff015;
1868                                 } else {
1869                                         if (rssi_level == 1)
1870                                                 ratr_bitmap &= 0x000f0000;
1871                                         else if (rssi_level == 2)
1872                                                 ratr_bitmap &= 0x000ff000;
1873                                         else
1874                                                 ratr_bitmap &= 0x000ff005;
1875                                 }
1876                         } else {
1877                                 if (curtxbw_40mhz) {
1878                                         if (rssi_level == 1)
1879                                                 ratr_bitmap &= 0x0f0f0000;
1880                                         else if (rssi_level == 2)
1881                                                 ratr_bitmap &= 0x0f0ff000;
1882                                         else
1883                                                 ratr_bitmap &= 0x0f0ff015;
1884                                 } else {
1885                                         if (rssi_level == 1)
1886                                                 ratr_bitmap &= 0x0f0f0000;
1887                                         else if (rssi_level == 2)
1888                                                 ratr_bitmap &= 0x0f0ff000;
1889                                         else
1890                                                 ratr_bitmap &= 0x0f0ff005;
1891                                 }
1892                         }
1893                 }
1894
1895                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1896                     (!curtxbw_40mhz && curshortgi_20mhz)) {
1897
1898                         if (macid == 0)
1899                                 shortgi = true;
1900                         else if (macid == 1)
1901                                 shortgi = false;
1902                 }
1903                 break;
1904         default:
1905                 ratr_index = RATR_INX_WIRELESS_NGB;
1906
1907                 if (rtlphy->rf_type == RF_1T2R)
1908                         ratr_bitmap &= 0x000ff0ff;
1909                 else
1910                         ratr_bitmap &= 0x0f0ff0ff;
1911                 break;
1912         }
1913         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1914                  "ratr_bitmap :%x\n", ratr_bitmap);
1915         *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1916                                      (ratr_index << 28));
1917         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1918         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1919                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
1920                  ratr_index, ratr_bitmap,
1921                  rate_mask[0], rate_mask[1], rate_mask[2], rate_mask[3],
1922                  rate_mask[4]);
1923         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1924
1925         if (macid != 0)
1926                 sta_entry->ratr_index = ratr_index;
1927 }
1928
1929 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1930                 struct ieee80211_sta *sta, u8 rssi_level)
1931 {
1932         struct rtl_priv *rtlpriv = rtl_priv(hw);
1933
1934         if (rtlpriv->dm.useramask)
1935                 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1936         else
1937                 rtl92ce_update_hal_rate_table(hw, sta);
1938 }
1939
1940 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1941 {
1942         struct rtl_priv *rtlpriv = rtl_priv(hw);
1943         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1944         u16 sifs_timer;
1945
1946         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1947                                       (u8 *)&mac->slot_time);
1948         if (!mac->ht_enable)
1949                 sifs_timer = 0x0a0a;
1950         else
1951                 sifs_timer = 0x1010;
1952         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1953 }
1954
1955 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1956 {
1957         struct rtl_priv *rtlpriv = rtl_priv(hw);
1958         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1959         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1960         enum rf_pwrstate e_rfpowerstate_toset;
1961         u8 u1tmp;
1962         bool actuallyset = false;
1963         unsigned long flag;
1964
1965         if (rtlpci->being_init_adapter)
1966                 return false;
1967
1968         if (ppsc->swrf_processing)
1969                 return false;
1970
1971         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1972         if (ppsc->rfchange_inprogress) {
1973                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1974                 return false;
1975         } else {
1976                 ppsc->rfchange_inprogress = true;
1977                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1978         }
1979
1980         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1981                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
1982
1983         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1984         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1985
1986         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
1987                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1988                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
1989
1990                 e_rfpowerstate_toset = ERFON;
1991                 ppsc->hwradiooff = false;
1992                 actuallyset = true;
1993         } else if ((ppsc->hwradiooff == false)
1994                    && (e_rfpowerstate_toset == ERFOFF)) {
1995                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1996                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
1997
1998                 e_rfpowerstate_toset = ERFOFF;
1999                 ppsc->hwradiooff = true;
2000                 actuallyset = true;
2001         }
2002
2003         if (actuallyset) {
2004                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2005                 ppsc->rfchange_inprogress = false;
2006                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2007         } else {
2008                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2009                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2010
2011                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2012                 ppsc->rfchange_inprogress = false;
2013                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2014         }
2015
2016         *valid = 1;
2017         return !ppsc->hwradiooff;
2018
2019 }
2020
2021 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2022                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2023                      bool is_wepkey, bool clear_all)
2024 {
2025         struct rtl_priv *rtlpriv = rtl_priv(hw);
2026         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2027         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2028         u8 *macaddr = p_macaddr;
2029         u32 entry_id = 0;
2030         bool is_pairwise = false;
2031
2032         static u8 cam_const_addr[4][6] = {
2033                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2034                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2035                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2036                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2037         };
2038         static u8 cam_const_broad[] = {
2039                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2040         };
2041
2042         if (clear_all) {
2043                 u8 idx = 0;
2044                 u8 cam_offset = 0;
2045                 u8 clear_number = 5;
2046
2047                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2048
2049                 for (idx = 0; idx < clear_number; idx++) {
2050                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2051                         rtl_cam_empty_entry(hw, cam_offset + idx);
2052
2053                         if (idx < 5) {
2054                                 memset(rtlpriv->sec.key_buf[idx], 0,
2055                                        MAX_KEY_LEN);
2056                                 rtlpriv->sec.key_len[idx] = 0;
2057                         }
2058                 }
2059
2060         } else {
2061                 switch (enc_algo) {
2062                 case WEP40_ENCRYPTION:
2063                         enc_algo = CAM_WEP40;
2064                         break;
2065                 case WEP104_ENCRYPTION:
2066                         enc_algo = CAM_WEP104;
2067                         break;
2068                 case TKIP_ENCRYPTION:
2069                         enc_algo = CAM_TKIP;
2070                         break;
2071                 case AESCCMP_ENCRYPTION:
2072                         enc_algo = CAM_AES;
2073                         break;
2074                 default:
2075                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2076                                  "switch case not processed\n");
2077                         enc_algo = CAM_TKIP;
2078                         break;
2079                 }
2080
2081                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2082                         macaddr = cam_const_addr[key_index];
2083                         entry_id = key_index;
2084                 } else {
2085                         if (is_group) {
2086                                 macaddr = cam_const_broad;
2087                                 entry_id = key_index;
2088                         } else {
2089                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2090                                         entry_id = rtl_cam_get_free_entry(hw,
2091                                                                  p_macaddr);
2092                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2093                                                 RT_TRACE(rtlpriv, COMP_SEC,
2094                                                          DBG_EMERG,
2095                                                          "Can not find free hw security cam entry\n");
2096                                                 return;
2097                                         }
2098                                 } else {
2099                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2100                                 }
2101
2102                                 key_index = PAIRWISE_KEYIDX;
2103                                 is_pairwise = true;
2104                         }
2105                 }
2106
2107                 if (rtlpriv->sec.key_len[key_index] == 0) {
2108                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2109                                  "delete one entry, entry_id is %d\n",
2110                                  entry_id);
2111                         if (mac->opmode == NL80211_IFTYPE_AP)
2112                                 rtl_cam_del_entry(hw, p_macaddr);
2113                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2114                 } else {
2115                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2116                                  "The insert KEY length is %d\n",
2117                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2118                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2119                                  "The insert KEY is %x %x\n",
2120                                  rtlpriv->sec.key_buf[0][0],
2121                                  rtlpriv->sec.key_buf[0][1]);
2122
2123                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2124                                  "add one entry\n");
2125                         if (is_pairwise) {
2126                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2127                                               "Pairwise Key content",
2128                                               rtlpriv->sec.pairwise_key,
2129                                               rtlpriv->sec.
2130                                               key_len[PAIRWISE_KEYIDX]);
2131
2132                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2133                                          "set Pairwise key\n");
2134
2135                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2136                                                       entry_id, enc_algo,
2137                                                       CAM_CONFIG_NO_USEDK,
2138                                                       rtlpriv->sec.
2139                                                       key_buf[key_index]);
2140                         } else {
2141                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2142                                          "set group key\n");
2143
2144                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2145                                         rtl_cam_add_one_entry(hw,
2146                                                 rtlefuse->dev_addr,
2147                                                 PAIRWISE_KEYIDX,
2148                                                 CAM_PAIRWISE_KEY_POSITION,
2149                                                 enc_algo,
2150                                                 CAM_CONFIG_NO_USEDK,
2151                                                 rtlpriv->sec.key_buf
2152                                                 [entry_id]);
2153                                 }
2154
2155                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2156                                                 entry_id, enc_algo,
2157                                                 CAM_CONFIG_NO_USEDK,
2158                                                 rtlpriv->sec.key_buf[entry_id]);
2159                         }
2160
2161                 }
2162         }
2163 }
2164
2165 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2166 {
2167         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2168
2169         rtlpcipriv->bt_coexist.bt_coexistence =
2170                         rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2171         rtlpcipriv->bt_coexist.bt_ant_num =
2172                         rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2173         rtlpcipriv->bt_coexist.bt_coexist_type =
2174                         rtlpcipriv->bt_coexist.eeprom_bt_type;
2175
2176         if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2177                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2178                         rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2179         else
2180                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2181                         rtlpcipriv->bt_coexist.reg_bt_iso;
2182
2183         rtlpcipriv->bt_coexist.bt_radio_shared_type =
2184                         rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2185
2186         if (rtlpcipriv->bt_coexist.bt_coexistence) {
2187
2188                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2189                         rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2190                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2191                         rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2192                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2193                         rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2194                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2195                         rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2196                 else
2197                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2198
2199                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2200                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2201                 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2202         }
2203 }
2204
2205 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2206                                               bool auto_load_fail, u8 *hwinfo)
2207 {
2208         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2209         u8 value;
2210
2211         if (!auto_load_fail) {
2212                 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2213                                         ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2214                 value = hwinfo[RF_OPTION4];
2215                 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2216                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2217                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2218                                                          ((value & 0x10) >> 4);
2219                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2220                                                          ((value & 0x20) >> 5);
2221         } else {
2222                 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2223                 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2224                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2225                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2226                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2227         }
2228
2229         rtl8192ce_bt_var_init(hw);
2230 }
2231
2232 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2233 {
2234         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2235
2236         /* 0:Low, 1:High, 2:From Efuse. */
2237         rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2238         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2239         rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2240         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2241         rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2242 }
2243
2244
2245 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2246 {
2247         struct rtl_priv *rtlpriv = rtl_priv(hw);
2248         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2249         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2250
2251         u8 u1_tmp;
2252
2253         if (rtlpcipriv->bt_coexist.bt_coexistence &&
2254             ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2255               rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2256
2257                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2258                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2259
2260                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2261                          BIT_OFFSET_LEN_MASK_32(0, 1);
2262                 u1_tmp = u1_tmp |
2263                          ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2264                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2265                          ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2266                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2267                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2268
2269                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2270                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2271                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2272
2273                 /* Config to 1T1R. */
2274                 if (rtlphy->rf_type == RF_1T1R) {
2275                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2276                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2277                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2278
2279                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2280                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2281                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2282                 }
2283         }
2284 }
2285
2286 void rtl92ce_suspend(struct ieee80211_hw *hw)
2287 {
2288 }
2289
2290 void rtl92ce_resume(struct ieee80211_hw *hw)
2291 {
2292 }