1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
39 #include "../rtl8192c/phy_common.h"
42 #include "../rtl8192c/dm_common.h"
43 #include "../rtl8192c/fw_common.h"
45 #include "../rtl8192ce/hw.h"
50 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
52 struct rtl_priv *rtlpriv = rtl_priv(hw);
53 struct rtl_phy *rtlphy = &(rtlpriv->phy);
54 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
56 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
57 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
58 if (IS_HIGHT_PA(rtlefuse->board_type)) {
59 rtlphy->hwparam_tables[PHY_REG_PG].length =
60 RTL8192CUPHY_REG_Array_PG_HPLength;
61 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
62 RTL8192CUPHY_REG_Array_PG_HP;
64 rtlphy->hwparam_tables[PHY_REG_PG].length =
65 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
66 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
67 RTL8192CUPHY_REG_ARRAY_PG;
70 rtlphy->hwparam_tables[PHY_REG_2T].length =
71 RTL8192CUPHY_REG_2TARRAY_LENGTH;
72 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
73 RTL8192CUPHY_REG_2TARRAY;
74 rtlphy->hwparam_tables[RADIOA_2T].length =
75 RTL8192CURADIOA_2TARRAYLENGTH;
76 rtlphy->hwparam_tables[RADIOA_2T].pdata =
77 RTL8192CURADIOA_2TARRAY;
78 rtlphy->hwparam_tables[RADIOB_2T].length =
79 RTL8192CURADIOB_2TARRAYLENGTH;
80 rtlphy->hwparam_tables[RADIOB_2T].pdata =
81 RTL8192CU_RADIOB_2TARRAY;
82 rtlphy->hwparam_tables[AGCTAB_2T].length =
83 RTL8192CUAGCTAB_2TARRAYLENGTH;
84 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
85 RTL8192CUAGCTAB_2TARRAY;
87 if (IS_HIGHT_PA(rtlefuse->board_type)) {
88 rtlphy->hwparam_tables[PHY_REG_1T].length =
89 RTL8192CUPHY_REG_1T_HPArrayLength;
90 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
91 RTL8192CUPHY_REG_1T_HPArray;
92 rtlphy->hwparam_tables[RADIOA_1T].length =
93 RTL8192CURadioA_1T_HPArrayLength;
94 rtlphy->hwparam_tables[RADIOA_1T].pdata =
95 RTL8192CURadioA_1T_HPArray;
96 rtlphy->hwparam_tables[RADIOB_1T].length =
97 RTL8192CURADIOB_1TARRAYLENGTH;
98 rtlphy->hwparam_tables[RADIOB_1T].pdata =
99 RTL8192CU_RADIOB_1TARRAY;
100 rtlphy->hwparam_tables[AGCTAB_1T].length =
101 RTL8192CUAGCTAB_1T_HPArrayLength;
102 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
103 Rtl8192CUAGCTAB_1T_HPArray;
105 rtlphy->hwparam_tables[PHY_REG_1T].length =
106 RTL8192CUPHY_REG_1TARRAY_LENGTH;
107 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
108 RTL8192CUPHY_REG_1TARRAY;
109 rtlphy->hwparam_tables[RADIOA_1T].length =
110 RTL8192CURADIOA_1TARRAYLENGTH;
111 rtlphy->hwparam_tables[RADIOA_1T].pdata =
112 RTL8192CU_RADIOA_1TARRAY;
113 rtlphy->hwparam_tables[RADIOB_1T].length =
114 RTL8192CURADIOB_1TARRAYLENGTH;
115 rtlphy->hwparam_tables[RADIOB_1T].pdata =
116 RTL8192CU_RADIOB_1TARRAY;
117 rtlphy->hwparam_tables[AGCTAB_1T].length =
118 RTL8192CUAGCTAB_1TARRAYLENGTH;
119 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
120 RTL8192CUAGCTAB_1TARRAY;
124 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
128 struct rtl_priv *rtlpriv = rtl_priv(hw);
129 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
130 u8 rf_path, index, tempval;
133 for (rf_path = 0; rf_path < 2; rf_path++) {
134 for (i = 0; i < 3; i++) {
135 if (!autoload_fail) {
137 eeprom_chnlarea_txpwr_cck[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
140 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
141 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
145 eeprom_chnlarea_txpwr_cck[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
148 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
149 EEPROM_DEFAULT_TXPOWERLEVEL;
153 for (i = 0; i < 3; i++) {
155 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
157 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
158 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
160 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
161 ((tempval & 0xf0) >> 4);
163 for (rf_path = 0; rf_path < 2; rf_path++)
164 for (i = 0; i < 3; i++)
165 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
166 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
169 eeprom_chnlarea_txpwr_cck[rf_path][i]);
170 for (rf_path = 0; rf_path < 2; rf_path++)
171 for (i = 0; i < 3; i++)
172 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
173 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
176 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
177 for (rf_path = 0; rf_path < 2; rf_path++)
178 for (i = 0; i < 3; i++)
179 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
180 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
183 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
184 for (rf_path = 0; rf_path < 2; rf_path++) {
185 for (i = 0; i < 14; i++) {
186 index = rtl92c_get_chnl_group((u8)i);
187 rtlefuse->txpwrlevel_cck[rf_path][i] =
188 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
189 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
191 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
193 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
195 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
197 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
199 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
201 eprom_chnl_txpwr_ht40_2sdf[rf_path]
204 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
207 for (i = 0; i < 14; i++) {
208 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
209 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
210 rtlefuse->txpwrlevel_cck[rf_path][i],
211 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
212 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
215 for (i = 0; i < 3; i++) {
216 if (!autoload_fail) {
217 rtlefuse->eeprom_pwrlimit_ht40[i] =
218 hwinfo[EEPROM_TXPWR_GROUP + i];
219 rtlefuse->eeprom_pwrlimit_ht20[i] =
220 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
222 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
223 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
226 for (rf_path = 0; rf_path < 2; rf_path++) {
227 for (i = 0; i < 14; i++) {
228 index = rtl92c_get_chnl_group((u8)i);
229 if (rf_path == RF90_PATH_A) {
230 rtlefuse->pwrgroup_ht20[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht20[index]
233 rtlefuse->pwrgroup_ht40[rf_path][i] =
234 (rtlefuse->eeprom_pwrlimit_ht40[index]
236 } else if (rf_path == RF90_PATH_B) {
237 rtlefuse->pwrgroup_ht20[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht20[index]
240 rtlefuse->pwrgroup_ht40[rf_path][i] =
241 ((rtlefuse->eeprom_pwrlimit_ht40[index]
244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
245 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
247 rtlefuse->pwrgroup_ht20[rf_path][i]);
248 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
249 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
251 rtlefuse->pwrgroup_ht40[rf_path][i]);
254 for (i = 0; i < 14; i++) {
255 index = rtl92c_get_chnl_group((u8)i);
257 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
259 tempval = EEPROM_DEFAULT_HT20_DIFF;
260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
261 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
262 ((tempval >> 4) & 0xF);
263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
264 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
265 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
266 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
267 index = rtl92c_get_chnl_group((u8)i);
269 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
271 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
272 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
274 ((tempval >> 4) & 0xF);
276 rtlefuse->legacy_ht_txpowerdiff =
277 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
278 for (i = 0; i < 14; i++)
279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
280 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
281 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
282 for (i = 0; i < 14; i++)
283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
284 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
285 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
286 for (i = 0; i < 14; i++)
287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
288 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
289 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
290 for (i = 0; i < 14; i++)
291 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
292 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
293 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
295 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
297 rtlefuse->eeprom_regulatory = 0;
298 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
299 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
300 if (!autoload_fail) {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
304 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
305 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
307 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
308 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
309 rtlefuse->eeprom_tssi[RF90_PATH_A],
310 rtlefuse->eeprom_tssi[RF90_PATH_B]);
312 tempval = hwinfo[EEPROM_THERMAL_METER];
314 tempval = EEPROM_DEFAULT_THERMALMETER;
315 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
316 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
317 rtlefuse->eeprom_thermalmeter > 0x1c)
318 rtlefuse->eeprom_thermalmeter = 0x12;
319 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
320 rtlefuse->apk_thermalmeterignore = true;
321 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
322 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
323 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
328 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
329 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
332 if (IS_NORMAL_CHIP(rtlhal->version)) {
333 boardType = ((contents[EEPROM_RF_OPT1]) &
334 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
336 boardType = contents[EEPROM_RF_OPT4];
337 boardType &= BOARD_TYPE_TEST_MASK;
339 rtlefuse->board_type = boardType;
340 if (IS_HIGHT_PA(rtlefuse->board_type))
341 rtlefuse->external_pa = 1;
342 pr_info("Board Type %x\n", rtlefuse->board_type);
345 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
347 struct rtl_priv *rtlpriv = rtl_priv(hw);
348 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
349 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
351 u8 hwinfo[HWSET_MAX_SIZE] = {0};
354 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
355 rtl_efuse_shadow_map_update(hw);
356 memcpy((void *)hwinfo,
357 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
359 } else if (rtlefuse->epromtype == EEPROM_93C46) {
360 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
361 "RTL819X Not boot from eeprom, check it !!\n");
363 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
364 hwinfo, HWSET_MAX_SIZE);
365 eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
366 if (eeprom_id != RTL8190_EEPROM_ID) {
367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
368 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
369 rtlefuse->autoload_failflag = true;
371 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
372 rtlefuse->autoload_failflag = false;
374 if (rtlefuse->autoload_failflag)
376 for (i = 0; i < 6; i += 2) {
377 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
378 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
380 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
381 _rtl92cu_read_txpower_info_from_hwpg(hw,
382 rtlefuse->autoload_failflag, hwinfo);
383 rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
384 rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
385 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
386 rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
387 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
388 rtlefuse->eeprom_version =
389 le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
390 rtlefuse->txpwr_fromeprom = true;
391 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
392 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
393 rtlefuse->eeprom_oemid);
394 if (rtlhal->oem_id == RT_CID_DEFAULT) {
395 switch (rtlefuse->eeprom_oemid) {
396 case EEPROM_CID_DEFAULT:
397 if (rtlefuse->eeprom_did == 0x8176) {
398 if ((rtlefuse->eeprom_svid == 0x103C &&
399 rtlefuse->eeprom_smid == 0x1629))
400 rtlhal->oem_id = RT_CID_819X_HP;
402 rtlhal->oem_id = RT_CID_DEFAULT;
404 rtlhal->oem_id = RT_CID_DEFAULT;
407 case EEPROM_CID_TOSHIBA:
408 rtlhal->oem_id = RT_CID_TOSHIBA;
411 rtlhal->oem_id = RT_CID_819X_QMI;
413 case EEPROM_CID_WHQL:
415 rtlhal->oem_id = RT_CID_DEFAULT;
419 _rtl92cu_read_board_type(hw, hwinfo);
422 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
424 struct rtl_priv *rtlpriv = rtl_priv(hw);
425 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
426 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
428 switch (rtlhal->oem_id) {
430 usb_priv->ledctl.led_opendrain = true;
432 case RT_CID_819X_LENOVO:
436 case RT_CID_819X_ACER:
441 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
445 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
448 struct rtl_priv *rtlpriv = rtl_priv(hw);
449 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
450 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
453 if (!IS_NORMAL_CHIP(rtlhal->version))
455 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
456 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
457 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
458 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
459 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
460 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
461 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
462 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
463 _rtl92cu_read_adapter_info(hw);
464 _rtl92cu_hal_customized_behavior(hw);
468 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
470 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 /* polling autoload done. */
475 u32 pollingCount = 0;
478 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
479 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
483 if (pollingCount++ > 100) {
484 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
485 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
489 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
490 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
491 /* Power on when re-enter from IPS/Radio off/card disable */
492 /* enable SPS into PWM mode */
493 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
495 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
496 if (0 == (value8 & LDV12_EN)) {
498 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
499 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
500 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
503 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
504 value8 &= ~ISO_MD2PP;
505 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
507 /* auto enable WLAN */
509 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
510 value16 |= APFM_ONMAC;
511 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
513 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
514 pr_info("MAC auto ON okay!\n");
517 if (pollingCount++ > 1000) {
518 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
519 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
523 /* Enable Radio ,GPIO ,and LED function */
524 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
525 /* release RF digital isolation */
526 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
527 value16 &= ~ISO_DIOR;
528 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
529 /* Reconsider when to do this operation after asking HWSD. */
531 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
532 REG_APSD_CTRL) & ~BIT(6)));
535 } while ((pollingCount < 200) &&
536 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
537 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
538 value16 = rtl_read_word(rtlpriv, REG_CR);
539 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
540 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
541 rtl_write_word(rtlpriv, REG_CR, value16);
545 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
550 struct rtl_priv *rtlpriv = rtl_priv(hw);
551 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
552 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
553 u32 outEPNum = (u32)out_ep_num;
560 u32 txQPageNum, txQPageUnit, txQRemainPage;
563 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
564 CHIP_A_PAGE_NUM_PUBQ;
565 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
567 txQPageUnit = txQPageNum/outEPNum;
568 txQRemainPage = txQPageNum % outEPNum;
569 if (queue_sel & TX_SELE_HQ)
571 if (queue_sel & TX_SELE_LQ)
573 /* HIGH priority queue always present in the configuration of
574 * 2 out-ep. Remainder pages have assigned to High queue */
575 if ((outEPNum > 1) && (txQRemainPage))
576 numHQ += txQRemainPage;
577 /* NOTE: This step done before writting REG_RQPN. */
579 if (queue_sel & TX_SELE_NQ)
581 value8 = (u8)_NPQ(numNQ);
582 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
585 /* for WMM ,number of out-ep must more than or equal to 2! */
586 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
587 WMM_CHIP_A_PAGE_NUM_PUBQ;
588 if (queue_sel & TX_SELE_HQ) {
589 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
590 WMM_CHIP_A_PAGE_NUM_HPQ;
592 if (queue_sel & TX_SELE_LQ) {
593 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
594 WMM_CHIP_A_PAGE_NUM_LPQ;
596 /* NOTE: This step done before writting REG_RQPN. */
598 if (queue_sel & TX_SELE_NQ)
599 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
600 value8 = (u8)_NPQ(numNQ);
601 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
605 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
606 rtl_write_dword(rtlpriv, REG_RQPN, value32);
609 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
611 struct rtl_priv *rtlpriv = rtl_priv(hw);
612 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
617 txpktbuf_bndy = TX_PAGE_BOUNDARY;
619 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
620 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
621 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
622 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
623 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
624 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
625 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
626 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
627 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
628 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
629 rtl_write_byte(rtlpriv, REG_PBP, value8);
632 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
633 u16 bkQ, u16 viQ, u16 voQ,
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
639 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
640 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
641 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
642 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
645 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
649 u16 uninitialized_var(value);
659 value = QUEUE_NORMAL;
662 WARN_ON(1); /* Shall not reach here! */
665 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
667 pr_info("Tx queue select: 0x%02x\n", queue_sel);
670 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
674 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
675 u16 uninitialized_var(valueHi);
676 u16 uninitialized_var(valueLow);
679 case (TX_SELE_HQ | TX_SELE_LQ):
680 valueHi = QUEUE_HIGH;
681 valueLow = QUEUE_LOW;
683 case (TX_SELE_NQ | TX_SELE_LQ):
684 valueHi = QUEUE_NORMAL;
685 valueLow = QUEUE_LOW;
687 case (TX_SELE_HQ | TX_SELE_NQ):
688 valueHi = QUEUE_HIGH;
689 valueLow = QUEUE_NORMAL;
702 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
710 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
711 pr_info("Tx queue select: 0x%02x\n", queue_sel);
714 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
718 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
719 struct rtl_priv *rtlpriv = rtl_priv(hw);
721 if (!wmm_enable) { /* typical setting */
728 } else { /* for WMM */
736 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
737 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
741 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
746 switch (out_ep_num) {
748 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
752 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
756 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
760 WARN_ON(1); /* Shall not reach here! */
765 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
771 struct rtl_priv *rtlpriv = rtl_priv(hw);
773 switch (out_ep_num) {
774 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
775 if (!wmm_enable) /* typical setting */
776 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
779 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
783 if (TX_SELE_LQ == queue_sel) {
784 /* map all endpoint to Low queue */
786 } else if (TX_SELE_HQ == queue_sel) {
787 /* map all endpoint to High queue */
788 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
789 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
793 WARN_ON(1); /* Shall not reach here! */
796 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
797 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
801 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
807 if (IS_NORMAL_CHIP(rtlhal->version))
808 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
811 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
815 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
819 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
823 struct rtl_priv *rtlpriv = rtl_priv(hw);
824 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
826 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
827 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
828 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
829 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
830 /* Accept all multicast address */
831 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
832 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
833 /* Accept all management frames */
835 rtl92c_set_mgt_filter(hw, value16);
836 /* Reject all control frame - default value is 0 */
837 rtl92c_set_ctrl_filter(hw, 0x0);
838 /* Accept all data frames */
840 rtl92c_set_data_filter(hw, value16);
843 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
845 struct rtl_priv *rtlpriv = rtl_priv(hw);
846 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
847 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
848 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
851 u8 wmm_enable = false; /* TODO */
852 u8 out_ep_nums = rtlusb->out_ep_nums;
853 u8 queue_sel = rtlusb->out_queue_sel;
854 err = _rtl92cu_init_power_on(hw);
857 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
858 "Failed to init power on!\n");
862 boundary = TX_PAGE_BOUNDARY;
863 } else { /* for WMM */
864 boundary = (IS_NORMAL_CHIP(rtlhal->version))
865 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
866 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
868 if (false == rtl92c_init_llt_table(hw, boundary)) {
869 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
870 "Failed to init LLT Table!\n");
873 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
875 _rtl92c_init_trx_buffer(hw, wmm_enable);
876 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
878 /* Get Rx PHY status in order to report RSSI and others. */
879 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
880 rtl92c_init_interrupt(hw);
881 rtl92c_init_network_type(hw);
882 _rtl92cu_init_wmac_setting(hw);
883 rtl92c_init_adaptive_ctrl(hw);
884 rtl92c_init_edca(hw);
885 rtl92c_init_rate_fallback(hw);
886 rtl92c_init_retry_function(hw);
887 _rtl92cu_init_usb_aggregation(hw);
888 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
889 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
890 rtl92c_init_beacon_parameters(hw, rtlhal->version);
891 rtl92c_init_ampdu_aggregation(hw);
892 rtl92c_init_beacon_max_error(hw, true);
896 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
898 struct rtl_priv *rtlpriv = rtl_priv(hw);
899 u8 sec_reg_value = 0x0;
900 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
902 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
903 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
904 rtlpriv->sec.pairwise_enc_algorithm,
905 rtlpriv->sec.group_enc_algorithm);
906 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
907 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
908 "not open sw encryption\n");
911 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
912 if (rtlpriv->sec.use_defaultkey) {
913 sec_reg_value |= SCR_TxUseDK;
914 sec_reg_value |= SCR_RxUseDK;
916 if (IS_NORMAL_CHIP(rtlhal->version))
917 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
918 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
919 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
921 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
924 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
926 struct rtl_priv *rtlpriv = rtl_priv(hw);
927 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
929 /* To Fix MAC loopback mode fail. */
930 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
931 rtl_write_byte(rtlpriv, 0x15, 0xe9);
933 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
934 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
935 /* fixed USB interface interference issue */
936 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
937 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
938 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
939 rtlusb->reg_bcn_ctrl_val = 0x18;
940 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
943 static void _InitPABias(struct ieee80211_hw *hw)
945 struct rtl_priv *rtlpriv = rtl_priv(hw);
946 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
949 /* FIXED PA current issue */
950 pa_setting = efuse_read_1byte(hw, 0x1FA);
951 if (!(pa_setting & BIT(0))) {
952 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
953 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
954 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
955 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
957 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
958 IS_92C_SERIAL(rtlhal->version)) {
959 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
960 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
961 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
962 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
964 if (!(pa_setting & BIT(4))) {
965 pa_setting = rtl_read_byte(rtlpriv, 0x16);
967 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
971 static void _update_mac_setting(struct ieee80211_hw *hw)
973 struct rtl_priv *rtlpriv = rtl_priv(hw);
974 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
976 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
977 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
978 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
979 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
982 int rtl92cu_hw_init(struct ieee80211_hw *hw)
984 struct rtl_priv *rtlpriv = rtl_priv(hw);
985 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
986 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
987 struct rtl_phy *rtlphy = &(rtlpriv->phy);
988 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
990 static bool iqk_initialized;
993 /* As this function can take a very long time (up to 350 ms)
994 * and can be called with irqs disabled, reenable the irqs
995 * to let the other devices continue being serviced.
997 * It is safe doing so since our own interrupts will only be enabled
998 * in a subsequent step.
1000 local_save_flags(flags);
1003 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1004 err = _rtl92cu_init_mac(hw);
1006 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
1009 err = rtl92c_download_fw(hw);
1011 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1012 "Failed to download FW. Init HW without FW now..\n");
1016 rtlhal->last_hmeboxnum = 0; /* h2c */
1017 _rtl92cu_phy_param_tab_init(hw);
1018 rtl92cu_phy_mac_config(hw);
1019 rtl92cu_phy_bb_config(hw);
1020 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1021 rtl92c_phy_rf_config(hw);
1022 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1023 !IS_92C_SERIAL(rtlhal->version)) {
1024 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1025 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1027 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1028 RF_CHNLBW, RFREG_OFFSET_MASK);
1029 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1030 RF_CHNLBW, RFREG_OFFSET_MASK);
1031 rtl92cu_bb_block_on(hw);
1032 rtl_cam_reset_all_entry(hw);
1033 rtl92cu_enable_hw_security_config(hw);
1034 ppsc->rfpwr_state = ERFON;
1035 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1036 if (ppsc->rfpwr_state == ERFON) {
1037 rtl92c_phy_set_rfpath_switch(hw, 1);
1038 if (iqk_initialized) {
1039 rtl92c_phy_iq_calibrate(hw, true);
1041 rtl92c_phy_iq_calibrate(hw, false);
1042 iqk_initialized = true;
1044 rtl92c_dm_check_txpower_tracking(hw);
1045 rtl92c_phy_lc_calibrate(hw);
1047 _rtl92cu_hw_configure(hw);
1049 _update_mac_setting(hw);
1052 local_irq_restore(flags);
1056 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1058 struct rtl_priv *rtlpriv = rtl_priv(hw);
1059 /**************************************
1060 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1061 b. RF path 0 offset 0x00 = 0x00 disable RF
1062 c. APSD_CTRL 0x600[7:0] = 0x40
1063 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1064 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1065 ***************************************/
1066 u8 eRFPath = 0, value8 = 0;
1067 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1068 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1071 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1073 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1074 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1075 value8 &= (~FEN_BB_GLB_RSTn);
1076 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1079 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1081 struct rtl_priv *rtlpriv = rtl_priv(hw);
1082 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1084 if (rtlhal->fw_version <= 0x20) {
1085 /*****************************
1086 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1087 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1088 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1089 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1090 ******************************/
1093 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1094 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1095 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1096 (~FEN_CPUEN))); /* reset MCU ,8051 */
1097 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1098 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1099 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1100 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1101 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1102 FEN_CPUEN)); /* enable MCU ,8051 */
1106 /* IF fw in RAM code, do reset */
1107 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1108 /* reset MCU ready status */
1109 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1110 /* 8051 reset by self */
1111 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1112 while ((retry_cnts++ < 100) &&
1113 (FEN_CPUEN & rtl_read_word(rtlpriv,
1114 REG_SYS_FUNC_EN))) {
1117 if (retry_cnts >= 100) {
1118 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1119 "#####=> 8051 reset failed!.........................\n");
1120 /* if 8051 reset fail, reset MAC. */
1121 rtl_write_byte(rtlpriv,
1122 REG_SYS_FUNC_EN + 1,
1127 /* Reset MAC and Enable 8051 */
1128 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1129 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1132 /*****************************
1133 Without HW auto state machine
1134 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1135 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1136 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1137 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1138 ******************************/
1139 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1140 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1141 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1142 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1146 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1148 struct rtl_priv *rtlpriv = rtl_priv(hw);
1149 /*****************************
1150 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1151 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1152 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1153 ******************************/
1154 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1155 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1158 static void _DisableGPIO(struct ieee80211_hw *hw)
1160 struct rtl_priv *rtlpriv = rtl_priv(hw);
1161 /***************************************
1162 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1163 k. Value = GPIO_PIN_CTRL[7:0]
1164 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1165 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1166 n. LEDCFG 0x4C[15:0] = 0x8080
1167 ***************************************/
1172 /* 1. Disable GPIO[7:0] */
1173 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1174 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1175 value8 = (u8)(value32&0x000000FF);
1176 value32 |= ((value8<<8) | 0x00FF0000);
1177 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1178 /* 2. Disable GPIO[10:8] */
1179 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1180 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1181 value8 = (u8)(value16&0x000F);
1182 value16 |= ((value8<<4) | 0x0780);
1183 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1184 /* 3. Disable LED0 & 1 */
1185 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1188 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1190 struct rtl_priv *rtlpriv = rtl_priv(hw);
1195 /*****************************
1196 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1197 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1198 r. When driver call disable, the ASIC will turn off remaining
1200 ******************************/
1201 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1202 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1203 value8 &= (~LDV12_EN);
1204 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1207 /*****************************
1208 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1209 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1210 ******************************/
1211 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1212 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1213 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1214 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1217 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1219 /* ==== RF Off Sequence ==== */
1220 _DisableRFAFEAndResetBB(hw);
1221 /* ==== Reset digital sequence ====== */
1222 _ResetDigitalProcedure1(hw, false);
1223 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1225 /* ==== Disable analog sequence === */
1226 _DisableAnalog(hw, false);
1229 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1231 /*==== RF Off Sequence ==== */
1232 _DisableRFAFEAndResetBB(hw);
1233 /* ==== Reset digital sequence ====== */
1234 _ResetDigitalProcedure1(hw, true);
1235 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1237 /* ==== Reset digital sequence ====== */
1238 _ResetDigitalProcedure2(hw);
1239 /* ==== Disable analog sequence === */
1240 _DisableAnalog(hw, true);
1243 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1244 u8 set_bits, u8 clear_bits)
1246 struct rtl_priv *rtlpriv = rtl_priv(hw);
1247 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1249 rtlusb->reg_bcn_ctrl_val |= set_bits;
1250 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1251 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1254 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1256 struct rtl_priv *rtlpriv = rtl_priv(hw);
1257 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1259 if (IS_NORMAL_CHIP(rtlhal->version)) {
1260 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1261 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1262 tmp1byte & (~BIT(6)));
1263 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1264 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1265 tmp1byte &= ~(BIT(0));
1266 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1268 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1269 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1273 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1275 struct rtl_priv *rtlpriv = rtl_priv(hw);
1276 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1279 if (IS_NORMAL_CHIP(rtlhal->version)) {
1280 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1281 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1283 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1284 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1286 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1288 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1289 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1293 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1295 struct rtl_priv *rtlpriv = rtl_priv(hw);
1296 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1298 if (IS_NORMAL_CHIP(rtlhal->version))
1299 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1301 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1304 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1306 struct rtl_priv *rtlpriv = rtl_priv(hw);
1307 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1309 if (IS_NORMAL_CHIP(rtlhal->version))
1310 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1312 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1315 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1316 enum nl80211_iftype type)
1318 struct rtl_priv *rtlpriv = rtl_priv(hw);
1319 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1320 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1323 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1324 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1325 NL80211_IFTYPE_STATION) {
1326 _rtl92cu_stop_tx_beacon(hw);
1327 _rtl92cu_enable_bcn_sub_func(hw);
1328 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1329 _rtl92cu_resume_tx_beacon(hw);
1330 _rtl92cu_disable_bcn_sub_func(hw);
1332 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1333 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1337 case NL80211_IFTYPE_UNSPECIFIED:
1338 bt_msr |= MSR_NOLINK;
1339 ledaction = LED_CTL_LINK;
1340 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1341 "Set Network type to NO LINK!\n");
1343 case NL80211_IFTYPE_ADHOC:
1344 bt_msr |= MSR_ADHOC;
1345 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1346 "Set Network type to Ad Hoc!\n");
1348 case NL80211_IFTYPE_STATION:
1349 bt_msr |= MSR_INFRA;
1350 ledaction = LED_CTL_LINK;
1351 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1352 "Set Network type to STA!\n");
1354 case NL80211_IFTYPE_AP:
1356 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1357 "Set Network type to AP!\n");
1360 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1361 "Network type %d not supported!\n", type);
1364 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1365 rtlpriv->cfg->ops->led_control(hw, ledaction);
1366 if ((bt_msr & MSR_MASK) == MSR_AP)
1367 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1369 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1375 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1377 struct rtl_priv *rtlpriv = rtl_priv(hw);
1378 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1379 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1380 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1381 enum nl80211_iftype opmode;
1383 mac->link_state = MAC80211_NOLINK;
1384 opmode = NL80211_IFTYPE_UNSPECIFIED;
1385 _rtl92cu_set_media_status(hw, opmode);
1386 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1387 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1388 if (rtlusb->disableHWSM)
1389 _CardDisableHWSM(hw);
1391 _CardDisableWithoutHWSM(hw);
1394 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1396 struct rtl_priv *rtlpriv = rtl_priv(hw);
1397 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1400 if (rtlpriv->psc.rfpwr_state != ERFON)
1403 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1407 if (IS_NORMAL_CHIP(rtlhal->version)) {
1408 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1411 reg_rcr |= RCR_CBSSID;
1412 tmp = BIT(4) | BIT(5);
1414 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1416 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1419 if (IS_NORMAL_CHIP(rtlhal->version)) {
1420 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1423 reg_rcr &= ~RCR_CBSSID;
1424 tmp = BIT(4) | BIT(5);
1426 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1427 rtlpriv->cfg->ops->set_hw_reg(hw,
1428 HW_VAR_RCR, (u8 *) (®_rcr));
1429 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1433 /*========================================================================== */
1435 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1437 struct rtl_priv *rtlpriv = rtl_priv(hw);
1439 if (_rtl92cu_set_media_status(hw, type))
1442 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1443 if (type != NL80211_IFTYPE_AP)
1444 rtl92cu_set_check_bssid(hw, true);
1446 rtl92cu_set_check_bssid(hw, false);
1452 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1454 struct rtl_priv *rtlpriv = rtl_priv(hw);
1455 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1457 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1459 /* TODO: Remove these magic number */
1460 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1461 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1462 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1463 /* Change beacon AIFS to the largest number
1464 * beacause test chip does not contension before sending beacon. */
1465 if (IS_NORMAL_CHIP(rtlhal->version))
1466 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1468 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1471 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1474 struct rtl_priv *rtlpriv = rtl_priv(hw);
1476 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1477 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1480 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1483 struct rtl_priv *rtlpriv = rtl_priv(hw);
1484 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1485 u16 bcn_interval, atim_window;
1488 bcn_interval = mac->beacon_interval;
1489 atim_window = 2; /*FIX MERGE */
1490 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1491 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1492 _InitBeaconParameters(hw);
1493 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1495 * Force beacon frame transmission even after receiving beacon frame
1496 * from other ad hoc STA
1499 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1501 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1503 rtl_write_dword(rtlpriv, REG_TCR, value32);
1505 rtl_write_dword(rtlpriv, REG_TCR, value32);
1506 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1507 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1509 /* TODO: Modify later (Find the right parameters)
1510 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1511 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1512 (mac->opmode == NL80211_IFTYPE_AP)) {
1513 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1514 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1516 _beacon_function_enable(hw, true, true);
1519 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1521 struct rtl_priv *rtlpriv = rtl_priv(hw);
1522 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1523 u16 bcn_interval = mac->beacon_interval;
1525 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1527 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1530 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1531 u32 add_msr, u32 rm_msr)
1535 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1537 struct rtl_priv *rtlpriv = rtl_priv(hw);
1538 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1539 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1543 *((u32 *)(val)) = mac->rx_conf;
1545 case HW_VAR_RF_STATE:
1546 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1548 case HW_VAR_FWLPS_RF_ON:{
1549 enum rf_pwrstate rfState;
1552 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1554 if (rfState == ERFOFF) {
1555 *((bool *) (val)) = true;
1557 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1558 val_rcr &= 0x00070000;
1560 *((bool *) (val)) = false;
1562 *((bool *) (val)) = true;
1566 case HW_VAR_FW_PSMODE_STATUS:
1567 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1569 case HW_VAR_CORRECT_TSF:{
1571 u32 *ptsf_low = (u32 *)&tsf;
1572 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1574 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1575 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1576 *((u64 *)(val)) = tsf;
1579 case HW_VAR_MGT_FILTER:
1580 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1582 case HW_VAR_CTRL_FILTER:
1583 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1585 case HW_VAR_DATA_FILTER:
1586 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1589 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1590 "switch case not processed\n");
1595 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1597 struct rtl_priv *rtlpriv = rtl_priv(hw);
1598 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1599 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1600 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1601 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1602 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1603 enum wireless_mode wirelessmode = mac->mode;
1607 case HW_VAR_ETHER_ADDR:{
1608 for (idx = 0; idx < ETH_ALEN; idx++) {
1609 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1614 case HW_VAR_BASIC_RATE:{
1615 u16 rate_cfg = ((u16 *) val)[0];
1620 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1621 * && ((rate_cfg & 0x150) == 0)) {
1622 * rate_cfg |= 0x010;
1625 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1626 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1627 (rate_cfg >> 8) & 0xff);
1628 while (rate_cfg > 0x1) {
1632 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1637 for (idx = 0; idx < ETH_ALEN; idx++) {
1638 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1644 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1645 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1646 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1647 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1648 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1649 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1650 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1653 case HW_VAR_SLOT_TIME:{
1657 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1658 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1659 "HW_VAR_SLOT_TIME %x\n", val[0]);
1661 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1662 rtlpriv->cfg->ops->set_hw_reg(hw,
1669 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1670 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1671 IS_WIRELESS_MODE_N_5G(wirelessmode))
1675 u1bAIFS = sifstime + (2 * val[0]);
1676 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1678 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1680 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1682 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1687 case HW_VAR_ACK_PREAMBLE:{
1689 u8 short_preamble = (bool)*val;
1693 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1696 case HW_VAR_AMPDU_MIN_SPACE:{
1697 u8 min_spacing_to_set;
1700 min_spacing_to_set = *val;
1701 if (min_spacing_to_set <= 7) {
1702 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1704 case AESCCMP_ENCRYPTION:
1707 case WEP40_ENCRYPTION:
1708 case WEP104_ENCRYPTION:
1709 case TKIP_ENCRYPTION:
1716 if (min_spacing_to_set < sec_min_space)
1717 min_spacing_to_set = sec_min_space;
1718 mac->min_space_cfg = ((mac->min_space_cfg &
1720 min_spacing_to_set);
1721 *val = min_spacing_to_set;
1722 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1723 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1724 mac->min_space_cfg);
1725 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1726 mac->min_space_cfg);
1730 case HW_VAR_SHORTGI_DENSITY:{
1733 density_to_set = *val;
1734 density_to_set &= 0x1f;
1735 mac->min_space_cfg &= 0x07;
1736 mac->min_space_cfg |= (density_to_set << 3);
1737 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1738 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1739 mac->min_space_cfg);
1740 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1741 mac->min_space_cfg);
1744 case HW_VAR_AMPDU_FACTOR:{
1745 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1747 u8 *p_regtoset = NULL;
1750 p_regtoset = regtoset_normal;
1751 factor_toset = *val;
1752 if (factor_toset <= 3) {
1753 factor_toset = (1 << (factor_toset + 2));
1754 if (factor_toset > 0xf)
1756 for (index = 0; index < 4; index++) {
1757 if ((p_regtoset[index] & 0xf0) >
1758 (factor_toset << 4))
1760 (p_regtoset[index] & 0x0f)
1761 | (factor_toset << 4);
1762 if ((p_regtoset[index] & 0x0f) >
1765 (p_regtoset[index] & 0xf0)
1767 rtl_write_byte(rtlpriv,
1768 (REG_AGGLEN_LMT + index),
1771 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1772 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1777 case HW_VAR_AC_PARAM:{
1780 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1781 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1782 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1784 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1785 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1786 AC_PARAM_ECW_MIN_OFFSET);
1787 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1788 AC_PARAM_ECW_MAX_OFFSET);
1789 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1790 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1791 "queue:%x, ac_param:%x\n",
1792 e_aci, u4b_ac_param);
1795 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1799 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1803 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1807 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1812 "SetHwReg8185(): invalid aci: %d !\n",
1816 if (rtlusb->acm_method != EACMWAY2_SW)
1817 rtlpriv->cfg->ops->set_hw_reg(hw,
1818 HW_VAR_ACM_CTRL, &e_aci);
1821 case HW_VAR_ACM_CTRL:{
1823 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
1824 (&(mac->ac[0].aifs));
1825 u8 acm = p_aci_aifsn->f.acm;
1826 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
1829 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
1833 acm_ctrl |= AcmHw_BeqEn;
1836 acm_ctrl |= AcmHw_ViqEn;
1839 acm_ctrl |= AcmHw_VoqEn;
1842 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1843 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
1850 acm_ctrl &= (~AcmHw_BeqEn);
1853 acm_ctrl &= (~AcmHw_ViqEn);
1856 acm_ctrl &= (~AcmHw_BeqEn);
1859 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1860 "switch case not processed\n");
1864 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
1865 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
1867 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
1871 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1872 mac->rx_conf = ((u32 *) (val))[0];
1873 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1874 "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1877 case HW_VAR_RETRY_LIMIT:{
1878 u8 retry_limit = val[0];
1880 rtl_write_word(rtlpriv, REG_RL,
1881 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1882 retry_limit << RETRY_LIMIT_LONG_SHIFT);
1883 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1884 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1888 case HW_VAR_DUAL_TSF_RST:
1889 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1891 case HW_VAR_EFUSE_BYTES:
1892 rtlefuse->efuse_usedbytes = *((u16 *) val);
1894 case HW_VAR_EFUSE_USAGE:
1895 rtlefuse->efuse_usedpercentage = *val;
1898 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1900 case HW_VAR_WPA_CONFIG:
1901 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1903 case HW_VAR_SET_RPWM:{
1904 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1906 if (rpwm_val & BIT(7))
1907 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1909 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1913 case HW_VAR_H2C_FW_PWRMODE:{
1916 if ((psmode != FW_PS_ACTIVE_MODE) &&
1917 (!IS_92C_SERIAL(rtlhal->version)))
1918 rtl92c_dm_rf_saving(hw, true);
1919 rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1922 case HW_VAR_FW_PSMODE_STATUS:
1923 ppsc->fw_current_inpsmode = *((bool *) val);
1925 case HW_VAR_H2C_FW_JOINBSSRPT:{
1928 bool recover = false;
1930 if (mstatus == RT_MEDIA_CONNECT) {
1931 rtlpriv->cfg->ops->set_hw_reg(hw,
1933 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1934 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1935 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1936 tmp_reg422 = rtl_read_byte(rtlpriv,
1937 REG_FWHW_TXQ_CTRL + 2);
1938 if (tmp_reg422 & BIT(6))
1940 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1941 tmp_reg422 & (~BIT(6)));
1942 rtl92c_set_fw_rsvdpagepkt(hw, 0);
1943 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1944 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1946 rtl_write_byte(rtlpriv,
1947 REG_FWHW_TXQ_CTRL + 2,
1948 tmp_reg422 | BIT(6));
1949 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1951 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1957 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1959 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1960 (u2btmp | mac->assoc_id));
1963 case HW_VAR_CORRECT_TSF:{
1964 u8 btype_ibss = val[0];
1967 _rtl92cu_stop_tx_beacon(hw);
1968 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1969 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1971 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1972 (u32)((mac->tsf >> 32) & 0xffffffff));
1973 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1975 _rtl92cu_resume_tx_beacon(hw);
1978 case HW_VAR_MGT_FILTER:
1979 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1981 case HW_VAR_CTRL_FILTER:
1982 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1984 case HW_VAR_DATA_FILTER:
1985 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1988 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1989 "switch case not processed\n");
1994 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1995 struct ieee80211_sta *sta)
1997 struct rtl_priv *rtlpriv = rtl_priv(hw);
1998 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1999 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2000 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2003 u8 nmode = mac->ht_enable;
2004 u8 mimo_ps = IEEE80211_SMPS_OFF;
2007 u8 curtxbw_40mhz = mac->bw_40;
2008 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2010 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2012 enum wireless_mode wirelessmode = mac->mode;
2014 if (rtlhal->current_bandtype == BAND_ON_5G)
2015 ratr_value = sta->supp_rates[1] << 4;
2017 ratr_value = sta->supp_rates[0];
2018 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2021 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2022 sta->ht_cap.mcs.rx_mask[0] << 12);
2023 switch (wirelessmode) {
2024 case WIRELESS_MODE_B:
2025 if (ratr_value & 0x0000000c)
2026 ratr_value &= 0x0000000d;
2028 ratr_value &= 0x0000000f;
2030 case WIRELESS_MODE_G:
2031 ratr_value &= 0x00000FF5;
2033 case WIRELESS_MODE_N_24G:
2034 case WIRELESS_MODE_N_5G:
2036 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2037 ratr_value &= 0x0007F005;
2041 if (get_rf_type(rtlphy) == RF_1T2R ||
2042 get_rf_type(rtlphy) == RF_1T1R)
2043 ratr_mask = 0x000ff005;
2045 ratr_mask = 0x0f0ff005;
2047 ratr_value &= ratr_mask;
2051 if (rtlphy->rf_type == RF_1T2R)
2052 ratr_value &= 0x000ff0ff;
2054 ratr_value &= 0x0f0ff0ff;
2059 ratr_value &= 0x0FFFFFFF;
2061 if (nmode && ((curtxbw_40mhz &&
2062 curshortgi_40mhz) || (!curtxbw_40mhz &&
2063 curshortgi_20mhz))) {
2065 ratr_value |= 0x10000000;
2066 tmp_ratr_value = (ratr_value >> 12);
2068 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2069 if ((1 << shortgi_rate) & tmp_ratr_value)
2073 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2074 (shortgi_rate << 4) | (shortgi_rate);
2077 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2079 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2080 rtl_read_dword(rtlpriv, REG_ARFR0));
2083 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2084 struct ieee80211_sta *sta,
2087 struct rtl_priv *rtlpriv = rtl_priv(hw);
2088 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2089 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2090 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2091 struct rtl_sta_info *sta_entry = NULL;
2094 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2095 u8 curshortgi_40mhz = curtxbw_40mhz &&
2096 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2098 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2100 enum wireless_mode wirelessmode = 0;
2101 bool shortgi = false;
2104 u8 mimo_ps = IEEE80211_SMPS_OFF;
2106 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2107 wirelessmode = sta_entry->wireless_mode;
2108 if (mac->opmode == NL80211_IFTYPE_STATION ||
2109 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2110 curtxbw_40mhz = mac->bw_40;
2111 else if (mac->opmode == NL80211_IFTYPE_AP ||
2112 mac->opmode == NL80211_IFTYPE_ADHOC)
2113 macid = sta->aid + 1;
2115 if (rtlhal->current_bandtype == BAND_ON_5G)
2116 ratr_bitmap = sta->supp_rates[1] << 4;
2118 ratr_bitmap = sta->supp_rates[0];
2119 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2120 ratr_bitmap = 0xfff;
2121 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2122 sta->ht_cap.mcs.rx_mask[0] << 12);
2123 switch (wirelessmode) {
2124 case WIRELESS_MODE_B:
2125 ratr_index = RATR_INX_WIRELESS_B;
2126 if (ratr_bitmap & 0x0000000c)
2127 ratr_bitmap &= 0x0000000d;
2129 ratr_bitmap &= 0x0000000f;
2131 case WIRELESS_MODE_G:
2132 ratr_index = RATR_INX_WIRELESS_GB;
2134 if (rssi_level == 1)
2135 ratr_bitmap &= 0x00000f00;
2136 else if (rssi_level == 2)
2137 ratr_bitmap &= 0x00000ff0;
2139 ratr_bitmap &= 0x00000ff5;
2141 case WIRELESS_MODE_A:
2142 ratr_index = RATR_INX_WIRELESS_A;
2143 ratr_bitmap &= 0x00000ff0;
2145 case WIRELESS_MODE_N_24G:
2146 case WIRELESS_MODE_N_5G:
2147 ratr_index = RATR_INX_WIRELESS_NGB;
2149 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2150 if (rssi_level == 1)
2151 ratr_bitmap &= 0x00070000;
2152 else if (rssi_level == 2)
2153 ratr_bitmap &= 0x0007f000;
2155 ratr_bitmap &= 0x0007f005;
2157 if (rtlphy->rf_type == RF_1T2R ||
2158 rtlphy->rf_type == RF_1T1R) {
2159 if (curtxbw_40mhz) {
2160 if (rssi_level == 1)
2161 ratr_bitmap &= 0x000f0000;
2162 else if (rssi_level == 2)
2163 ratr_bitmap &= 0x000ff000;
2165 ratr_bitmap &= 0x000ff015;
2167 if (rssi_level == 1)
2168 ratr_bitmap &= 0x000f0000;
2169 else if (rssi_level == 2)
2170 ratr_bitmap &= 0x000ff000;
2172 ratr_bitmap &= 0x000ff005;
2175 if (curtxbw_40mhz) {
2176 if (rssi_level == 1)
2177 ratr_bitmap &= 0x0f0f0000;
2178 else if (rssi_level == 2)
2179 ratr_bitmap &= 0x0f0ff000;
2181 ratr_bitmap &= 0x0f0ff015;
2183 if (rssi_level == 1)
2184 ratr_bitmap &= 0x0f0f0000;
2185 else if (rssi_level == 2)
2186 ratr_bitmap &= 0x0f0ff000;
2188 ratr_bitmap &= 0x0f0ff005;
2193 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2194 (!curtxbw_40mhz && curshortgi_20mhz)) {
2198 else if (macid == 1)
2203 ratr_index = RATR_INX_WIRELESS_NGB;
2205 if (rtlphy->rf_type == RF_1T2R)
2206 ratr_bitmap &= 0x000ff0ff;
2208 ratr_bitmap &= 0x0f0ff0ff;
2211 sta_entry->ratr_index = ratr_index;
2213 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2214 "ratr_bitmap :%x\n", ratr_bitmap);
2215 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2217 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2218 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2219 "Rate_index:%x, ratr_val:%x, %5phC\n",
2220 ratr_index, ratr_bitmap, rate_mask);
2221 memcpy(rtlpriv->rate_mask, rate_mask, 5);
2222 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2223 * "scheduled while atomic" if called directly */
2224 schedule_work(&rtlpriv->works.fill_h2c_cmd);
2227 sta_entry->ratr_index = ratr_index;
2230 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2231 struct ieee80211_sta *sta,
2234 struct rtl_priv *rtlpriv = rtl_priv(hw);
2236 if (rtlpriv->dm.useramask)
2237 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2239 rtl92cu_update_hal_rate_table(hw, sta);
2242 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2244 struct rtl_priv *rtlpriv = rtl_priv(hw);
2245 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2248 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2250 if (!mac->ht_enable)
2251 sifs_timer = 0x0a0a;
2253 sifs_timer = 0x0e0e;
2254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2257 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2259 struct rtl_priv *rtlpriv = rtl_priv(hw);
2260 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2261 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2262 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2264 bool actuallyset = false;
2265 unsigned long flag = 0;
2266 /* to do - usb autosuspend */
2267 u8 usb_autosuspend = 0;
2269 if (ppsc->swrf_processing)
2271 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2272 if (ppsc->rfchange_inprogress) {
2273 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2276 ppsc->rfchange_inprogress = true;
2277 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2279 cur_rfstate = ppsc->rfpwr_state;
2280 if (usb_autosuspend) {
2281 /* to do................... */
2283 if (ppsc->pwrdown_mode) {
2284 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2285 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2287 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2288 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2290 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2291 rtl_read_byte(rtlpriv,
2292 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2293 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2294 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2296 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2297 "GPIO_IN=%02x\n", u1tmp);
2299 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2300 e_rfpowerstate_toset);
2302 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2303 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2304 "GPIOChangeRF - HW Radio ON, RF ON\n");
2305 ppsc->hwradiooff = false;
2307 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2309 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2310 "GPIOChangeRF - HW Radio OFF\n");
2311 ppsc->hwradiooff = true;
2314 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2315 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2316 ppsc->hwradiooff, e_rfpowerstate_toset);
2319 ppsc->hwradiooff = true;
2320 if (e_rfpowerstate_toset == ERFON) {
2321 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2322 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2323 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2324 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2325 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2326 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2328 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2329 ppsc->rfchange_inprogress = false;
2330 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2331 /* For power down module, we need to enable register block
2332 * contrl reg at 0x1c. Then enable power down control bit
2333 * of register 0x04 BIT4 and BIT15 as 1.
2335 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2336 /* Enable register area 0x0-0xc. */
2337 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2338 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2340 * We should configure HW PDn source for WiFi
2341 * ONLY, and then our HW will be set in
2342 * power-down mode if PDn source from all
2343 * functions are configured.
2345 u1tmp = rtl_read_byte(rtlpriv,
2346 REG_MULTI_FUNC_CTRL);
2347 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2348 (u1tmp|WL_HWPDN_EN));
2350 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2353 if (e_rfpowerstate_toset == ERFOFF) {
2354 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2355 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2356 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2357 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2359 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2360 /* Enter D3 or ASPM after GPIO had been done. */
2361 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2362 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2363 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2364 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2365 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2366 ppsc->rfchange_inprogress = false;
2367 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2369 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2370 ppsc->rfchange_inprogress = false;
2371 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2374 return !ppsc->hwradiooff;