1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
44 #include "pwrseqcmd.h"
48 static void _rtl8723ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
49 u8 set_bits, u8 clear_bits)
51 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
52 struct rtl_priv *rtlpriv = rtl_priv(hw);
54 rtlpci->reg_bcn_ctrl_val |= set_bits;
55 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
57 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
60 static void _rtl8723ae_stop_tx_beacon(struct ieee80211_hw *hw)
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
65 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
66 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
68 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
69 tmp1byte &= ~(BIT(0));
70 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
73 static void _rtl8723ae_resume_tx_beacon(struct ieee80211_hw *hw)
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
78 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
79 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
81 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
83 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
86 static void _rtl8723ae_enable_bcn_sufunc(struct ieee80211_hw *hw)
88 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
91 static void _rtl8723ae_disable_bcn_sufunc(struct ieee80211_hw *hw)
93 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
96 void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
98 struct rtl_priv *rtlpriv = rtl_priv(hw);
99 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
100 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
104 *((u32 *) (val)) = rtlpci->receive_config;
106 case HW_VAR_RF_STATE:
107 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
109 case HW_VAR_FWLPS_RF_ON:{
110 enum rf_pwrstate rfState;
113 rtlpriv->cfg->ops->get_hw_reg(hw,
116 if (rfState == ERFOFF) {
117 *((bool *) (val)) = true;
119 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
120 val_rcr &= 0x00070000;
122 *((bool *) (val)) = false;
124 *((bool *) (val)) = true;
127 case HW_VAR_FW_PSMODE_STATUS:
128 *((bool *) (val)) = ppsc->fw_current_inpsmode;
130 case HW_VAR_CORRECT_TSF:{
132 u32 *ptsf_low = (u32 *)&tsf;
133 u32 *ptsf_high = ((u32 *)&tsf) + 1;
135 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
136 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
138 *((u64 *) (val)) = tsf;
142 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
143 "switch case not process\n");
148 void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150 struct rtl_priv *rtlpriv = rtl_priv(hw);
151 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
152 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
153 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
154 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
155 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
159 case HW_VAR_ETHER_ADDR:
160 for (idx = 0; idx < ETH_ALEN; idx++) {
161 rtl_write_byte(rtlpriv, (REG_MACID + idx),
165 case HW_VAR_BASIC_RATE:{
166 u16 rate_cfg = ((u16 *) val)[0];
168 rate_cfg = rate_cfg & 0x15f;
170 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
171 rtl_write_byte(rtlpriv, REG_RRSR + 1,
172 (rate_cfg >> 8) & 0xff);
173 while (rate_cfg > 0x1) {
174 rate_cfg = (rate_cfg >> 1);
177 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
181 for (idx = 0; idx < ETH_ALEN; idx++) {
182 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
187 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
188 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
190 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
191 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
194 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
197 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
200 case HW_VAR_SLOT_TIME:{
203 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
204 "HW_VAR_SLOT_TIME %x\n", val[0]);
206 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
208 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
209 rtlpriv->cfg->ops->set_hw_reg(hw,
214 case HW_VAR_ACK_PREAMBLE:{
216 u8 short_preamble = (bool) (*(u8 *) val);
217 reg_tmp = (mac->cur_40_prime_sc) << 5;
221 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
223 case HW_VAR_AMPDU_MIN_SPACE:{
224 u8 min_spacing_to_set;
227 min_spacing_to_set = *((u8 *) val);
228 if (min_spacing_to_set <= 7) {
231 if (min_spacing_to_set < sec_min_space)
232 min_spacing_to_set = sec_min_space;
234 mac->min_space_cfg = ((mac->min_space_cfg &
238 *val = min_spacing_to_set;
240 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
241 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
244 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
248 case HW_VAR_SHORTGI_DENSITY:{
251 density_to_set = *((u8 *) val);
252 mac->min_space_cfg |= (density_to_set << 3);
254 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
255 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
258 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
262 case HW_VAR_AMPDU_FACTOR:{
263 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
264 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
266 u8 *p_regtoset = NULL;
269 if ((pcipriv->bt_coexist.bt_coexistence) &&
270 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
271 p_regtoset = regtoset_bt;
273 p_regtoset = regtoset_normal;
275 factor_toset = *((u8 *) val);
276 if (factor_toset <= 3) {
277 factor_toset = (1 << (factor_toset + 2));
278 if (factor_toset > 0xf)
281 for (index = 0; index < 4; index++) {
282 if ((p_regtoset[index] & 0xf0) >
285 (p_regtoset[index] & 0x0f) |
288 if ((p_regtoset[index] & 0x0f) >
291 (p_regtoset[index] & 0xf0) |
294 rtl_write_byte(rtlpriv,
295 (REG_AGGLEN_LMT + index),
300 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
301 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
305 case HW_VAR_AC_PARAM:{
306 u8 e_aci = *((u8 *) val);
307 rtl8723ae_dm_init_edca_turbo(hw);
309 if (rtlpci->acm_method != eAcmWay2_SW)
310 rtlpriv->cfg->ops->set_hw_reg(hw,
314 case HW_VAR_ACM_CTRL:{
315 u8 e_aci = *((u8 *) val);
316 union aci_aifsn *p_aci_aifsn =
317 (union aci_aifsn *)(&(mac->ac[0].aifs));
318 u8 acm = p_aci_aifsn->f.acm;
319 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
321 acm_ctrl |= ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
326 acm_ctrl |= AcmHw_BeqEn;
329 acm_ctrl |= AcmHw_ViqEn;
332 acm_ctrl |= AcmHw_VoqEn;
335 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
336 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
343 acm_ctrl &= (~AcmHw_BeqEn);
346 acm_ctrl &= (~AcmHw_ViqEn);
349 acm_ctrl &= (~AcmHw_BeqEn);
352 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
353 "switch case not processed\n");
358 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
359 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
361 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
364 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
365 rtlpci->receive_config = ((u32 *) (val))[0];
367 case HW_VAR_RETRY_LIMIT:{
368 u8 retry_limit = ((u8 *) (val))[0];
370 rtl_write_word(rtlpriv, REG_RL,
371 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
372 retry_limit << RETRY_LIMIT_LONG_SHIFT);
374 case HW_VAR_DUAL_TSF_RST:
375 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
377 case HW_VAR_EFUSE_BYTES:
378 rtlefuse->efuse_usedbytes = *((u16 *) val);
380 case HW_VAR_EFUSE_USAGE:
381 rtlefuse->efuse_usedpercentage = *((u8 *) val);
384 rtl8723ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
386 case HW_VAR_WPA_CONFIG:
387 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
389 case HW_VAR_SET_RPWM:{
392 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
395 if (rpwm_val & BIT(7)) {
396 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
399 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
400 ((*(u8 *) val) | BIT(7)));
404 case HW_VAR_H2C_FW_PWRMODE:{
405 u8 psmode = (*(u8 *) val);
407 if (psmode != FW_PS_ACTIVE_MODE)
408 rtl8723ae_dm_rf_saving(hw, true);
410 rtl8723ae_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
412 case HW_VAR_FW_PSMODE_STATUS:
413 ppsc->fw_current_inpsmode = *((bool *) val);
415 case HW_VAR_H2C_FW_JOINBSSRPT:{
416 u8 mstatus = (*(u8 *) val);
417 u8 tmp_regcr, tmp_reg422;
418 bool recover = false;
420 if (mstatus == RT_MEDIA_CONNECT) {
421 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
423 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
424 rtl_write_byte(rtlpriv, REG_CR + 1,
425 (tmp_regcr | BIT(0)));
427 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
428 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
430 tmp_reg422 = rtl_read_byte(rtlpriv,
431 REG_FWHW_TXQ_CTRL + 2);
432 if (tmp_reg422 & BIT(6))
434 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
435 tmp_reg422 & (~BIT(6)));
437 rtl8723ae_set_fw_rsvdpagepkt(hw, 0);
439 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
440 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
443 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
446 rtl_write_byte(rtlpriv, REG_CR + 1,
447 (tmp_regcr & ~(BIT(0))));
449 rtl8723ae_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
454 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
456 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
459 case HW_VAR_CORRECT_TSF:{
460 u8 btype_ibss = ((u8 *) (val))[0];
462 if (btype_ibss == true)
463 _rtl8723ae_stop_tx_beacon(hw);
465 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
467 rtl_write_dword(rtlpriv, REG_TSFTR,
468 (u32) (mac->tsf & 0xffffffff));
469 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
470 (u32) ((mac->tsf >> 32) & 0xffffffff));
472 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
474 if (btype_ibss == true)
475 _rtl8723ae_resume_tx_beacon(hw);
478 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
479 "switch case not processed\n");
484 static bool _rtl8723ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
489 u32 value = _LLT_INIT_ADDR(address) |
490 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
492 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
495 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
496 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
499 if (count > POLLING_LLT_THRESHOLD) {
500 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
501 "Failed to polling write LLT done at address %d!\n",
511 static bool _rtl8723ae_llt_table_init(struct ieee80211_hw *hw)
513 struct rtl_priv *rtlpriv = rtl_priv(hw);
523 rtl_write_byte(rtlpriv, REG_CR, 0x8B);
525 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
527 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
528 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
530 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
531 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
533 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
534 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
536 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
537 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
538 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
540 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
541 status = _rtl8723ae_llt_write(hw, i, i + 1);
546 status = _rtl8723ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
550 for (i = txpktbuf_bndy; i < maxPage; i++) {
551 status = _rtl8723ae_llt_write(hw, i, (i + 1));
556 status = _rtl8723ae_llt_write(hw, maxPage, txpktbuf_bndy);
560 rtl_write_byte(rtlpriv, REG_CR, 0xff);
561 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
562 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
567 static void _rtl8723ae_gen_refresh_led_state(struct ieee80211_hw *hw)
569 struct rtl_priv *rtlpriv = rtl_priv(hw);
570 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
571 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
572 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
574 if (rtlpriv->rtlhal.up_first_time)
577 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
578 rtl8723ae_sw_led_on(hw, pLed0);
579 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
580 rtl8723ae_sw_led_on(hw, pLed0);
582 rtl8723ae_sw_led_off(hw, pLed0);
585 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
587 struct rtl_priv *rtlpriv = rtl_priv(hw);
588 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
589 unsigned char bytetmp;
590 unsigned short wordtmp;
593 bool mac_func_enable;
595 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
596 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
598 mac_func_enable = true;
600 mac_func_enable = false;
603 /* HW Power on sequence */
604 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
605 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW))
608 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
609 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
611 /* eMAC time out function enable, 0x369[7]=1 */
612 bytetmp = rtl_read_byte(rtlpriv, 0x369);
613 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
615 /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
616 * we should do this before Enabling ASPM backdoor.
619 rtl_write_word(rtlpriv, 0x358, 0x5e);
621 rtl_write_word(rtlpriv, 0x356, 0xc280);
622 rtl_write_word(rtlpriv, 0x354, 0xc290);
623 rtl_write_word(rtlpriv, 0x358, 0x3e);
625 rtl_write_word(rtlpriv, 0x358, 0x5e);
627 tmpu2b = rtl_read_word(rtlpriv, 0x356);
629 } while (tmpu2b != 0xc290 && retry < 100);
632 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
633 "InitMAC(): ePHY configure fail!!!\n");
637 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
638 rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
640 if (!mac_func_enable) {
641 if (_rtl8723ae_llt_table_init(hw) == false)
645 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
646 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
648 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
650 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0xf;
652 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
654 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
655 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
656 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
657 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
659 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
661 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
662 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
664 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
665 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
667 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
668 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
669 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
670 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
671 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
672 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
673 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
674 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
675 rtl_write_dword(rtlpriv, REG_HQ_DESA,
676 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
678 rtl_write_dword(rtlpriv, REG_RX_DESA,
679 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
682 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
684 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
686 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
687 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
690 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
691 } while ((retry < 200) && (bytetmp & BIT(7)));
693 _rtl8723ae_gen_refresh_led_state(hw);
695 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
700 static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw)
702 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
703 struct rtl_priv *rtlpriv = rtl_priv(hw);
704 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
708 reg_bw_opmode = BW_OPMODE_20MHZ;
709 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
711 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
713 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
715 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
717 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
719 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
721 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
723 rtl_write_word(rtlpriv, REG_RL, 0x0707);
725 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
727 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
729 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
730 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
731 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
732 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
734 if ((pcipriv->bt_coexist.bt_coexistence) &&
735 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
736 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
738 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
740 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
742 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
744 rtlpci->reg_bcn_ctrl_val = 0x1f;
745 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
747 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
749 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
751 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
752 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
754 if ((pcipriv->bt_coexist.bt_coexistence) &&
755 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
756 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
757 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
759 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
760 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
763 if ((pcipriv->bt_coexist.bt_coexistence) &&
764 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
765 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
767 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
769 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
771 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
772 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
774 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
776 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
778 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
779 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
781 rtl_write_dword(rtlpriv, 0x394, 0x1);
784 static void _rtl8723ae_enable_aspm_back_door(struct ieee80211_hw *hw)
786 struct rtl_priv *rtlpriv = rtl_priv(hw);
787 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
789 rtl_write_byte(rtlpriv, 0x34b, 0x93);
790 rtl_write_word(rtlpriv, 0x350, 0x870c);
791 rtl_write_byte(rtlpriv, 0x352, 0x1);
793 if (ppsc->support_backdoor)
794 rtl_write_byte(rtlpriv, 0x349, 0x1b);
796 rtl_write_byte(rtlpriv, 0x349, 0x03);
798 rtl_write_word(rtlpriv, 0x350, 0x2718);
799 rtl_write_byte(rtlpriv, 0x352, 0x1);
802 void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw)
804 struct rtl_priv *rtlpriv = rtl_priv(hw);
807 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
808 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
809 rtlpriv->sec.pairwise_enc_algorithm,
810 rtlpriv->sec.group_enc_algorithm);
812 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
813 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
814 "not open hw encryption\n");
818 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
820 if (rtlpriv->sec.use_defaultkey) {
821 sec_reg_value |= SCR_TxUseDK;
822 sec_reg_value |= SCR_RxUseDK;
825 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
827 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
829 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
830 "The SECR-value %x\n", sec_reg_value);
832 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
836 int rtl8723ae_hw_init(struct ieee80211_hw *hw)
838 struct rtl_priv *rtlpriv = rtl_priv(hw);
839 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
840 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
841 struct rtl_phy *rtlphy = &(rtlpriv->phy);
842 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
843 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
844 bool rtstatus = true;
848 rtlpriv->rtlhal.being_init_adapter = true;
849 rtlpriv->intf_ops->disable_aspm(hw);
850 rtstatus = _rtl8712e_init_mac(hw);
851 if (rtstatus != true) {
852 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
857 err = rtl8723ae_download_fw(hw);
859 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
860 "Failed to download FW. Init HW without FW now..\n");
862 rtlhal->fw_ready = false;
865 rtlhal->fw_ready = true;
868 rtlhal->last_hmeboxnum = 0;
869 rtl8723ae_phy_mac_config(hw);
870 /* because the last function modifies RCR, we update
871 * rcr var here, or TP will be unstable as ther receive_config
872 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
873 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
875 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
876 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
877 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
879 rtl8723ae_phy_bb_config(hw);
880 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
881 rtl8723ae_phy_rf_config(hw);
882 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
883 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
884 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
885 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
886 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
887 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
888 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
889 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
890 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
891 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
893 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
894 RF_CHNLBW, RFREG_OFFSET_MASK);
895 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
896 RF_CHNLBW, RFREG_OFFSET_MASK);
897 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
898 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
899 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
900 _rtl8723ae_hw_configure(hw);
901 rtl_cam_reset_all_entry(hw);
902 rtl8723ae_enable_hw_security_config(hw);
904 ppsc->rfpwr_state = ERFON;
906 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
907 _rtl8723ae_enable_aspm_back_door(hw);
908 rtlpriv->intf_ops->enable_aspm(hw);
910 rtl8723ae_bt_hw_init(hw);
912 if (ppsc->rfpwr_state == ERFON) {
913 rtl8723ae_phy_set_rfpath_switch(hw, 1);
914 if (rtlphy->iqk_initialized) {
915 rtl8723ae_phy_iq_calibrate(hw, true);
917 rtl8723ae_phy_iq_calibrate(hw, false);
918 rtlphy->iqk_initialized = true;
921 rtl8723ae_phy_lc_calibrate(hw);
924 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
925 if (!(tmp_u1b & BIT(0))) {
926 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
927 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
930 if (!(tmp_u1b & BIT(4))) {
931 tmp_u1b = rtl_read_byte(rtlpriv, 0x16) & 0x0F;
932 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
934 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
935 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
937 rtl8723ae_dm_init(hw);
938 rtlpriv->rtlhal.being_init_adapter = false;
942 static enum version_8723e _rtl8723ae_read_chip_version(struct ieee80211_hw *hw)
944 struct rtl_priv *rtlpriv = rtl_priv(hw);
945 struct rtl_phy *rtlphy = &(rtlpriv->phy);
946 enum version_8723e version = 0x0000;
949 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
950 if (value32 & TRP_VAUX_EN) {
951 version = (enum version_8723e)(version |
952 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
953 /* RTL8723 with BT function. */
954 version = (enum version_8723e)(version |
955 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
958 /* Normal mass production chip. */
959 version = (enum version_8723e) NORMAL_CHIP;
960 version = (enum version_8723e)(version |
961 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
962 /* RTL8723 with BT function. */
963 version = (enum version_8723e)(version |
964 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
965 if (IS_CHIP_VENDOR_UMC(version))
966 version = (enum version_8723e)(version |
967 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
968 if (IS_8723_SERIES(version)) {
969 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
970 /* ROM code version */
971 version = (enum version_8723e)(version |
972 ((value32 & RF_RL_ID)>>20));
976 if (IS_8723_SERIES(version)) {
977 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
978 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
979 RT_POLARITY_HIGH_ACT :
980 RT_POLARITY_LOW_ACT);
983 case VERSION_TEST_UMC_CHIP_8723:
984 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
985 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
987 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
988 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
989 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
991 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
992 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
993 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
996 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
997 "Chip Version ID: Unknown. Bug?\n");
1001 if (IS_8723_SERIES(version))
1002 rtlphy->rf_type = RF_1T1R;
1004 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1005 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1010 static int _rtl8723ae_set_media_status(struct ieee80211_hw *hw,
1011 enum nl80211_iftype type)
1013 struct rtl_priv *rtlpriv = rtl_priv(hw);
1014 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1015 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1017 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1018 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1019 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1021 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1022 type == NL80211_IFTYPE_STATION) {
1023 _rtl8723ae_stop_tx_beacon(hw);
1024 _rtl8723ae_enable_bcn_sufunc(hw);
1025 } else if (type == NL80211_IFTYPE_ADHOC ||
1026 type == NL80211_IFTYPE_AP) {
1027 _rtl8723ae_resume_tx_beacon(hw);
1028 _rtl8723ae_disable_bcn_sufunc(hw);
1030 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1031 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1036 case NL80211_IFTYPE_UNSPECIFIED:
1037 bt_msr |= MSR_NOLINK;
1038 ledaction = LED_CTL_LINK;
1039 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1040 "Set Network type to NO LINK!\n");
1042 case NL80211_IFTYPE_ADHOC:
1043 bt_msr |= MSR_ADHOC;
1044 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1045 "Set Network type to Ad Hoc!\n");
1047 case NL80211_IFTYPE_STATION:
1048 bt_msr |= MSR_INFRA;
1049 ledaction = LED_CTL_LINK;
1050 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1051 "Set Network type to STA!\n");
1053 case NL80211_IFTYPE_AP:
1055 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1056 "Set Network type to AP!\n");
1059 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1060 "Network type %d not supported!\n",
1067 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1068 rtlpriv->cfg->ops->led_control(hw, ledaction);
1069 if ((bt_msr & 0x03) == MSR_AP)
1070 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1072 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1076 void rtl8723ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1078 struct rtl_priv *rtlpriv = rtl_priv(hw);
1079 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1080 u32 reg_rcr = rtlpci->receive_config;
1082 if (rtlpriv->psc.rfpwr_state != ERFON)
1085 if (check_bssid == true) {
1086 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1087 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1089 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
1090 } else if (check_bssid == false) {
1091 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1092 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
1093 rtlpriv->cfg->ops->set_hw_reg(hw,
1094 HW_VAR_RCR, (u8 *) (®_rcr));
1098 int rtl8723ae_set_network_type(struct ieee80211_hw *hw,
1099 enum nl80211_iftype type)
1101 struct rtl_priv *rtlpriv = rtl_priv(hw);
1103 if (_rtl8723ae_set_media_status(hw, type))
1106 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1107 if (type != NL80211_IFTYPE_AP)
1108 rtl8723ae_set_check_bssid(hw, true);
1110 rtl8723ae_set_check_bssid(hw, false);
1115 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1116 void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci)
1118 struct rtl_priv *rtlpriv = rtl_priv(hw);
1120 rtl8723ae_dm_init_edca_turbo(hw);
1123 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1126 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4ac_param); */
1129 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1132 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1135 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1140 void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw)
1142 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1145 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1146 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1147 rtlpci->irq_enabled = true;
1150 void rtl8723ae_disable_interrupt(struct ieee80211_hw *hw)
1152 struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1155 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1156 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1157 rtlpci->irq_enabled = false;
1158 synchronize_irq(rtlpci->pdev->irq);
1161 static void _rtl8723ae_poweroff_adapter(struct ieee80211_hw *hw)
1163 struct rtl_priv *rtlpriv = rtl_priv(hw);
1164 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1167 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1168 /* 1. Run LPS WL RFOFF flow */
1169 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1170 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW);
1172 /* 2. 0x1F[7:0] = 0 */
1174 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1175 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1176 rtl8723ae_firmware_selfreset(hw);
1178 /* Reset MCU. Suggested by Filen. */
1179 u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1180 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1tmp & (~BIT(2))));
1182 /* g. MCUFWDL 0x80[1:0]=0 */
1183 /* reset MCU ready status */
1184 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1186 /* HW card disable configuration. */
1187 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1188 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW);
1190 /* Reset MCU IO Wrapper */
1191 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1192 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1tmp & (~BIT(0))));
1193 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1194 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1tmp | BIT(0));
1196 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1197 /* lock ISO/CLK/Power control register */
1198 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1201 void rtl8723ae_card_disable(struct ieee80211_hw *hw)
1203 struct rtl_priv *rtlpriv = rtl_priv(hw);
1204 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1205 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1206 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1207 enum nl80211_iftype opmode;
1209 mac->link_state = MAC80211_NOLINK;
1210 opmode = NL80211_IFTYPE_UNSPECIFIED;
1211 _rtl8723ae_set_media_status(hw, opmode);
1212 if (rtlpci->driver_is_goingto_unload ||
1213 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1214 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1215 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1216 _rtl8723ae_poweroff_adapter(hw);
1218 /* after power off we should do iqk again */
1219 rtlpriv->phy.iqk_initialized = false;
1222 void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw,
1223 u32 *p_inta, u32 *p_intb)
1225 struct rtl_priv *rtlpriv = rtl_priv(hw);
1226 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1228 *p_inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1229 rtl_write_dword(rtlpriv, 0x3a0, *p_inta);
1232 void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw)
1235 struct rtl_priv *rtlpriv = rtl_priv(hw);
1236 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1237 u16 bcn_interval, atim_window;
1239 bcn_interval = mac->beacon_interval;
1240 atim_window = 2; /*FIX MERGE */
1241 rtl8723ae_disable_interrupt(hw);
1242 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1243 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1244 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1245 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1246 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1247 rtl_write_byte(rtlpriv, 0x606, 0x30);
1248 rtl8723ae_enable_interrupt(hw);
1251 void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw)
1253 struct rtl_priv *rtlpriv = rtl_priv(hw);
1254 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1255 u16 bcn_interval = mac->beacon_interval;
1257 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1258 "beacon_interval:%d\n", bcn_interval);
1259 rtl8723ae_disable_interrupt(hw);
1260 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1261 rtl8723ae_enable_interrupt(hw);
1264 void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw,
1265 u32 add_msr, u32 rm_msr)
1267 struct rtl_priv *rtlpriv = rtl_priv(hw);
1268 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1270 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1271 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1274 rtlpci->irq_mask[0] |= add_msr;
1276 rtlpci->irq_mask[0] &= (~rm_msr);
1277 rtl8723ae_disable_interrupt(hw);
1278 rtl8723ae_enable_interrupt(hw);
1281 static u8 _rtl8723ae_get_chnl_group(u8 chnl)
1294 static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1298 struct rtl_priv *rtlpriv = rtl_priv(hw);
1299 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1300 u8 rf_path, index, tempval;
1303 for (rf_path = 0; rf_path < 1; rf_path++) {
1304 for (i = 0; i < 3; i++) {
1305 if (!autoload_fail) {
1306 rtlefuse->eeprom_chnlarea_txpwr_cck
1308 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1309 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1311 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path *
1314 rtlefuse->eeprom_chnlarea_txpwr_cck
1316 EEPROM_DEFAULT_TXPOWERLEVEL;
1317 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1319 EEPROM_DEFAULT_TXPOWERLEVEL;
1324 for (i = 0; i < 3; i++) {
1326 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1328 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1329 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1331 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1332 ((tempval & 0xf0) >> 4);
1335 for (rf_path = 0; rf_path < 2; rf_path++)
1336 for (i = 0; i < 3; i++)
1337 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1338 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1339 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1341 for (rf_path = 0; rf_path < 2; rf_path++)
1342 for (i = 0; i < 3; i++)
1343 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1344 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1346 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1348 for (rf_path = 0; rf_path < 2; rf_path++)
1349 for (i = 0; i < 3; i++)
1350 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1351 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1353 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1356 for (rf_path = 0; rf_path < 2; rf_path++) {
1357 for (i = 0; i < 14; i++) {
1358 index = _rtl8723ae_get_chnl_group((u8) i);
1360 rtlefuse->txpwrlevel_cck[rf_path][i] =
1361 rtlefuse->eeprom_chnlarea_txpwr_cck
1363 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1364 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1367 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1369 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path]
1371 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1372 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1374 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1377 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1381 for (i = 0; i < 14; i++) {
1382 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1383 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1384 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1385 rtlefuse->txpwrlevel_cck[rf_path][i],
1386 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1387 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1391 for (i = 0; i < 3; i++) {
1392 if (!autoload_fail) {
1393 rtlefuse->eeprom_pwrlimit_ht40[i] =
1394 hwinfo[EEPROM_TXPWR_GROUP + i];
1395 rtlefuse->eeprom_pwrlimit_ht20[i] =
1396 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1398 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1399 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1403 for (rf_path = 0; rf_path < 2; rf_path++) {
1404 for (i = 0; i < 14; i++) {
1405 index = _rtl8723ae_get_chnl_group((u8) i);
1407 if (rf_path == RF90_PATH_A) {
1408 rtlefuse->pwrgroup_ht20[rf_path][i] =
1409 (rtlefuse->eeprom_pwrlimit_ht20[index] &
1411 rtlefuse->pwrgroup_ht40[rf_path][i] =
1412 (rtlefuse->eeprom_pwrlimit_ht40[index] &
1414 } else if (rf_path == RF90_PATH_B) {
1415 rtlefuse->pwrgroup_ht20[rf_path][i] =
1416 ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1418 rtlefuse->pwrgroup_ht40[rf_path][i] =
1419 ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1423 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1424 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1425 rtlefuse->pwrgroup_ht20[rf_path][i]);
1426 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1427 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1428 rtlefuse->pwrgroup_ht40[rf_path][i]);
1432 for (i = 0; i < 14; i++) {
1433 index = _rtl8723ae_get_chnl_group((u8) i);
1436 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1438 tempval = EEPROM_DEFAULT_HT20_DIFF;
1440 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1441 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1442 ((tempval >> 4) & 0xF);
1444 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1445 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1447 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1448 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1450 index = _rtl8723ae_get_chnl_group((u8) i);
1453 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1455 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1457 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1458 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1459 ((tempval >> 4) & 0xF);
1462 rtlefuse->legacy_ht_txpowerdiff =
1463 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1465 for (i = 0; i < 14; i++)
1466 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1467 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1468 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1469 for (i = 0; i < 14; i++)
1470 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1471 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1472 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1473 for (i = 0; i < 14; i++)
1474 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1475 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1476 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1477 for (i = 0; i < 14; i++)
1478 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1479 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1480 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1483 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1485 rtlefuse->eeprom_regulatory = 0;
1486 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1487 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1490 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1492 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1493 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1494 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1495 rtlefuse->eeprom_tssi[RF90_PATH_A],
1496 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1499 tempval = hwinfo[EEPROM_THERMAL_METER];
1501 tempval = EEPROM_DEFAULT_THERMALMETER;
1502 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1504 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1505 rtlefuse->apk_thermalmeterignore = true;
1507 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1508 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1509 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1512 static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1515 struct rtl_priv *rtlpriv = rtl_priv(hw);
1516 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1517 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1519 u8 hwinfo[HWSET_MAX_SIZE];
1526 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1527 rtl_efuse_shadow_map_update(hw);
1529 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1531 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1532 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1533 "RTL819X Not boot from eeprom, check it !!");
1536 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1537 hwinfo, HWSET_MAX_SIZE);
1539 eeprom_id = *((u16 *)&hwinfo[0]);
1540 if (eeprom_id != RTL8190_EEPROM_ID) {
1541 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1542 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1543 rtlefuse->autoload_failflag = true;
1545 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1546 rtlefuse->autoload_failflag = false;
1549 if (rtlefuse->autoload_failflag == true)
1552 rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
1553 rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
1554 rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
1555 rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
1556 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1557 "EEPROMId = 0x%4x\n", eeprom_id);
1558 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1559 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1560 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1561 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1562 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1563 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1564 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1565 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1567 for (i = 0; i < 6; i += 2) {
1568 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1569 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1572 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1573 "dev_addr: %pM\n", rtlefuse->dev_addr);
1575 _rtl8723ae_read_txpower_info_from_hwpg(hw,
1576 rtlefuse->autoload_failflag, hwinfo);
1578 rtl8723ae_read_bt_coexist_info_from_hwpg(hw,
1579 rtlefuse->autoload_failflag, hwinfo);
1581 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1582 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1583 rtlefuse->txpwr_fromeprom = true;
1584 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1586 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1587 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1589 /* set channel paln to world wide 13 */
1590 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1592 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1593 switch (rtlefuse->eeprom_oemid) {
1594 case EEPROM_CID_DEFAULT:
1595 if (rtlefuse->eeprom_did == 0x8176) {
1596 if (CHK_SVID_SMID(0x10EC, 0x6151) ||
1597 CHK_SVID_SMID(0x10EC, 0x6152) ||
1598 CHK_SVID_SMID(0x10EC, 0x6154) ||
1599 CHK_SVID_SMID(0x10EC, 0x6155) ||
1600 CHK_SVID_SMID(0x10EC, 0x6177) ||
1601 CHK_SVID_SMID(0x10EC, 0x6178) ||
1602 CHK_SVID_SMID(0x10EC, 0x6179) ||
1603 CHK_SVID_SMID(0x10EC, 0x6180) ||
1604 CHK_SVID_SMID(0x10EC, 0x8151) ||
1605 CHK_SVID_SMID(0x10EC, 0x8152) ||
1606 CHK_SVID_SMID(0x10EC, 0x8154) ||
1607 CHK_SVID_SMID(0x10EC, 0x8155) ||
1608 CHK_SVID_SMID(0x10EC, 0x8181) ||
1609 CHK_SVID_SMID(0x10EC, 0x8182) ||
1610 CHK_SVID_SMID(0x10EC, 0x8184) ||
1611 CHK_SVID_SMID(0x10EC, 0x8185) ||
1612 CHK_SVID_SMID(0x10EC, 0x9151) ||
1613 CHK_SVID_SMID(0x10EC, 0x9152) ||
1614 CHK_SVID_SMID(0x10EC, 0x9154) ||
1615 CHK_SVID_SMID(0x10EC, 0x9155) ||
1616 CHK_SVID_SMID(0x10EC, 0x9181) ||
1617 CHK_SVID_SMID(0x10EC, 0x9182) ||
1618 CHK_SVID_SMID(0x10EC, 0x9184) ||
1619 CHK_SVID_SMID(0x10EC, 0x9185))
1620 rtlhal->oem_id = RT_CID_TOSHIBA;
1621 else if (rtlefuse->eeprom_svid == 0x1025)
1622 rtlhal->oem_id = RT_CID_819x_Acer;
1623 else if (CHK_SVID_SMID(0x10EC, 0x6191) ||
1624 CHK_SVID_SMID(0x10EC, 0x6192) ||
1625 CHK_SVID_SMID(0x10EC, 0x6193) ||
1626 CHK_SVID_SMID(0x10EC, 0x7191) ||
1627 CHK_SVID_SMID(0x10EC, 0x7192) ||
1628 CHK_SVID_SMID(0x10EC, 0x7193) ||
1629 CHK_SVID_SMID(0x10EC, 0x8191) ||
1630 CHK_SVID_SMID(0x10EC, 0x8192) ||
1631 CHK_SVID_SMID(0x10EC, 0x8193))
1632 rtlhal->oem_id = RT_CID_819x_SAMSUNG;
1633 else if (CHK_SVID_SMID(0x10EC, 0x8195) ||
1634 CHK_SVID_SMID(0x10EC, 0x9195) ||
1635 CHK_SVID_SMID(0x10EC, 0x7194) ||
1636 CHK_SVID_SMID(0x10EC, 0x8200) ||
1637 CHK_SVID_SMID(0x10EC, 0x8201) ||
1638 CHK_SVID_SMID(0x10EC, 0x8202) ||
1639 CHK_SVID_SMID(0x10EC, 0x9200))
1640 rtlhal->oem_id = RT_CID_819x_Lenovo;
1641 else if (CHK_SVID_SMID(0x10EC, 0x8197) ||
1642 CHK_SVID_SMID(0x10EC, 0x9196))
1643 rtlhal->oem_id = RT_CID_819x_CLEVO;
1644 else if (CHK_SVID_SMID(0x1028, 0x8194) ||
1645 CHK_SVID_SMID(0x1028, 0x8198) ||
1646 CHK_SVID_SMID(0x1028, 0x9197) ||
1647 CHK_SVID_SMID(0x1028, 0x9198))
1648 rtlhal->oem_id = RT_CID_819x_DELL;
1649 else if (CHK_SVID_SMID(0x103C, 0x1629))
1650 rtlhal->oem_id = RT_CID_819x_HP;
1651 else if (CHK_SVID_SMID(0x1A32, 0x2315))
1652 rtlhal->oem_id = RT_CID_819x_QMI;
1653 else if (CHK_SVID_SMID(0x10EC, 0x8203))
1654 rtlhal->oem_id = RT_CID_819x_PRONETS;
1655 else if (CHK_SVID_SMID(0x1043, 0x84B5))
1657 RT_CID_819x_Edimax_ASUS;
1659 rtlhal->oem_id = RT_CID_DEFAULT;
1660 } else if (rtlefuse->eeprom_did == 0x8178) {
1661 if (CHK_SVID_SMID(0x10EC, 0x6181) ||
1662 CHK_SVID_SMID(0x10EC, 0x6182) ||
1663 CHK_SVID_SMID(0x10EC, 0x6184) ||
1664 CHK_SVID_SMID(0x10EC, 0x6185) ||
1665 CHK_SVID_SMID(0x10EC, 0x7181) ||
1666 CHK_SVID_SMID(0x10EC, 0x7182) ||
1667 CHK_SVID_SMID(0x10EC, 0x7184) ||
1668 CHK_SVID_SMID(0x10EC, 0x7185) ||
1669 CHK_SVID_SMID(0x10EC, 0x8181) ||
1670 CHK_SVID_SMID(0x10EC, 0x8182) ||
1671 CHK_SVID_SMID(0x10EC, 0x8184) ||
1672 CHK_SVID_SMID(0x10EC, 0x8185) ||
1673 CHK_SVID_SMID(0x10EC, 0x9181) ||
1674 CHK_SVID_SMID(0x10EC, 0x9182) ||
1675 CHK_SVID_SMID(0x10EC, 0x9184) ||
1676 CHK_SVID_SMID(0x10EC, 0x9185))
1677 rtlhal->oem_id = RT_CID_TOSHIBA;
1678 else if (rtlefuse->eeprom_svid == 0x1025)
1679 rtlhal->oem_id = RT_CID_819x_Acer;
1680 else if (CHK_SVID_SMID(0x10EC, 0x8186))
1681 rtlhal->oem_id = RT_CID_819x_PRONETS;
1682 else if (CHK_SVID_SMID(0x1043, 0x8486))
1684 RT_CID_819x_Edimax_ASUS;
1686 rtlhal->oem_id = RT_CID_DEFAULT;
1688 rtlhal->oem_id = RT_CID_DEFAULT;
1691 case EEPROM_CID_TOSHIBA:
1692 rtlhal->oem_id = RT_CID_TOSHIBA;
1694 case EEPROM_CID_CCX:
1695 rtlhal->oem_id = RT_CID_CCX;
1697 case EEPROM_CID_QMI:
1698 rtlhal->oem_id = RT_CID_819x_QMI;
1700 case EEPROM_CID_WHQL:
1703 rtlhal->oem_id = RT_CID_DEFAULT;
1710 static void _rtl8723ae_hal_customized_behavior(struct ieee80211_hw *hw)
1712 struct rtl_priv *rtlpriv = rtl_priv(hw);
1713 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1714 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1716 switch (rtlhal->oem_id) {
1717 case RT_CID_819x_HP:
1718 pcipriv->ledctl.led_opendrain = true;
1720 case RT_CID_819x_Lenovo:
1721 case RT_CID_DEFAULT:
1722 case RT_CID_TOSHIBA:
1724 case RT_CID_819x_Acer:
1729 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1730 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1733 void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw)
1735 struct rtl_priv *rtlpriv = rtl_priv(hw);
1736 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1737 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1738 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1742 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1743 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1744 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1746 rtlhal->version = _rtl8723ae_read_chip_version(hw);
1748 if (get_rf_type(rtlphy) == RF_1T1R)
1749 rtlpriv->dm.rfpath_rxenable[0] = true;
1751 rtlpriv->dm.rfpath_rxenable[0] =
1752 rtlpriv->dm.rfpath_rxenable[1] = true;
1753 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1756 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1757 if (tmp_u1b & BIT(4)) {
1758 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1759 rtlefuse->epromtype = EEPROM_93C46;
1761 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1762 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1764 if (tmp_u1b & BIT(5)) {
1765 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1766 rtlefuse->autoload_failflag = false;
1767 _rtl8723ae_read_adapter_info(hw, false);
1769 rtlefuse->autoload_failflag = true;
1770 _rtl8723ae_read_adapter_info(hw, false);
1771 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1773 _rtl8723ae_hal_customized_behavior(hw);
1776 static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw,
1777 struct ieee80211_sta *sta)
1779 struct rtl_priv *rtlpriv = rtl_priv(hw);
1780 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1781 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1782 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1783 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1786 u8 nmode = mac->ht_enable;
1787 u8 mimo_ps = IEEE80211_SMPS_OFF;
1788 u8 curtxbw_40mhz = mac->bw_40;
1789 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1791 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1793 enum wireless_mode wirelessmode = mac->mode;
1795 if (rtlhal->current_bandtype == BAND_ON_5G)
1796 ratr_value = sta->supp_rates[1] << 4;
1798 ratr_value = sta->supp_rates[0];
1799 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1801 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1802 sta->ht_cap.mcs.rx_mask[0] << 12);
1803 switch (wirelessmode) {
1804 case WIRELESS_MODE_B:
1805 if (ratr_value & 0x0000000c)
1806 ratr_value &= 0x0000000d;
1808 ratr_value &= 0x0000000f;
1810 case WIRELESS_MODE_G:
1811 ratr_value &= 0x00000FF5;
1813 case WIRELESS_MODE_N_24G:
1814 case WIRELESS_MODE_N_5G:
1816 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1817 ratr_value &= 0x0007F005;
1821 if (get_rf_type(rtlphy) == RF_1T2R ||
1822 get_rf_type(rtlphy) == RF_1T1R)
1823 ratr_mask = 0x000ff005;
1825 ratr_mask = 0x0f0ff005;
1827 ratr_value &= ratr_mask;
1831 if (rtlphy->rf_type == RF_1T2R)
1832 ratr_value &= 0x000ff0ff;
1834 ratr_value &= 0x0f0ff0ff;
1839 if ((pcipriv->bt_coexist.bt_coexistence) &&
1840 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1841 (pcipriv->bt_coexist.bt_cur_state) &&
1842 (pcipriv->bt_coexist.bt_ant_isolation) &&
1843 ((pcipriv->bt_coexist.bt_service == BT_SCO) ||
1844 (pcipriv->bt_coexist.bt_service == BT_BUSY)))
1845 ratr_value &= 0x0fffcfc0;
1847 ratr_value &= 0x0FFFFFFF;
1849 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1850 (!curtxbw_40mhz && curshortgi_20mhz)))
1851 ratr_value |= 0x10000000;
1853 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1855 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1856 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1859 static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw,
1860 struct ieee80211_sta *sta, u8 rssi_level)
1862 struct rtl_priv *rtlpriv = rtl_priv(hw);
1863 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1864 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1865 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1866 struct rtl_sta_info *sta_entry = NULL;
1869 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1870 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1872 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1874 enum wireless_mode wirelessmode = 0;
1875 bool shortgi = false;
1878 u8 mimo_ps = IEEE80211_SMPS_OFF;
1880 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1881 wirelessmode = sta_entry->wireless_mode;
1882 if (mac->opmode == NL80211_IFTYPE_STATION)
1883 curtxbw_40mhz = mac->bw_40;
1884 else if (mac->opmode == NL80211_IFTYPE_AP ||
1885 mac->opmode == NL80211_IFTYPE_ADHOC)
1886 macid = sta->aid + 1;
1888 if (rtlhal->current_bandtype == BAND_ON_5G)
1889 ratr_bitmap = sta->supp_rates[1] << 4;
1891 ratr_bitmap = sta->supp_rates[0];
1892 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1893 ratr_bitmap = 0xfff;
1894 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1895 sta->ht_cap.mcs.rx_mask[0] << 12);
1896 switch (wirelessmode) {
1897 case WIRELESS_MODE_B:
1898 ratr_index = RATR_INX_WIRELESS_B;
1899 if (ratr_bitmap & 0x0000000c)
1900 ratr_bitmap &= 0x0000000d;
1902 ratr_bitmap &= 0x0000000f;
1904 case WIRELESS_MODE_G:
1905 ratr_index = RATR_INX_WIRELESS_GB;
1907 if (rssi_level == 1)
1908 ratr_bitmap &= 0x00000f00;
1909 else if (rssi_level == 2)
1910 ratr_bitmap &= 0x00000ff0;
1912 ratr_bitmap &= 0x00000ff5;
1914 case WIRELESS_MODE_A:
1915 ratr_index = RATR_INX_WIRELESS_A;
1916 ratr_bitmap &= 0x00000ff0;
1918 case WIRELESS_MODE_N_24G:
1919 case WIRELESS_MODE_N_5G:
1920 ratr_index = RATR_INX_WIRELESS_NGB;
1922 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1923 if (rssi_level == 1)
1924 ratr_bitmap &= 0x00070000;
1925 else if (rssi_level == 2)
1926 ratr_bitmap &= 0x0007f000;
1928 ratr_bitmap &= 0x0007f005;
1930 if (rtlphy->rf_type == RF_1T2R ||
1931 rtlphy->rf_type == RF_1T1R) {
1932 if (curtxbw_40mhz) {
1933 if (rssi_level == 1)
1934 ratr_bitmap &= 0x000f0000;
1935 else if (rssi_level == 2)
1936 ratr_bitmap &= 0x000ff000;
1938 ratr_bitmap &= 0x000ff015;
1940 if (rssi_level == 1)
1941 ratr_bitmap &= 0x000f0000;
1942 else if (rssi_level == 2)
1943 ratr_bitmap &= 0x000ff000;
1945 ratr_bitmap &= 0x000ff005;
1948 if (curtxbw_40mhz) {
1949 if (rssi_level == 1)
1950 ratr_bitmap &= 0x0f0f0000;
1951 else if (rssi_level == 2)
1952 ratr_bitmap &= 0x0f0ff000;
1954 ratr_bitmap &= 0x0f0ff015;
1956 if (rssi_level == 1)
1957 ratr_bitmap &= 0x0f0f0000;
1958 else if (rssi_level == 2)
1959 ratr_bitmap &= 0x0f0ff000;
1961 ratr_bitmap &= 0x0f0ff005;
1966 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1967 (!curtxbw_40mhz && curshortgi_20mhz)) {
1970 else if (macid == 1)
1975 ratr_index = RATR_INX_WIRELESS_NGB;
1977 if (rtlphy->rf_type == RF_1T2R)
1978 ratr_bitmap &= 0x000ff0ff;
1980 ratr_bitmap &= 0x0f0ff0ff;
1983 sta_entry->ratr_index = ratr_index;
1985 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1986 "ratr_bitmap :%x\n", ratr_bitmap);
1987 /* convert ratr_bitmap to le byte array */
1988 rate_mask[0] = ratr_bitmap;
1989 rate_mask[1] = (ratr_bitmap >>= 8);
1990 rate_mask[2] = (ratr_bitmap >>= 8);
1991 rate_mask[3] = ((ratr_bitmap >> 8) & 0x0f) | (ratr_index << 4);
1992 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1993 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1994 "Rate_index:%x, ratr_bitmap: %*phC\n",
1995 ratr_index, 5, rate_mask);
1996 rtl8723ae_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1999 void rtl8723ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
2000 struct ieee80211_sta *sta, u8 rssi_level)
2002 struct rtl_priv *rtlpriv = rtl_priv(hw);
2004 if (rtlpriv->dm.useramask)
2005 rtl8723ae_update_hal_rate_mask(hw, sta, rssi_level);
2007 rtl8723ae_update_hal_rate_table(hw, sta);
2010 void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw)
2012 struct rtl_priv *rtlpriv = rtl_priv(hw);
2013 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2016 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2017 (u8 *)&mac->slot_time);
2018 if (!mac->ht_enable)
2019 sifs_timer = 0x0a0a;
2021 sifs_timer = 0x1010;
2022 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2025 bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2027 struct rtl_priv *rtlpriv = rtl_priv(hw);
2028 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2029 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2030 enum rf_pwrstate e_rfpowerstate_toset;
2032 bool actuallyset = false;
2034 if (rtlpriv->rtlhal.being_init_adapter)
2037 if (ppsc->swrf_processing)
2040 spin_lock(&rtlpriv->locks.rf_ps_lock);
2041 if (ppsc->rfchange_inprogress) {
2042 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2045 ppsc->rfchange_inprogress = true;
2046 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2049 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2050 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2052 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2054 if (rtlphy->polarity_ctl)
2055 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2057 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2059 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
2060 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2061 "GPIOChangeRF - HW Radio ON, RF ON\n");
2063 e_rfpowerstate_toset = ERFON;
2064 ppsc->hwradiooff = false;
2066 } else if ((ppsc->hwradiooff == false)
2067 && (e_rfpowerstate_toset == ERFOFF)) {
2068 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2069 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2071 e_rfpowerstate_toset = ERFOFF;
2072 ppsc->hwradiooff = true;
2077 spin_lock(&rtlpriv->locks.rf_ps_lock);
2078 ppsc->rfchange_inprogress = false;
2079 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2081 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2082 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2084 spin_lock(&rtlpriv->locks.rf_ps_lock);
2085 ppsc->rfchange_inprogress = false;
2086 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2090 return !ppsc->hwradiooff;
2093 void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2094 u8 *p_macaddr, bool is_group, u8 enc_algo,
2095 bool is_wepkey, bool clear_all)
2097 struct rtl_priv *rtlpriv = rtl_priv(hw);
2098 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2099 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2100 u8 *macaddr = p_macaddr;
2102 bool is_pairwise = false;
2103 static u8 cam_const_addr[4][6] = {
2104 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2105 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2106 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2107 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2109 static u8 cam_const_broad[] = {
2110 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2116 u8 clear_number = 5;
2118 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2120 for (idx = 0; idx < clear_number; idx++) {
2121 rtl_cam_mark_invalid(hw, cam_offset + idx);
2122 rtl_cam_empty_entry(hw, cam_offset + idx);
2125 memset(rtlpriv->sec.key_buf[idx], 0,
2127 rtlpriv->sec.key_len[idx] = 0;
2132 case WEP40_ENCRYPTION:
2133 enc_algo = CAM_WEP40;
2135 case WEP104_ENCRYPTION:
2136 enc_algo = CAM_WEP104;
2138 case TKIP_ENCRYPTION:
2139 enc_algo = CAM_TKIP;
2141 case AESCCMP_ENCRYPTION:
2145 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2146 "switch case not processed\n");
2147 enc_algo = CAM_TKIP;
2151 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2152 macaddr = cam_const_addr[key_index];
2153 entry_id = key_index;
2156 macaddr = cam_const_broad;
2157 entry_id = key_index;
2159 if (mac->opmode == NL80211_IFTYPE_AP) {
2160 entry_id = rtl_cam_get_free_entry(hw,
2162 if (entry_id >= TOTAL_CAM_ENTRY) {
2163 RT_TRACE(rtlpriv, COMP_SEC,
2165 "Can not find free hw security cam entry\n");
2169 entry_id = CAM_PAIRWISE_KEY_POSITION;
2172 key_index = PAIRWISE_KEYIDX;
2177 if (rtlpriv->sec.key_len[key_index] == 0) {
2178 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2179 "delete one entry, entry_id is %d\n",
2181 if (mac->opmode == NL80211_IFTYPE_AP)
2182 rtl_cam_del_entry(hw, p_macaddr);
2183 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2185 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2188 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2189 "set Pairwiase key\n");
2191 rtl_cam_add_one_entry(hw, macaddr, key_index,
2193 CAM_CONFIG_NO_USEDK,
2194 rtlpriv->sec.key_buf[key_index]);
2196 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2199 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2200 rtl_cam_add_one_entry(hw,
2203 CAM_PAIRWISE_KEY_POSITION,
2205 CAM_CONFIG_NO_USEDK,
2206 rtlpriv->sec.key_buf
2210 rtl_cam_add_one_entry(hw, macaddr, key_index,
2212 CAM_CONFIG_NO_USEDK,
2213 rtlpriv->sec.key_buf[entry_id]);
2220 static void rtl8723ae_bt_var_init(struct ieee80211_hw *hw)
2222 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2223 struct rtl_priv *rtlpriv = rtl_priv(hw);
2225 pcipriv->bt_coexist.bt_coexistence =
2226 pcipriv->bt_coexist.eeprom_bt_coexist;
2227 pcipriv->bt_coexist.bt_ant_num =
2228 pcipriv->bt_coexist.eeprom_bt_ant_num;
2229 pcipriv->bt_coexist.bt_coexist_type =
2230 pcipriv->bt_coexist.eeprom_bt_type;
2232 pcipriv->bt_coexist.bt_ant_isolation =
2233 pcipriv->bt_coexist.eeprom_bt_ant_isol;
2235 pcipriv->bt_coexist.bt_radio_shared_type =
2236 pcipriv->bt_coexist.eeprom_bt_radio_shared;
2238 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2239 "BT Coexistance = 0x%x\n",
2240 pcipriv->bt_coexist.bt_coexistence);
2242 if (pcipriv->bt_coexist.bt_coexistence) {
2243 pcipriv->bt_coexist.bt_busy_traffic = false;
2244 pcipriv->bt_coexist.bt_traffic_mode_set = false;
2245 pcipriv->bt_coexist.bt_non_traffic_mode_set = false;
2247 pcipriv->bt_coexist.cstate = 0;
2248 pcipriv->bt_coexist.previous_state = 0;
2250 if (pcipriv->bt_coexist.bt_ant_num == ANT_X2) {
2251 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2252 "BlueTooth BT_Ant_Num = Antx2\n");
2253 } else if (pcipriv->bt_coexist.bt_ant_num == ANT_X1) {
2254 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2255 "BlueTooth BT_Ant_Num = Antx1\n");
2258 switch (pcipriv->bt_coexist.bt_coexist_type) {
2260 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2261 "BlueTooth BT_CoexistType = BT_2Wire\n");
2264 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2265 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2268 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2269 "BlueTooth BT_CoexistType = BT_ACCEL\n");
2272 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2273 "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2276 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2277 "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2280 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2281 "BlueTooth BT_CoexistType = BT_RTL8756\n");
2284 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2285 "BlueTooth BT_CoexistType = Unknown\n");
2288 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2289 "BlueTooth BT_Ant_isolation = %d\n",
2290 pcipriv->bt_coexist.bt_ant_isolation);
2291 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2292 "BT_RadioSharedType = 0x%x\n",
2293 pcipriv->bt_coexist.bt_radio_shared_type);
2294 pcipriv->bt_coexist.bt_active_zero_cnt = 0;
2295 pcipriv->bt_coexist.cur_bt_disabled = false;
2296 pcipriv->bt_coexist.pre_bt_disabled = false;
2300 void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2301 bool auto_load_fail, u8 *hwinfo)
2303 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2304 struct rtl_priv *rtlpriv = rtl_priv(hw);
2308 if (!auto_load_fail) {
2309 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2310 if (tmpu_32 & BIT(18))
2311 pcipriv->bt_coexist.eeprom_bt_coexist = 1;
2313 pcipriv->bt_coexist.eeprom_bt_coexist = 0;
2314 value = hwinfo[RF_OPTION4];
2315 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A;
2316 pcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2317 pcipriv->bt_coexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2318 pcipriv->bt_coexist.eeprom_bt_radio_shared =
2319 ((value & 0x20) >> 5);
2321 pcipriv->bt_coexist.eeprom_bt_coexist = 0;
2322 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A;
2323 pcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2324 pcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2325 pcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2328 rtl8723ae_bt_var_init(hw);
2331 void rtl8723ae_bt_reg_init(struct ieee80211_hw *hw)
2333 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2335 /* 0:Low, 1:High, 2:From Efuse. */
2336 pcipriv->bt_coexist.reg_bt_iso = 2;
2337 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2338 pcipriv->bt_coexist.reg_bt_sco = 3;
2339 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2340 pcipriv->bt_coexist.reg_bt_sco = 0;
2344 void rtl8723ae_bt_hw_init(struct ieee80211_hw *hw)
2348 void rtl8723ae_suspend(struct ieee80211_hw *hw)
2352 void rtl8723ae_resume(struct ieee80211_hw *hw)
2356 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2357 void rtl8723ae_allow_all_destaddr(struct ieee80211_hw *hw,
2358 bool allow_all_da, bool write_into_reg)
2360 struct rtl_priv *rtlpriv = rtl_priv(hw);
2361 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2363 if (allow_all_da) /* Set BIT0 */
2364 rtlpci->receive_config |= RCR_AAP;
2365 else /* Clear BIT0 */
2366 rtlpci->receive_config &= ~RCR_AAP;
2369 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2372 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2373 "receive_config=0x%08X, write_into_reg=%d\n",
2374 rtlpci->receive_config, write_into_reg);