1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <linux/sched.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <linux/vmalloc.h>
39 #include <linux/usb.h>
40 #include <net/mac80211.h>
41 #include <linux/completion.h>
44 #define RF_CHANGE_BY_INIT 0
45 #define RF_CHANGE_BY_IPS BIT(28)
46 #define RF_CHANGE_BY_PS BIT(29)
47 #define RF_CHANGE_BY_HW BIT(30)
48 #define RF_CHANGE_BY_SW BIT(31)
50 #define IQK_ADDA_REG_NUM 16
51 #define IQK_MAC_REG_NUM 4
53 #define MAX_KEY_LEN 61
54 #define KEY_BUF_SIZE 5
57 /*aci: 0x00 Best Effort*/
58 /*aci: 0x01 Background*/
61 /*Max: define total number.*/
67 #define QOS_QUEUE_NUM 4
68 #define RTL_MAC80211_NUM_QUEUE 5
69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
70 #define RTL_USB_MAX_RX_COUNT 100
71 #define QBSS_LOAD_SIZE 5
72 #define MAX_WMMELE_LENGTH 64
74 #define TOTAL_CAM_ENTRY 32
76 /*slot time for 11g. */
77 #define RTL_SLOT_TIME_9 9
78 #define RTL_SLOT_TIME_20 20
80 /*related with tcp/ip. */
82 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
83 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
84 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
86 #define PROTOC_TYPE_SIZE 2
88 /*related with 802.11 frame*/
89 #define MAC80211_3ADDR_LEN 24
90 #define MAC80211_4ADDR_LEN 30
92 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
93 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
94 #define MAX_PG_GROUP 13
95 #define CHANNEL_GROUP_MAX_2G 3
96 #define CHANNEL_GROUP_IDX_5GL 3
97 #define CHANNEL_GROUP_IDX_5GM 6
98 #define CHANNEL_GROUP_IDX_5GH 9
99 #define CHANNEL_GROUP_MAX_5G 9
100 #define CHANNEL_MAX_NUMBER_2G 14
101 #define AVG_THERMAL_NUM 8
102 #define MAX_TID_COUNT 9
119 enum rt_eeprom_type {
126 RTL_STATUS_INTERFACE_START = 0,
130 HARDWARE_TYPE_RTL8192E,
131 HARDWARE_TYPE_RTL8192U,
132 HARDWARE_TYPE_RTL8192SE,
133 HARDWARE_TYPE_RTL8192SU,
134 HARDWARE_TYPE_RTL8192CE,
135 HARDWARE_TYPE_RTL8192CU,
136 HARDWARE_TYPE_RTL8192DE,
137 HARDWARE_TYPE_RTL8192DU,
138 HARDWARE_TYPE_RTL8723E,
139 HARDWARE_TYPE_RTL8723U,
145 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
146 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
147 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
148 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
149 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
150 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
151 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
152 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
153 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
154 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
155 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
156 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
157 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
158 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
159 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
160 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
161 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
162 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
163 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
164 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
165 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
166 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
167 #define IS_HARDWARE_TYPE_8723(rtlhal) \
168 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
169 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
170 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
172 #define RX_HAL_IS_CCK_RATE(_pdesc)\
173 (_pdesc->rxmcs == DESC92_RATE1M || \
174 _pdesc->rxmcs == DESC92_RATE2M || \
175 _pdesc->rxmcs == DESC92_RATE5_5M || \
176 _pdesc->rxmcs == DESC92_RATE11M)
178 enum scan_operation_backup_opt {
201 u32 rfswitch_control;
204 u32 rfrxiq_imbalance;
206 u32 rftxiq_imbalance;
209 u32 rflssi_readbackpi;
213 IO_CMD_PAUSE_DM_BY_SCAN = 0,
214 IO_CMD_RESUME_DM_BY_SCAN = 1,
219 HW_VAR_MULTICAST_REG,
223 HW_VAR_SECURITY_CONF,
224 HW_VAR_BEACON_INTERVAL,
226 HW_VAR_LISTEN_INTERVAL,
239 HW_VAR_RATE_FALLBACK_CONTROL,
240 HW_VAR_CONTENTION_WINDOW,
245 HW_VAR_AMPDU_MIN_SPACE,
246 HW_VAR_SHORTGI_DENSITY,
248 HW_VAR_MCS_RATE_AVAILABLE,
251 HW_VAR_DIS_Req_Qsize,
252 HW_VAR_CCX_CHNL_LOAD,
253 HW_VAR_CCX_NOISE_HISTOGRAM,
260 HW_VAR_SET_DEV_POWER,
270 HW_VAR_USER_CONTROL_TURBO_MODE,
276 HW_VAR_AUTOLOAD_STATUS,
277 HW_VAR_RF_2R_DISABLE,
279 HW_VAR_H2C_FW_PWRMODE,
280 HW_VAR_H2C_FW_JOINBSSRPT,
281 HW_VAR_FW_PSMODE_STATUS,
282 HW_VAR_1X1_RECV_COMBINE,
283 HW_VAR_STOP_SEND_BEACON,
288 HW_VAR_H2C_FW_UPDATE_GTK,
291 HW_VAR_WF_IS_MAC_ADDR,
292 HW_VAR_H2C_FW_OFFLOAD,
295 HW_VAR_HANDLE_FW_C2H,
296 HW_VAR_DL_FW_RSVD_PAGE,
298 HW_VAR_HW_SEQ_ENABLE,
303 HW_VAR_SWITCH_EPHY_WoWLAN,
304 HW_VAR_INT_MIGRATION,
315 enum _RT_MEDIA_STATUS {
316 RT_MEDIA_DISCONNECT = 0,
322 RT_CID_8187_ALPHA0 = 1,
323 RT_CID_8187_SERCOMM_PS = 2,
324 RT_CID_8187_HW_LED = 3,
325 RT_CID_8187_NETGEAR = 4,
327 RT_CID_819x_CAMEO = 6,
328 RT_CID_819x_RUNTOP = 7,
329 RT_CID_819x_Senao = 8,
331 RT_CID_819x_Netcore = 10,
332 RT_CID_Nettronix = 11,
336 RT_CID_819x_ALPHA = 15,
337 RT_CID_819x_Sitecom = 16,
339 RT_CID_819x_Lenovo = 18,
340 RT_CID_819x_QMI = 19,
341 RT_CID_819x_Edimax_Belkin = 20,
342 RT_CID_819x_Sercomm_Belkin = 21,
343 RT_CID_819x_CAMEO1 = 22,
344 RT_CID_819x_MSI = 23,
345 RT_CID_819x_Acer = 24,
347 RT_CID_819x_CLEVO = 28,
348 RT_CID_819x_Arcadyan_Belkin = 29,
349 RT_CID_819x_SAMSUNG = 30,
350 RT_CID_819x_WNC_COREGA = 31,
351 RT_CID_819x_Foxcoon = 32,
352 RT_CID_819x_DELL = 33,
358 HW_DESC_TX_NEXTDESC_ADDR,
366 PRIME_CHNL_OFFSET_DONT_CARE = 0,
367 PRIME_CHNL_OFFSET_LOWER = 1,
368 PRIME_CHNL_OFFSET_UPPER = 2,
378 enum ht_channel_width {
379 HT_CHANNEL_WIDTH_20 = 0,
380 HT_CHANNEL_WIDTH_20_40 = 1,
383 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
384 Cipher Suites Encryption Algorithms */
387 WEP40_ENCRYPTION = 1,
389 RSERVED_ENCRYPTION = 3,
390 AESCCMP_ENCRYPTION = 4,
391 WEP104_ENCRYPTION = 5,
396 _HAL_STATE_START = 1,
399 enum rtl_desc92_rate {
400 DESC92_RATE1M = 0x00,
401 DESC92_RATE2M = 0x01,
402 DESC92_RATE5_5M = 0x02,
403 DESC92_RATE11M = 0x03,
405 DESC92_RATE6M = 0x04,
406 DESC92_RATE9M = 0x05,
407 DESC92_RATE12M = 0x06,
408 DESC92_RATE18M = 0x07,
409 DESC92_RATE24M = 0x08,
410 DESC92_RATE36M = 0x09,
411 DESC92_RATE48M = 0x0a,
412 DESC92_RATE54M = 0x0b,
414 DESC92_RATEMCS0 = 0x0c,
415 DESC92_RATEMCS1 = 0x0d,
416 DESC92_RATEMCS2 = 0x0e,
417 DESC92_RATEMCS3 = 0x0f,
418 DESC92_RATEMCS4 = 0x10,
419 DESC92_RATEMCS5 = 0x11,
420 DESC92_RATEMCS6 = 0x12,
421 DESC92_RATEMCS7 = 0x13,
422 DESC92_RATEMCS8 = 0x14,
423 DESC92_RATEMCS9 = 0x15,
424 DESC92_RATEMCS10 = 0x16,
425 DESC92_RATEMCS11 = 0x17,
426 DESC92_RATEMCS12 = 0x18,
427 DESC92_RATEMCS13 = 0x19,
428 DESC92_RATEMCS14 = 0x1a,
429 DESC92_RATEMCS15 = 0x1b,
430 DESC92_RATEMCS15_SG = 0x1c,
431 DESC92_RATEMCS32 = 0x20,
454 EFUSE_HWSET_MAX_SIZE,
455 EFUSE_MAX_SECTION_MAP,
456 EFUSE_REAL_CONTENT_SIZE,
457 EFUSE_OOB_PROTECT_BYTES_LEN,
472 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
473 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
474 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
475 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
476 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
477 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
478 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
479 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
480 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
481 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
482 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
483 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
484 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
485 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
486 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
487 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
488 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
489 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
490 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
491 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
492 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
493 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
494 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
495 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
496 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
497 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
498 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
499 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
500 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
501 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
502 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
503 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
504 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
505 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
508 /*CCK Rates, TxHT = 0 */
514 /*OFDM Rates, TxHT = 0 */
531 /*Firmware PS mode for control LPS.*/
533 FW_PS_ACTIVE_MODE = 0,
538 FW_PS_UAPSD_WMM_MODE = 5,
539 FW_PS_UAPSD_MODE = 6,
541 FW_PS_WWLAN_MODE = 8,
542 FW_PS_PM_Radio_Off = 9,
543 FW_PS_PM_Card_Disable = 10,
547 EACTIVE, /*Active/Continuous access. */
548 EMAXPS, /*Max power save mode. */
549 EFASTPS, /*Fast power save mode. */
550 EAUTOPS, /*Auto power save mode. */
555 LED_CTL_POWER_ON = 1,
560 LED_CTL_SITE_SURVEY = 6,
561 LED_CTL_POWER_OFF = 7,
562 LED_CTL_START_TO_LINK = 8,
563 LED_CTL_START_WPS = 9,
564 LED_CTL_STOP_WPS = 10,
575 /*acm implementation method.*/
577 eAcmWay0_SwAndHw = 0,
583 SINGLEMAC_SINGLEPHY = 0,
596 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
610 WIRELESS_MODE_UNKNOWN = 0x00,
611 WIRELESS_MODE_A = 0x01,
612 WIRELESS_MODE_B = 0x02,
613 WIRELESS_MODE_G = 0x04,
614 WIRELESS_MODE_AUTO = 0x08,
615 WIRELESS_MODE_N_24G = 0x10,
616 WIRELESS_MODE_N_5G = 0x20
619 #define IS_WIRELESS_MODE_A(wirelessmode) \
620 (wirelessmode == WIRELESS_MODE_A)
621 #define IS_WIRELESS_MODE_B(wirelessmode) \
622 (wirelessmode == WIRELESS_MODE_B)
623 #define IS_WIRELESS_MODE_G(wirelessmode) \
624 (wirelessmode == WIRELESS_MODE_G)
625 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
626 (wirelessmode == WIRELESS_MODE_N_24G)
627 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
628 (wirelessmode == WIRELESS_MODE_N_5G)
630 enum ratr_table_mode {
631 RATR_INX_WIRELESS_NGB = 0,
632 RATR_INX_WIRELESS_NG = 1,
633 RATR_INX_WIRELESS_NB = 2,
634 RATR_INX_WIRELESS_N = 3,
635 RATR_INX_WIRELESS_GB = 4,
636 RATR_INX_WIRELESS_G = 5,
637 RATR_INX_WIRELESS_B = 6,
638 RATR_INX_WIRELESS_MC = 7,
639 RATR_INX_WIRELESS_A = 8,
642 enum rtl_link_state {
644 MAC80211_LINKING = 1,
646 MAC80211_LINKED_SCANNING = 3,
663 struct octet_string {
668 struct rtl_hdr_3addr {
678 struct rtl_info_element {
684 struct rtl_probe_rsp {
685 struct rtl_hdr_3addr header;
687 __le16 beacon_interval;
689 /*SSID, supported rates, FH params, DS params,
690 CF params, IBSS params, TIM (if beacon), RSN */
691 struct rtl_info_element info_element[0];
695 /*ledpin Identify how to implement this SW led.*/
698 enum rtl_led_pin ledpin;
704 struct rtl_led sw_led0;
705 struct rtl_led sw_led1;
708 struct rtl_qos_parameters {
716 struct rt_smooth_data {
717 u32 elements[100]; /*array to store values */
718 u32 index; /*index to current array to store */
719 u32 total_num; /*num of valid elements */
720 u32 total_val; /*sum of valid elements */
723 struct false_alarm_statistics {
725 u32 cnt_rate_illegal;
728 u32 cnt_fast_fsync_fail;
729 u32 cnt_sb_search_fail;
744 struct wireless_stats {
745 unsigned long txbytesunicast;
746 unsigned long txbytesmulticast;
747 unsigned long txbytesbroadcast;
748 unsigned long rxbytesunicast;
751 /*Correct smoothed ss in Dbm, only used
752 in driver to report real power now. */
753 long recv_signal_power;
755 long last_sigstrength_inpercent;
757 u32 rssi_calculate_cnt;
759 /*Transformed, in dbm. Beautified signal
760 strength for UI, not correct. */
761 long signal_strength;
763 u8 rx_rssi_percentage[4];
764 u8 rx_evm_percentage[2];
766 struct rt_smooth_data ui_rssi;
767 struct rt_smooth_data ui_link_quality;
770 struct rate_adaptive {
771 u8 rate_adaptive_disabled;
775 u32 high_rssi_thresh_for_ra;
776 u32 high2low_rssi_thresh_for_ra;
777 u8 low2high_rssi_thresh_for_ra40m;
778 u32 low_rssi_thresh_for_ra40M;
779 u8 low2high_rssi_thresh_for_ra20m;
780 u32 low_rssi_thresh_for_ra20M;
781 u32 upper_rssi_threshold_ratr;
782 u32 middleupper_rssi_threshold_ratr;
783 u32 middle_rssi_threshold_ratr;
784 u32 middlelow_rssi_threshold_ratr;
785 u32 low_rssi_threshold_ratr;
786 u32 ultralow_rssi_threshold_ratr;
787 u32 low_rssi_threshold_ratr_40m;
788 u32 low_rssi_threshold_ratr_20m;
791 u32 ping_rssi_thresh_for_ra;
796 struct regd_pair_mapping {
802 struct rtl_regulatory {
810 struct regd_pair_mapping *regpair;
814 bool rfkill_state; /*0 is off, 1 is on */
817 #define IQK_MATRIX_REG_NUM 8
818 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
819 struct iqk_matrix_regs {
821 long value[1][IQK_MATRIX_REG_NUM];
824 struct phy_parameters {
829 enum hw_param_tab_index {
844 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
845 struct init_gain initgain_backup;
846 enum io_type current_io_type;
851 u8 set_bwmode_inprogress;
852 u8 sw_chnl_inprogress;
857 u8 set_io_inprogress;
860 /* record for power tracking */
872 u32 reg_c04, reg_c08, reg_874;
874 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
875 u32 iqk_bb_backup[10];
879 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
885 /* MAX_PG_GROUP groups of pwr diff by rates */
886 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
887 u8 default_initialgain[4];
889 /* the current Tx power level */
891 u8 cur_ofdm24g_txpwridx;
893 u32 rfreg_chnlval[2];
895 u32 reg_rf3c[2]; /* pathA / pathB */
902 struct phy_parameters hwparam_tables[MAX_TAB];
906 #define MAX_TID_COUNT 9
907 #define RTL_AGG_STOP 0
908 #define RTL_AGG_PROGRESS 1
909 #define RTL_AGG_START 2
910 #define RTL_AGG_OPERATIONAL 3
911 #define RTL_AGG_OFF 0
913 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
914 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
925 struct rtl_tid_data {
927 struct rtl_ht_agg agg;
930 struct rtl_sta_info {
934 struct rtl_tid_data tids[MAX_TID_COUNT];
940 struct mutex bb_mutex;
943 unsigned long pci_mem_end; /*shared mem end */
944 unsigned long pci_mem_start; /*shared mem start */
947 unsigned long pci_base_addr; /*device I/O address */
949 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
950 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
951 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
952 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
955 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
956 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
957 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
962 u8 mac_addr[ETH_ALEN];
963 u8 mac80211_registered;
969 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
970 struct ieee80211_hw *hw;
971 struct ieee80211_vif *vif;
972 enum nl80211_iftype opmode;
974 /*Probe Beacon management */
975 struct rtl_tid_data tids[MAX_TID_COUNT];
976 enum rtl_link_state link_state;
994 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
995 u8 earlymode_threshold;
1003 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1004 u32 basic_rates; /* b/g rates */
1009 u8 mode; /* wireless mode */
1014 u8 cur_40_prime_sc_bk;
1021 int beacon_interval;
1024 u8 min_space_cfg; /*For Min spacing configurations */
1026 u8 current_ampdu_factor;
1027 u8 current_ampdu_density;
1030 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1031 struct rtl_qos_parameters ac[AC_MAX];
1035 struct ieee80211_hw *hw;
1037 enum intf_type interface;
1038 u16 hw_type; /*92c or 92d or 92s and so on */
1041 u32 version; /*version of chip */
1042 u8 state; /*stop 0, start 1 */
1049 bool h2c_setinprogress;
1051 /*Reserve page start offset except beacon in TxQ. */
1052 u8 fw_rsvdpage_startoffset;
1055 /* FW Cmd IO related */
1058 bool set_fwcmd_inprogress;
1059 u8 current_fwcmd_io;
1062 bool driver_going2unload;
1064 /*AMPDU init min space*/
1065 u8 minspace_cfg; /*For Min spacing configurations */
1068 enum macphy_mode macphymode;
1069 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1070 enum band_type current_bandtypebackup;
1071 enum band_type bandset;
1072 /* dual MAC 0--Mac0 1--Mac1 */
1074 /* just for DualMac S3S4 */
1076 bool earlymode_enable;
1078 bool during_mac0init_radiob;
1079 bool during_mac1init_radioa;
1080 bool reloadtxpowerindex;
1081 /* True if IMR or IQK have done
1082 for 2.4G in scan progress */
1083 bool load_imrandiqk_setting_for2g;
1085 bool disable_amsdu_8k;
1088 struct rtl_security {
1093 bool use_defaultkey;
1094 /*Encryption Algorithm for Unicast Packet */
1095 enum rt_enc_alg pairwise_enc_algorithm;
1096 /*Encryption Algorithm for Brocast/Multicast */
1097 enum rt_enc_alg group_enc_algorithm;
1098 /*Cam Entry Bitmap */
1099 u32 hwsec_cam_bitmap;
1100 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1101 /*local Key buffer, indx 0 is for
1102 pairwise key 1-4 is for agoup key. */
1103 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1104 u8 key_len[KEY_BUF_SIZE];
1106 /*The pointer of Pairwise Key,
1107 it always points to KeyBuf[4] */
1112 /*PHY status for Dynamic Management */
1113 long entry_min_undecoratedsmoothed_pwdb;
1114 long undecorated_smoothed_pwdb; /*out dm */
1115 long entry_max_undecoratedsmoothed_pwdb;
1116 bool dm_initialgain_enable;
1117 bool dynamic_txpower_enable;
1118 bool current_turbo_edca;
1119 bool is_any_nonbepkts; /*out dm */
1120 bool is_cur_rdlstate;
1121 bool txpower_trackinginit;
1122 bool disable_framebursting;
1124 bool txpower_tracking;
1126 bool rfpath_rxenable[4];
1127 bool inform_fw_driverctrldm;
1128 bool current_mrc_switch;
1131 u8 thermalvalue_rxgain;
1132 u8 thermalvalue_iqk;
1133 u8 thermalvalue_lck;
1136 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1137 u8 thermalvalue_avg_index;
1139 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1140 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1142 u8 txpower_track_control;
1143 bool interrupt_migration;
1144 bool disable_tx_int;
1149 #define EFUSE_MAX_LOGICAL_SIZE 256
1154 u16 max_physical_size;
1156 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1157 u16 efuse_usedbytes;
1158 u8 efuse_usedpercentage;
1159 #ifdef EFUSE_REPG_WORKAROUND
1160 bool efuse_re_pg_sec1flag;
1161 u8 efuse_re_pg_data[8];
1164 u8 autoload_failflag;
1173 u16 eeprom_channelplan;
1180 bool txpwr_fromeprom;
1181 u8 eeprom_crystalcap;
1183 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1184 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1185 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1186 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1187 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1188 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1189 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1190 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1191 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1193 u8 internal_pa_5g[2]; /* pathA / pathB */
1197 /*For power group */
1198 u8 eeprom_pwrgroup[2][3];
1199 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1200 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1202 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1203 /*For HT<->legacy pwr diff*/
1204 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1205 u8 txpwr_safetyflag; /* Band edge enable flag */
1206 u16 eeprom_txpowerdiff;
1207 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1208 u8 antenna_txpwdiff[3];
1210 u8 eeprom_regulatory;
1211 u8 eeprom_thermalmeter;
1212 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1214 u8 crystalcap; /* CrystalCap. */
1218 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1219 bool apk_thermalmeterignore;
1221 bool b1x1_recvcombine;
1229 bool pwrdomain_protect;
1230 bool in_powersavemode;
1231 bool rfchange_inprogress;
1232 bool swrf_processing;
1236 * just for PCIE ASPM
1237 * If it supports ASPM, Offset[560h] = 0x40,
1238 * otherwise Offset[560h] = 0x00.
1242 bool support_backdoor;
1245 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1250 /*For Fw control LPS mode */
1252 /*Record Fw PS mode status. */
1253 bool fw_current_inpsmode;
1254 u8 reg_max_lps_awakeintvl;
1266 /*just for PCIE ASPM */
1267 u8 const_amdpci_aspm;
1270 enum rf_pwrstate inactive_pwrstate;
1271 enum rf_pwrstate rfpwr_state; /*cur power state */
1277 bool multi_buffered;
1279 unsigned int dtim_counter;
1280 unsigned int sleep_ms;
1281 unsigned long last_sleep_jiffies;
1282 unsigned long last_awake_jiffies;
1283 unsigned long last_delaylps_stamp_jiffies;
1284 unsigned long last_dtim;
1285 unsigned long last_beacon;
1286 unsigned long last_action;
1287 unsigned long last_slept;
1295 u16 rate; /*in 100 kbps */
1296 u8 received_channel;
1305 u8 signalquality; /*in 0-100 index. */
1307 * Real power in dBm for this packet,
1308 * no beautification and aggregation.
1310 s32 recvsignalpower;
1311 s8 rxpower; /*in dBm Translate from PWdB */
1312 u8 signalstrength; /*in 0-100 index. */
1316 u16 shortpreamble:1;
1327 bool rx_is40Mhzpacket;
1329 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1330 s8 rx_mimo_signalquality[2];
1331 bool packet_matchbssid;
1335 bool packet_beacon; /*for rssi */
1336 char cck_adc_pwdb[4]; /*for rx path selection */
1339 struct rt_link_detect {
1340 u32 num_tx_in4period[4];
1341 u32 num_rx_in4period[4];
1343 u32 num_tx_inperiod;
1344 u32 num_rx_inperiod;
1347 bool higher_busytraffic;
1348 bool higher_busyrxtraffic;
1350 u32 tidtx_in4period[MAX_TID_COUNT][4];
1351 u32 tidtx_inperiod[MAX_TID_COUNT];
1352 bool higher_busytxtraffic[MAX_TID_COUNT];
1355 struct rtl_tcb_desc {
1363 u8 rts_use_shortpreamble:1;
1364 u8 rts_use_shortgi:1;
1370 u8 use_shortpreamble:1;
1371 u8 use_driver_rate:1;
1372 u8 disable_ratefallback:1;
1384 /* The max value by HW */
1388 struct rtl_hal_ops {
1389 int (*init_sw_vars) (struct ieee80211_hw *hw);
1390 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1391 void (*read_chip_version)(struct ieee80211_hw *hw);
1392 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1393 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1394 u32 *p_inta, u32 *p_intb);
1395 int (*hw_init) (struct ieee80211_hw *hw);
1396 void (*hw_disable) (struct ieee80211_hw *hw);
1397 void (*hw_suspend) (struct ieee80211_hw *hw);
1398 void (*hw_resume) (struct ieee80211_hw *hw);
1399 void (*enable_interrupt) (struct ieee80211_hw *hw);
1400 void (*disable_interrupt) (struct ieee80211_hw *hw);
1401 int (*set_network_type) (struct ieee80211_hw *hw,
1402 enum nl80211_iftype type);
1403 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1405 void (*set_bw_mode) (struct ieee80211_hw *hw,
1406 enum nl80211_channel_type ch_type);
1407 u8(*switch_channel) (struct ieee80211_hw *hw);
1408 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1409 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1410 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1411 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1412 u32 add_msr, u32 rm_msr);
1413 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1414 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1415 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1416 struct ieee80211_sta *sta, u8 rssi_level);
1417 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1418 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1419 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1420 struct ieee80211_tx_info *info,
1421 struct ieee80211_sta *sta,
1422 struct sk_buff *skb, u8 hw_queue,
1423 struct rtl_tcb_desc *ptcb_desc);
1424 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1425 u32 buffer_len, bool bIsPsPoll);
1426 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1427 bool firstseg, bool lastseg,
1428 struct sk_buff *skb);
1429 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1430 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1431 struct rtl_stats *stats,
1432 struct ieee80211_rx_status *rx_status,
1433 u8 *pdesc, struct sk_buff *skb);
1434 void (*set_channel_access) (struct ieee80211_hw *hw);
1435 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1436 void (*dm_watchdog) (struct ieee80211_hw *hw);
1437 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1438 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1439 enum rf_pwrstate rfpwr_state);
1440 void (*led_control) (struct ieee80211_hw *hw,
1441 enum led_ctl_mode ledaction);
1442 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1443 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1444 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1445 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1446 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1447 u8 *macaddr, bool is_group, u8 enc_algo,
1448 bool is_wepkey, bool clear_all);
1449 void (*init_sw_leds) (struct ieee80211_hw *hw);
1450 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1451 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1452 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1454 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1455 u32 regaddr, u32 bitmask);
1456 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1457 u32 regaddr, u32 bitmask, u32 data);
1458 void (*linked_set_reg) (struct ieee80211_hw *hw);
1459 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1460 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1462 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1463 u8 *ppowerlevel, u8 channel);
1464 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1466 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1468 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1469 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1470 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1473 struct rtl_intf_ops {
1475 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1476 int (*adapter_start) (struct ieee80211_hw *hw);
1477 void (*adapter_stop) (struct ieee80211_hw *hw);
1479 int (*adapter_tx) (struct ieee80211_hw *hw,
1480 struct ieee80211_sta *sta,
1481 struct sk_buff *skb,
1482 struct rtl_tcb_desc *ptcb_desc);
1483 void (*flush)(struct ieee80211_hw *hw, bool drop);
1484 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1485 bool (*waitq_insert) (struct ieee80211_hw *hw,
1486 struct ieee80211_sta *sta,
1487 struct sk_buff *skb);
1490 void (*disable_aspm) (struct ieee80211_hw *hw);
1491 void (*enable_aspm) (struct ieee80211_hw *hw);
1496 struct rtl_mod_params {
1497 /* default: 0 = using hardware encryption */
1500 /* default: 0 = DBG_EMERG (0)*/
1503 /* default: 1 = using no linked power save */
1506 /* default: 1 = using linked sw power save */
1509 /* default: 1 = using linked fw power save */
1513 struct rtl_hal_usbint_cfg {
1520 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1521 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1522 struct sk_buff_head *);
1525 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1526 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1528 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1529 struct sk_buff_head *);
1531 /* endpoint mapping */
1532 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1533 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1536 struct rtl_hal_cfg {
1538 bool write_readback;
1541 struct rtl_hal_ops *ops;
1542 struct rtl_mod_params *mod_params;
1543 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1545 /*this map used for some registers or vars
1546 defined int HAL but used in MAIN */
1547 u32 maps[RTL_VAR_MAP_MAX];
1553 struct mutex conf_mutex;
1554 struct mutex ps_mutex;
1557 spinlock_t ips_lock;
1558 spinlock_t irq_th_lock;
1559 spinlock_t h2c_lock;
1560 spinlock_t rf_ps_lock;
1562 spinlock_t waitq_lock;
1563 spinlock_t usb_lock;
1566 spinlock_t cck_and_rw_pagea_lock;
1570 struct ieee80211_hw *hw;
1573 struct timer_list watchdog_timer;
1576 struct tasklet_struct irq_tasklet;
1577 struct tasklet_struct irq_prepare_bcn_tasklet;
1580 struct workqueue_struct *rtl_wq;
1581 struct delayed_work watchdog_wq;
1582 struct delayed_work ips_nic_off_wq;
1585 struct delayed_work ps_work;
1586 struct delayed_work ps_rfon_wq;
1588 struct work_struct lps_leave_work;
1592 u32 dbgp_type[DBGP_TYPE_MAX];
1593 u32 global_debuglevel;
1594 u64 global_debugcomponents;
1596 /* add for proc debug */
1597 struct proc_dir_entry *proc_dir;
1611 u32 rssi_highthresh;
1614 long last_min_undecorated_pwdb_for_dm;
1615 long rssi_highpower_lowthresh;
1616 long rssi_highpower_highthresh;
1622 u8 dig_ext_port_stage;
1624 u8 dig_twoport_algorithm;
1626 u8 dig_slgorithm_switch;
1627 u8 cursta_connectctate;
1628 u8 presta_connectstate;
1629 u8 curmultista_connectstate;
1631 char backoff_val_range_max;
1632 char backoff_val_range_min;
1633 u8 rx_gain_range_max;
1634 u8 rx_gain_range_min;
1635 u8 min_undecorated_pwdb_for_dm;
1637 u8 pre_cck_pd_state;
1638 u8 cur_cck_pd_state;
1639 u8 pre_cck_fa_state;
1640 u8 cur_cck_fa_state;
1646 u8 dig_highpwrstate;
1647 u8 cur_sta_connectstate;
1648 u8 pre_sta_connectstate;
1649 u8 cur_ap_connectstate;
1650 u8 pre_ap_connectstate;
1653 u8 cur_cs_ratiostate;
1654 u8 pre_cs_ratiostate;
1655 u8 backoff_enable_flag;
1656 char backoffval_range_max;
1657 char backoffval_range_min;
1661 struct completion firmware_loading_complete;
1662 struct rtl_locks locks;
1663 struct rtl_works works;
1664 struct rtl_mac mac80211;
1665 struct rtl_hal rtlhal;
1666 struct rtl_regulatory regd;
1667 struct rtl_rfkill rfkill;
1671 struct rtl_security sec;
1672 struct rtl_efuse efuse;
1674 struct rtl_ps_ctl psc;
1675 struct rate_adaptive ra;
1676 struct wireless_stats stats;
1677 struct rt_link_detect link_info;
1678 struct false_alarm_statistics falsealm_cnt;
1680 struct rtl_rate_priv *rate_priv;
1682 struct rtl_debug dbg;
1686 *hal_cfg : for diff cards
1687 *intf_ops : for diff interrface usb/pcie
1689 struct rtl_hal_cfg *cfg;
1690 struct rtl_intf_ops *intf_ops;
1692 /*this var will be set by set_bit,
1693 and was used to indicate status of
1694 interface or hardware */
1695 unsigned long status;
1698 struct dig_t dm_digtable;
1699 struct ps_t dm_pstable;
1701 /* data buffer pointer for USB reads */
1705 /*This must be the last item so
1706 that it points to the data allocated
1707 beyond this structure like:
1708 rtl_pci_priv or rtl_usb_priv */
1712 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1713 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1714 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1715 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1716 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1719 /***************************************
1720 Bluetooth Co-existence Related
1721 ****************************************/
1742 enum bt_service_type {
1749 BT_OTHER_ACTION = 6,
1755 enum bt_radio_shared {
1756 BT_RADIO_SHARED = 0,
1757 BT_RADIO_INDIVIDUAL = 1,
1760 struct bt_coexist_info {
1762 /* EEPROM BT info. */
1763 u8 eeprom_bt_coexist;
1765 u8 eeprom_bt_ant_num;
1766 u8 eeprom_bt_ant_isolation;
1767 u8 eeprom_bt_radio_shared;
1773 u8 bt_cur_state; /* 0:on, 1:off */
1774 u8 bt_ant_isolation; /* 0:good, 1:bad */
1775 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1777 u8 bt_radio_shared_type;
1778 u8 bt_rfreg_origin_1e;
1779 u8 bt_rfreg_origin_1f;
1787 bool bt_busy_traffic;
1788 bool bt_traffic_mode_set;
1789 bool bt_non_traffic_mode_set;
1791 bool fw_coexist_all_off;
1792 bool sw_coexist_all_off;
1795 u8 bt_pre_rssi_state;
1803 /****************************************
1804 mem access macro define start
1805 Call endian free function when
1806 1. Read/write packet content.
1807 2. Before write integer to IO.
1808 3. After read integer from IO.
1809 ****************************************/
1810 /* Convert little data endian to host ordering */
1811 #define EF1BYTE(_val) \
1813 #define EF2BYTE(_val) \
1815 #define EF4BYTE(_val) \
1818 /* Read data from memory */
1819 #define READEF1BYTE(_ptr) \
1820 EF1BYTE(*((u8 *)(_ptr)))
1821 /* Read le16 data from memory and convert to host ordering */
1822 #define READEF2BYTE(_ptr) \
1823 EF2BYTE(*((u16 *)(_ptr)))
1824 #define READEF4BYTE(_ptr) \
1825 EF4BYTE(*((u32 *)(_ptr)))
1827 /* Write data to memory */
1828 #define WRITEEF1BYTE(_ptr, _val) \
1829 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1830 /* Write le16 data to memory in host ordering */
1831 #define WRITEEF2BYTE(_ptr, _val) \
1832 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1833 #define WRITEEF4BYTE(_ptr, _val) \
1834 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1836 /* Create a bit mask
1838 * BIT_LEN_MASK_32(0) => 0x00000000
1839 * BIT_LEN_MASK_32(1) => 0x00000001
1840 * BIT_LEN_MASK_32(2) => 0x00000003
1841 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1843 #define BIT_LEN_MASK_32(__bitlen) \
1844 (0xFFFFFFFF >> (32 - (__bitlen)))
1845 #define BIT_LEN_MASK_16(__bitlen) \
1846 (0xFFFF >> (16 - (__bitlen)))
1847 #define BIT_LEN_MASK_8(__bitlen) \
1848 (0xFF >> (8 - (__bitlen)))
1850 /* Create an offset bit mask
1852 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1853 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1855 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1856 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1857 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1858 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1859 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1860 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1863 * Return 4-byte value in host byte ordering from
1864 * 4-byte pointer in little-endian system.
1866 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1867 (EF4BYTE(*((u32 *)(__pstart))))
1868 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1869 (EF2BYTE(*((u16 *)(__pstart))))
1870 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1871 (EF1BYTE(*((u8 *)(__pstart))))
1874 Translate subfield (continuous bits in little-endian) of 4-byte
1875 value to host byte ordering.*/
1876 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1878 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1879 BIT_LEN_MASK_32(__bitlen) \
1881 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1883 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1884 BIT_LEN_MASK_16(__bitlen) \
1886 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1888 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1889 BIT_LEN_MASK_8(__bitlen) \
1893 * Mask subfield (continuous bits in little-endian) of 4-byte value
1894 * and return the result in 4-byte value in host byte ordering.
1896 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1898 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1899 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1901 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1903 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1904 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1906 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1908 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1909 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1913 * Set subfield of little-endian 4-byte value to specified value.
1915 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1916 *((u32 *)(__pstart)) = EF4BYTE \
1918 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1919 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1921 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1922 *((u16 *)(__pstart)) = EF2BYTE \
1924 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1925 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1927 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1928 *((u8 *)(__pstart)) = EF1BYTE \
1930 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1931 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1934 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1935 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1937 /****************************************
1938 mem access macro define end
1939 ****************************************/
1941 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1943 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1944 #define RTL_WATCH_DOG_TIME 2000
1945 #define MSECS(t) msecs_to_jiffies(t)
1946 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1947 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1948 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1949 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1950 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1951 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1952 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1954 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1955 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1956 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1957 /*NIC halt, re-initialize hw parameters*/
1958 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1959 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1960 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1961 /*Always enable ASPM and Clock Req in initialization.*/
1962 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1963 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1964 #define RT_PS_LEVEL_ASPM BIT(7)
1965 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1966 #define RT_RF_LPS_DISALBE_2R BIT(30)
1967 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1968 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1969 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1970 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1971 (ppsc->cur_ps_level &= (~(_ps_flg)))
1972 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1973 (ppsc->cur_ps_level |= _ps_flg)
1975 #define container_of_dwork_rtl(x, y, z) \
1976 container_of(container_of(x, struct delayed_work, work), y, z)
1978 #define FILL_OCTET_STRING(_os, _octet, _len) \
1979 (_os).octet = (u8 *)(_octet); \
1980 (_os).length = (_len);
1982 #define CP_MACADDR(des, src) \
1983 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1984 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1985 (des)[4] = (src)[4], (des)[5] = (src)[5])
1987 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1989 return rtlpriv->io.read8_sync(rtlpriv, addr);
1992 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1994 return rtlpriv->io.read16_sync(rtlpriv, addr);
1997 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1999 return rtlpriv->io.read32_sync(rtlpriv, addr);
2002 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2004 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2006 if (rtlpriv->cfg->write_readback)
2007 rtlpriv->io.read8_sync(rtlpriv, addr);
2010 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2012 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2014 if (rtlpriv->cfg->write_readback)
2015 rtlpriv->io.read16_sync(rtlpriv, addr);
2018 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2019 u32 addr, u32 val32)
2021 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2023 if (rtlpriv->cfg->write_readback)
2024 rtlpriv->io.read32_sync(rtlpriv, addr);
2027 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2028 u32 regaddr, u32 bitmask)
2030 struct rtl_priv *rtlpriv = hw->priv;
2032 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2035 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2036 u32 bitmask, u32 data)
2038 struct rtl_priv *rtlpriv = hw->priv;
2040 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2043 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2044 enum radio_path rfpath, u32 regaddr,
2047 struct rtl_priv *rtlpriv = hw->priv;
2049 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2052 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2053 enum radio_path rfpath, u32 regaddr,
2054 u32 bitmask, u32 data)
2056 struct rtl_priv *rtlpriv = hw->priv;
2058 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2061 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2063 return (_HAL_STATE_STOP == rtlhal->state);
2066 static inline void set_hal_start(struct rtl_hal *rtlhal)
2068 rtlhal->state = _HAL_STATE_START;
2071 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2073 rtlhal->state = _HAL_STATE_STOP;
2076 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2078 return rtlphy->rf_type;
2081 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2083 return (struct ieee80211_hdr *)(skb->data);
2086 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2088 return rtl_get_hdr(skb)->frame_control;
2091 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2093 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2096 static inline u16 rtl_get_tid(struct sk_buff *skb)
2098 return rtl_get_tid_h(rtl_get_hdr(skb));
2101 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2102 struct ieee80211_vif *vif,
2105 return ieee80211_find_sta(vif, bssid);