1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <linux/sched.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <linux/vmalloc.h>
39 #include <linux/usb.h>
40 #include <net/mac80211.h>
41 #include <linux/completion.h>
44 #define RF_CHANGE_BY_INIT 0
45 #define RF_CHANGE_BY_IPS BIT(28)
46 #define RF_CHANGE_BY_PS BIT(29)
47 #define RF_CHANGE_BY_HW BIT(30)
48 #define RF_CHANGE_BY_SW BIT(31)
50 #define IQK_ADDA_REG_NUM 16
51 #define IQK_MAC_REG_NUM 4
53 #define MAX_KEY_LEN 61
54 #define KEY_BUF_SIZE 5
57 /*aci: 0x00 Best Effort*/
58 /*aci: 0x01 Background*/
61 /*Max: define total number.*/
67 #define QOS_QUEUE_NUM 4
68 #define RTL_MAC80211_NUM_QUEUE 5
69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
70 #define RTL_USB_MAX_RX_COUNT 100
71 #define QBSS_LOAD_SIZE 5
72 #define MAX_WMMELE_LENGTH 64
74 #define TOTAL_CAM_ENTRY 32
76 /*slot time for 11g. */
77 #define RTL_SLOT_TIME_9 9
78 #define RTL_SLOT_TIME_20 20
80 /*related with tcp/ip. */
82 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
83 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
84 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
86 #define PROTOC_TYPE_SIZE 2
88 /*related with 802.11 frame*/
89 #define MAC80211_3ADDR_LEN 24
90 #define MAC80211_4ADDR_LEN 30
92 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
93 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
94 #define MAX_PG_GROUP 13
95 #define CHANNEL_GROUP_MAX_2G 3
96 #define CHANNEL_GROUP_IDX_5GL 3
97 #define CHANNEL_GROUP_IDX_5GM 6
98 #define CHANNEL_GROUP_IDX_5GH 9
99 #define CHANNEL_GROUP_MAX_5G 9
100 #define CHANNEL_MAX_NUMBER_2G 14
101 #define AVG_THERMAL_NUM 8
102 #define AVG_THERMAL_NUM_88E 4
103 #define MAX_TID_COUNT 9
109 #define MAX_TX_COUNT 4
110 #define MAX_RF_PATH 4
111 #define MAX_CHNL_GROUP_24G 6
112 #define MAX_CHNL_GROUP_5G 14
114 struct txpower_info_2g {
115 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
116 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
117 /*If only one tx, only BW20 and OFDM are used.*/
118 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
119 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
120 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
121 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
124 struct txpower_info_5g {
125 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
126 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
127 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
128 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
129 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
144 enum rt_eeprom_type {
151 RTL_STATUS_INTERFACE_START = 0,
155 HARDWARE_TYPE_RTL8192E,
156 HARDWARE_TYPE_RTL8192U,
157 HARDWARE_TYPE_RTL8192SE,
158 HARDWARE_TYPE_RTL8192SU,
159 HARDWARE_TYPE_RTL8192CE,
160 HARDWARE_TYPE_RTL8192CU,
161 HARDWARE_TYPE_RTL8192DE,
162 HARDWARE_TYPE_RTL8192DU,
163 HARDWARE_TYPE_RTL8723AE,
164 HARDWARE_TYPE_RTL8723U,
165 HARDWARE_TYPE_RTL8188EE,
171 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
172 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
173 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
174 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
175 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
176 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
177 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
178 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
179 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
180 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
181 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
182 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
183 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
184 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
185 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
186 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
187 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
188 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
189 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
190 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
191 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
192 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
193 #define IS_HARDWARE_TYPE_8723(rtlhal) \
194 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
195 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
196 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
198 #define RX_HAL_IS_CCK_RATE(_pdesc)\
199 (_pdesc->rxmcs == DESC92_RATE1M || \
200 _pdesc->rxmcs == DESC92_RATE2M || \
201 _pdesc->rxmcs == DESC92_RATE5_5M || \
202 _pdesc->rxmcs == DESC92_RATE11M)
204 enum scan_operation_backup_opt {
234 u32 rf_rb; /* rflssi_readback */
235 u32 rf_rbpi; /* rflssi_readbackpi */
239 IO_CMD_PAUSE_DM_BY_SCAN = 0,
240 IO_CMD_RESUME_DM_BY_SCAN = 1,
245 HW_VAR_MULTICAST_REG,
249 HW_VAR_SECURITY_CONF,
250 HW_VAR_BEACON_INTERVAL,
252 HW_VAR_LISTEN_INTERVAL,
265 HW_VAR_RATE_FALLBACK_CONTROL,
266 HW_VAR_CONTENTION_WINDOW,
271 HW_VAR_AMPDU_MIN_SPACE,
272 HW_VAR_SHORTGI_DENSITY,
274 HW_VAR_MCS_RATE_AVAILABLE,
277 HW_VAR_DIS_Req_Qsize,
278 HW_VAR_CCX_CHNL_LOAD,
279 HW_VAR_CCX_NOISE_HISTOGRAM,
286 HW_VAR_SET_DEV_POWER,
296 HW_VAR_USER_CONTROL_TURBO_MODE,
302 HW_VAR_AUTOLOAD_STATUS,
303 HW_VAR_RF_2R_DISABLE,
305 HW_VAR_H2C_FW_PWRMODE,
306 HW_VAR_H2C_FW_JOINBSSRPT,
307 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
308 HW_VAR_FW_PSMODE_STATUS,
309 HW_VAR_RESUME_CLK_ON,
310 HW_VAR_FW_LPS_ACTION,
311 HW_VAR_1X1_RECV_COMBINE,
312 HW_VAR_STOP_SEND_BEACON,
317 HW_VAR_H2C_FW_UPDATE_GTK,
320 HW_VAR_WF_IS_MAC_ADDR,
321 HW_VAR_H2C_FW_OFFLOAD,
324 HW_VAR_HANDLE_FW_C2H,
325 HW_VAR_DL_FW_RSVD_PAGE,
327 HW_VAR_HW_SEQ_ENABLE,
332 HW_VAR_SWITCH_EPHY_WoWLAN,
333 HW_VAR_INT_MIGRATION,
345 enum _RT_MEDIA_STATUS {
346 RT_MEDIA_DISCONNECT = 0,
352 RT_CID_8187_ALPHA0 = 1,
353 RT_CID_8187_SERCOMM_PS = 2,
354 RT_CID_8187_HW_LED = 3,
355 RT_CID_8187_NETGEAR = 4,
357 RT_CID_819x_CAMEO = 6,
358 RT_CID_819x_RUNTOP = 7,
359 RT_CID_819x_Senao = 8,
361 RT_CID_819x_Netcore = 10,
362 RT_CID_Nettronix = 11,
366 RT_CID_819x_ALPHA = 15,
367 RT_CID_819x_Sitecom = 16,
369 RT_CID_819x_Lenovo = 18,
370 RT_CID_819x_QMI = 19,
371 RT_CID_819x_Edimax_Belkin = 20,
372 RT_CID_819x_Sercomm_Belkin = 21,
373 RT_CID_819x_CAMEO1 = 22,
374 RT_CID_819x_MSI = 23,
375 RT_CID_819x_Acer = 24,
377 RT_CID_819x_CLEVO = 28,
378 RT_CID_819x_Arcadyan_Belkin = 29,
379 RT_CID_819x_SAMSUNG = 30,
380 RT_CID_819x_WNC_COREGA = 31,
381 RT_CID_819x_Foxcoon = 32,
382 RT_CID_819x_DELL = 33,
383 RT_CID_819x_PRONETS = 34,
384 RT_CID_819x_Edimax_ASUS = 35,
393 HW_DESC_TX_NEXTDESC_ADDR,
401 PRIME_CHNL_OFFSET_DONT_CARE = 0,
402 PRIME_CHNL_OFFSET_LOWER = 1,
403 PRIME_CHNL_OFFSET_UPPER = 2,
413 enum ht_channel_width {
414 HT_CHANNEL_WIDTH_20 = 0,
415 HT_CHANNEL_WIDTH_20_40 = 1,
418 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
419 Cipher Suites Encryption Algorithms */
422 WEP40_ENCRYPTION = 1,
424 RSERVED_ENCRYPTION = 3,
425 AESCCMP_ENCRYPTION = 4,
426 WEP104_ENCRYPTION = 5,
427 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
432 _HAL_STATE_START = 1,
435 enum rtl_desc92_rate {
436 DESC92_RATE1M = 0x00,
437 DESC92_RATE2M = 0x01,
438 DESC92_RATE5_5M = 0x02,
439 DESC92_RATE11M = 0x03,
441 DESC92_RATE6M = 0x04,
442 DESC92_RATE9M = 0x05,
443 DESC92_RATE12M = 0x06,
444 DESC92_RATE18M = 0x07,
445 DESC92_RATE24M = 0x08,
446 DESC92_RATE36M = 0x09,
447 DESC92_RATE48M = 0x0a,
448 DESC92_RATE54M = 0x0b,
450 DESC92_RATEMCS0 = 0x0c,
451 DESC92_RATEMCS1 = 0x0d,
452 DESC92_RATEMCS2 = 0x0e,
453 DESC92_RATEMCS3 = 0x0f,
454 DESC92_RATEMCS4 = 0x10,
455 DESC92_RATEMCS5 = 0x11,
456 DESC92_RATEMCS6 = 0x12,
457 DESC92_RATEMCS7 = 0x13,
458 DESC92_RATEMCS8 = 0x14,
459 DESC92_RATEMCS9 = 0x15,
460 DESC92_RATEMCS10 = 0x16,
461 DESC92_RATEMCS11 = 0x17,
462 DESC92_RATEMCS12 = 0x18,
463 DESC92_RATEMCS13 = 0x19,
464 DESC92_RATEMCS14 = 0x1a,
465 DESC92_RATEMCS15 = 0x1b,
466 DESC92_RATEMCS15_SG = 0x1c,
467 DESC92_RATEMCS32 = 0x20,
490 EFUSE_HWSET_MAX_SIZE,
491 EFUSE_MAX_SECTION_MAP,
492 EFUSE_REAL_CONTENT_SIZE,
493 EFUSE_OOB_PROTECT_BYTES_LEN,
509 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
510 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
511 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
512 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
513 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
514 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
515 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
516 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
517 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
518 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
519 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
520 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
521 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
522 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
523 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
524 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
525 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
526 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
527 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
528 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
529 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
530 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
531 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
532 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
533 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
534 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
535 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
536 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
537 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
538 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
539 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
540 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
541 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
542 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
544 RTL_IMR_C2HCMD, /*fw interrupt*/
546 /*CCK Rates, TxHT = 0 */
552 /*OFDM Rates, TxHT = 0 */
569 /*Firmware PS mode for control LPS.*/
571 FW_PS_ACTIVE_MODE = 0,
576 FW_PS_UAPSD_WMM_MODE = 5,
577 FW_PS_UAPSD_MODE = 6,
579 FW_PS_WWLAN_MODE = 8,
580 FW_PS_PM_Radio_Off = 9,
581 FW_PS_PM_Card_Disable = 10,
585 EACTIVE, /*Active/Continuous access. */
586 EMAXPS, /*Max power save mode. */
587 EFASTPS, /*Fast power save mode. */
588 EAUTOPS, /*Auto power save mode. */
593 LED_CTL_POWER_ON = 1,
598 LED_CTL_SITE_SURVEY = 6,
599 LED_CTL_POWER_OFF = 7,
600 LED_CTL_START_TO_LINK = 8,
601 LED_CTL_START_WPS = 9,
602 LED_CTL_STOP_WPS = 10,
613 /*acm implementation method.*/
615 eAcmWay0_SwAndHw = 0,
621 SINGLEMAC_SINGLEPHY = 0,
634 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
648 WIRELESS_MODE_UNKNOWN = 0x00,
649 WIRELESS_MODE_A = 0x01,
650 WIRELESS_MODE_B = 0x02,
651 WIRELESS_MODE_G = 0x04,
652 WIRELESS_MODE_AUTO = 0x08,
653 WIRELESS_MODE_N_24G = 0x10,
654 WIRELESS_MODE_N_5G = 0x20
657 #define IS_WIRELESS_MODE_A(wirelessmode) \
658 (wirelessmode == WIRELESS_MODE_A)
659 #define IS_WIRELESS_MODE_B(wirelessmode) \
660 (wirelessmode == WIRELESS_MODE_B)
661 #define IS_WIRELESS_MODE_G(wirelessmode) \
662 (wirelessmode == WIRELESS_MODE_G)
663 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
664 (wirelessmode == WIRELESS_MODE_N_24G)
665 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
666 (wirelessmode == WIRELESS_MODE_N_5G)
668 enum ratr_table_mode {
669 RATR_INX_WIRELESS_NGB = 0,
670 RATR_INX_WIRELESS_NG = 1,
671 RATR_INX_WIRELESS_NB = 2,
672 RATR_INX_WIRELESS_N = 3,
673 RATR_INX_WIRELESS_GB = 4,
674 RATR_INX_WIRELESS_G = 5,
675 RATR_INX_WIRELESS_B = 6,
676 RATR_INX_WIRELESS_MC = 7,
677 RATR_INX_WIRELESS_A = 8,
680 enum rtl_link_state {
682 MAC80211_LINKING = 1,
684 MAC80211_LINKED_SCANNING = 3,
701 enum rt_polarity_ctl {
702 RT_POLARITY_LOW_ACT = 0,
703 RT_POLARITY_HIGH_ACT = 1,
706 struct octet_string {
711 struct rtl_hdr_3addr {
721 struct rtl_info_element {
727 struct rtl_probe_rsp {
728 struct rtl_hdr_3addr header;
730 __le16 beacon_interval;
732 /*SSID, supported rates, FH params, DS params,
733 CF params, IBSS params, TIM (if beacon), RSN */
734 struct rtl_info_element info_element[0];
738 /*ledpin Identify how to implement this SW led.*/
741 enum rtl_led_pin ledpin;
747 struct rtl_led sw_led0;
748 struct rtl_led sw_led1;
751 struct rtl_qos_parameters {
759 struct rt_smooth_data {
760 u32 elements[100]; /*array to store values */
761 u32 index; /*index to current array to store */
762 u32 total_num; /*num of valid elements */
763 u32 total_val; /*sum of valid elements */
766 struct false_alarm_statistics {
768 u32 cnt_rate_illegal;
771 u32 cnt_fast_fsync_fail;
772 u32 cnt_sb_search_fail;
792 struct wireless_stats {
793 unsigned long txbytesunicast;
794 unsigned long txbytesmulticast;
795 unsigned long txbytesbroadcast;
796 unsigned long rxbytesunicast;
799 /*Correct smoothed ss in Dbm, only used
800 in driver to report real power now. */
801 long recv_signal_power;
803 long last_sigstrength_inpercent;
805 u32 rssi_calculate_cnt;
807 /*Transformed, in dbm. Beautified signal
808 strength for UI, not correct. */
809 long signal_strength;
811 u8 rx_rssi_percentage[4];
812 u8 rx_evm_percentage[2];
814 struct rt_smooth_data ui_rssi;
815 struct rt_smooth_data ui_link_quality;
818 struct rate_adaptive {
819 u8 rate_adaptive_disabled;
823 u32 high_rssi_thresh_for_ra;
824 u32 high2low_rssi_thresh_for_ra;
825 u8 low2high_rssi_thresh_for_ra40m;
826 u32 low_rssi_thresh_for_ra40M;
827 u8 low2high_rssi_thresh_for_ra20m;
828 u32 low_rssi_thresh_for_ra20M;
829 u32 upper_rssi_threshold_ratr;
830 u32 middleupper_rssi_threshold_ratr;
831 u32 middle_rssi_threshold_ratr;
832 u32 middlelow_rssi_threshold_ratr;
833 u32 low_rssi_threshold_ratr;
834 u32 ultralow_rssi_threshold_ratr;
835 u32 low_rssi_threshold_ratr_40m;
836 u32 low_rssi_threshold_ratr_20m;
839 u32 ping_rssi_thresh_for_ra;
844 struct regd_pair_mapping {
850 struct rtl_regulatory {
858 struct regd_pair_mapping *regpair;
862 bool rfkill_state; /*0 is off, 1 is on */
866 #define P2P_MAX_NOA_NUM 2
869 P2P_ROLE_DISABLE = 0,
879 P2P_PS_SCAN_DONE = 3,
880 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
887 P2P_PS_MIX = 3, /* CTWindow and NoA */
890 struct rtl_p2p_ps_info {
891 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
892 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
893 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
894 /* Client traffic window. A period of time in TU after TBTT. */
896 u8 opp_ps; /* opportunistic power save. */
897 u8 noa_num; /* number of NoA descriptor in P2P IE. */
898 /* Count for owner, Type of client. */
899 u8 noa_count_type[P2P_MAX_NOA_NUM];
900 /* Max duration for owner, preferred or min acceptable duration
903 u32 noa_duration[P2P_MAX_NOA_NUM];
904 /* Length of interval for owner, preferred or max acceptable intervali
907 u32 noa_interval[P2P_MAX_NOA_NUM];
908 /* schedule in terms of the lower 4 bytes of the TSF timer. */
909 u32 noa_start_time[P2P_MAX_NOA_NUM];
912 struct p2p_ps_offload_t {
914 u8 role:1; /* 1: Owner, 0: Client */
923 #define IQK_MATRIX_REG_NUM 8
924 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
926 struct iqk_matrix_regs {
928 long value[1][IQK_MATRIX_REG_NUM];
931 struct phy_parameters {
936 enum hw_param_tab_index {
951 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
952 struct init_gain initgain_backup;
953 enum io_type current_io_type;
958 u8 set_bwmode_inprogress;
959 u8 sw_chnl_inprogress;
964 u8 set_io_inprogress;
967 /* record for power tracking */
979 u32 reg_c04, reg_c08, reg_874;
981 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
982 u32 iqk_bb_backup[10];
983 bool iqk_initialized;
987 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
993 /* MAX_PG_GROUP groups of pwr diff by rates */
994 u32 mcs_offset[MAX_PG_GROUP][16];
995 u8 default_initialgain[4];
997 /* the current Tx power level */
999 u8 cur_ofdm24g_txpwridx;
1000 u8 cur_bw20_txpwridx;
1001 u8 cur_bw40_txpwridx;
1003 u32 rfreg_chnlval[2];
1005 u32 reg_rf3c[2]; /* pathA / pathB */
1011 u8 num_total_rfpath;
1012 struct phy_parameters hwparam_tables[MAX_TAB];
1015 enum rt_polarity_ctl polarity_ctl;
1018 #define MAX_TID_COUNT 9
1019 #define RTL_AGG_STOP 0
1020 #define RTL_AGG_PROGRESS 1
1021 #define RTL_AGG_START 2
1022 #define RTL_AGG_OPERATIONAL 3
1023 #define RTL_AGG_OFF 0
1024 #define RTL_AGG_ON 1
1025 #define RTL_RX_AGG_START 1
1026 #define RTL_RX_AGG_STOP 0
1027 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1028 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1044 struct rtl_tid_data {
1046 struct rtl_ht_agg agg;
1049 struct rtl_sta_info {
1050 struct list_head list;
1054 u8 mac_addr[ETH_ALEN];
1055 struct rtl_tid_data tids[MAX_TID_COUNT];
1057 /* just used for ap adhoc or mesh*/
1058 struct rssi_sta rssi_stat;
1064 struct mutex bb_mutex;
1067 unsigned long pci_mem_end; /*shared mem end */
1068 unsigned long pci_mem_start; /*shared mem start */
1071 unsigned long pci_base_addr; /*device I/O address */
1073 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1074 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1075 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1076 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1079 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1080 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1081 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1086 u8 mac_addr[ETH_ALEN];
1087 u8 mac80211_registered;
1093 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1094 struct ieee80211_hw *hw;
1095 struct ieee80211_vif *vif;
1096 enum nl80211_iftype opmode;
1098 /*Probe Beacon management */
1099 struct rtl_tid_data tids[MAX_TID_COUNT];
1100 enum rtl_link_state link_state;
1106 u8 p2p; /*using p2p role*/
1116 u8 cnt_after_linked;
1120 /* skb wait queue */
1121 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1129 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1130 u32 basic_rates; /* b/g rates */
1135 u8 mode; /* wireless mode */
1140 u8 cur_40_prime_sc_bk;
1148 int beacon_interval;
1151 u8 min_space_cfg; /*For Min spacing configurations */
1153 u8 current_ampdu_factor;
1154 u8 current_ampdu_density;
1157 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1158 struct rtl_qos_parameters ac[AC_MAX];
1163 u32 last_bt_edca_ul;
1164 u32 last_bt_edca_dl;
1170 bool adc_back_off_on;
1172 bool low_penalty_rate_adaptive;
1173 bool rf_rx_lpf_shrink;
1174 bool reject_aggre_pkt;
1182 u8 fw_dac_swing_lvl;
1189 bool sw_dac_swing_on;
1190 u32 sw_dac_swing_lvl;
1195 bool ignore_wlan_act;
1198 struct bt_coexist_8723 {
1199 u32 high_priority_tx;
1200 u32 high_priority_rx;
1201 u32 low_priority_tx;
1202 u32 low_priority_rx;
1204 bool c2h_bt_info_req_sent;
1205 bool c2h_bt_inquiry_page;
1206 u32 bt_inq_page_start_time;
1208 u8 c2h_bt_info_original;
1209 u8 bt_inquiry_page_cnt;
1210 struct btdm_8723 btdm;
1214 struct ieee80211_hw *hw;
1215 bool driver_is_goingto_unload;
1218 bool being_init_adapter;
1220 bool mac_func_enable;
1221 struct bt_coexist_8723 hal_coex_8723;
1223 enum intf_type interface;
1224 u16 hw_type; /*92c or 92d or 92s and so on */
1227 u32 version; /*version of chip */
1228 u8 state; /*stop 0, start 1 */
1236 bool h2c_setinprogress;
1239 /*Reserve page start offset except beacon in TxQ. */
1240 u8 fw_rsvdpage_startoffset;
1243 /* FW Cmd IO related */
1246 bool set_fwcmd_inprogress;
1247 u8 current_fwcmd_io;
1249 struct p2p_ps_offload_t p2p_ps_offload;
1250 bool fw_clk_change_in_progress;
1251 bool allow_sw_to_change_hwclc;
1254 bool driver_going2unload;
1256 /*AMPDU init min space*/
1257 u8 minspace_cfg; /*For Min spacing configurations */
1260 enum macphy_mode macphymode;
1261 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1262 enum band_type current_bandtypebackup;
1263 enum band_type bandset;
1264 /* dual MAC 0--Mac0 1--Mac1 */
1266 /* just for DualMac S3S4 */
1268 bool earlymode_enable;
1269 u8 max_earlymode_num;
1271 bool during_mac0init_radiob;
1272 bool during_mac1init_radioa;
1273 bool reloadtxpowerindex;
1274 /* True if IMR or IQK have done
1275 for 2.4G in scan progress */
1276 bool load_imrandiqk_setting_for2g;
1278 bool disable_amsdu_8k;
1279 bool master_of_dmsp;
1283 struct rtl_security {
1288 bool use_defaultkey;
1289 /*Encryption Algorithm for Unicast Packet */
1290 enum rt_enc_alg pairwise_enc_algorithm;
1291 /*Encryption Algorithm for Brocast/Multicast */
1292 enum rt_enc_alg group_enc_algorithm;
1293 /*Cam Entry Bitmap */
1294 u32 hwsec_cam_bitmap;
1295 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1296 /*local Key buffer, indx 0 is for
1297 pairwise key 1-4 is for agoup key. */
1298 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1299 u8 key_len[KEY_BUF_SIZE];
1301 /*The pointer of Pairwise Key,
1302 it always points to KeyBuf[4] */
1306 #define ASSOCIATE_ENTRY_NUM 33
1308 struct fast_ant_training {
1310 u8 antsel_rx_keep_0;
1311 u8 antsel_rx_keep_1;
1312 u8 antsel_rx_keep_2;
1318 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1319 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1320 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1321 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1322 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1323 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1324 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1330 /*PHY status for Dynamic Management */
1331 long entry_min_undec_sm_pwdb;
1332 long undec_sm_pwdb; /*out dm */
1333 long entry_max_undec_sm_pwdb;
1334 bool dm_initialgain_enable;
1335 bool dynamic_txpower_enable;
1336 bool current_turbo_edca;
1337 bool is_any_nonbepkts; /*out dm */
1338 bool is_cur_rdlstate;
1339 bool txpower_trackinginit;
1340 bool disable_framebursting;
1342 bool txpower_tracking;
1344 bool rfpath_rxenable[4];
1345 bool inform_fw_driverctrldm;
1346 bool current_mrc_switch;
1349 u8 thermalvalue_rxgain;
1350 u8 thermalvalue_iqk;
1351 u8 thermalvalue_lck;
1354 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1355 u8 thermalvalue_avg_index;
1357 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1358 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1360 u8 txpower_track_control;
1361 bool interrupt_migration;
1362 bool disable_tx_int;
1365 char delta_power_index;
1366 char delta_power_index_last;
1367 char power_index_offset;
1369 /*88e tx power tracking*/
1370 u8 swing_idx_ofdm[2];
1371 u8 swing_idx_ofdm_cur;
1372 u8 swing_idx_ofdm_base;
1373 bool swing_flag_ofdm;
1375 u8 swing_idx_cck_cur;
1376 u8 swing_idx_cck_base;
1377 bool swing_flag_cck;
1380 bool supp_phymode_switch;
1382 struct fast_ant_training fat_table;
1385 #define EFUSE_MAX_LOGICAL_SIZE 256
1390 u16 max_physical_size;
1392 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1393 u16 efuse_usedbytes;
1394 u8 efuse_usedpercentage;
1395 #ifdef EFUSE_REPG_WORKAROUND
1396 bool efuse_re_pg_sec1flag;
1397 u8 efuse_re_pg_data[8];
1400 u8 autoload_failflag;
1409 u16 eeprom_channelplan;
1417 u8 antenna_div_type;
1419 bool txpwr_fromeprom;
1420 u8 eeprom_crystalcap;
1422 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1423 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1424 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1425 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1426 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1427 u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
1428 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1429 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1430 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1432 u8 internal_pa_5g[2]; /* pathA / pathB */
1436 /*For power group */
1437 u8 eeprom_pwrgroup[2][3];
1438 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1439 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1441 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1442 /*For HT<->legacy pwr diff*/
1443 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1444 u8 txpwr_safetyflag; /* Band edge enable flag */
1445 u16 eeprom_txpowerdiff;
1446 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1447 u8 antenna_txpwdiff[3];
1449 u8 eeprom_regulatory;
1450 u8 eeprom_thermalmeter;
1451 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1453 u8 crystalcap; /* CrystalCap. */
1457 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1458 bool apk_thermalmeterignore;
1460 bool b1x1_recvcombine;
1468 bool pwrdomain_protect;
1469 bool in_powersavemode;
1470 bool rfchange_inprogress;
1471 bool swrf_processing;
1474 * just for PCIE ASPM
1475 * If it supports ASPM, Offset[560h] = 0x40,
1476 * otherwise Offset[560h] = 0x00.
1479 bool support_backdoor;
1482 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1487 /*For Fw control LPS mode */
1489 /*Record Fw PS mode status. */
1490 bool fw_current_inpsmode;
1491 u8 reg_max_lps_awakeintvl;
1493 bool low_power_enable;/*for 32k*/
1504 /*just for PCIE ASPM */
1505 u8 const_amdpci_aspm;
1508 enum rf_pwrstate inactive_pwrstate;
1509 enum rf_pwrstate rfpwr_state; /*cur power state */
1515 bool multi_buffered;
1517 unsigned int dtim_counter;
1518 unsigned int sleep_ms;
1519 unsigned long last_sleep_jiffies;
1520 unsigned long last_awake_jiffies;
1521 unsigned long last_delaylps_stamp_jiffies;
1522 unsigned long last_dtim;
1523 unsigned long last_beacon;
1524 unsigned long last_action;
1525 unsigned long last_slept;
1528 struct rtl_p2p_ps_info p2p_ps_info;
1534 u8 psaddr[ETH_ALEN];
1539 u8 rate; /* hw desc rate */
1540 u8 received_channel;
1549 u8 signalquality; /*in 0-100 index. */
1551 * Real power in dBm for this packet,
1552 * no beautification and aggregation.
1554 s32 recvsignalpower;
1555 s8 rxpower; /*in dBm Translate from PWdB */
1556 u8 signalstrength; /*in 0-100 index. */
1560 u16 shortpreamble:1;
1571 bool rx_is40Mhzpacket;
1573 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1574 s8 rx_mimo_sig_qual[2];
1575 bool packet_matchbssid;
1579 bool packet_beacon; /*for rssi */
1580 char cck_adc_pwdb[4]; /*for rx path selection */
1582 u8 packet_report_type;
1586 u32 bt_rx_rssi_percentage;
1587 u32 macid_valid_entry[2];
1591 struct rt_link_detect {
1592 /* count for roaming */
1593 u32 bcn_rx_inperiod;
1596 u32 num_tx_in4period[4];
1597 u32 num_rx_in4period[4];
1599 u32 num_tx_inperiod;
1600 u32 num_rx_inperiod;
1603 bool tx_busy_traffic;
1604 bool rx_busy_traffic;
1605 bool higher_busytraffic;
1606 bool higher_busyrxtraffic;
1608 u32 tidtx_in4period[MAX_TID_COUNT][4];
1609 u32 tidtx_inperiod[MAX_TID_COUNT];
1610 bool higher_busytxtraffic[MAX_TID_COUNT];
1613 struct rtl_tcb_desc {
1621 u8 rts_use_shortpreamble:1;
1622 u8 rts_use_shortgi:1;
1628 u8 use_shortpreamble:1;
1629 u8 use_driver_rate:1;
1630 u8 disable_ratefallback:1;
1642 /* The max value by HW */
1644 bool btx_enable_sw_calc_duration;
1647 struct rtl_hal_ops {
1648 int (*init_sw_vars) (struct ieee80211_hw *hw);
1649 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1650 void (*read_chip_version)(struct ieee80211_hw *hw);
1651 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1652 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1653 u32 *p_inta, u32 *p_intb);
1654 int (*hw_init) (struct ieee80211_hw *hw);
1655 void (*hw_disable) (struct ieee80211_hw *hw);
1656 void (*hw_suspend) (struct ieee80211_hw *hw);
1657 void (*hw_resume) (struct ieee80211_hw *hw);
1658 void (*enable_interrupt) (struct ieee80211_hw *hw);
1659 void (*disable_interrupt) (struct ieee80211_hw *hw);
1660 int (*set_network_type) (struct ieee80211_hw *hw,
1661 enum nl80211_iftype type);
1662 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1664 void (*set_bw_mode) (struct ieee80211_hw *hw,
1665 enum nl80211_channel_type ch_type);
1666 u8(*switch_channel) (struct ieee80211_hw *hw);
1667 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1668 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1669 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1670 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1671 u32 add_msr, u32 rm_msr);
1672 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1673 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1674 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1675 struct ieee80211_sta *sta, u8 rssi_level);
1676 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1677 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1678 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1679 struct ieee80211_tx_info *info,
1680 struct ieee80211_sta *sta,
1681 struct sk_buff *skb, u8 hw_queue,
1682 struct rtl_tcb_desc *ptcb_desc);
1683 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1684 u32 buffer_len, bool bIsPsPoll);
1685 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1686 bool firstseg, bool lastseg,
1687 struct sk_buff *skb);
1688 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1689 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1690 struct rtl_stats *stats,
1691 struct ieee80211_rx_status *rx_status,
1692 u8 *pdesc, struct sk_buff *skb);
1693 void (*set_channel_access) (struct ieee80211_hw *hw);
1694 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1695 void (*dm_watchdog) (struct ieee80211_hw *hw);
1696 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1697 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1698 enum rf_pwrstate rfpwr_state);
1699 void (*led_control) (struct ieee80211_hw *hw,
1700 enum led_ctl_mode ledaction);
1701 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1702 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1703 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1704 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1705 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1706 u8 *macaddr, bool is_group, u8 enc_algo,
1707 bool is_wepkey, bool clear_all);
1708 void (*init_sw_leds) (struct ieee80211_hw *hw);
1709 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1710 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1711 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1713 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1714 u32 regaddr, u32 bitmask);
1715 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1716 u32 regaddr, u32 bitmask, u32 data);
1717 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1718 bool allow_all_da, bool write_into_reg);
1719 void (*linked_set_reg) (struct ieee80211_hw *hw);
1720 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
1721 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1722 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1723 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1724 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1726 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1727 u8 *ppowerlevel, u8 channel);
1728 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1730 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1732 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1733 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1734 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1735 void (*c2h_command_handle) (struct ieee80211_hw *hw);
1736 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1738 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
1741 struct rtl_intf_ops {
1743 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1744 int (*adapter_start) (struct ieee80211_hw *hw);
1745 void (*adapter_stop) (struct ieee80211_hw *hw);
1746 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1747 struct rtl_priv **buddy_priv);
1749 int (*adapter_tx) (struct ieee80211_hw *hw,
1750 struct ieee80211_sta *sta,
1751 struct sk_buff *skb,
1752 struct rtl_tcb_desc *ptcb_desc);
1753 void (*flush)(struct ieee80211_hw *hw, bool drop);
1754 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1755 bool (*waitq_insert) (struct ieee80211_hw *hw,
1756 struct ieee80211_sta *sta,
1757 struct sk_buff *skb);
1760 void (*disable_aspm) (struct ieee80211_hw *hw);
1761 void (*enable_aspm) (struct ieee80211_hw *hw);
1766 struct rtl_mod_params {
1767 /* default: 0 = using hardware encryption */
1770 /* default: 0 = DBG_EMERG (0)*/
1773 /* default: 1 = using no linked power save */
1776 /* default: 1 = using linked sw power save */
1779 /* default: 1 = using linked fw power save */
1783 struct rtl_hal_usbint_cfg {
1790 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1791 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1792 struct sk_buff_head *);
1795 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1796 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1798 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1799 struct sk_buff_head *);
1801 /* endpoint mapping */
1802 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1803 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1806 struct rtl_hal_cfg {
1808 bool write_readback;
1811 struct rtl_hal_ops *ops;
1812 struct rtl_mod_params *mod_params;
1813 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1815 /*this map used for some registers or vars
1816 defined int HAL but used in MAIN */
1817 u32 maps[RTL_VAR_MAP_MAX];
1823 struct mutex conf_mutex;
1824 struct mutex ps_mutex;
1827 spinlock_t ips_lock;
1828 spinlock_t irq_th_lock;
1829 spinlock_t irq_pci_lock;
1831 spinlock_t h2c_lock;
1832 spinlock_t rf_ps_lock;
1834 spinlock_t lps_lock;
1835 spinlock_t waitq_lock;
1836 spinlock_t entry_list_lock;
1837 spinlock_t usb_lock;
1839 /*FW clock change */
1840 spinlock_t fw_ps_lock;
1843 spinlock_t cck_and_rw_pagea_lock;
1846 spinlock_t check_sendpkt_lock;
1850 struct ieee80211_hw *hw;
1853 struct timer_list watchdog_timer;
1854 struct timer_list dualmac_easyconcurrent_retrytimer;
1855 struct timer_list fw_clockoff_timer;
1856 struct timer_list fast_antenna_training_timer;
1858 struct tasklet_struct irq_tasklet;
1859 struct tasklet_struct irq_prepare_bcn_tasklet;
1862 struct workqueue_struct *rtl_wq;
1863 struct delayed_work watchdog_wq;
1864 struct delayed_work ips_nic_off_wq;
1867 struct delayed_work ps_work;
1868 struct delayed_work ps_rfon_wq;
1869 struct delayed_work fwevt_wq;
1871 struct work_struct lps_change_work;
1875 u32 dbgp_type[DBGP_TYPE_MAX];
1876 int global_debuglevel;
1877 u64 global_debugcomponents;
1879 /* add for proc debug */
1880 struct proc_dir_entry *proc_dir;
1884 #define MIMO_PS_STATIC 0
1885 #define MIMO_PS_DYNAMIC 1
1886 #define MIMO_PS_NOLIMIT 3
1888 struct rtl_dualmac_easy_concurrent_ctl {
1889 enum band_type currentbandtype_backfordmdp;
1890 bool close_bbandrf_for_dmsp;
1891 bool change_to_dmdp;
1892 bool change_to_dmsp;
1893 bool switch_in_process;
1896 struct rtl_dmsp_ctl {
1897 bool activescan_for_slaveofdmsp;
1898 bool scan_for_anothermac_fordmsp;
1899 bool scan_for_itself_fordmsp;
1900 bool writedig_for_anothermacofdmsp;
1901 u32 curdigvalue_for_anothermacofdmsp;
1902 bool changecckpdstate_for_anothermacofdmsp;
1903 u8 curcckpdstate_for_anothermacofdmsp;
1904 bool changetxhighpowerlvl_for_anothermacofdmsp;
1905 u8 curtxhighlvl_for_anothermacofdmsp;
1906 long rssivalmin_for_anothermacofdmsp;
1919 u32 rssi_highthresh;
1922 long last_min_undec_pwdb_for_dm;
1923 long rssi_highpower_lowthresh;
1924 long rssi_highpower_highthresh;
1930 u8 dig_ext_port_stage;
1932 u8 dig_twoport_algorithm;
1934 u8 dig_slgorithm_switch;
1937 u8 curmultista_cstate;
1939 char back_range_max;
1940 char back_range_min;
1943 u8 min_undec_pwdb_for_dm;
1945 u8 pre_cck_cca_thres;
1946 u8 cur_cck_cca_thres;
1947 u8 pre_cck_pd_state;
1948 u8 cur_cck_pd_state;
1949 u8 pre_cck_fa_state;
1950 u8 cur_cck_fa_state;
1956 u8 dig_highpwrstate;
1963 u8 cur_cs_ratiostate;
1964 u8 pre_cs_ratiostate;
1965 u8 backoff_enable_flag;
1966 char backoffval_range_max;
1967 char backoffval_range_min;
1970 bool media_connect_0;
1971 bool media_connect_1;
1973 u32 antdiv_rssi_max;
1977 struct rtl_global_var {
1978 /* from this list we can get
1979 * other adapter's rtl_priv */
1980 struct list_head glb_priv_list;
1981 spinlock_t glb_list_lock;
1985 struct ieee80211_hw *hw;
1986 struct completion firmware_loading_complete;
1987 struct list_head list;
1988 struct rtl_priv *buddy_priv;
1989 struct rtl_global_var *glb_var;
1990 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
1991 struct rtl_dmsp_ctl dmsp_ctl;
1992 struct rtl_locks locks;
1993 struct rtl_works works;
1994 struct rtl_mac mac80211;
1995 struct rtl_hal rtlhal;
1996 struct rtl_regulatory regd;
1997 struct rtl_rfkill rfkill;
2001 struct rtl_security sec;
2002 struct rtl_efuse efuse;
2004 struct rtl_ps_ctl psc;
2005 struct rate_adaptive ra;
2006 struct wireless_stats stats;
2007 struct rt_link_detect link_info;
2008 struct false_alarm_statistics falsealm_cnt;
2010 struct rtl_rate_priv *rate_priv;
2012 /* sta entry list for ap adhoc or mesh */
2013 struct list_head entry_list;
2015 struct rtl_debug dbg;
2019 *hal_cfg : for diff cards
2020 *intf_ops : for diff interrface usb/pcie
2022 struct rtl_hal_cfg *cfg;
2023 struct rtl_intf_ops *intf_ops;
2025 /*this var will be set by set_bit,
2026 and was used to indicate status of
2027 interface or hardware */
2028 unsigned long status;
2031 struct dig_t dm_digtable;
2032 struct ps_t dm_pstable;
2034 /* section shared by individual drivers */
2036 struct { /* data buffer pointer for USB reads */
2041 struct { /* section for 8723ae */
2042 bool reg_init; /* true if regs saved */
2047 bool bt_operation_on;
2050 bool enter_ps; /* true when entering PS */
2052 /*This must be the last item so
2053 that it points to the data allocated
2054 beyond this structure like:
2055 rtl_pci_priv or rtl_usb_priv */
2059 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2060 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2061 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2062 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2063 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2066 /***************************************
2067 Bluetooth Co-existence Related
2068 ****************************************/
2090 enum bt_service_type {
2097 BT_OTHER_ACTION = 6,
2103 enum bt_radio_shared {
2104 BT_RADIO_SHARED = 0,
2105 BT_RADIO_INDIVIDUAL = 1,
2108 struct bt_coexist_info {
2110 /* EEPROM BT info. */
2111 u8 eeprom_bt_coexist;
2113 u8 eeprom_bt_ant_num;
2114 u8 eeprom_bt_ant_isol;
2115 u8 eeprom_bt_radio_shared;
2121 u8 bt_cur_state; /* 0:on, 1:off */
2122 u8 bt_ant_isolation; /* 0:good, 1:bad */
2123 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2125 u8 bt_radio_shared_type;
2126 u8 bt_rfreg_origin_1e;
2127 u8 bt_rfreg_origin_1f;
2135 bool bt_busy_traffic;
2136 bool bt_traffic_mode_set;
2137 bool bt_non_traffic_mode_set;
2139 bool fw_coexist_all_off;
2140 bool sw_coexist_all_off;
2141 bool hw_coexist_all_off;
2145 u32 previous_state_h;
2147 u8 bt_pre_rssi_state;
2148 u8 bt_pre_rssi_state1;
2153 u8 bt_active_zero_cnt;
2154 bool cur_bt_disabled;
2155 bool pre_bt_disabled;
2158 u8 bt_profile_action;
2160 bool hold_for_bt_operation;
2165 /****************************************
2166 mem access macro define start
2167 Call endian free function when
2168 1. Read/write packet content.
2169 2. Before write integer to IO.
2170 3. After read integer from IO.
2171 ****************************************/
2172 /* Convert little data endian to host ordering */
2173 #define EF1BYTE(_val) \
2175 #define EF2BYTE(_val) \
2177 #define EF4BYTE(_val) \
2180 /* Read data from memory */
2181 #define READEF1BYTE(_ptr) \
2182 EF1BYTE(*((u8 *)(_ptr)))
2183 /* Read le16 data from memory and convert to host ordering */
2184 #define READEF2BYTE(_ptr) \
2186 #define READEF4BYTE(_ptr) \
2189 /* Write data to memory */
2190 #define WRITEEF1BYTE(_ptr, _val) \
2191 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2192 /* Write le16 data to memory in host ordering */
2193 #define WRITEEF2BYTE(_ptr, _val) \
2194 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2195 #define WRITEEF4BYTE(_ptr, _val) \
2196 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2198 /* Create a bit mask
2200 * BIT_LEN_MASK_32(0) => 0x00000000
2201 * BIT_LEN_MASK_32(1) => 0x00000001
2202 * BIT_LEN_MASK_32(2) => 0x00000003
2203 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2205 #define BIT_LEN_MASK_32(__bitlen) \
2206 (0xFFFFFFFF >> (32 - (__bitlen)))
2207 #define BIT_LEN_MASK_16(__bitlen) \
2208 (0xFFFF >> (16 - (__bitlen)))
2209 #define BIT_LEN_MASK_8(__bitlen) \
2210 (0xFF >> (8 - (__bitlen)))
2212 /* Create an offset bit mask
2214 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2215 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2217 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2218 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2219 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2220 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2221 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2222 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2225 * Return 4-byte value in host byte ordering from
2226 * 4-byte pointer in little-endian system.
2228 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2229 (EF4BYTE(*((__le32 *)(__pstart))))
2230 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2231 (EF2BYTE(*((__le16 *)(__pstart))))
2232 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2233 (EF1BYTE(*((u8 *)(__pstart))))
2236 Translate subfield (continuous bits in little-endian) of 4-byte
2237 value to host byte ordering.*/
2238 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2240 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2241 BIT_LEN_MASK_32(__bitlen) \
2243 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2245 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2246 BIT_LEN_MASK_16(__bitlen) \
2248 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2250 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2251 BIT_LEN_MASK_8(__bitlen) \
2255 * Mask subfield (continuous bits in little-endian) of 4-byte value
2256 * and return the result in 4-byte value in host byte ordering.
2258 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2260 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2261 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2263 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2265 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2266 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2268 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2270 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2271 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2275 * Set subfield of little-endian 4-byte value to specified value.
2277 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2278 *((u32 *)(__pstart)) = \
2280 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2281 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2283 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2284 *((u16 *)(__pstart)) = \
2286 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2287 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2289 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2290 *((u8 *)(__pstart)) = EF1BYTE \
2292 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2293 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2296 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2297 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2299 /****************************************
2300 mem access macro define end
2301 ****************************************/
2303 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2305 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2306 #define RTL_WATCH_DOG_TIME 2000
2307 #define MSECS(t) msecs_to_jiffies(t)
2308 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2309 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2310 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2311 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2312 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2314 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2315 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2316 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2317 /*NIC halt, re-initialize hw parameters*/
2318 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2319 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2320 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2321 /*Always enable ASPM and Clock Req in initialization.*/
2322 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2323 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2324 #define RT_PS_LEVEL_ASPM BIT(7)
2325 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2326 #define RT_RF_LPS_DISALBE_2R BIT(30)
2327 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2328 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2329 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2330 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2331 (ppsc->cur_ps_level &= (~(_ps_flg)))
2332 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2333 (ppsc->cur_ps_level |= _ps_flg)
2335 #define container_of_dwork_rtl(x, y, z) \
2336 container_of(container_of(x, struct delayed_work, work), y, z)
2338 #define FILL_OCTET_STRING(_os, _octet, _len) \
2339 (_os).octet = (u8 *)(_octet); \
2340 (_os).length = (_len);
2342 #define CP_MACADDR(des, src) \
2343 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2344 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2345 (des)[4] = (src)[4], (des)[5] = (src)[5])
2347 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2349 return rtlpriv->io.read8_sync(rtlpriv, addr);
2352 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2354 return rtlpriv->io.read16_sync(rtlpriv, addr);
2357 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2359 return rtlpriv->io.read32_sync(rtlpriv, addr);
2362 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2364 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2366 if (rtlpriv->cfg->write_readback)
2367 rtlpriv->io.read8_sync(rtlpriv, addr);
2370 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2372 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2374 if (rtlpriv->cfg->write_readback)
2375 rtlpriv->io.read16_sync(rtlpriv, addr);
2378 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2379 u32 addr, u32 val32)
2381 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2383 if (rtlpriv->cfg->write_readback)
2384 rtlpriv->io.read32_sync(rtlpriv, addr);
2387 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2388 u32 regaddr, u32 bitmask)
2390 struct rtl_priv *rtlpriv = hw->priv;
2392 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2395 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2396 u32 bitmask, u32 data)
2398 struct rtl_priv *rtlpriv = hw->priv;
2400 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2403 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2404 enum radio_path rfpath, u32 regaddr,
2407 struct rtl_priv *rtlpriv = hw->priv;
2409 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2412 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2413 enum radio_path rfpath, u32 regaddr,
2414 u32 bitmask, u32 data)
2416 struct rtl_priv *rtlpriv = hw->priv;
2418 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2421 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2423 return (_HAL_STATE_STOP == rtlhal->state);
2426 static inline void set_hal_start(struct rtl_hal *rtlhal)
2428 rtlhal->state = _HAL_STATE_START;
2431 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2433 rtlhal->state = _HAL_STATE_STOP;
2436 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2438 return rtlphy->rf_type;
2441 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2443 return (struct ieee80211_hdr *)(skb->data);
2446 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2448 return rtl_get_hdr(skb)->frame_control;
2451 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2453 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2456 static inline u16 rtl_get_tid(struct sk_buff *skb)
2458 return rtl_get_tid_h(rtl_get_hdr(skb));
2461 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2462 struct ieee80211_vif *vif,
2465 return ieee80211_find_sta(vif, bssid);
2468 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2471 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2472 return ieee80211_find_sta(mac->vif, mac_addr);