2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
25 #include <linux/err.h>
27 #include <linux/wl12xx.h>
29 #include "../wlcore/wlcore.h"
30 #include "../wlcore/debug.h"
31 #include "../wlcore/io.h"
32 #include "../wlcore/acx.h"
33 #include "../wlcore/tx.h"
34 #include "../wlcore/rx.h"
35 #include "../wlcore/io.h"
36 #include "../wlcore/boot.h"
44 static char *fref_param;
45 static char *tcxo_param;
47 static struct wlcore_conf wl12xx_conf = {
50 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
51 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
52 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
53 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
54 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
55 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
56 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
57 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
58 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
59 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
60 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
61 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
62 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
63 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
64 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
65 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
66 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
67 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
68 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
69 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
70 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
71 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
72 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
73 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
74 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
75 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
76 /* active scan params */
77 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
78 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
79 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
80 /* passive scan params */
81 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
82 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
83 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
84 /* passive scan in dual antenna params */
85 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
86 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
87 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
89 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
90 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
91 [CONF_SG_BEACON_MISS_PERCENT] = 60,
92 [CONF_SG_DHCP_TIME] = 5000,
95 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
96 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
97 [CONF_SG_HV3_MAX_SERVED] = 6,
98 [CONF_SG_PS_POLL_TIMEOUT] = 10,
99 [CONF_SG_UPSD_TIMEOUT] = 10,
100 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
101 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
102 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
104 [CONF_AP_BEACON_MISS_TX] = 3,
105 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
106 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
107 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
108 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
109 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
110 /* CTS Diluting params */
111 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
112 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
114 .state = CONF_SG_PROTECTIVE,
117 .rx_msdu_life_time = 512000,
118 .packet_detection_threshold = 0,
119 .ps_poll_timeout = 15,
121 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
122 .rx_cca_threshold = 0,
123 .irq_blk_threshold = 0xFFFF,
124 .irq_pkt_threshold = 0,
126 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
129 .tx_energy_detection = 0,
132 .short_retry_limit = 10,
133 .long_retry_limit = 10,
156 .aifsn = CONF_TX_AIFS_PIFS,
163 .aifsn = CONF_TX_AIFS_PIFS,
167 .max_tx_retries = 100,
168 .ap_aging_period = 300,
172 .queue_id = CONF_TX_AC_BE,
173 .channel_type = CONF_CHANNEL_TYPE_EDCF,
174 .tsid = CONF_TX_AC_BE,
175 .ps_scheme = CONF_PS_SCHEME_LEGACY,
176 .ack_policy = CONF_ACK_POLICY_LEGACY,
180 .queue_id = CONF_TX_AC_BK,
181 .channel_type = CONF_CHANNEL_TYPE_EDCF,
182 .tsid = CONF_TX_AC_BK,
183 .ps_scheme = CONF_PS_SCHEME_LEGACY,
184 .ack_policy = CONF_ACK_POLICY_LEGACY,
188 .queue_id = CONF_TX_AC_VI,
189 .channel_type = CONF_CHANNEL_TYPE_EDCF,
190 .tsid = CONF_TX_AC_VI,
191 .ps_scheme = CONF_PS_SCHEME_LEGACY,
192 .ack_policy = CONF_ACK_POLICY_LEGACY,
196 .queue_id = CONF_TX_AC_VO,
197 .channel_type = CONF_CHANNEL_TYPE_EDCF,
198 .tsid = CONF_TX_AC_VO,
199 .ps_scheme = CONF_PS_SCHEME_LEGACY,
200 .ack_policy = CONF_ACK_POLICY_LEGACY,
204 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
205 .tx_compl_timeout = 700,
206 .tx_compl_threshold = 4,
207 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
208 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
209 .tmpl_short_retry_limit = 10,
210 .tmpl_long_retry_limit = 10,
211 .tx_watchdog_timeout = 5000,
214 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
215 .listen_interval = 1,
216 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
217 .suspend_listen_interval = 3,
218 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
219 .bcn_filt_ie_count = 3,
222 .ie = WLAN_EID_CHANNEL_SWITCH,
223 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
226 .ie = WLAN_EID_HT_OPERATION,
227 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
230 .ie = WLAN_EID_ERP_INFO,
231 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
234 .synch_fail_thold = 12,
235 .bss_lose_timeout = 400,
236 .beacon_rx_timeout = 10000,
237 .broadcast_timeout = 20000,
238 .rx_broadcast_in_ps = 1,
239 .ps_poll_threshold = 10,
240 .bet_enable = CONF_BET_MODE_ENABLE,
241 .bet_max_consecutive = 50,
242 .psm_entry_retries = 8,
243 .psm_exit_retries = 16,
244 .psm_entry_nullfunc_retries = 3,
245 .dynamic_ps_timeout = 1500,
247 .keep_alive_interval = 55000,
248 .max_listen_interval = 20,
249 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
256 .host_clk_settling_time = 5000,
257 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
261 .avg_weight_rssi_beacon = 20,
262 .avg_weight_rssi_data = 10,
263 .avg_weight_snr_beacon = 20,
264 .avg_weight_snr_data = 10,
267 .min_dwell_time_active = 7500,
268 .max_dwell_time_active = 30000,
269 .min_dwell_time_passive = 100000,
270 .max_dwell_time_passive = 100000,
272 .split_scan_timeout = 50000,
276 * Values are in TU/1000 but since sched scan FW command
277 * params are in TUs rounding up may occur.
279 .base_dwell_time = 7500,
280 .max_dwell_time_delta = 22500,
281 /* based on 250bits per probe @1Mbps */
282 .dwell_time_delta_per_probe = 2000,
283 /* based on 250bits per probe @6Mbps (plus a bit more) */
284 .dwell_time_delta_per_probe_5 = 350,
285 .dwell_time_passive = 100000,
286 .dwell_time_dfs = 150000,
288 .rssi_threshold = -90,
293 .tx_ba_win_size = 64,
294 .inactivity_timeout = 10000,
295 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
298 * Memory config for wl127x chips is given in the
299 * wl12xx_default_priv_conf struct. The below configuration is
306 .tx_min_block_num = 40,
308 .min_req_tx_blocks = 45,
309 .min_req_rx_blocks = 22,
315 .n_divider_fref_set_1 = 0xff, /* default */
316 .n_divider_fref_set_2 = 12,
317 .m_divider_fref_set_1 = 0xffff,
318 .m_divider_fref_set_2 = 148, /* default */
319 .coex_pll_stabilization_time = 0xffffffff, /* default */
320 .ldo_stabilization_time = 0xffff, /* default */
321 .fm_disturbed_band_margin = 0xff, /* default */
322 .swallow_clk_diff = 0xff, /* default */
331 .mode = WL12XX_FWLOG_ON_DEMAND,
334 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
335 .output = WL12XX_FWLOG_OUTPUT_HOST,
339 .rate_retry_score = 32000,
344 .inverse_curiosity_factor = 5,
346 .tx_fail_high_th = 10,
347 .per_alpha_shift = 4,
349 .per_beta1_shift = 10,
350 .per_beta2_shift = 8,
352 .rate_check_down = 12,
353 .rate_retry_policy = {
354 0x00, 0x00, 0x00, 0x00, 0x00,
355 0x00, 0x00, 0x00, 0x00, 0x00,
361 .hangover_period = 20,
363 .early_termination_mode = 1,
374 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
376 .tx_per_channel_power_compensation_2 = {
377 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
379 .tx_per_channel_power_compensation_5 = {
380 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
382 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
389 .tx_min_block_num = 40,
391 .min_req_tx_blocks = 100,
392 .min_req_rx_blocks = 22,
398 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
399 #define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
400 #define WL12XX_TX_HW_BLOCK_SIZE 252
402 static const u8 wl12xx_rate_to_idx_2ghz[] = {
403 /* MCS rates are used only with 11n */
404 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
405 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
406 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
407 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
408 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
409 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
410 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
411 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
412 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
414 11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
415 10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
416 9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
417 8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
419 /* TI-specific rate */
420 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
422 7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
423 6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
424 3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
425 5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
426 4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
427 2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
428 1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
429 0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
432 static const u8 wl12xx_rate_to_idx_5ghz[] = {
433 /* MCS rates are used only with 11n */
434 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
435 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
436 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
437 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
438 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
439 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
440 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
441 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
442 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
444 7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
445 6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
446 5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
447 4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
449 /* TI-specific rate */
450 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
452 3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
453 2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
454 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
455 1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
456 0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
457 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
458 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
459 CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
462 static const u8 *wl12xx_band_rate_to_idx[] = {
463 [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
464 [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
467 enum wl12xx_hw_rates {
468 WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
469 WL12XX_CONF_HW_RXTX_RATE_MCS7,
470 WL12XX_CONF_HW_RXTX_RATE_MCS6,
471 WL12XX_CONF_HW_RXTX_RATE_MCS5,
472 WL12XX_CONF_HW_RXTX_RATE_MCS4,
473 WL12XX_CONF_HW_RXTX_RATE_MCS3,
474 WL12XX_CONF_HW_RXTX_RATE_MCS2,
475 WL12XX_CONF_HW_RXTX_RATE_MCS1,
476 WL12XX_CONF_HW_RXTX_RATE_MCS0,
477 WL12XX_CONF_HW_RXTX_RATE_54,
478 WL12XX_CONF_HW_RXTX_RATE_48,
479 WL12XX_CONF_HW_RXTX_RATE_36,
480 WL12XX_CONF_HW_RXTX_RATE_24,
481 WL12XX_CONF_HW_RXTX_RATE_22,
482 WL12XX_CONF_HW_RXTX_RATE_18,
483 WL12XX_CONF_HW_RXTX_RATE_12,
484 WL12XX_CONF_HW_RXTX_RATE_11,
485 WL12XX_CONF_HW_RXTX_RATE_9,
486 WL12XX_CONF_HW_RXTX_RATE_6,
487 WL12XX_CONF_HW_RXTX_RATE_5_5,
488 WL12XX_CONF_HW_RXTX_RATE_2,
489 WL12XX_CONF_HW_RXTX_RATE_1,
490 WL12XX_CONF_HW_RXTX_RATE_MAX,
493 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
500 .start = REGISTERS_BASE,
513 [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
520 .start = REGISTERS_BASE,
539 .start = REGISTERS_BASE,
572 static const int wl12xx_rtable[REG_TABLE_LEN] = {
573 [REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
574 [REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
575 [REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
576 [REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
577 [REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
578 [REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
579 [REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
580 [REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
581 [REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
582 [REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
584 /* data access memory addresses, used with partition translation */
585 [REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
586 [REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
588 /* raw data access memory addresses */
589 [REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
592 /* TODO: maybe move to a new header file? */
593 #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
594 #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
595 #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
597 #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
598 #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
599 #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
601 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
605 if (wl->chip.id != CHIP_ID_1283_PG20) {
606 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
607 struct wl127x_rx_mem_pool_addr rx_mem_addr;
610 * Choose the block we want to read
611 * For aggregated packets, only the first memory block
612 * should be retrieved. The FW takes care of the rest.
614 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
616 rx_mem_addr.addr = (mem_block << 8) +
617 le32_to_cpu(wl_mem_map->packet_memory_pool_start);
619 rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
621 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, &rx_mem_addr,
622 sizeof(rx_mem_addr), false);
630 static int wl12xx_identify_chip(struct wl1271 *wl)
634 switch (wl->chip.id) {
635 case CHIP_ID_1271_PG10:
636 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
639 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
640 WLCORE_QUIRK_DUAL_PROBE_TMPL |
641 WLCORE_QUIRK_TKIP_HEADER_SPACE;
642 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
643 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
644 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
645 sizeof(wl->conf.mem));
647 /* read data preparation is only needed by wl127x */
648 wl->ops->prepare_read = wl127x_prepare_read;
650 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
651 WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
655 case CHIP_ID_1271_PG20:
656 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
659 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
660 WLCORE_QUIRK_DUAL_PROBE_TMPL |
661 WLCORE_QUIRK_TKIP_HEADER_SPACE;
662 wl->plt_fw_name = WL127X_PLT_FW_NAME;
663 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
664 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
665 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
666 sizeof(wl->conf.mem));
668 /* read data preparation is only needed by wl127x */
669 wl->ops->prepare_read = wl127x_prepare_read;
671 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
672 WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
676 case CHIP_ID_1283_PG20:
677 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
679 wl->plt_fw_name = WL128X_PLT_FW_NAME;
680 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
681 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
683 /* wl128x requires TX blocksize alignment */
684 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
685 WLCORE_QUIRK_DUAL_PROBE_TMPL |
686 WLCORE_QUIRK_TKIP_HEADER_SPACE;
688 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER, WL128X_IFTYPE_VER,
689 WL128X_MAJOR_VER, WL128X_SUBTYPE_VER,
692 case CHIP_ID_1283_PG10:
694 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
703 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
708 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
709 addr = (addr >> 1) + 0x30000;
710 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
714 /* write value to OCP_POR_WDATA */
715 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
719 /* write 1 to OCP_CMD */
720 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
728 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
732 int timeout = OCP_CMD_LOOP;
735 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
736 addr = (addr >> 1) + 0x30000;
737 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
741 /* write 2 to OCP_CMD */
742 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
746 /* poll for data ready */
748 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
751 } while (!(val & OCP_READY_MASK) && --timeout);
754 wl1271_warning("Top register access timed out.");
758 /* check data status and return if OK */
759 if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
760 wl1271_warning("Top register access returned error.");
770 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
775 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
776 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
780 if (spare_reg == 0xFFFF)
782 spare_reg |= (BIT(3) | BIT(5) | BIT(6));
783 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
787 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
788 ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
789 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
793 /* Delay execution for 15msec, to let the HW settle */
799 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
804 ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
808 if (tcxo_detection & TCXO_DET_FAILED)
814 static bool wl128x_is_fref_valid(struct wl1271 *wl)
819 ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
823 if (fref_detection & FREF_CLK_DETECT_FAIL)
829 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
833 ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
837 ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
841 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
842 MCS_PLL_CONFIG_REG_VAL);
848 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
853 struct wl12xx_priv *priv = wl->priv;
856 /* Mask bits [3:1] in the sys_clk_cfg register */
857 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
861 if (spare_reg == 0xFFFF)
864 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
868 /* Handle special cases of the TCXO clock */
869 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
870 priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
871 return wl128x_manually_configure_mcs_pll(wl);
873 /* Set the input frequency according to the selected clock source */
874 input_freq = (clk & 1) + 1;
876 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
880 if (pll_config == 0xFFFF)
882 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
883 pll_config |= MCS_PLL_ENABLE_HP;
884 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
890 * WL128x has two clocks input - TCXO and FREF.
891 * TCXO is the main clock of the device, while FREF is used to sync
892 * between the GPS and the cellular modem.
893 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
894 * as the WLAN/BT main clock.
896 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
898 struct wl12xx_priv *priv = wl->priv;
902 /* For XTAL-only modes, FREF will be used after switching from TCXO */
903 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
904 priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
905 if (!wl128x_switch_tcxo_to_fref(wl))
910 /* Query the HW, to determine which clock source we should use */
911 ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
915 if (sys_clk_cfg == 0xFFFF)
917 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
920 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
921 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
922 priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
923 if (!wl128x_switch_tcxo_to_fref(wl))
928 /* TCXO clock is selected */
929 if (!wl128x_is_tcxo_valid(wl))
931 *selected_clock = priv->tcxo_clock;
935 /* FREF clock is selected */
936 if (!wl128x_is_fref_valid(wl))
938 *selected_clock = priv->ref_clock;
941 return wl128x_configure_mcs_pll(wl, *selected_clock);
944 static int wl127x_boot_clk(struct wl1271 *wl)
946 struct wl12xx_priv *priv = wl->priv;
951 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
952 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
954 if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
955 priv->ref_clock == CONF_REF_CLK_38_4_E ||
956 priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
957 /* ref clk: 19.2/38.4/38.4-XTAL */
959 else if (priv->ref_clock == CONF_REF_CLK_26_E ||
960 priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
961 priv->ref_clock == CONF_REF_CLK_52_E)
967 if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
969 /* Set clock type (open drain) */
970 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
974 val &= FREF_CLK_TYPE_BITS;
975 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
979 /* Set clock pull mode (no pull) */
980 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
985 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
990 /* Set clock polarity */
991 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
995 val &= FREF_CLK_POLARITY_BITS;
996 val |= CLK_REQ_OUTN_SEL;
997 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1002 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1006 ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1010 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1012 pause &= ~(WU_COUNTER_PAUSE_VAL);
1013 pause |= WU_COUNTER_PAUSE_VAL;
1014 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1020 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1022 unsigned long timeout;
1026 /* perform soft reset */
1027 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1031 /* SOFT_RESET is self clearing */
1032 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1034 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1038 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1039 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1042 if (time_after(jiffies, timeout)) {
1043 /* 1.2 check pWhalBus->uSelfClearTime if the
1044 * timeout was reached */
1045 wl1271_error("soft reset timeout");
1049 udelay(SOFT_RESET_STALL_TIME);
1053 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1057 /* disable auto calibration on start*/
1058 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1064 static int wl12xx_pre_boot(struct wl1271 *wl)
1066 struct wl12xx_priv *priv = wl->priv;
1069 int selected_clock = -1;
1071 if (wl->chip.id == CHIP_ID_1283_PG20) {
1072 ret = wl128x_boot_clk(wl, &selected_clock);
1076 ret = wl127x_boot_clk(wl);
1081 /* Continue the ELP wake up sequence */
1082 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1088 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1092 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1093 to be used by DRPw FW. The RTRIM value will be added by the FW
1094 before taking DRPw out of reset */
1096 ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1100 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1102 if (wl->chip.id == CHIP_ID_1283_PG20)
1103 clk |= ((selected_clock & 0x3) << 1) << 4;
1105 clk |= (priv->ref_clock << 1) << 4;
1107 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1111 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1115 /* Disable interrupts */
1116 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1120 ret = wl1271_boot_soft_reset(wl);
1128 static int wl12xx_pre_upload(struct wl1271 *wl)
1134 /* write firmware's last address (ie. it's length) to
1135 * ACX_EEPROMLESS_IND_REG */
1136 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1138 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1142 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1146 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1148 /* 6. read the EEPROM parameters */
1149 ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1153 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1156 if (wl->chip.id == CHIP_ID_1283_PG20) {
1157 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1162 /* polarity must be set before the firmware is loaded */
1163 ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1167 /* We use HIGH polarity, so unset the LOW bit */
1168 polarity &= ~POLARITY_LOW;
1169 ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1175 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1179 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1180 WL12XX_ACX_ALL_EVENTS_VECTOR);
1184 wlcore_enable_interrupts(wl);
1185 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1186 WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1190 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1196 static int wl12xx_boot(struct wl1271 *wl)
1200 ret = wl12xx_pre_boot(wl);
1204 ret = wlcore_boot_upload_nvs(wl);
1208 ret = wl12xx_pre_upload(wl);
1212 ret = wlcore_boot_upload_firmware(wl);
1216 ret = wlcore_boot_run_firmware(wl);
1220 ret = wl12xx_enable_interrupts(wl);
1226 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1227 void *buf, size_t len)
1231 ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1235 ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1240 static int wl12xx_ack_event(struct wl1271 *wl)
1242 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1243 WL12XX_INTR_TRIG_EVENT_ACK);
1246 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1248 u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1249 u32 align_len = wlcore_calc_packet_alignment(wl, len);
1251 return (align_len + blk_size - 1) / blk_size + spare_blks;
1255 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1256 u32 blks, u32 spare_blks)
1258 if (wl->chip.id == CHIP_ID_1283_PG20) {
1259 desc->wl128x_mem.total_mem_blocks = blks;
1261 desc->wl127x_mem.extra_blocks = spare_blks;
1262 desc->wl127x_mem.total_mem_blocks = blks;
1267 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1268 struct sk_buff *skb)
1270 u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1272 if (wl->chip.id == CHIP_ID_1283_PG20) {
1273 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1274 desc->length = cpu_to_le16(aligned_len >> 2);
1276 wl1271_debug(DEBUG_TX,
1277 "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1279 le16_to_cpu(desc->length),
1280 le16_to_cpu(desc->life_time),
1281 desc->wl128x_mem.total_mem_blocks,
1282 desc->wl128x_mem.extra_bytes);
1284 /* calculate number of padding bytes */
1285 int pad = aligned_len - skb->len;
1287 cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1289 /* Store the aligned length in terms of words */
1290 desc->length = cpu_to_le16(aligned_len >> 2);
1292 wl1271_debug(DEBUG_TX,
1293 "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1295 le16_to_cpu(desc->length),
1296 le16_to_cpu(desc->life_time),
1297 desc->wl127x_mem.total_mem_blocks);
1301 static enum wl_rx_buf_align
1302 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1304 if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1305 return WLCORE_RX_BUF_UNALIGNED;
1307 return WLCORE_RX_BUF_ALIGNED;
1310 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1313 struct wl1271_rx_descriptor *desc = rx_data;
1315 /* invalid packet */
1316 if (data_len < sizeof(*desc) ||
1317 data_len < sizeof(*desc) + desc->pad_len)
1320 return data_len - sizeof(*desc) - desc->pad_len;
1323 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1325 if (wl->fw_status_1->tx_results_counter ==
1326 (wl->tx_results_count & 0xff))
1329 return wlcore_tx_complete(wl);
1332 static int wl12xx_hw_init(struct wl1271 *wl)
1336 if (wl->chip.id == CHIP_ID_1283_PG20) {
1337 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1339 ret = wl128x_cmd_general_parms(wl);
1344 * If we are in calibrator based auto detect then we got the FEM nr
1345 * in wl->fem_manuf. No need to continue further
1347 if (wl->plt_mode == PLT_FEM_DETECT)
1350 ret = wl128x_cmd_radio_parms(wl);
1354 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1355 /* Enable SDIO padding */
1356 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1358 /* Must be before wl1271_acx_init_mem_config() */
1359 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1363 ret = wl1271_cmd_general_parms(wl);
1368 * If we are in calibrator based auto detect then we got the FEM nr
1369 * in wl->fem_manuf. No need to continue further
1371 if (wl->plt_mode == PLT_FEM_DETECT)
1374 ret = wl1271_cmd_radio_parms(wl);
1377 ret = wl1271_cmd_ext_radio_parms(wl);
1385 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1386 struct wl12xx_vif *wlvif)
1388 return wlvif->rate_set;
1391 static int wl12xx_identify_fw(struct wl1271 *wl)
1393 unsigned int *fw_ver = wl->chip.fw_ver;
1395 /* Only new station firmwares support routing fw logs to the host */
1396 if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
1397 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
1398 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1400 /* This feature is not yet supported for AP mode */
1401 if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
1402 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1407 static void wl12xx_conf_init(struct wl1271 *wl)
1409 struct wl12xx_priv *priv = wl->priv;
1411 /* apply driver default configuration */
1412 memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1414 /* apply default private configuration */
1415 memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1418 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1420 bool supported = false;
1423 if (wl->chip.id == CHIP_ID_1283_PG20) {
1424 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1425 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1427 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1428 if (major > 2 || (major == 2 && minor >= 1))
1431 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1432 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1434 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1435 if (major == 3 && minor >= 1)
1439 wl1271_debug(DEBUG_PROBE,
1440 "PG Ver major = %d minor = %d, MAC %s present",
1441 major, minor, supported ? "is" : "is not");
1446 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1451 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1455 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1459 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1463 /* these are the two parts of the BD_ADDR */
1464 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1465 ((mac1 & 0xff000000) >> 24);
1466 wl->fuse_nic_addr = mac1 & 0xffffff;
1468 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1474 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1479 if (wl->chip.id == CHIP_ID_1283_PG20)
1480 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1483 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1486 if (ret >= 0 && ver)
1487 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1492 static int wl12xx_get_mac(struct wl1271 *wl)
1494 if (wl12xx_mac_in_fuse(wl))
1495 return wl12xx_get_fuse_mac(wl);
1500 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1501 struct wl1271_tx_hw_descr *desc,
1502 struct sk_buff *skb)
1504 desc->wl12xx_reserved = 0;
1507 static int wl12xx_plt_init(struct wl1271 *wl)
1511 ret = wl->ops->boot(wl);
1515 ret = wl->ops->hw_init(wl);
1517 goto out_irq_disable;
1520 * If we are in calibrator based auto detect then we got the FEM nr
1521 * in wl->fem_manuf. No need to continue further
1523 if (wl->plt_mode == PLT_FEM_DETECT)
1526 ret = wl1271_acx_init_mem_config(wl);
1528 goto out_irq_disable;
1530 ret = wl12xx_acx_mem_cfg(wl);
1532 goto out_free_memmap;
1534 /* Enable data path */
1535 ret = wl1271_cmd_data_path(wl, 1);
1537 goto out_free_memmap;
1539 /* Configure for CAM power saving (ie. always active) */
1540 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1542 goto out_free_memmap;
1545 ret = wl1271_acx_pm_config(wl);
1547 goto out_free_memmap;
1552 kfree(wl->target_mem_map);
1553 wl->target_mem_map = NULL;
1556 mutex_unlock(&wl->mutex);
1557 /* Unlocking the mutex in the middle of handling is
1558 inherently unsafe. In this case we deem it safe to do,
1559 because we need to let any possibly pending IRQ out of
1560 the system (and while we are WL1271_STATE_OFF the IRQ
1561 work function will not do anything.) Also, any other
1562 possible concurrent operations will fail due to the
1563 current state, hence the wl1271 struct should be safe. */
1564 wlcore_disable_interrupts(wl);
1565 mutex_lock(&wl->mutex);
1570 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1573 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1575 return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1578 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1579 struct ieee80211_vif *vif,
1580 struct ieee80211_sta *sta,
1581 struct ieee80211_key_conf *key_conf)
1583 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1586 static struct wlcore_ops wl12xx_ops = {
1587 .identify_chip = wl12xx_identify_chip,
1588 .identify_fw = wl12xx_identify_fw,
1589 .boot = wl12xx_boot,
1590 .plt_init = wl12xx_plt_init,
1591 .trigger_cmd = wl12xx_trigger_cmd,
1592 .ack_event = wl12xx_ack_event,
1593 .calc_tx_blocks = wl12xx_calc_tx_blocks,
1594 .set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
1595 .set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
1596 .get_rx_buf_align = wl12xx_get_rx_buf_align,
1597 .get_rx_packet_len = wl12xx_get_rx_packet_len,
1598 .tx_immediate_compl = NULL,
1599 .tx_delayed_compl = wl12xx_tx_delayed_compl,
1600 .hw_init = wl12xx_hw_init,
1602 .sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
1603 .get_pg_ver = wl12xx_get_pg_ver,
1604 .get_mac = wl12xx_get_mac,
1605 .set_tx_desc_csum = wl12xx_set_tx_desc_csum,
1606 .set_rx_csum = NULL,
1607 .ap_get_mimo_wide_rate_mask = NULL,
1608 .debugfs_init = wl12xx_debugfs_add_files,
1609 .get_spare_blocks = wl12xx_get_spare_blocks,
1610 .set_key = wl12xx_set_key,
1611 .pre_pkt_send = NULL,
1614 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1615 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1616 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1617 .ht_supported = true,
1618 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1619 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1621 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1622 .rx_highest = cpu_to_le16(72),
1623 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1627 static int __devinit wl12xx_probe(struct platform_device *pdev)
1629 struct wl12xx_platform_data *pdata = pdev->dev.platform_data;
1631 struct ieee80211_hw *hw;
1632 struct wl12xx_priv *priv;
1634 hw = wlcore_alloc_hw(sizeof(*priv));
1636 wl1271_error("can't allocate hw");
1642 wl->ops = &wl12xx_ops;
1643 wl->ptable = wl12xx_ptable;
1644 wl->rtable = wl12xx_rtable;
1645 wl->num_tx_desc = 16;
1646 wl->num_rx_desc = 8;
1647 wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1648 wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1649 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1650 wl->fw_status_priv_len = 0;
1651 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1652 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1653 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1654 wl12xx_conf_init(wl);
1657 priv->ref_clock = pdata->board_ref_clock;
1659 if (!strcmp(fref_param, "19.2"))
1660 priv->ref_clock = WL12XX_REFCLOCK_19;
1661 else if (!strcmp(fref_param, "26"))
1662 priv->ref_clock = WL12XX_REFCLOCK_26;
1663 else if (!strcmp(fref_param, "26x"))
1664 priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1665 else if (!strcmp(fref_param, "38.4"))
1666 priv->ref_clock = WL12XX_REFCLOCK_38;
1667 else if (!strcmp(fref_param, "38.4x"))
1668 priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1669 else if (!strcmp(fref_param, "52"))
1670 priv->ref_clock = WL12XX_REFCLOCK_52;
1672 wl1271_error("Invalid fref parameter %s", fref_param);
1676 priv->tcxo_clock = pdata->board_tcxo_clock;
1678 if (!strcmp(tcxo_param, "19.2"))
1679 priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1680 else if (!strcmp(tcxo_param, "26"))
1681 priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1682 else if (!strcmp(tcxo_param, "38.4"))
1683 priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1684 else if (!strcmp(tcxo_param, "52"))
1685 priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1686 else if (!strcmp(tcxo_param, "16.368"))
1687 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1688 else if (!strcmp(tcxo_param, "32.736"))
1689 priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1690 else if (!strcmp(tcxo_param, "16.8"))
1691 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1692 else if (!strcmp(tcxo_param, "33.6"))
1693 priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1695 wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1698 return wlcore_probe(wl, pdev);
1701 static const struct platform_device_id wl12xx_id_table[] __devinitconst = {
1703 { } /* Terminating Entry */
1705 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1707 static struct platform_driver wl12xx_driver = {
1708 .probe = wl12xx_probe,
1709 .remove = __devexit_p(wlcore_remove),
1710 .id_table = wl12xx_id_table,
1712 .name = "wl12xx_driver",
1713 .owner = THIS_MODULE,
1717 static int __init wl12xx_init(void)
1719 return platform_driver_register(&wl12xx_driver);
1721 module_init(wl12xx_init);
1723 static void __exit wl12xx_exit(void)
1725 platform_driver_unregister(&wl12xx_driver);
1727 module_exit(wl12xx_exit);
1729 module_param_named(fref, fref_param, charp, 0);
1730 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1732 module_param_named(tcxo, tcxo_param, charp, 0);
1733 MODULE_PARM_DESC(tcxo,
1734 "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1736 MODULE_LICENSE("GPL v2");
1737 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1738 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1739 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1740 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1741 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1742 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1743 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);