2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
25 #include <linux/err.h>
27 #include <linux/wl12xx.h>
29 #include "../wlcore/wlcore.h"
30 #include "../wlcore/debug.h"
31 #include "../wlcore/io.h"
32 #include "../wlcore/acx.h"
33 #include "../wlcore/tx.h"
34 #include "../wlcore/rx.h"
35 #include "../wlcore/boot.h"
45 static char *fref_param;
46 static char *tcxo_param;
48 static struct wlcore_conf wl12xx_conf = {
51 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
52 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
53 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
54 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
55 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
56 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
57 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
58 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
59 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
60 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
61 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
62 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
63 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
64 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
65 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
66 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
67 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
68 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
69 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
70 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
71 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
72 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
73 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
74 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
75 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
76 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
77 /* active scan params */
78 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
79 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
80 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
81 /* passive scan params */
82 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
83 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
84 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
85 /* passive scan in dual antenna params */
86 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
87 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
88 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
90 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
91 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
92 [CONF_SG_BEACON_MISS_PERCENT] = 60,
93 [CONF_SG_DHCP_TIME] = 5000,
96 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
97 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
98 [CONF_SG_HV3_MAX_SERVED] = 6,
99 [CONF_SG_PS_POLL_TIMEOUT] = 10,
100 [CONF_SG_UPSD_TIMEOUT] = 10,
101 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
102 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
103 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
105 [CONF_AP_BEACON_MISS_TX] = 3,
106 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
107 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
108 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
109 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
110 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
111 /* CTS Diluting params */
112 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
113 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
115 .state = CONF_SG_PROTECTIVE,
118 .rx_msdu_life_time = 512000,
119 .packet_detection_threshold = 0,
120 .ps_poll_timeout = 15,
122 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
123 .rx_cca_threshold = 0,
124 .irq_blk_threshold = 0xFFFF,
125 .irq_pkt_threshold = 0,
127 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
130 .tx_energy_detection = 0,
133 .short_retry_limit = 10,
134 .long_retry_limit = 10,
157 .aifsn = CONF_TX_AIFS_PIFS,
164 .aifsn = CONF_TX_AIFS_PIFS,
168 .max_tx_retries = 100,
169 .ap_aging_period = 300,
173 .queue_id = CONF_TX_AC_BE,
174 .channel_type = CONF_CHANNEL_TYPE_EDCF,
175 .tsid = CONF_TX_AC_BE,
176 .ps_scheme = CONF_PS_SCHEME_LEGACY,
177 .ack_policy = CONF_ACK_POLICY_LEGACY,
181 .queue_id = CONF_TX_AC_BK,
182 .channel_type = CONF_CHANNEL_TYPE_EDCF,
183 .tsid = CONF_TX_AC_BK,
184 .ps_scheme = CONF_PS_SCHEME_LEGACY,
185 .ack_policy = CONF_ACK_POLICY_LEGACY,
189 .queue_id = CONF_TX_AC_VI,
190 .channel_type = CONF_CHANNEL_TYPE_EDCF,
191 .tsid = CONF_TX_AC_VI,
192 .ps_scheme = CONF_PS_SCHEME_LEGACY,
193 .ack_policy = CONF_ACK_POLICY_LEGACY,
197 .queue_id = CONF_TX_AC_VO,
198 .channel_type = CONF_CHANNEL_TYPE_EDCF,
199 .tsid = CONF_TX_AC_VO,
200 .ps_scheme = CONF_PS_SCHEME_LEGACY,
201 .ack_policy = CONF_ACK_POLICY_LEGACY,
205 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
206 .tx_compl_timeout = 700,
207 .tx_compl_threshold = 4,
208 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
209 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
210 .tmpl_short_retry_limit = 10,
211 .tmpl_long_retry_limit = 10,
212 .tx_watchdog_timeout = 5000,
213 .slow_link_thold = 3,
214 .fast_link_thold = 10,
217 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
218 .listen_interval = 1,
219 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
220 .suspend_listen_interval = 3,
221 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
222 .bcn_filt_ie_count = 3,
225 .ie = WLAN_EID_CHANNEL_SWITCH,
226 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
229 .ie = WLAN_EID_HT_OPERATION,
230 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
233 .ie = WLAN_EID_ERP_INFO,
234 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
237 .synch_fail_thold = 12,
238 .bss_lose_timeout = 400,
239 .beacon_rx_timeout = 10000,
240 .broadcast_timeout = 20000,
241 .rx_broadcast_in_ps = 1,
242 .ps_poll_threshold = 10,
243 .bet_enable = CONF_BET_MODE_ENABLE,
244 .bet_max_consecutive = 50,
245 .psm_entry_retries = 8,
246 .psm_exit_retries = 16,
247 .psm_entry_nullfunc_retries = 3,
248 .dynamic_ps_timeout = 1500,
250 .keep_alive_interval = 55000,
251 .max_listen_interval = 20,
252 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
259 .host_clk_settling_time = 5000,
260 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
264 .avg_weight_rssi_beacon = 20,
265 .avg_weight_rssi_data = 10,
266 .avg_weight_snr_beacon = 20,
267 .avg_weight_snr_data = 10,
270 .min_dwell_time_active = 7500,
271 .max_dwell_time_active = 30000,
272 .min_dwell_time_active_long = 25000,
273 .max_dwell_time_active_long = 50000,
274 .dwell_time_passive = 100000,
275 .dwell_time_dfs = 150000,
277 .split_scan_timeout = 50000,
281 * Values are in TU/1000 but since sched scan FW command
282 * params are in TUs rounding up may occur.
284 .base_dwell_time = 7500,
285 .max_dwell_time_delta = 22500,
286 /* based on 250bits per probe @1Mbps */
287 .dwell_time_delta_per_probe = 2000,
288 /* based on 250bits per probe @6Mbps (plus a bit more) */
289 .dwell_time_delta_per_probe_5 = 350,
290 .dwell_time_passive = 100000,
291 .dwell_time_dfs = 150000,
293 .rssi_threshold = -90,
298 .tx_ba_win_size = 64,
299 .inactivity_timeout = 10000,
300 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
303 * Memory config for wl127x chips is given in the
304 * wl12xx_default_priv_conf struct. The below configuration is
311 .tx_min_block_num = 40,
313 .min_req_tx_blocks = 45,
314 .min_req_rx_blocks = 22,
320 .n_divider_fref_set_1 = 0xff, /* default */
321 .n_divider_fref_set_2 = 12,
322 .m_divider_fref_set_1 = 0xffff,
323 .m_divider_fref_set_2 = 148, /* default */
324 .coex_pll_stabilization_time = 0xffffffff, /* default */
325 .ldo_stabilization_time = 0xffff, /* default */
326 .fm_disturbed_band_margin = 0xff, /* default */
327 .swallow_clk_diff = 0xff, /* default */
336 .mode = WL12XX_FWLOG_ON_DEMAND,
339 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
340 .output = WL12XX_FWLOG_OUTPUT_HOST,
344 .rate_retry_score = 32000,
349 .inverse_curiosity_factor = 5,
351 .tx_fail_high_th = 10,
352 .per_alpha_shift = 4,
354 .per_beta1_shift = 10,
355 .per_beta2_shift = 8,
357 .rate_check_down = 12,
358 .rate_retry_policy = {
359 0x00, 0x00, 0x00, 0x00, 0x00,
360 0x00, 0x00, 0x00, 0x00, 0x00,
366 .hangover_period = 20,
368 .early_termination_mode = 1,
378 .bug_on_recovery = 0,
383 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
385 .tx_per_channel_power_compensation_2 = {
386 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
388 .tx_per_channel_power_compensation_5 = {
389 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
390 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
391 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
398 .tx_min_block_num = 40,
400 .min_req_tx_blocks = 100,
401 .min_req_rx_blocks = 22,
407 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
408 #define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
409 #define WL12XX_TX_HW_BLOCK_SIZE 252
411 static const u8 wl12xx_rate_to_idx_2ghz[] = {
412 /* MCS rates are used only with 11n */
413 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
414 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
415 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
416 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
417 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
418 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
419 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
420 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
421 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
423 11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
424 10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
425 9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
426 8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
428 /* TI-specific rate */
429 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
431 7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
432 6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
433 3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
434 5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
435 4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
436 2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
437 1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
438 0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
441 static const u8 wl12xx_rate_to_idx_5ghz[] = {
442 /* MCS rates are used only with 11n */
443 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
444 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
445 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
446 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
447 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
448 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
449 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
450 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
451 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
453 7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
454 6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
455 5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
456 4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
458 /* TI-specific rate */
459 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
461 3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
462 2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
463 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
464 1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
465 0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
466 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
467 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
468 CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
471 static const u8 *wl12xx_band_rate_to_idx[] = {
472 [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
473 [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
476 enum wl12xx_hw_rates {
477 WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
478 WL12XX_CONF_HW_RXTX_RATE_MCS7,
479 WL12XX_CONF_HW_RXTX_RATE_MCS6,
480 WL12XX_CONF_HW_RXTX_RATE_MCS5,
481 WL12XX_CONF_HW_RXTX_RATE_MCS4,
482 WL12XX_CONF_HW_RXTX_RATE_MCS3,
483 WL12XX_CONF_HW_RXTX_RATE_MCS2,
484 WL12XX_CONF_HW_RXTX_RATE_MCS1,
485 WL12XX_CONF_HW_RXTX_RATE_MCS0,
486 WL12XX_CONF_HW_RXTX_RATE_54,
487 WL12XX_CONF_HW_RXTX_RATE_48,
488 WL12XX_CONF_HW_RXTX_RATE_36,
489 WL12XX_CONF_HW_RXTX_RATE_24,
490 WL12XX_CONF_HW_RXTX_RATE_22,
491 WL12XX_CONF_HW_RXTX_RATE_18,
492 WL12XX_CONF_HW_RXTX_RATE_12,
493 WL12XX_CONF_HW_RXTX_RATE_11,
494 WL12XX_CONF_HW_RXTX_RATE_9,
495 WL12XX_CONF_HW_RXTX_RATE_6,
496 WL12XX_CONF_HW_RXTX_RATE_5_5,
497 WL12XX_CONF_HW_RXTX_RATE_2,
498 WL12XX_CONF_HW_RXTX_RATE_1,
499 WL12XX_CONF_HW_RXTX_RATE_MAX,
502 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
509 .start = REGISTERS_BASE,
522 [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
529 .start = REGISTERS_BASE,
548 .start = REGISTERS_BASE,
581 static const int wl12xx_rtable[REG_TABLE_LEN] = {
582 [REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
583 [REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
584 [REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
585 [REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
586 [REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
587 [REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
588 [REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
589 [REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
590 [REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
591 [REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
593 /* data access memory addresses, used with partition translation */
594 [REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
595 [REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
597 /* raw data access memory addresses */
598 [REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
601 /* TODO: maybe move to a new header file? */
602 #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
603 #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
604 #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
606 #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
607 #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
608 #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
610 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
614 if (wl->chip.id != CHIP_ID_128X_PG20) {
615 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
616 struct wl12xx_priv *priv = wl->priv;
619 * Choose the block we want to read
620 * For aggregated packets, only the first memory block
621 * should be retrieved. The FW takes care of the rest.
623 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
625 priv->rx_mem_addr->addr = (mem_block << 8) +
626 le32_to_cpu(wl_mem_map->packet_memory_pool_start);
628 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4;
630 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
631 sizeof(*priv->rx_mem_addr), false);
639 static int wl12xx_identify_chip(struct wl1271 *wl)
643 switch (wl->chip.id) {
644 case CHIP_ID_127X_PG10:
645 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
648 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
649 WLCORE_QUIRK_DUAL_PROBE_TMPL |
650 WLCORE_QUIRK_TKIP_HEADER_SPACE |
651 WLCORE_QUIRK_START_STA_FAILS |
652 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
653 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
654 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
655 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
656 sizeof(wl->conf.mem));
658 /* read data preparation is only needed by wl127x */
659 wl->ops->prepare_read = wl127x_prepare_read;
661 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
662 WL127X_IFTYPE_SR_VER, WL127X_MAJOR_SR_VER,
663 WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
664 WL127X_IFTYPE_MR_VER, WL127X_MAJOR_MR_VER,
665 WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
668 case CHIP_ID_127X_PG20:
669 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
672 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
673 WLCORE_QUIRK_DUAL_PROBE_TMPL |
674 WLCORE_QUIRK_TKIP_HEADER_SPACE |
675 WLCORE_QUIRK_START_STA_FAILS |
676 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
677 wl->plt_fw_name = WL127X_PLT_FW_NAME;
678 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
679 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
680 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
681 sizeof(wl->conf.mem));
683 /* read data preparation is only needed by wl127x */
684 wl->ops->prepare_read = wl127x_prepare_read;
686 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
687 WL127X_IFTYPE_SR_VER, WL127X_MAJOR_SR_VER,
688 WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
689 WL127X_IFTYPE_MR_VER, WL127X_MAJOR_MR_VER,
690 WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
693 case CHIP_ID_128X_PG20:
694 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
696 wl->plt_fw_name = WL128X_PLT_FW_NAME;
697 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
698 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
700 /* wl128x requires TX blocksize alignment */
701 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
702 WLCORE_QUIRK_DUAL_PROBE_TMPL |
703 WLCORE_QUIRK_TKIP_HEADER_SPACE |
704 WLCORE_QUIRK_START_STA_FAILS |
705 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
707 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
708 WL128X_IFTYPE_SR_VER, WL128X_MAJOR_SR_VER,
709 WL128X_SUBTYPE_SR_VER, WL128X_MINOR_SR_VER,
710 WL128X_IFTYPE_MR_VER, WL128X_MAJOR_MR_VER,
711 WL128X_SUBTYPE_MR_VER, WL128X_MINOR_MR_VER);
713 case CHIP_ID_128X_PG10:
715 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
720 /* common settings */
721 wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
722 wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
723 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
724 wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
725 wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
730 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
735 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
736 addr = (addr >> 1) + 0x30000;
737 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
741 /* write value to OCP_POR_WDATA */
742 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
746 /* write 1 to OCP_CMD */
747 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
755 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
759 int timeout = OCP_CMD_LOOP;
762 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
763 addr = (addr >> 1) + 0x30000;
764 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
768 /* write 2 to OCP_CMD */
769 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
773 /* poll for data ready */
775 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
778 } while (!(val & OCP_READY_MASK) && --timeout);
781 wl1271_warning("Top register access timed out.");
785 /* check data status and return if OK */
786 if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
787 wl1271_warning("Top register access returned error.");
797 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
802 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
803 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
807 if (spare_reg == 0xFFFF)
809 spare_reg |= (BIT(3) | BIT(5) | BIT(6));
810 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
814 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
815 ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
816 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
820 /* Delay execution for 15msec, to let the HW settle */
826 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
831 ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
835 if (tcxo_detection & TCXO_DET_FAILED)
841 static bool wl128x_is_fref_valid(struct wl1271 *wl)
846 ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
850 if (fref_detection & FREF_CLK_DETECT_FAIL)
856 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
860 ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
864 ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
868 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
869 MCS_PLL_CONFIG_REG_VAL);
875 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
880 struct wl12xx_priv *priv = wl->priv;
883 /* Mask bits [3:1] in the sys_clk_cfg register */
884 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
888 if (spare_reg == 0xFFFF)
891 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
895 /* Handle special cases of the TCXO clock */
896 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
897 priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
898 return wl128x_manually_configure_mcs_pll(wl);
900 /* Set the input frequency according to the selected clock source */
901 input_freq = (clk & 1) + 1;
903 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
907 if (pll_config == 0xFFFF)
909 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
910 pll_config |= MCS_PLL_ENABLE_HP;
911 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
917 * WL128x has two clocks input - TCXO and FREF.
918 * TCXO is the main clock of the device, while FREF is used to sync
919 * between the GPS and the cellular modem.
920 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
921 * as the WLAN/BT main clock.
923 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
925 struct wl12xx_priv *priv = wl->priv;
929 /* For XTAL-only modes, FREF will be used after switching from TCXO */
930 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
931 priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
932 if (!wl128x_switch_tcxo_to_fref(wl))
937 /* Query the HW, to determine which clock source we should use */
938 ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
942 if (sys_clk_cfg == 0xFFFF)
944 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
947 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
948 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
949 priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
950 if (!wl128x_switch_tcxo_to_fref(wl))
955 /* TCXO clock is selected */
956 if (!wl128x_is_tcxo_valid(wl))
958 *selected_clock = priv->tcxo_clock;
962 /* FREF clock is selected */
963 if (!wl128x_is_fref_valid(wl))
965 *selected_clock = priv->ref_clock;
968 return wl128x_configure_mcs_pll(wl, *selected_clock);
971 static int wl127x_boot_clk(struct wl1271 *wl)
973 struct wl12xx_priv *priv = wl->priv;
978 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
979 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
981 if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
982 priv->ref_clock == CONF_REF_CLK_38_4_E ||
983 priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
984 /* ref clk: 19.2/38.4/38.4-XTAL */
986 else if (priv->ref_clock == CONF_REF_CLK_26_E ||
987 priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
988 priv->ref_clock == CONF_REF_CLK_52_E)
994 if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
996 /* Set clock type (open drain) */
997 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
1001 val &= FREF_CLK_TYPE_BITS;
1002 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
1006 /* Set clock pull mode (no pull) */
1007 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
1012 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1017 /* Set clock polarity */
1018 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1022 val &= FREF_CLK_POLARITY_BITS;
1023 val |= CLK_REQ_OUTN_SEL;
1024 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1029 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1033 ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1037 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1039 pause &= ~(WU_COUNTER_PAUSE_VAL);
1040 pause |= WU_COUNTER_PAUSE_VAL;
1041 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1047 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1049 unsigned long timeout;
1053 /* perform soft reset */
1054 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1058 /* SOFT_RESET is self clearing */
1059 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1061 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1065 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1066 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1069 if (time_after(jiffies, timeout)) {
1070 /* 1.2 check pWhalBus->uSelfClearTime if the
1071 * timeout was reached */
1072 wl1271_error("soft reset timeout");
1076 udelay(SOFT_RESET_STALL_TIME);
1080 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1084 /* disable auto calibration on start*/
1085 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1091 static int wl12xx_pre_boot(struct wl1271 *wl)
1093 struct wl12xx_priv *priv = wl->priv;
1096 int selected_clock = -1;
1098 if (wl->chip.id == CHIP_ID_128X_PG20) {
1099 ret = wl128x_boot_clk(wl, &selected_clock);
1103 ret = wl127x_boot_clk(wl);
1108 /* Continue the ELP wake up sequence */
1109 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1115 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1119 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1120 to be used by DRPw FW. The RTRIM value will be added by the FW
1121 before taking DRPw out of reset */
1123 ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1127 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1129 if (wl->chip.id == CHIP_ID_128X_PG20)
1130 clk |= ((selected_clock & 0x3) << 1) << 4;
1132 clk |= (priv->ref_clock << 1) << 4;
1134 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1138 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1142 /* Disable interrupts */
1143 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1147 ret = wl1271_boot_soft_reset(wl);
1155 static int wl12xx_pre_upload(struct wl1271 *wl)
1161 /* write firmware's last address (ie. it's length) to
1162 * ACX_EEPROMLESS_IND_REG */
1163 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1165 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1169 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1173 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1175 /* 6. read the EEPROM parameters */
1176 ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1180 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1183 if (wl->chip.id == CHIP_ID_128X_PG20) {
1184 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1189 /* polarity must be set before the firmware is loaded */
1190 ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1194 /* We use HIGH polarity, so unset the LOW bit */
1195 polarity &= ~POLARITY_LOW;
1196 ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1202 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1206 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1207 WL12XX_ACX_ALL_EVENTS_VECTOR);
1211 wlcore_enable_interrupts(wl);
1212 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1213 WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1215 goto disable_interrupts;
1217 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1219 goto disable_interrupts;
1224 wlcore_disable_interrupts(wl);
1230 static int wl12xx_boot(struct wl1271 *wl)
1234 ret = wl12xx_pre_boot(wl);
1238 ret = wlcore_boot_upload_nvs(wl);
1242 ret = wl12xx_pre_upload(wl);
1246 ret = wlcore_boot_upload_firmware(wl);
1250 wl->event_mask = BSS_LOSE_EVENT_ID |
1251 REGAINED_BSS_EVENT_ID |
1252 SCAN_COMPLETE_EVENT_ID |
1253 ROLE_STOP_COMPLETE_EVENT_ID |
1254 RSSI_SNR_TRIGGER_0_EVENT_ID |
1255 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
1256 SOFT_GEMINI_SENSE_EVENT_ID |
1257 PERIODIC_SCAN_REPORT_EVENT_ID |
1258 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1259 DUMMY_PACKET_EVENT_ID |
1260 PEER_REMOVE_COMPLETE_EVENT_ID |
1261 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1262 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1263 INACTIVE_STA_EVENT_ID |
1264 MAX_TX_RETRY_EVENT_ID |
1265 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
1267 ret = wlcore_boot_run_firmware(wl);
1271 ret = wl12xx_enable_interrupts(wl);
1277 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1278 void *buf, size_t len)
1282 ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1286 ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1291 static int wl12xx_ack_event(struct wl1271 *wl)
1293 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1294 WL12XX_INTR_TRIG_EVENT_ACK);
1297 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1299 u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1300 u32 align_len = wlcore_calc_packet_alignment(wl, len);
1302 return (align_len + blk_size - 1) / blk_size + spare_blks;
1306 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1307 u32 blks, u32 spare_blks)
1309 if (wl->chip.id == CHIP_ID_128X_PG20) {
1310 desc->wl128x_mem.total_mem_blocks = blks;
1312 desc->wl127x_mem.extra_blocks = spare_blks;
1313 desc->wl127x_mem.total_mem_blocks = blks;
1318 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1319 struct sk_buff *skb)
1321 u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1323 if (wl->chip.id == CHIP_ID_128X_PG20) {
1324 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1325 desc->length = cpu_to_le16(aligned_len >> 2);
1327 wl1271_debug(DEBUG_TX,
1328 "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1330 le16_to_cpu(desc->length),
1331 le16_to_cpu(desc->life_time),
1332 desc->wl128x_mem.total_mem_blocks,
1333 desc->wl128x_mem.extra_bytes);
1335 /* calculate number of padding bytes */
1336 int pad = aligned_len - skb->len;
1338 cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1340 /* Store the aligned length in terms of words */
1341 desc->length = cpu_to_le16(aligned_len >> 2);
1343 wl1271_debug(DEBUG_TX,
1344 "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1346 le16_to_cpu(desc->length),
1347 le16_to_cpu(desc->life_time),
1348 desc->wl127x_mem.total_mem_blocks);
1352 static enum wl_rx_buf_align
1353 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1355 if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1356 return WLCORE_RX_BUF_UNALIGNED;
1358 return WLCORE_RX_BUF_ALIGNED;
1361 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1364 struct wl1271_rx_descriptor *desc = rx_data;
1366 /* invalid packet */
1367 if (data_len < sizeof(*desc) ||
1368 data_len < sizeof(*desc) + desc->pad_len)
1371 return data_len - sizeof(*desc) - desc->pad_len;
1374 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1376 if (wl->fw_status_1->tx_results_counter ==
1377 (wl->tx_results_count & 0xff))
1380 return wlcore_tx_complete(wl);
1383 static int wl12xx_hw_init(struct wl1271 *wl)
1387 if (wl->chip.id == CHIP_ID_128X_PG20) {
1388 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1390 ret = wl128x_cmd_general_parms(wl);
1395 * If we are in calibrator based auto detect then we got the FEM nr
1396 * in wl->fem_manuf. No need to continue further
1398 if (wl->plt_mode == PLT_FEM_DETECT)
1401 ret = wl128x_cmd_radio_parms(wl);
1405 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1406 /* Enable SDIO padding */
1407 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1409 /* Must be before wl1271_acx_init_mem_config() */
1410 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1414 ret = wl1271_cmd_general_parms(wl);
1419 * If we are in calibrator based auto detect then we got the FEM nr
1420 * in wl->fem_manuf. No need to continue further
1422 if (wl->plt_mode == PLT_FEM_DETECT)
1425 ret = wl1271_cmd_radio_parms(wl);
1428 ret = wl1271_cmd_ext_radio_parms(wl);
1436 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1437 struct wl12xx_vif *wlvif)
1439 return wlvif->rate_set;
1442 static void wl12xx_conf_init(struct wl1271 *wl)
1444 struct wl12xx_priv *priv = wl->priv;
1446 /* apply driver default configuration */
1447 memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1449 /* apply default private configuration */
1450 memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1453 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1455 bool supported = false;
1458 if (wl->chip.id == CHIP_ID_128X_PG20) {
1459 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1460 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1462 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1463 if (major > 2 || (major == 2 && minor >= 1))
1466 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1467 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1469 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1470 if (major == 3 && minor >= 1)
1474 wl1271_debug(DEBUG_PROBE,
1475 "PG Ver major = %d minor = %d, MAC %s present",
1476 major, minor, supported ? "is" : "is not");
1481 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1486 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1490 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1494 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1498 /* these are the two parts of the BD_ADDR */
1499 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1500 ((mac1 & 0xff000000) >> 24);
1501 wl->fuse_nic_addr = mac1 & 0xffffff;
1503 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1509 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1514 if (wl->chip.id == CHIP_ID_128X_PG20)
1515 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1518 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1521 if (ret >= 0 && ver)
1522 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1527 static int wl12xx_get_mac(struct wl1271 *wl)
1529 if (wl12xx_mac_in_fuse(wl))
1530 return wl12xx_get_fuse_mac(wl);
1535 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1536 struct wl1271_tx_hw_descr *desc,
1537 struct sk_buff *skb)
1539 desc->wl12xx_reserved = 0;
1542 static int wl12xx_plt_init(struct wl1271 *wl)
1546 ret = wl->ops->boot(wl);
1550 ret = wl->ops->hw_init(wl);
1552 goto out_irq_disable;
1555 * If we are in calibrator based auto detect then we got the FEM nr
1556 * in wl->fem_manuf. No need to continue further
1558 if (wl->plt_mode == PLT_FEM_DETECT)
1561 ret = wl1271_acx_init_mem_config(wl);
1563 goto out_irq_disable;
1565 ret = wl12xx_acx_mem_cfg(wl);
1567 goto out_free_memmap;
1569 /* Enable data path */
1570 ret = wl1271_cmd_data_path(wl, 1);
1572 goto out_free_memmap;
1574 /* Configure for CAM power saving (ie. always active) */
1575 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1577 goto out_free_memmap;
1580 ret = wl1271_acx_pm_config(wl);
1582 goto out_free_memmap;
1587 kfree(wl->target_mem_map);
1588 wl->target_mem_map = NULL;
1591 mutex_unlock(&wl->mutex);
1592 /* Unlocking the mutex in the middle of handling is
1593 inherently unsafe. In this case we deem it safe to do,
1594 because we need to let any possibly pending IRQ out of
1595 the system (and while we are WL1271_STATE_OFF the IRQ
1596 work function will not do anything.) Also, any other
1597 possible concurrent operations will fail due to the
1598 current state, hence the wl1271 struct should be safe. */
1599 wlcore_disable_interrupts(wl);
1600 mutex_lock(&wl->mutex);
1605 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1608 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1610 return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1613 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1614 struct ieee80211_vif *vif,
1615 struct ieee80211_sta *sta,
1616 struct ieee80211_key_conf *key_conf)
1618 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1621 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1622 struct ieee80211_sta_ht_cap *ht_cap,
1623 bool allow_ht_operation,
1624 u32 rate_set, u8 hlid)
1626 return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1630 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1631 struct wl1271_link *lnk)
1635 if (test_bit(hlid, (unsigned long *)&wl->fw_fast_lnk_map))
1636 thold = wl->conf.tx.fast_link_thold;
1638 thold = wl->conf.tx.slow_link_thold;
1640 return lnk->allocated_pkts < thold;
1643 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1644 struct wl1271_link *lnk)
1646 /* any link is good for low priority */
1650 static int wl12xx_setup(struct wl1271 *wl);
1652 static struct wlcore_ops wl12xx_ops = {
1653 .setup = wl12xx_setup,
1654 .identify_chip = wl12xx_identify_chip,
1655 .boot = wl12xx_boot,
1656 .plt_init = wl12xx_plt_init,
1657 .trigger_cmd = wl12xx_trigger_cmd,
1658 .ack_event = wl12xx_ack_event,
1659 .wait_for_event = wl12xx_wait_for_event,
1660 .process_mailbox_events = wl12xx_process_mailbox_events,
1661 .calc_tx_blocks = wl12xx_calc_tx_blocks,
1662 .set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
1663 .set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
1664 .get_rx_buf_align = wl12xx_get_rx_buf_align,
1665 .get_rx_packet_len = wl12xx_get_rx_packet_len,
1666 .tx_immediate_compl = NULL,
1667 .tx_delayed_compl = wl12xx_tx_delayed_compl,
1668 .hw_init = wl12xx_hw_init,
1670 .sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
1671 .get_pg_ver = wl12xx_get_pg_ver,
1672 .get_mac = wl12xx_get_mac,
1673 .set_tx_desc_csum = wl12xx_set_tx_desc_csum,
1674 .set_rx_csum = NULL,
1675 .ap_get_mimo_wide_rate_mask = NULL,
1676 .debugfs_init = wl12xx_debugfs_add_files,
1677 .scan_start = wl12xx_scan_start,
1678 .scan_stop = wl12xx_scan_stop,
1679 .sched_scan_start = wl12xx_sched_scan_start,
1680 .sched_scan_stop = wl12xx_scan_sched_scan_stop,
1681 .get_spare_blocks = wl12xx_get_spare_blocks,
1682 .set_key = wl12xx_set_key,
1683 .channel_switch = wl12xx_cmd_channel_switch,
1684 .pre_pkt_send = NULL,
1685 .set_peer_cap = wl12xx_set_peer_cap,
1686 .lnk_high_prio = wl12xx_lnk_high_prio,
1687 .lnk_low_prio = wl12xx_lnk_low_prio,
1690 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1691 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1692 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1693 .ht_supported = true,
1694 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1695 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1697 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1698 .rx_highest = cpu_to_le16(72),
1699 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1703 static int wl12xx_setup(struct wl1271 *wl)
1705 struct wl12xx_priv *priv = wl->priv;
1706 struct wlcore_platdev_data *pdev_data = wl->pdev->dev.platform_data;
1707 struct wl12xx_platform_data *pdata = pdev_data->pdata;
1709 wl->rtable = wl12xx_rtable;
1710 wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1711 wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1712 wl->num_channels = 1;
1713 wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1714 wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1715 wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1716 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1717 wl->fw_status_priv_len = 0;
1718 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1719 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1720 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1721 wl12xx_conf_init(wl);
1724 priv->ref_clock = pdata->board_ref_clock;
1726 if (!strcmp(fref_param, "19.2"))
1727 priv->ref_clock = WL12XX_REFCLOCK_19;
1728 else if (!strcmp(fref_param, "26"))
1729 priv->ref_clock = WL12XX_REFCLOCK_26;
1730 else if (!strcmp(fref_param, "26x"))
1731 priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1732 else if (!strcmp(fref_param, "38.4"))
1733 priv->ref_clock = WL12XX_REFCLOCK_38;
1734 else if (!strcmp(fref_param, "38.4x"))
1735 priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1736 else if (!strcmp(fref_param, "52"))
1737 priv->ref_clock = WL12XX_REFCLOCK_52;
1739 wl1271_error("Invalid fref parameter %s", fref_param);
1743 priv->tcxo_clock = pdata->board_tcxo_clock;
1745 if (!strcmp(tcxo_param, "19.2"))
1746 priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1747 else if (!strcmp(tcxo_param, "26"))
1748 priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1749 else if (!strcmp(tcxo_param, "38.4"))
1750 priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1751 else if (!strcmp(tcxo_param, "52"))
1752 priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1753 else if (!strcmp(tcxo_param, "16.368"))
1754 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1755 else if (!strcmp(tcxo_param, "32.736"))
1756 priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1757 else if (!strcmp(tcxo_param, "16.8"))
1758 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1759 else if (!strcmp(tcxo_param, "33.6"))
1760 priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1762 wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1765 priv->rx_mem_addr = kmalloc(sizeof(*priv->rx_mem_addr), GFP_KERNEL);
1766 if (!priv->rx_mem_addr)
1772 static int wl12xx_probe(struct platform_device *pdev)
1775 struct ieee80211_hw *hw;
1778 hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1779 WL12XX_AGGR_BUFFER_SIZE,
1780 sizeof(struct wl12xx_event_mailbox));
1782 wl1271_error("can't allocate hw");
1788 wl->ops = &wl12xx_ops;
1789 wl->ptable = wl12xx_ptable;
1790 ret = wlcore_probe(wl, pdev);
1802 static int wl12xx_remove(struct platform_device *pdev)
1804 struct wl1271 *wl = platform_get_drvdata(pdev);
1805 struct wl12xx_priv *priv;
1811 kfree(priv->rx_mem_addr);
1814 return wlcore_remove(pdev);
1817 static const struct platform_device_id wl12xx_id_table[] = {
1819 { } /* Terminating Entry */
1821 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1823 static struct platform_driver wl12xx_driver = {
1824 .probe = wl12xx_probe,
1825 .remove = wl12xx_remove,
1826 .id_table = wl12xx_id_table,
1828 .name = "wl12xx_driver",
1829 .owner = THIS_MODULE,
1833 module_platform_driver(wl12xx_driver);
1835 module_param_named(fref, fref_param, charp, 0);
1836 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1838 module_param_named(tcxo, tcxo_param, charp, 0);
1839 MODULE_PARM_DESC(tcxo,
1840 "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1842 MODULE_LICENSE("GPL v2");
1843 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1844 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1845 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1846 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1847 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1848 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1849 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);