drivers/net/wireless/ti/wl18xx/main.c

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ip.h>
  25 #include <linux/firmware.h>
  26
  27 #include "../wlcore/wlcore.h"
  28 #include "../wlcore/debug.h"
  29 #include "../wlcore/io.h"
  30 #include "../wlcore/acx.h"
  31 #include "../wlcore/tx.h"
  32 #include "../wlcore/rx.h"
  33 #include "../wlcore/io.h"
  34 #include "../wlcore/boot.h"
  35
  36 #include "reg.h"
  37 #include "conf.h"
  38 #include "acx.h"
  39 #include "tx.h"
  40 #include "wl18xx.h"
  41 #include "io.h"
  42 #include "debugfs.h"
  43
  44 #define WL18XX_RX_CHECKSUM_MASK      0x40
  45
  46 static char *ht_mode_param = "wide";
  47 static char *board_type_param = "hdk";
  48 static bool checksum_param = false;
  49 static bool enable_11a_param = true;
  50 static int num_rx_desc_param = -1;
  51
  52 /* phy paramters */
  53 static int dc2dc_param = -1;
  54 static int n_antennas_2_param = -1;
  55 static int n_antennas_5_param = -1;
  56 static int low_band_component_param = -1;
  57 static int low_band_component_type_param = -1;
  58 static int high_band_component_param = -1;
  59 static int high_band_component_type_param = -1;
  60 static int pwr_limit_reference_11_abg_param = -1;
  61
  62 static const u8 wl18xx_rate_to_idx_2ghz[] = {
  63         /* MCS rates are used only with 11n */
  64         15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  65         14,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  66         13,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  67         12,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  68         11,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  69         10,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  70         9,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  71         8,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  72         7,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  73         6,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  74         5,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  75         4,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  76         3,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  77         2,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  78         1,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  79         0,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  80
  81         11,                            /* WL18XX_CONF_HW_RXTX_RATE_54   */
  82         10,                            /* WL18XX_CONF_HW_RXTX_RATE_48   */
  83         9,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
  84         8,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
  85
  86         /* TI-specific rate */
  87         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
  88
  89         7,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
  90         6,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
  91         3,                             /* WL18XX_CONF_HW_RXTX_RATE_11   */
  92         5,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
  93         4,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
  94         2,                             /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
  95         1,                             /* WL18XX_CONF_HW_RXTX_RATE_2    */
  96         0                              /* WL18XX_CONF_HW_RXTX_RATE_1    */
  97 };
  98
  99 static const u8 wl18xx_rate_to_idx_5ghz[] = {
 100         /* MCS rates are used only with 11n */
 101         15,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
 102         14,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
 103         13,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
 104         12,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
 105         11,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
 106         10,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
 107         9,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
 108         8,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
 109         7,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
 110         6,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
 111         5,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
 112         4,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
 113         3,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
 114         2,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
 115         1,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
 116         0,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
 117
 118         7,                             /* WL18XX_CONF_HW_RXTX_RATE_54   */
 119         6,                             /* WL18XX_CONF_HW_RXTX_RATE_48   */
 120         5,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
 121         4,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
 122
 123         /* TI-specific rate */
 124         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
 125
 126         3,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
 127         2,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
 128         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11   */
 129         1,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
 130         0,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
 131         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
 132         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2    */
 133         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1    */
 134 };
 135
 136 static const u8 *wl18xx_band_rate_to_idx[] = {
 137         [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
 138         [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
 139 };
 140
 141 enum wl18xx_hw_rates {
 142         WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
 143         WL18XX_CONF_HW_RXTX_RATE_MCS14,
 144         WL18XX_CONF_HW_RXTX_RATE_MCS13,
 145         WL18XX_CONF_HW_RXTX_RATE_MCS12,
 146         WL18XX_CONF_HW_RXTX_RATE_MCS11,
 147         WL18XX_CONF_HW_RXTX_RATE_MCS10,
 148         WL18XX_CONF_HW_RXTX_RATE_MCS9,
 149         WL18XX_CONF_HW_RXTX_RATE_MCS8,
 150         WL18XX_CONF_HW_RXTX_RATE_MCS7,
 151         WL18XX_CONF_HW_RXTX_RATE_MCS6,
 152         WL18XX_CONF_HW_RXTX_RATE_MCS5,
 153         WL18XX_CONF_HW_RXTX_RATE_MCS4,
 154         WL18XX_CONF_HW_RXTX_RATE_MCS3,
 155         WL18XX_CONF_HW_RXTX_RATE_MCS2,
 156         WL18XX_CONF_HW_RXTX_RATE_MCS1,
 157         WL18XX_CONF_HW_RXTX_RATE_MCS0,
 158         WL18XX_CONF_HW_RXTX_RATE_54,
 159         WL18XX_CONF_HW_RXTX_RATE_48,
 160         WL18XX_CONF_HW_RXTX_RATE_36,
 161         WL18XX_CONF_HW_RXTX_RATE_24,
 162         WL18XX_CONF_HW_RXTX_RATE_22,
 163         WL18XX_CONF_HW_RXTX_RATE_18,
 164         WL18XX_CONF_HW_RXTX_RATE_12,
 165         WL18XX_CONF_HW_RXTX_RATE_11,
 166         WL18XX_CONF_HW_RXTX_RATE_9,
 167         WL18XX_CONF_HW_RXTX_RATE_6,
 168         WL18XX_CONF_HW_RXTX_RATE_5_5,
 169         WL18XX_CONF_HW_RXTX_RATE_2,
 170         WL18XX_CONF_HW_RXTX_RATE_1,
 171         WL18XX_CONF_HW_RXTX_RATE_MAX,
 172 };
 173
 174 static struct wlcore_conf wl18xx_conf = {
 175         .sg = {
 176                 .params = {
 177                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
 178                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
 179                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
 180                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
 181                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
 182                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
 183                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
 184                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
 185                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
 186                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
 187                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
 188                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
 189                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
 190                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
 191                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
 192                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
 193                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
 194                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
 195                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
 196                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
 197                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
 198                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
 199                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
 200                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
 201                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
 202                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
 203                         /* active scan params */
 204                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
 205                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
 206                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
 207                         /* passive scan params */
 208                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
 209                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
 210                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
 211                         /* passive scan in dual antenna params */
 212                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
 213                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
 214                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
 215                         /* general params */
 216                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
 217                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
 218                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
 219                         [CONF_SG_DHCP_TIME] = 5000,
 220                         [CONF_SG_RXT] = 1200,
 221                         [CONF_SG_TXT] = 1000,
 222                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
 223                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
 224                         [CONF_SG_HV3_MAX_SERVED] = 6,
 225                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
 226                         [CONF_SG_UPSD_TIMEOUT] = 10,
 227                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 228                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 229                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 230                         /* AP params */
 231                         [CONF_AP_BEACON_MISS_TX] = 3,
 232                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 233                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 234                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 235                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 236                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 237                         /* CTS Diluting params */
 238                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 239                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 240                 },
 241                 .state = CONF_SG_PROTECTIVE,
 242         },
 243         .rx = {
 244                 .rx_msdu_life_time           = 512000,
 245                 .packet_detection_threshold  = 0,
 246                 .ps_poll_timeout             = 15,
 247                 .upsd_timeout                = 15,
 248                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 249                 .rx_cca_threshold            = 0,
 250                 .irq_blk_threshold           = 0xFFFF,
 251                 .irq_pkt_threshold           = 0,
 252                 .irq_timeout                 = 600,
 253                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 254         },
 255         .tx = {
 256                 .tx_energy_detection         = 0,
 257                 .sta_rc_conf                 = {
 258                         .enabled_rates       = 0,
 259                         .short_retry_limit   = 10,
 260                         .long_retry_limit    = 10,
 261                         .aflags              = 0,
 262                 },
 263                 .ac_conf_count               = 4,
 264                 .ac_conf                     = {
 265                         [CONF_TX_AC_BE] = {
 266                                 .ac          = CONF_TX_AC_BE,
 267                                 .cw_min      = 15,
 268                                 .cw_max      = 63,
 269                                 .aifsn       = 3,
 270                                 .tx_op_limit = 0,
 271                         },
 272                         [CONF_TX_AC_BK] = {
 273                                 .ac          = CONF_TX_AC_BK,
 274                                 .cw_min      = 15,
 275                                 .cw_max      = 63,
 276                                 .aifsn       = 7,
 277                                 .tx_op_limit = 0,
 278                         },
 279                         [CONF_TX_AC_VI] = {
 280                                 .ac          = CONF_TX_AC_VI,
 281                                 .cw_min      = 15,
 282                                 .cw_max      = 63,
 283                                 .aifsn       = CONF_TX_AIFS_PIFS,
 284                                 .tx_op_limit = 3008,
 285                         },
 286                         [CONF_TX_AC_VO] = {
 287                                 .ac          = CONF_TX_AC_VO,
 288                                 .cw_min      = 15,
 289                                 .cw_max      = 63,
 290                                 .aifsn       = CONF_TX_AIFS_PIFS,
 291                                 .tx_op_limit = 1504,
 292                         },
 293                 },
 294                 .max_tx_retries = 100,
 295                 .ap_aging_period = 300,
 296                 .tid_conf_count = 4,
 297                 .tid_conf = {
 298                         [CONF_TX_AC_BE] = {
 299                                 .queue_id    = CONF_TX_AC_BE,
 300                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 301                                 .tsid        = CONF_TX_AC_BE,
 302                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 303                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 304                                 .apsd_conf   = {0, 0},
 305                         },
 306                         [CONF_TX_AC_BK] = {
 307                                 .queue_id    = CONF_TX_AC_BK,
 308                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 309                                 .tsid        = CONF_TX_AC_BK,
 310                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 311                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 312                                 .apsd_conf   = {0, 0},
 313                         },
 314                         [CONF_TX_AC_VI] = {
 315                                 .queue_id    = CONF_TX_AC_VI,
 316                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 317                                 .tsid        = CONF_TX_AC_VI,
 318                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 319                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 320                                 .apsd_conf   = {0, 0},
 321                         },
 322                         [CONF_TX_AC_VO] = {
 323                                 .queue_id    = CONF_TX_AC_VO,
 324                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 325                                 .tsid        = CONF_TX_AC_VO,
 326                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 327                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 328                                 .apsd_conf   = {0, 0},
 329                         },
 330                 },
 331                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 332                 .tx_compl_timeout            = 350,
 333                 .tx_compl_threshold          = 10,
 334                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 335                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 336                 .tmpl_short_retry_limit      = 10,
 337                 .tmpl_long_retry_limit       = 10,
 338                 .tx_watchdog_timeout         = 5000,
 339         },
 340         .conn = {
 341                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 342                 .listen_interval             = 1,
 343                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 344                 .suspend_listen_interval     = 3,
 345                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 346                 .bcn_filt_ie_count           = 3,
 347                 .bcn_filt_ie = {
 348                         [0] = {
 349                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 350                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 351                         },
 352                         [1] = {
 353                                 .ie          = WLAN_EID_HT_OPERATION,
 354                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 355                         },
 356                         [2] = {
 357                                 .ie          = WLAN_EID_ERP_INFO,
 358                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 359                         },
 360                 },
 361                 .synch_fail_thold            = 12,
 362                 .bss_lose_timeout            = 400,
 363                 .beacon_rx_timeout           = 10000,
 364                 .broadcast_timeout           = 20000,
 365                 .rx_broadcast_in_ps          = 1,
 366                 .ps_poll_threshold           = 10,
 367                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 368                 .bet_max_consecutive         = 50,
 369                 .psm_entry_retries           = 8,
 370                 .psm_exit_retries            = 16,
 371                 .psm_entry_nullfunc_retries  = 3,
 372                 .dynamic_ps_timeout          = 200,
 373                 .forced_ps                   = false,
 374                 .keep_alive_interval         = 55000,
 375                 .max_listen_interval         = 20,
 376                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 377         },
 378         .itrim = {
 379                 .enable = false,
 380                 .timeout = 50000,
 381         },
 382         .pm_config = {
 383                 .host_clk_settling_time = 5000,
 384                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 385         },
 386         .roam_trigger = {
 387                 .trigger_pacing               = 1,
 388                 .avg_weight_rssi_beacon       = 20,
 389                 .avg_weight_rssi_data         = 10,
 390                 .avg_weight_snr_beacon        = 20,
 391                 .avg_weight_snr_data          = 10,
 392         },
 393         .scan = {
 394                 .min_dwell_time_active        = 7500,
 395                 .max_dwell_time_active        = 30000,
 396                 .min_dwell_time_passive       = 100000,
 397                 .max_dwell_time_passive       = 100000,
 398                 .num_probe_reqs               = 2,
 399                 .split_scan_timeout           = 50000,
 400         },
 401         .sched_scan = {
 402                 /*
 403                  * Values are in TU/1000 but since sched scan FW command
 404                  * params are in TUs rounding up may occur.
 405                  */
 406                 .base_dwell_time                = 7500,
 407                 .max_dwell_time_delta           = 22500,
 408                 /* based on 250bits per probe @1Mbps */
 409                 .dwell_time_delta_per_probe     = 2000,
 410                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 411                 .dwell_time_delta_per_probe_5   = 350,
 412                 .dwell_time_passive             = 100000,
 413                 .dwell_time_dfs                 = 150000,
 414                 .num_probe_reqs                 = 2,
 415                 .rssi_threshold                 = -90,
 416                 .snr_threshold                  = 0,
 417         },
 418         .ht = {
 419                 .rx_ba_win_size = 10,
 420                 .tx_ba_win_size = 64,
 421                 .inactivity_timeout = 10000,
 422                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 423         },
 424         .mem = {
 425                 .num_stations                 = 1,
 426                 .ssid_profiles                = 1,
 427                 .rx_block_num                 = 40,
 428                 .tx_min_block_num             = 40,
 429                 .dynamic_memory               = 1,
 430                 .min_req_tx_blocks            = 45,
 431                 .min_req_rx_blocks            = 22,
 432                 .tx_min                       = 27,
 433         },
 434         .fm_coex = {
 435                 .enable                       = true,
 436                 .swallow_period               = 5,
 437                 .n_divider_fref_set_1         = 0xff,       /* default */
 438                 .n_divider_fref_set_2         = 12,
 439                 .m_divider_fref_set_1         = 0xffff,
 440                 .m_divider_fref_set_2         = 148,        /* default */
 441                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 442                 .ldo_stabilization_time       = 0xffff,     /* default */
 443                 .fm_disturbed_band_margin     = 0xff,       /* default */
 444                 .swallow_clk_diff             = 0xff,       /* default */
 445         },
 446         .rx_streaming = {
 447                 .duration                      = 150,
 448                 .queues                        = 0x1,
 449                 .interval                      = 20,
 450                 .always                        = 0,
 451         },
 452         .fwlog = {
 453                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 454                 .mem_blocks                   = 2,
 455                 .severity                     = 0,
 456                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 457                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 458                 .threshold                    = 0,
 459         },
 460         .rate = {
 461                 .rate_retry_score = 32000,
 462                 .per_add = 8192,
 463                 .per_th1 = 2048,
 464                 .per_th2 = 4096,
 465                 .max_per = 8100,
 466                 .inverse_curiosity_factor = 5,
 467                 .tx_fail_low_th = 4,
 468                 .tx_fail_high_th = 10,
 469                 .per_alpha_shift = 4,
 470                 .per_add_shift = 13,
 471                 .per_beta1_shift = 10,
 472                 .per_beta2_shift = 8,
 473                 .rate_check_up = 2,
 474                 .rate_check_down = 12,
 475                 .rate_retry_policy = {
 476                         0x00, 0x00, 0x00, 0x00, 0x00,
 477                         0x00, 0x00, 0x00, 0x00, 0x00,
 478                         0x00, 0x00, 0x00,
 479                 },
 480         },
 481         .hangover = {
 482                 .recover_time               = 0,
 483                 .hangover_period            = 20,
 484                 .dynamic_mode               = 1,
 485                 .early_termination_mode     = 1,
 486                 .max_period                 = 20,
 487                 .min_period                 = 1,
 488                 .increase_delta             = 1,
 489                 .decrease_delta             = 2,
 490                 .quiet_time                 = 4,
 491                 .increase_time              = 1,
 492                 .window_size                = 16,
 493         },
 494 };
 495
 496 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
 497         .phy = {
 498                 .phy_standalone                 = 0x00,
 499                 .primary_clock_setting_time     = 0x05,
 500                 .clock_valid_on_wake_up         = 0x00,
 501                 .secondary_clock_setting_time   = 0x05,
 502                 .rdl                            = 0x01,
 503                 .auto_detect                    = 0x00,
 504                 .dedicated_fem                  = FEM_NONE,
 505                 .low_band_component             = COMPONENT_2_WAY_SWITCH,
 506                 .low_band_component_type        = 0x05,
 507                 .high_band_component            = COMPONENT_2_WAY_SWITCH,
 508                 .high_band_component_type       = 0x09,
 509                 .tcxo_ldo_voltage               = 0x00,
 510                 .xtal_itrim_val                 = 0x04,
 511                 .srf_state                      = 0x00,
 512                 .io_configuration               = 0x01,
 513                 .sdio_configuration             = 0x00,
 514                 .settings                       = 0x00,
 515                 .enable_clpc                    = 0x00,
 516                 .enable_tx_low_pwr_on_siso_rdl  = 0x00,
 517                 .rx_profile                     = 0x00,
 518                 .pwr_limit_reference_11_abg     = 0xc8,
 519                 .psat                           = 0,
 520                 .low_power_val                  = 0x00,
 521                 .med_power_val                  = 0x0a,
 522                 .high_power_val                 = 0x1e,
 523                 .external_pa_dc2dc              = 0,
 524                 .number_of_assembled_ant2_4     = 1,
 525                 .number_of_assembled_ant5       = 1,
 526         },
 527 };
 528
 529 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
 530         [PART_TOP_PRCM_ELP_SOC] = {
 531                 .mem  = { .start = 0x00A02000, .size  = 0x00010000 },
 532                 .reg  = { .start = 0x00807000, .size  = 0x00005000 },
 533                 .mem2 = { .start = 0x00800000, .size  = 0x0000B000 },
 534                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 535         },
 536         [PART_DOWN] = {
 537                 .mem  = { .start = 0x00000000, .size  = 0x00014000 },
 538                 .reg  = { .start = 0x00810000, .size  = 0x0000BFFF },
 539                 .mem2 = { .start = 0x00000000, .size  = 0x00000000 },
 540                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 541         },
 542         [PART_BOOT] = {
 543                 .mem  = { .start = 0x00700000, .size = 0x0000030c },
 544                 .reg  = { .start = 0x00802000, .size = 0x00014578 },
 545                 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
 546                 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
 547         },
 548         [PART_WORK] = {
 549                 .mem  = { .start = 0x00800000, .size  = 0x000050FC },
 550                 .reg  = { .start = 0x00B00404, .size  = 0x00001000 },
 551                 .mem2 = { .start = 0x00C00000, .size  = 0x00000400 },
 552                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 553         },
 554         [PART_PHY_INIT] = {
 555                 .mem  = { .start = 0x80926000,
 556                           .size = sizeof(struct wl18xx_mac_and_phy_params) },
 557                 .reg  = { .start = 0x00000000, .size = 0x00000000 },
 558                 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
 559                 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
 560         },
 561 };
 562
 563 static const int wl18xx_rtable[REG_TABLE_LEN] = {
 564         [REG_ECPU_CONTROL]              = WL18XX_REG_ECPU_CONTROL,
 565         [REG_INTERRUPT_NO_CLEAR]        = WL18XX_REG_INTERRUPT_NO_CLEAR,
 566         [REG_INTERRUPT_ACK]             = WL18XX_REG_INTERRUPT_ACK,
 567         [REG_COMMAND_MAILBOX_PTR]       = WL18XX_REG_COMMAND_MAILBOX_PTR,
 568         [REG_EVENT_MAILBOX_PTR]         = WL18XX_REG_EVENT_MAILBOX_PTR,
 569         [REG_INTERRUPT_TRIG]            = WL18XX_REG_INTERRUPT_TRIG_H,
 570         [REG_INTERRUPT_MASK]            = WL18XX_REG_INTERRUPT_MASK,
 571         [REG_PC_ON_RECOVERY]            = WL18XX_SCR_PAD4,
 572         [REG_CHIP_ID_B]                 = WL18XX_REG_CHIP_ID_B,
 573         [REG_CMD_MBOX_ADDRESS]          = WL18XX_CMD_MBOX_ADDRESS,
 574
 575         /* data access memory addresses, used with partition translation */
 576         [REG_SLV_MEM_DATA]              = WL18XX_SLV_MEM_DATA,
 577         [REG_SLV_REG_DATA]              = WL18XX_SLV_REG_DATA,
 578
 579         /* raw data access memory addresses */
 580         [REG_RAW_FW_STATUS_ADDR]        = WL18XX_FW_STATUS_ADDR,
 581 };
 582
 583 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
 584         [CLOCK_CONFIG_16_2_M]   = { 7,  104,  801, 4,  true },
 585         [CLOCK_CONFIG_16_368_M] = { 9,  132, 3751, 4,  true },
 586         [CLOCK_CONFIG_16_8_M]   = { 7,  100,    0, 0, false },
 587         [CLOCK_CONFIG_19_2_M]   = { 8,  100,    0, 0, false },
 588         [CLOCK_CONFIG_26_M]     = { 13, 120,    0, 0, false },
 589         [CLOCK_CONFIG_32_736_M] = { 9,  132, 3751, 4,  true },
 590         [CLOCK_CONFIG_33_6_M]   = { 7,  100,    0, 0, false },
 591         [CLOCK_CONFIG_38_468_M] = { 8,  100,    0, 0, false },
 592         [CLOCK_CONFIG_52_M]     = { 13, 120,    0, 0, false },
 593 };
 594
 595 /* TODO: maybe move to a new header file? */
 596 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
 597
 598 static int wl18xx_identify_chip(struct wl1271 *wl)
 599 {
 600         int ret = 0;
 601
 602         switch (wl->chip.id) {
 603         case CHIP_ID_185x_PG20:
 604                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
 605                                  wl->chip.id);
 606                 wl->sr_fw_name = WL18XX_FW_NAME;
 607                 /* wl18xx uses the same firmware for PLT */
 608                 wl->plt_fw_name = WL18XX_FW_NAME;
 609                 wl->quirks |= WLCORE_QUIRK_NO_ELP |
 610                               WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
 611                               WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 612                               WLCORE_QUIRK_TX_PAD_LAST_FRAME;
 613                 break;
 614         case CHIP_ID_185x_PG10:
 615                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
 616                              wl->chip.id);
 617                 wl->sr_fw_name = WL18XX_FW_NAME;
 618                 /* wl18xx uses the same firmware for PLT */
 619                 wl->plt_fw_name = WL18XX_FW_NAME;
 620                 wl->quirks |= WLCORE_QUIRK_NO_ELP |
 621                         WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
 622                         WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
 623                         WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
 624
 625                 /* PG 1.0 has some problems with MCS_13, so disable it */
 626                 wl->ht_cap[IEEE80211_BAND_2GHZ].mcs.rx_mask[1] &= ~BIT(5);
 627
 628                 break;
 629         default:
 630                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 631                 ret = -ENODEV;
 632                 goto out;
 633         }
 634
 635 out:
 636         return ret;
 637 }
 638
 639 static void wl18xx_set_clk(struct wl1271 *wl)
 640 {
 641         u32 clk_freq;
 642
 643         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 644
 645         /* TODO: PG2: apparently we need to read the clk type */
 646
 647         clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT);
 648         wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
 649                      wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
 650                      wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
 651                      wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
 652
 653         wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n);
 654         wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m);
 655
 656         if (wl18xx_clk_table[clk_freq].swallow) {
 657                 /* first the 16 lower bits */
 658                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
 659                                      wl18xx_clk_table[clk_freq].q &
 660                                      PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
 661                 /* then the 16 higher bits, masked out */
 662                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
 663                                      (wl18xx_clk_table[clk_freq].q >> 16) &
 664                                      PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
 665
 666                 /* first the 16 lower bits */
 667                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
 668                                      wl18xx_clk_table[clk_freq].p &
 669                                      PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
 670                 /* then the 16 higher bits, masked out */
 671                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
 672                                      (wl18xx_clk_table[clk_freq].p >> 16) &
 673                                      PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
 674         } else {
 675                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
 676                                      PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
 677         }
 678 }
 679
 680 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
 681 {
 682         /* disable Rx/Tx */
 683         wl1271_write32(wl, WL18XX_ENABLE, 0x0);
 684
 685         /* disable auto calibration on start*/
 686         wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
 687 }
 688
 689 static int wl18xx_pre_boot(struct wl1271 *wl)
 690 {
 691         wl18xx_set_clk(wl);
 692
 693         /* Continue the ELP wake up sequence */
 694         wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 695         udelay(500);
 696
 697         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 698
 699         /* Disable interrupts */
 700         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 701
 702         wl18xx_boot_soft_reset(wl);
 703
 704         return 0;
 705 }
 706
 707 static void wl18xx_pre_upload(struct wl1271 *wl)
 708 {
 709         u32 tmp;
 710
 711         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 712
 713         /* TODO: check if this is all needed */
 714         wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 715
 716         tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
 717
 718         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 719
 720         tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
 721 }
 722
 723 static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
 724 {
 725         struct wl18xx_priv *priv = wl->priv;
 726         size_t len;
 727
 728         /* the parameters struct is smaller for PG1 */
 729         if (wl->chip.id == CHIP_ID_185x_PG10)
 730                 len = offsetof(struct wl18xx_mac_and_phy_params, psat) + 1;
 731         else
 732                 len = sizeof(struct wl18xx_mac_and_phy_params);
 733
 734         wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 735         wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&priv->conf.phy, len,
 736                      false);
 737 }
 738
 739 static void wl18xx_enable_interrupts(struct wl1271 *wl)
 740 {
 741         u32 event_mask, intr_mask;
 742
 743         if (wl->chip.id == CHIP_ID_185x_PG10) {
 744                 event_mask = WL18XX_ACX_EVENTS_VECTOR_PG1;
 745                 intr_mask = WL18XX_INTR_MASK_PG1;
 746         } else {
 747                 event_mask = WL18XX_ACX_EVENTS_VECTOR_PG2;
 748                 intr_mask = WL18XX_INTR_MASK_PG2;
 749         }
 750
 751         wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
 752
 753         wlcore_enable_interrupts(wl);
 754         wlcore_write_reg(wl, REG_INTERRUPT_MASK,
 755                          WL1271_ACX_INTR_ALL & ~intr_mask);
 756 }
 757
 758 static int wl18xx_boot(struct wl1271 *wl)
 759 {
 760         int ret;
 761
 762         ret = wl18xx_pre_boot(wl);
 763         if (ret < 0)
 764                 goto out;
 765
 766         wl18xx_pre_upload(wl);
 767
 768         ret = wlcore_boot_upload_firmware(wl);
 769         if (ret < 0)
 770                 goto out;
 771
 772         wl18xx_set_mac_and_phy(wl);
 773
 774         ret = wlcore_boot_run_firmware(wl);
 775         if (ret < 0)
 776                 goto out;
 777
 778         wl18xx_enable_interrupts(wl);
 779
 780 out:
 781         return ret;
 782 }
 783
 784 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
 785                                void *buf, size_t len)
 786 {
 787         struct wl18xx_priv *priv = wl->priv;
 788
 789         memcpy(priv->cmd_buf, buf, len);
 790         memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
 791
 792         wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
 793                      false);
 794 }
 795
 796 static void wl18xx_ack_event(struct wl1271 *wl)
 797 {
 798         wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
 799 }
 800
 801 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
 802 {
 803         u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
 804         return (len + blk_size - 1) / blk_size + spare_blks;
 805 }
 806
 807 static void
 808 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 809                           u32 blks, u32 spare_blks)
 810 {
 811         desc->wl18xx_mem.total_mem_blocks = blks;
 812 }
 813
 814 static void
 815 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 816                             struct sk_buff *skb)
 817 {
 818         desc->length = cpu_to_le16(skb->len);
 819
 820         /* if only the last frame is to be padded, we unset this bit on Tx */
 821         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
 822                 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
 823         else
 824                 desc->wl18xx_mem.ctrl = 0;
 825
 826         wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
 827                      "len: %d life: %d mem: %d", desc->hlid,
 828                      le16_to_cpu(desc->length),
 829                      le16_to_cpu(desc->life_time),
 830                      desc->wl18xx_mem.total_mem_blocks);
 831 }
 832
 833 static enum wl_rx_buf_align
 834 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
 835 {
 836         if (rx_desc & RX_BUF_PADDED_PAYLOAD)
 837                 return WLCORE_RX_BUF_PADDED;
 838
 839         return WLCORE_RX_BUF_ALIGNED;
 840 }
 841
 842 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
 843                                     u32 data_len)
 844 {
 845         struct wl1271_rx_descriptor *desc = rx_data;
 846
 847         /* invalid packet */
 848         if (data_len < sizeof(*desc))
 849                 return 0;
 850
 851         return data_len - sizeof(*desc);
 852 }
 853
 854 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
 855 {
 856         wl18xx_tx_immediate_complete(wl);
 857 }
 858
 859 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
 860 {
 861         int ret;
 862         u32 sdio_align_size = 0;
 863         u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
 864                               HOST_IF_CFG_ADD_RX_ALIGNMENT;
 865
 866         /* Enable Tx SDIO padding */
 867         if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
 868                 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
 869                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 870         }
 871
 872         /* Enable Rx SDIO padding */
 873         if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
 874                 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
 875                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 876         }
 877
 878         ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
 879                                             sdio_align_size, extra_mem_blk,
 880                                             WL18XX_HOST_IF_LEN_SIZE_FIELD);
 881         if (ret < 0)
 882                 return ret;
 883
 884         return 0;
 885 }
 886
 887 static int wl18xx_hw_init(struct wl1271 *wl)
 888 {
 889         int ret;
 890         struct wl18xx_priv *priv = wl->priv;
 891
 892         /* (re)init private structures. Relevant on recovery as well. */
 893         priv->last_fw_rls_idx = 0;
 894         priv->extra_spare_vif_count = 0;
 895
 896         /* set the default amount of spare blocks in the bitmap */
 897         ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
 898         if (ret < 0)
 899                 return ret;
 900
 901         if (checksum_param) {
 902                 ret = wl18xx_acx_set_checksum_state(wl);
 903                 if (ret != 0)
 904                         return ret;
 905         }
 906
 907         return ret;
 908 }
 909
 910 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
 911                                     struct wl1271_tx_hw_descr *desc,
 912                                     struct sk_buff *skb)
 913 {
 914         u32 ip_hdr_offset;
 915         struct iphdr *ip_hdr;
 916
 917         if (!checksum_param) {
 918                 desc->wl18xx_checksum_data = 0;
 919                 return;
 920         }
 921
 922         if (skb->ip_summed != CHECKSUM_PARTIAL) {
 923                 desc->wl18xx_checksum_data = 0;
 924                 return;
 925         }
 926
 927         ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
 928         if (WARN_ON(ip_hdr_offset >= (1<<7))) {
 929                 desc->wl18xx_checksum_data = 0;
 930                 return;
 931         }
 932
 933         desc->wl18xx_checksum_data = ip_hdr_offset << 1;
 934
 935         /* FW is interested only in the LSB of the protocol  TCP=0 UDP=1 */
 936         ip_hdr = (void *)skb_network_header(skb);
 937         desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
 938 }
 939
 940 static void wl18xx_set_rx_csum(struct wl1271 *wl,
 941                                struct wl1271_rx_descriptor *desc,
 942                                struct sk_buff *skb)
 943 {
 944         if (desc->status & WL18XX_RX_CHECKSUM_MASK)
 945                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 946 }
 947
 948 /*
 949  * TODO: instead of having these two functions to get the rate mask,
 950  * we should modify the wlvif->rate_set instead
 951  */
 952 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
 953                                        struct wl12xx_vif *wlvif)
 954 {
 955         u32 hw_rate_set = wlvif->rate_set;
 956
 957         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 958             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
 959                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 960                 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
 961
 962                 /* we don't support MIMO in wide-channel mode */
 963                 hw_rate_set &= ~CONF_TX_MIMO_RATES;
 964         }
 965
 966         return hw_rate_set;
 967 }
 968
 969 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
 970                                              struct wl12xx_vif *wlvif)
 971 {
 972         if ((wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 973              wlvif->channel_type == NL80211_CHAN_HT40PLUS) &&
 974             !strcmp(ht_mode_param, "wide")) {
 975                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 976                 return CONF_TX_RATE_USE_WIDE_CHAN;
 977         } else if (!strcmp(ht_mode_param, "mimo")) {
 978                 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
 979
 980                 /*
 981                  * PG 1.0 has some problems with MCS_13, so disable it
 982                  *
 983                  * TODO: instead of hacking this in here, we should
 984                  * make it more general and change a bit in the
 985                  * wlvif->rate_set instead.
 986                  */
 987                 if (wl->chip.id == CHIP_ID_185x_PG10)
 988                         return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13;
 989
 990                 return CONF_TX_MIMO_RATES;
 991         } else {
 992                 return 0;
 993         }
 994 }
 995
 996 static s8 wl18xx_get_pg_ver(struct wl1271 *wl)
 997 {
 998         u32 fuse;
 999
1000         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1001
1002         fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3);
1003         fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1004
1005         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1006
1007         return (s8)fuse;
1008 }
1009
1010 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1011 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1012 {
1013         struct wl18xx_priv *priv = wl->priv;
1014         struct wlcore_conf_file *conf_file;
1015         const struct firmware *fw;
1016         int ret;
1017
1018         ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1019         if (ret < 0) {
1020                 wl1271_error("could not get configuration binary %s: %d",
1021                              WL18XX_CONF_FILE_NAME, ret);
1022                 goto out_fallback;
1023         }
1024
1025         if (fw->size != WL18XX_CONF_SIZE) {
1026                 wl1271_error("configuration binary file size is wrong, "
1027                              "expected %d got %d", WL18XX_CONF_SIZE, fw->size);
1028                 ret = -EINVAL;
1029                 goto out;
1030         }
1031
1032         conf_file = (struct wlcore_conf_file *) fw->data;
1033
1034         if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1035                 wl1271_error("configuration binary file magic number mismatch, "
1036                              "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1037                              conf_file->header.magic);
1038                 ret = -EINVAL;
1039                 goto out;
1040         }
1041
1042         if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1043                 wl1271_error("configuration binary file version not supported, "
1044                              "expected 0x%08x got 0x%08x",
1045                              WL18XX_CONF_VERSION, conf_file->header.version);
1046                 ret = -EINVAL;
1047                 goto out;
1048         }
1049
1050         memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1051         memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1052
1053         goto out;
1054
1055 out_fallback:
1056         wl1271_warning("falling back to default config");
1057
1058         /* apply driver default configuration */
1059         memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1060         /* apply default private configuration */
1061         memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1062
1063         /* For now we just fallback */
1064         return 0;
1065
1066 out:
1067         release_firmware(fw);
1068         return ret;
1069 }
1070
1071 static int wl18xx_plt_init(struct wl1271 *wl)
1072 {
1073         wl1271_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1074
1075         return wl->ops->boot(wl);
1076 }
1077
1078 static void wl18xx_get_mac(struct wl1271 *wl)
1079 {
1080         u32 mac1, mac2;
1081
1082         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1083
1084         mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1);
1085         mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2);
1086
1087         /* these are the two parts of the BD_ADDR */
1088         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1089                 ((mac1 & 0xff000000) >> 24);
1090         wl->fuse_nic_addr = (mac1 & 0xffffff);
1091
1092         wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1093 }
1094
1095 static int wl18xx_handle_static_data(struct wl1271 *wl,
1096                                      struct wl1271_static_data *static_data)
1097 {
1098         struct wl18xx_static_data_priv *static_data_priv =
1099                 (struct wl18xx_static_data_priv *) static_data->priv;
1100
1101         wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1102
1103         return 0;
1104 }
1105
1106 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1107 {
1108         struct wl18xx_priv *priv = wl->priv;
1109
1110         /* If we have VIFs requiring extra spare, indulge them */
1111         if (priv->extra_spare_vif_count)
1112                 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1113
1114         return WL18XX_TX_HW_BLOCK_SPARE;
1115 }
1116
1117 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1118                           struct ieee80211_vif *vif,
1119                           struct ieee80211_sta *sta,
1120                           struct ieee80211_key_conf *key_conf)
1121 {
1122         struct wl18xx_priv *priv = wl->priv;
1123         bool change_spare = false;
1124         int ret;
1125
1126         /*
1127          * when adding the first or removing the last GEM/TKIP interface,
1128          * we have to adjust the number of spare blocks.
1129          */
1130         change_spare = (key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1131                 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP) &&
1132                 ((priv->extra_spare_vif_count == 0 && cmd == SET_KEY) ||
1133                  (priv->extra_spare_vif_count == 1 && cmd == DISABLE_KEY));
1134
1135         /* no need to change spare - just regular set_key */
1136         if (!change_spare)
1137                 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1138
1139         /*
1140          * stop the queues and flush to ensure the next packets are
1141          * in sync with FW spare block accounting
1142          */
1143         wlcore_stop_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK);
1144         wl1271_tx_flush(wl);
1145
1146         ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1147         if (ret < 0)
1148                 goto out;
1149
1150         /* key is now set, change the spare blocks */
1151         if (cmd == SET_KEY) {
1152                 ret = wl18xx_set_host_cfg_bitmap(wl,
1153                                         WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1154                 if (ret < 0)
1155                         goto out;
1156
1157                 priv->extra_spare_vif_count++;
1158         } else {
1159                 ret = wl18xx_set_host_cfg_bitmap(wl,
1160                                         WL18XX_TX_HW_BLOCK_SPARE);
1161                 if (ret < 0)
1162                         goto out;
1163
1164                 priv->extra_spare_vif_count--;
1165         }
1166
1167 out:
1168         wlcore_wake_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK);
1169         return ret;
1170 }
1171
1172 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1173                                u32 buf_offset, u32 last_len)
1174 {
1175         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1176                 struct wl1271_tx_hw_descr *last_desc;
1177
1178                 /* get the last TX HW descriptor written to the aggr buf */
1179                 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1180                                                         buf_offset - last_len);
1181
1182                 /* the last frame is padded up to an SDIO block */
1183                 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1184                 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1185         }
1186
1187         /* no modifications */
1188         return buf_offset;
1189 }
1190
1191 static struct wlcore_ops wl18xx_ops = {
1192         .identify_chip  = wl18xx_identify_chip,
1193         .boot           = wl18xx_boot,
1194         .plt_init       = wl18xx_plt_init,
1195         .trigger_cmd    = wl18xx_trigger_cmd,
1196         .ack_event      = wl18xx_ack_event,
1197         .calc_tx_blocks = wl18xx_calc_tx_blocks,
1198         .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1199         .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1200         .get_rx_buf_align = wl18xx_get_rx_buf_align,
1201         .get_rx_packet_len = wl18xx_get_rx_packet_len,
1202         .tx_immediate_compl = wl18xx_tx_immediate_completion,
1203         .tx_delayed_compl = NULL,
1204         .hw_init        = wl18xx_hw_init,
1205         .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1206         .get_pg_ver     = wl18xx_get_pg_ver,
1207         .set_rx_csum = wl18xx_set_rx_csum,
1208         .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1209         .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1210         .get_mac        = wl18xx_get_mac,
1211         .debugfs_init   = wl18xx_debugfs_add_files,
1212         .handle_static_data     = wl18xx_handle_static_data,
1213         .get_spare_blocks = wl18xx_get_spare_blocks,
1214         .set_key        = wl18xx_set_key,
1215         .pre_pkt_send   = wl18xx_pre_pkt_send,
1216 };
1217
1218 /* HT cap appropriate for wide channels */
1219 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap = {
1220         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1221                IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1222         .ht_supported = true,
1223         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1224         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1225         .mcs = {
1226                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1227                 .rx_highest = cpu_to_le16(150),
1228                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1229                 },
1230 };
1231
1232 /* HT cap appropriate for SISO 20 */
1233 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1234         .cap = IEEE80211_HT_CAP_SGI_20,
1235         .ht_supported = true,
1236         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1237         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1238         .mcs = {
1239                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1240                 .rx_highest = cpu_to_le16(72),
1241                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1242                 },
1243 };
1244
1245 /* HT cap appropriate for MIMO rates in 20mhz channel */
1246 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1247         .cap = IEEE80211_HT_CAP_SGI_20,
1248         .ht_supported = true,
1249         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1250         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1251         .mcs = {
1252                 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1253                 .rx_highest = cpu_to_le16(144),
1254                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1255                 },
1256 };
1257
1258 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_5ghz = {
1259         .cap = IEEE80211_HT_CAP_SGI_20,
1260         .ht_supported = true,
1261         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1262         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1263         .mcs = {
1264                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1265                 .rx_highest = cpu_to_le16(72),
1266                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1267                 },
1268 };
1269
1270 static int __devinit wl18xx_probe(struct platform_device *pdev)
1271 {
1272         struct wl1271 *wl;
1273         struct ieee80211_hw *hw;
1274         struct wl18xx_priv *priv;
1275         int ret;
1276
1277         hw = wlcore_alloc_hw(sizeof(*priv));
1278         if (IS_ERR(hw)) {
1279                 wl1271_error("can't allocate hw");
1280                 ret = PTR_ERR(hw);
1281                 goto out;
1282         }
1283
1284         wl = hw->priv;
1285         priv = wl->priv;
1286         wl->ops = &wl18xx_ops;
1287         wl->ptable = wl18xx_ptable;
1288         wl->rtable = wl18xx_rtable;
1289         wl->num_tx_desc = 32;
1290         wl->num_rx_desc = 32;
1291         wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1292         wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1293         wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1294         wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1295         wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1296         wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1297
1298         if (num_rx_desc_param != -1)
1299                 wl->num_rx_desc = num_rx_desc_param;
1300
1301         if (!strcmp(ht_mode_param, "wide")) {
1302                 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
1303                        &wl18xx_siso40_ht_cap,
1304                        sizeof(wl18xx_siso40_ht_cap));
1305                 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
1306                        &wl18xx_siso40_ht_cap,
1307                        sizeof(wl18xx_siso40_ht_cap));
1308         } else if (!strcmp(ht_mode_param, "mimo")) {
1309                 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
1310                        &wl18xx_mimo_ht_cap_2ghz,
1311                        sizeof(wl18xx_mimo_ht_cap_2ghz));
1312                 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
1313                        &wl18xx_mimo_ht_cap_5ghz,
1314                        sizeof(wl18xx_mimo_ht_cap_5ghz));
1315         } else if (!strcmp(ht_mode_param, "siso20")) {
1316                 memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
1317                        &wl18xx_siso20_ht_cap,
1318                        sizeof(wl18xx_siso20_ht_cap));
1319                 memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
1320                        &wl18xx_siso20_ht_cap,
1321                        sizeof(wl18xx_siso20_ht_cap));
1322         } else {
1323                 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1324                 ret = -EINVAL;
1325                 goto out_free;
1326         }
1327
1328         ret = wl18xx_conf_init(wl, &pdev->dev);
1329         if (ret < 0)
1330                 goto out_free;
1331
1332         if (!strcmp(board_type_param, "fpga")) {
1333                 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1334         } else if (!strcmp(board_type_param, "hdk")) {
1335                 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1336                 /* HACK! Just for now we hardcode HDK to 0x06 */
1337                 priv->conf.phy.low_band_component_type = 0x06;
1338         } else if (!strcmp(board_type_param, "dvp")) {
1339                 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1340         } else if (!strcmp(board_type_param, "evb")) {
1341                 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1342         } else if (!strcmp(board_type_param, "com8")) {
1343                 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1344                 /* HACK! Just for now we hardcode COM8 to 0x06 */
1345                 priv->conf.phy.low_band_component_type = 0x06;
1346         } else {
1347                 wl1271_error("invalid board type '%s'", board_type_param);
1348                 ret = -EINVAL;
1349                 goto out_free;
1350         }
1351
1352         /* If the module param is set, update it in conf */
1353         if (low_band_component_param != -1)
1354                 priv->conf.phy.low_band_component = low_band_component_param;
1355         if (low_band_component_type_param != -1)
1356                 priv->conf.phy.low_band_component_type =
1357                         low_band_component_type_param;
1358         if (high_band_component_param != -1)
1359                 priv->conf.phy.high_band_component = high_band_component_param;
1360         if (high_band_component_type_param != -1)
1361                 priv->conf.phy.high_band_component_type =
1362                         high_band_component_type_param;
1363         if (pwr_limit_reference_11_abg_param != -1)
1364                 priv->conf.phy.pwr_limit_reference_11_abg =
1365                         pwr_limit_reference_11_abg_param;
1366         if (n_antennas_2_param != -1)
1367                 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1368         if (n_antennas_5_param != -1)
1369                 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1370         if (dc2dc_param != -1)
1371                 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1372
1373         if (!checksum_param) {
1374                 wl18xx_ops.set_rx_csum = NULL;
1375                 wl18xx_ops.init_vif = NULL;
1376         }
1377
1378         wl->enable_11a = enable_11a_param;
1379
1380         return wlcore_probe(wl, pdev);
1381
1382 out_free:
1383         wlcore_free_hw(wl);
1384 out:
1385         return ret;
1386 }
1387
1388 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1389         { "wl18xx", 0 },
1390         {  } /* Terminating Entry */
1391 };
1392 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1393
1394 static struct platform_driver wl18xx_driver = {
1395         .probe          = wl18xx_probe,
1396         .remove         = __devexit_p(wlcore_remove),
1397         .id_table       = wl18xx_id_table,
1398         .driver = {
1399                 .name   = "wl18xx_driver",
1400                 .owner  = THIS_MODULE,
1401         }
1402 };
1403
1404 static int __init wl18xx_init(void)
1405 {
1406         return platform_driver_register(&wl18xx_driver);
1407 }
1408 module_init(wl18xx_init);
1409
1410 static void __exit wl18xx_exit(void)
1411 {
1412         platform_driver_unregister(&wl18xx_driver);
1413 }
1414 module_exit(wl18xx_exit);
1415
1416 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1417 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide (default), mimo or siso20");
1418
1419 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1420 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1421                  "dvp");
1422
1423 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1424 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1425
1426 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR);
1427 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)");
1428
1429 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1430 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1431
1432 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1433 MODULE_PARM_DESC(n_antennas_2,
1434                  "Number of installed 2.4GHz antennas: 1 (default) or 2");
1435
1436 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1437 MODULE_PARM_DESC(n_antennas_5,
1438                  "Number of installed 5GHz antennas: 1 (default) or 2");
1439
1440 module_param_named(low_band_component, low_band_component_param, int,
1441                    S_IRUSR);
1442 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1443                  "(default is 0x01)");
1444
1445 module_param_named(low_band_component_type, low_band_component_type_param,
1446                    int, S_IRUSR);
1447 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1448                  "(default is 0x05 or 0x06 depending on the board_type)");
1449
1450 module_param_named(high_band_component, high_band_component_param, int,
1451                    S_IRUSR);
1452 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1453                  "(default is 0x01)");
1454
1455 module_param_named(high_band_component_type, high_band_component_type_param,
1456                    int, S_IRUSR);
1457 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1458                  "(default is 0x09)");
1459
1460 module_param_named(pwr_limit_reference_11_abg,
1461                    pwr_limit_reference_11_abg_param, int, S_IRUSR);
1462 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1463                  "(default is 0xc8)");
1464
1465 module_param_named(num_rx_desc,
1466                    num_rx_desc_param, int, S_IRUSR);
1467 MODULE_PARM_DESC(num_rx_desc_param,
1468                  "Number of Rx descriptors: u8 (default is 32)");
1469
1470 MODULE_LICENSE("GPL v2");
1471 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1472 MODULE_FIRMWARE(WL18XX_FW_NAME);