drivers/net/wireless/ti/wl18xx/main.c

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ip.h>
  25 #include <linux/firmware.h>
  26 #include <linux/etherdevice.h>
  27
  28 #include "../wlcore/wlcore.h"
  29 #include "../wlcore/debug.h"
  30 #include "../wlcore/io.h"
  31 #include "../wlcore/acx.h"
  32 #include "../wlcore/tx.h"
  33 #include "../wlcore/rx.h"
  34 #include "../wlcore/boot.h"
  35
  36 #include "reg.h"
  37 #include "conf.h"
  38 #include "cmd.h"
  39 #include "acx.h"
  40 #include "tx.h"
  41 #include "wl18xx.h"
  42 #include "io.h"
  43 #include "scan.h"
  44 #include "event.h"
  45 #include "debugfs.h"
  46
  47 #define WL18XX_RX_CHECKSUM_MASK      0x40
  48
  49 static char *ht_mode_param = NULL;
  50 static char *board_type_param = NULL;
  51 static bool checksum_param = false;
  52 static int num_rx_desc_param = -1;
  53
  54 /* phy paramters */
  55 static int dc2dc_param = -1;
  56 static int n_antennas_2_param = -1;
  57 static int n_antennas_5_param = -1;
  58 static int low_band_component_param = -1;
  59 static int low_band_component_type_param = -1;
  60 static int high_band_component_param = -1;
  61 static int high_band_component_type_param = -1;
  62 static int pwr_limit_reference_11_abg_param = -1;
  63
  64 static const u8 wl18xx_rate_to_idx_2ghz[] = {
  65         /* MCS rates are used only with 11n */
  66         15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  67         14,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  68         13,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  69         12,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  70         11,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  71         10,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  72         9,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  73         8,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  74         7,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  75         6,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  76         5,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  77         4,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  78         3,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  79         2,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  80         1,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  81         0,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  82
  83         11,                            /* WL18XX_CONF_HW_RXTX_RATE_54   */
  84         10,                            /* WL18XX_CONF_HW_RXTX_RATE_48   */
  85         9,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
  86         8,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
  87
  88         /* TI-specific rate */
  89         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
  90
  91         7,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
  92         6,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
  93         3,                             /* WL18XX_CONF_HW_RXTX_RATE_11   */
  94         5,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
  95         4,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
  96         2,                             /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
  97         1,                             /* WL18XX_CONF_HW_RXTX_RATE_2    */
  98         0                              /* WL18XX_CONF_HW_RXTX_RATE_1    */
  99 };
 100
 101 static const u8 wl18xx_rate_to_idx_5ghz[] = {
 102         /* MCS rates are used only with 11n */
 103         15,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
 104         14,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
 105         13,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
 106         12,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
 107         11,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
 108         10,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
 109         9,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
 110         8,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
 111         7,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
 112         6,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
 113         5,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
 114         4,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
 115         3,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
 116         2,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
 117         1,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
 118         0,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
 119
 120         7,                             /* WL18XX_CONF_HW_RXTX_RATE_54   */
 121         6,                             /* WL18XX_CONF_HW_RXTX_RATE_48   */
 122         5,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
 123         4,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
 124
 125         /* TI-specific rate */
 126         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
 127
 128         3,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
 129         2,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
 130         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11   */
 131         1,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
 132         0,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
 133         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
 134         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2    */
 135         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1    */
 136 };
 137
 138 static const u8 *wl18xx_band_rate_to_idx[] = {
 139         [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
 140         [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
 141 };
 142
 143 enum wl18xx_hw_rates {
 144         WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
 145         WL18XX_CONF_HW_RXTX_RATE_MCS14,
 146         WL18XX_CONF_HW_RXTX_RATE_MCS13,
 147         WL18XX_CONF_HW_RXTX_RATE_MCS12,
 148         WL18XX_CONF_HW_RXTX_RATE_MCS11,
 149         WL18XX_CONF_HW_RXTX_RATE_MCS10,
 150         WL18XX_CONF_HW_RXTX_RATE_MCS9,
 151         WL18XX_CONF_HW_RXTX_RATE_MCS8,
 152         WL18XX_CONF_HW_RXTX_RATE_MCS7,
 153         WL18XX_CONF_HW_RXTX_RATE_MCS6,
 154         WL18XX_CONF_HW_RXTX_RATE_MCS5,
 155         WL18XX_CONF_HW_RXTX_RATE_MCS4,
 156         WL18XX_CONF_HW_RXTX_RATE_MCS3,
 157         WL18XX_CONF_HW_RXTX_RATE_MCS2,
 158         WL18XX_CONF_HW_RXTX_RATE_MCS1,
 159         WL18XX_CONF_HW_RXTX_RATE_MCS0,
 160         WL18XX_CONF_HW_RXTX_RATE_54,
 161         WL18XX_CONF_HW_RXTX_RATE_48,
 162         WL18XX_CONF_HW_RXTX_RATE_36,
 163         WL18XX_CONF_HW_RXTX_RATE_24,
 164         WL18XX_CONF_HW_RXTX_RATE_22,
 165         WL18XX_CONF_HW_RXTX_RATE_18,
 166         WL18XX_CONF_HW_RXTX_RATE_12,
 167         WL18XX_CONF_HW_RXTX_RATE_11,
 168         WL18XX_CONF_HW_RXTX_RATE_9,
 169         WL18XX_CONF_HW_RXTX_RATE_6,
 170         WL18XX_CONF_HW_RXTX_RATE_5_5,
 171         WL18XX_CONF_HW_RXTX_RATE_2,
 172         WL18XX_CONF_HW_RXTX_RATE_1,
 173         WL18XX_CONF_HW_RXTX_RATE_MAX,
 174 };
 175
 176 static struct wlcore_conf wl18xx_conf = {
 177         .sg = {
 178                 .params = {
 179                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
 180                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
 181                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
 182                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
 183                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
 184                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
 185                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
 186                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
 187                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
 188                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
 189                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
 190                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
 191                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
 192                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
 193                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
 194                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
 195                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
 196                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
 197                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
 198                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
 199                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
 200                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
 201                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
 202                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
 203                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
 204                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
 205                         /* active scan params */
 206                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
 207                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
 208                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
 209                         /* passive scan params */
 210                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
 211                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
 212                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
 213                         /* passive scan in dual antenna params */
 214                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
 215                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
 216                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
 217                         /* general params */
 218                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
 219                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
 220                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
 221                         [CONF_SG_DHCP_TIME] = 5000,
 222                         [CONF_SG_RXT] = 1200,
 223                         [CONF_SG_TXT] = 1000,
 224                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
 225                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
 226                         [CONF_SG_HV3_MAX_SERVED] = 6,
 227                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
 228                         [CONF_SG_UPSD_TIMEOUT] = 10,
 229                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 230                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 231                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 232                         /* AP params */
 233                         [CONF_AP_BEACON_MISS_TX] = 3,
 234                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 235                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 236                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 237                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 238                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 239                         /* CTS Diluting params */
 240                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 241                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 242                 },
 243                 .state = CONF_SG_PROTECTIVE,
 244         },
 245         .rx = {
 246                 .rx_msdu_life_time           = 512000,
 247                 .packet_detection_threshold  = 0,
 248                 .ps_poll_timeout             = 15,
 249                 .upsd_timeout                = 15,
 250                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 251                 .rx_cca_threshold            = 0,
 252                 .irq_blk_threshold           = 0xFFFF,
 253                 .irq_pkt_threshold           = 0,
 254                 .irq_timeout                 = 600,
 255                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 256         },
 257         .tx = {
 258                 .tx_energy_detection         = 0,
 259                 .sta_rc_conf                 = {
 260                         .enabled_rates       = 0,
 261                         .short_retry_limit   = 10,
 262                         .long_retry_limit    = 10,
 263                         .aflags              = 0,
 264                 },
 265                 .ac_conf_count               = 4,
 266                 .ac_conf                     = {
 267                         [CONF_TX_AC_BE] = {
 268                                 .ac          = CONF_TX_AC_BE,
 269                                 .cw_min      = 15,
 270                                 .cw_max      = 63,
 271                                 .aifsn       = 3,
 272                                 .tx_op_limit = 0,
 273                         },
 274                         [CONF_TX_AC_BK] = {
 275                                 .ac          = CONF_TX_AC_BK,
 276                                 .cw_min      = 15,
 277                                 .cw_max      = 63,
 278                                 .aifsn       = 7,
 279                                 .tx_op_limit = 0,
 280                         },
 281                         [CONF_TX_AC_VI] = {
 282                                 .ac          = CONF_TX_AC_VI,
 283                                 .cw_min      = 15,
 284                                 .cw_max      = 63,
 285                                 .aifsn       = CONF_TX_AIFS_PIFS,
 286                                 .tx_op_limit = 3008,
 287                         },
 288                         [CONF_TX_AC_VO] = {
 289                                 .ac          = CONF_TX_AC_VO,
 290                                 .cw_min      = 15,
 291                                 .cw_max      = 63,
 292                                 .aifsn       = CONF_TX_AIFS_PIFS,
 293                                 .tx_op_limit = 1504,
 294                         },
 295                 },
 296                 .max_tx_retries = 100,
 297                 .ap_aging_period = 300,
 298                 .tid_conf_count = 4,
 299                 .tid_conf = {
 300                         [CONF_TX_AC_BE] = {
 301                                 .queue_id    = CONF_TX_AC_BE,
 302                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 303                                 .tsid        = CONF_TX_AC_BE,
 304                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 305                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 306                                 .apsd_conf   = {0, 0},
 307                         },
 308                         [CONF_TX_AC_BK] = {
 309                                 .queue_id    = CONF_TX_AC_BK,
 310                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 311                                 .tsid        = CONF_TX_AC_BK,
 312                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 313                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 314                                 .apsd_conf   = {0, 0},
 315                         },
 316                         [CONF_TX_AC_VI] = {
 317                                 .queue_id    = CONF_TX_AC_VI,
 318                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 319                                 .tsid        = CONF_TX_AC_VI,
 320                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 321                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 322                                 .apsd_conf   = {0, 0},
 323                         },
 324                         [CONF_TX_AC_VO] = {
 325                                 .queue_id    = CONF_TX_AC_VO,
 326                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 327                                 .tsid        = CONF_TX_AC_VO,
 328                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 329                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 330                                 .apsd_conf   = {0, 0},
 331                         },
 332                 },
 333                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 334                 .tx_compl_timeout            = 350,
 335                 .tx_compl_threshold          = 10,
 336                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 337                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 338                 .tmpl_short_retry_limit      = 10,
 339                 .tmpl_long_retry_limit       = 10,
 340                 .tx_watchdog_timeout         = 5000,
 341                 .slow_link_thold             = 3,
 342                 .fast_link_thold             = 30,
 343         },
 344         .conn = {
 345                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 346                 .listen_interval             = 1,
 347                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 348                 .suspend_listen_interval     = 3,
 349                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 350                 .bcn_filt_ie_count           = 3,
 351                 .bcn_filt_ie = {
 352                         [0] = {
 353                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 354                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 355                         },
 356                         [1] = {
 357                                 .ie          = WLAN_EID_HT_OPERATION,
 358                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 359                         },
 360                         [2] = {
 361                                 .ie          = WLAN_EID_ERP_INFO,
 362                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 363                         },
 364                 },
 365                 .synch_fail_thold            = 12,
 366                 .bss_lose_timeout            = 400,
 367                 .beacon_rx_timeout           = 10000,
 368                 .broadcast_timeout           = 20000,
 369                 .rx_broadcast_in_ps          = 1,
 370                 .ps_poll_threshold           = 10,
 371                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 372                 .bet_max_consecutive         = 50,
 373                 .psm_entry_retries           = 8,
 374                 .psm_exit_retries            = 16,
 375                 .psm_entry_nullfunc_retries  = 3,
 376                 .dynamic_ps_timeout          = 1500,
 377                 .forced_ps                   = false,
 378                 .keep_alive_interval         = 55000,
 379                 .max_listen_interval         = 20,
 380                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 381         },
 382         .itrim = {
 383                 .enable = false,
 384                 .timeout = 50000,
 385         },
 386         .pm_config = {
 387                 .host_clk_settling_time = 5000,
 388                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 389         },
 390         .roam_trigger = {
 391                 .trigger_pacing               = 1,
 392                 .avg_weight_rssi_beacon       = 20,
 393                 .avg_weight_rssi_data         = 10,
 394                 .avg_weight_snr_beacon        = 20,
 395                 .avg_weight_snr_data          = 10,
 396         },
 397         .scan = {
 398                 .min_dwell_time_active        = 7500,
 399                 .max_dwell_time_active        = 30000,
 400                 .min_dwell_time_active_long   = 25000,
 401                 .max_dwell_time_active_long   = 50000,
 402                 .dwell_time_passive           = 100000,
 403                 .dwell_time_dfs               = 150000,
 404                 .num_probe_reqs               = 2,
 405                 .split_scan_timeout           = 50000,
 406         },
 407         .sched_scan = {
 408                 /*
 409                  * Values are in TU/1000 but since sched scan FW command
 410                  * params are in TUs rounding up may occur.
 411                  */
 412                 .base_dwell_time                = 7500,
 413                 .max_dwell_time_delta           = 22500,
 414                 /* based on 250bits per probe @1Mbps */
 415                 .dwell_time_delta_per_probe     = 2000,
 416                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 417                 .dwell_time_delta_per_probe_5   = 350,
 418                 .dwell_time_passive             = 100000,
 419                 .dwell_time_dfs                 = 150000,
 420                 .num_probe_reqs                 = 2,
 421                 .rssi_threshold                 = -90,
 422                 .snr_threshold                  = 0,
 423         },
 424         .ht = {
 425                 .rx_ba_win_size = 32,
 426                 .tx_ba_win_size = 64,
 427                 .inactivity_timeout = 10000,
 428                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 429         },
 430         .mem = {
 431                 .num_stations                 = 1,
 432                 .ssid_profiles                = 1,
 433                 .rx_block_num                 = 40,
 434                 .tx_min_block_num             = 40,
 435                 .dynamic_memory               = 1,
 436                 .min_req_tx_blocks            = 45,
 437                 .min_req_rx_blocks            = 22,
 438                 .tx_min                       = 27,
 439         },
 440         .fm_coex = {
 441                 .enable                       = true,
 442                 .swallow_period               = 5,
 443                 .n_divider_fref_set_1         = 0xff,       /* default */
 444                 .n_divider_fref_set_2         = 12,
 445                 .m_divider_fref_set_1         = 0xffff,
 446                 .m_divider_fref_set_2         = 148,        /* default */
 447                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 448                 .ldo_stabilization_time       = 0xffff,     /* default */
 449                 .fm_disturbed_band_margin     = 0xff,       /* default */
 450                 .swallow_clk_diff             = 0xff,       /* default */
 451         },
 452         .rx_streaming = {
 453                 .duration                      = 150,
 454                 .queues                        = 0x1,
 455                 .interval                      = 20,
 456                 .always                        = 0,
 457         },
 458         .fwlog = {
 459                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 460                 .mem_blocks                   = 2,
 461                 .severity                     = 0,
 462                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 463                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 464                 .threshold                    = 0,
 465         },
 466         .rate = {
 467                 .rate_retry_score = 32000,
 468                 .per_add = 8192,
 469                 .per_th1 = 2048,
 470                 .per_th2 = 4096,
 471                 .max_per = 8100,
 472                 .inverse_curiosity_factor = 5,
 473                 .tx_fail_low_th = 4,
 474                 .tx_fail_high_th = 10,
 475                 .per_alpha_shift = 4,
 476                 .per_add_shift = 13,
 477                 .per_beta1_shift = 10,
 478                 .per_beta2_shift = 8,
 479                 .rate_check_up = 2,
 480                 .rate_check_down = 12,
 481                 .rate_retry_policy = {
 482                         0x00, 0x00, 0x00, 0x00, 0x00,
 483                         0x00, 0x00, 0x00, 0x00, 0x00,
 484                         0x00, 0x00, 0x00,
 485                 },
 486         },
 487         .hangover = {
 488                 .recover_time               = 0,
 489                 .hangover_period            = 20,
 490                 .dynamic_mode               = 1,
 491                 .early_termination_mode     = 1,
 492                 .max_period                 = 20,
 493                 .min_period                 = 1,
 494                 .increase_delta             = 1,
 495                 .decrease_delta             = 2,
 496                 .quiet_time                 = 4,
 497                 .increase_time              = 1,
 498                 .window_size                = 16,
 499         },
 500         .recovery = {
 501                 .bug_on_recovery            = 0,
 502                 .no_recovery                = 0,
 503         },
 504 };
 505
 506 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
 507         .ht = {
 508                 .mode                           = HT_MODE_DEFAULT,
 509         },
 510         .phy = {
 511                 .phy_standalone                 = 0x00,
 512                 .primary_clock_setting_time     = 0x05,
 513                 .clock_valid_on_wake_up         = 0x00,
 514                 .secondary_clock_setting_time   = 0x05,
 515                 .board_type                     = BOARD_TYPE_HDK_18XX,
 516                 .auto_detect                    = 0x00,
 517                 .dedicated_fem                  = FEM_NONE,
 518                 .low_band_component             = COMPONENT_3_WAY_SWITCH,
 519                 .low_band_component_type        = 0x04,
 520                 .high_band_component            = COMPONENT_2_WAY_SWITCH,
 521                 .high_band_component_type       = 0x09,
 522                 .tcxo_ldo_voltage               = 0x00,
 523                 .xtal_itrim_val                 = 0x04,
 524                 .srf_state                      = 0x00,
 525                 .io_configuration               = 0x01,
 526                 .sdio_configuration             = 0x00,
 527                 .settings                       = 0x00,
 528                 .enable_clpc                    = 0x00,
 529                 .enable_tx_low_pwr_on_siso_rdl  = 0x00,
 530                 .rx_profile                     = 0x00,
 531                 .pwr_limit_reference_11_abg     = 0x64,
 532                 .per_chan_pwr_limit_arr_11abg   = {
 533                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 534                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 535                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 536                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 537                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 538                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 539                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 540                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 541                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 542                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 543                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 544                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 545                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 546                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 547                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 548                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 549                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
 550                 .pwr_limit_reference_11p        = 0x64,
 551                 .per_chan_bo_mode_11_abg        = { 0x00, 0x00, 0x00, 0x00,
 552                                                     0x00, 0x00, 0x00, 0x00,
 553                                                     0x00, 0x00, 0x00, 0x00,
 554                                                     0x00 },
 555                 .per_chan_bo_mode_11_p          = { 0x00, 0x00, 0x00, 0x00 },
 556                 .per_chan_pwr_limit_arr_11p     = { 0xff, 0xff, 0xff, 0xff,
 557                                                     0xff, 0xff, 0xff },
 558                 .psat                           = 0,
 559                 .low_power_val                  = 0x08,
 560                 .med_power_val                  = 0x12,
 561                 .high_power_val                 = 0x18,
 562                 .low_power_val_2nd              = 0x05,
 563                 .med_power_val_2nd              = 0x0a,
 564                 .high_power_val_2nd             = 0x14,
 565                 .external_pa_dc2dc              = 0,
 566                 .number_of_assembled_ant2_4     = 2,
 567                 .number_of_assembled_ant5       = 1,
 568                 .tx_rf_margin                   = 1,
 569         },
 570 };
 571
 572 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
 573         [PART_TOP_PRCM_ELP_SOC] = {
 574                 .mem  = { .start = 0x00A02000, .size  = 0x00010000 },
 575                 .reg  = { .start = 0x00807000, .size  = 0x00005000 },
 576                 .mem2 = { .start = 0x00800000, .size  = 0x0000B000 },
 577                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 578         },
 579         [PART_DOWN] = {
 580                 .mem  = { .start = 0x00000000, .size  = 0x00014000 },
 581                 .reg  = { .start = 0x00810000, .size  = 0x0000BFFF },
 582                 .mem2 = { .start = 0x00000000, .size  = 0x00000000 },
 583                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 584         },
 585         [PART_BOOT] = {
 586                 .mem  = { .start = 0x00700000, .size = 0x0000030c },
 587                 .reg  = { .start = 0x00802000, .size = 0x00014578 },
 588                 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
 589                 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
 590         },
 591         [PART_WORK] = {
 592                 .mem  = { .start = 0x00800000, .size  = 0x000050FC },
 593                 .reg  = { .start = 0x00B00404, .size  = 0x00001000 },
 594                 .mem2 = { .start = 0x00C00000, .size  = 0x00000400 },
 595                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 596         },
 597         [PART_PHY_INIT] = {
 598                 .mem  = { .start = WL18XX_PHY_INIT_MEM_ADDR,
 599                           .size  = WL18XX_PHY_INIT_MEM_SIZE },
 600                 .reg  = { .start = 0x00000000, .size = 0x00000000 },
 601                 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
 602                 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
 603         },
 604 };
 605
 606 static const int wl18xx_rtable[REG_TABLE_LEN] = {
 607         [REG_ECPU_CONTROL]              = WL18XX_REG_ECPU_CONTROL,
 608         [REG_INTERRUPT_NO_CLEAR]        = WL18XX_REG_INTERRUPT_NO_CLEAR,
 609         [REG_INTERRUPT_ACK]             = WL18XX_REG_INTERRUPT_ACK,
 610         [REG_COMMAND_MAILBOX_PTR]       = WL18XX_REG_COMMAND_MAILBOX_PTR,
 611         [REG_EVENT_MAILBOX_PTR]         = WL18XX_REG_EVENT_MAILBOX_PTR,
 612         [REG_INTERRUPT_TRIG]            = WL18XX_REG_INTERRUPT_TRIG_H,
 613         [REG_INTERRUPT_MASK]            = WL18XX_REG_INTERRUPT_MASK,
 614         [REG_PC_ON_RECOVERY]            = WL18XX_SCR_PAD4,
 615         [REG_CHIP_ID_B]                 = WL18XX_REG_CHIP_ID_B,
 616         [REG_CMD_MBOX_ADDRESS]          = WL18XX_CMD_MBOX_ADDRESS,
 617
 618         /* data access memory addresses, used with partition translation */
 619         [REG_SLV_MEM_DATA]              = WL18XX_SLV_MEM_DATA,
 620         [REG_SLV_REG_DATA]              = WL18XX_SLV_REG_DATA,
 621
 622         /* raw data access memory addresses */
 623         [REG_RAW_FW_STATUS_ADDR]        = WL18XX_FW_STATUS_ADDR,
 624 };
 625
 626 static const struct wl18xx_clk_cfg wl18xx_clk_table_coex[NUM_CLOCK_CONFIGS] = {
 627         [CLOCK_CONFIG_16_2_M]   = { 8,  121, 0, 0, false },
 628         [CLOCK_CONFIG_16_368_M] = { 8,  120, 0, 0, false },
 629         [CLOCK_CONFIG_16_8_M]   = { 8,  117, 0, 0, false },
 630         [CLOCK_CONFIG_19_2_M]   = { 10, 128, 0, 0, false },
 631         [CLOCK_CONFIG_26_M]     = { 11, 104, 0, 0, false },
 632         [CLOCK_CONFIG_32_736_M] = { 8,  120, 0, 0, false },
 633         [CLOCK_CONFIG_33_6_M]   = { 8,  117, 0, 0, false },
 634         [CLOCK_CONFIG_38_468_M] = { 10, 128, 0, 0, false },
 635         [CLOCK_CONFIG_52_M]     = { 11, 104, 0, 0, false },
 636 };
 637
 638 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
 639         [CLOCK_CONFIG_16_2_M]   = { 7,  104,  801, 4,  true },
 640         [CLOCK_CONFIG_16_368_M] = { 9,  132, 3751, 4,  true },
 641         [CLOCK_CONFIG_16_8_M]   = { 7,  100,    0, 0, false },
 642         [CLOCK_CONFIG_19_2_M]   = { 8,  100,    0, 0, false },
 643         [CLOCK_CONFIG_26_M]     = { 13, 120,    0, 0, false },
 644         [CLOCK_CONFIG_32_736_M] = { 9,  132, 3751, 4,  true },
 645         [CLOCK_CONFIG_33_6_M]   = { 7,  100,    0, 0, false },
 646         [CLOCK_CONFIG_38_468_M] = { 8,  100,    0, 0, false },
 647         [CLOCK_CONFIG_52_M]     = { 13, 120,    0, 0, false },
 648 };
 649
 650 /* TODO: maybe move to a new header file? */
 651 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-2.bin"
 652
 653 static int wl18xx_identify_chip(struct wl1271 *wl)
 654 {
 655         int ret = 0;
 656
 657         switch (wl->chip.id) {
 658         case CHIP_ID_185x_PG20:
 659                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
 660                                  wl->chip.id);
 661                 wl->sr_fw_name = WL18XX_FW_NAME;
 662                 /* wl18xx uses the same firmware for PLT */
 663                 wl->plt_fw_name = WL18XX_FW_NAME;
 664                 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
 665                               WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 666                               WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
 667                               WLCORE_QUIRK_TX_PAD_LAST_FRAME |
 668                               WLCORE_QUIRK_REGDOMAIN_CONF |
 669                               WLCORE_QUIRK_DUAL_PROBE_TMPL;
 670
 671                 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
 672                                       WL18XX_IFTYPE_VER,  WL18XX_MAJOR_VER,
 673                                       WL18XX_SUBTYPE_VER, WL18XX_MINOR_VER,
 674                                       /* there's no separate multi-role FW */
 675                                       0, 0, 0, 0);
 676                 break;
 677         case CHIP_ID_185x_PG10:
 678                 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
 679                                wl->chip.id);
 680                 ret = -ENODEV;
 681                 goto out;
 682
 683         default:
 684                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 685                 ret = -ENODEV;
 686                 goto out;
 687         }
 688
 689         wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
 690         wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
 691         wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
 692         wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
 693         wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
 694         wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS;
 695 out:
 696         return ret;
 697 }
 698
 699 static int wl18xx_set_clk(struct wl1271 *wl)
 700 {
 701         u16 clk_freq;
 702         int ret;
 703
 704         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 705         if (ret < 0)
 706                 goto out;
 707
 708         /* TODO: PG2: apparently we need to read the clk type */
 709
 710         ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
 711         if (ret < 0)
 712                 goto out;
 713
 714         wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
 715                      wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
 716                      wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
 717                      wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
 718
 719         /* coex PLL configuration */
 720         ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N,
 721                                    wl18xx_clk_table_coex[clk_freq].n);
 722         if (ret < 0)
 723                 goto out;
 724
 725         ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M,
 726                                    wl18xx_clk_table_coex[clk_freq].m);
 727         if (ret < 0)
 728                 goto out;
 729
 730         /* bypass the swallowing logic */
 731         ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
 732                                    PLLSH_COEX_PLL_SWALLOW_EN_VAL1);
 733         if (ret < 0)
 734                 goto out;
 735
 736         ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
 737                                    wl18xx_clk_table[clk_freq].n);
 738         if (ret < 0)
 739                 goto out;
 740
 741         ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
 742                                    wl18xx_clk_table[clk_freq].m);
 743         if (ret < 0)
 744                 goto out;
 745
 746         if (wl18xx_clk_table[clk_freq].swallow) {
 747                 /* first the 16 lower bits */
 748                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
 749                                            wl18xx_clk_table[clk_freq].q &
 750                                            PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
 751                 if (ret < 0)
 752                         goto out;
 753
 754                 /* then the 16 higher bits, masked out */
 755                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
 756                                         (wl18xx_clk_table[clk_freq].q >> 16) &
 757                                         PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
 758                 if (ret < 0)
 759                         goto out;
 760
 761                 /* first the 16 lower bits */
 762                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
 763                                            wl18xx_clk_table[clk_freq].p &
 764                                            PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
 765                 if (ret < 0)
 766                         goto out;
 767
 768                 /* then the 16 higher bits, masked out */
 769                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
 770                                         (wl18xx_clk_table[clk_freq].p >> 16) &
 771                                         PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
 772         } else {
 773                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
 774                                            PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
 775         }
 776
 777         /* choose WCS PLL */
 778         ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL,
 779                                    PLLSH_WL_PLL_SEL_WCS_PLL);
 780         if (ret < 0)
 781                 goto out;
 782
 783         /* enable both PLLs */
 784         ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1);
 785         if (ret < 0)
 786                 goto out;
 787
 788         udelay(1000);
 789
 790         /* disable coex PLL */
 791         ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2);
 792         if (ret < 0)
 793                 goto out;
 794
 795         /* reset the swallowing logic */
 796         ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
 797                                    PLLSH_COEX_PLL_SWALLOW_EN_VAL2);
 798         if (ret < 0)
 799                 goto out;
 800
 801 out:
 802         return ret;
 803 }
 804
 805 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
 806 {
 807         int ret;
 808
 809         /* disable Rx/Tx */
 810         ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
 811         if (ret < 0)
 812                 goto out;
 813
 814         /* disable auto calibration on start*/
 815         ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
 816
 817 out:
 818         return ret;
 819 }
 820
 821 static int wl18xx_pre_boot(struct wl1271 *wl)
 822 {
 823         int ret;
 824
 825         ret = wl18xx_set_clk(wl);
 826         if (ret < 0)
 827                 goto out;
 828
 829         /* Continue the ELP wake up sequence */
 830         ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 831         if (ret < 0)
 832                 goto out;
 833
 834         udelay(500);
 835
 836         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 837         if (ret < 0)
 838                 goto out;
 839
 840         /* Disable interrupts */
 841         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 842         if (ret < 0)
 843                 goto out;
 844
 845         ret = wl18xx_boot_soft_reset(wl);
 846
 847 out:
 848         return ret;
 849 }
 850
 851 static int wl18xx_pre_upload(struct wl1271 *wl)
 852 {
 853         u32 tmp;
 854         int ret;
 855
 856         BUILD_BUG_ON(sizeof(struct wl18xx_mac_and_phy_params) >
 857                 WL18XX_PHY_INIT_MEM_SIZE);
 858
 859         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 860         if (ret < 0)
 861                 goto out;
 862
 863         /* TODO: check if this is all needed */
 864         ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 865         if (ret < 0)
 866                 goto out;
 867
 868         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
 869         if (ret < 0)
 870                 goto out;
 871
 872         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 873
 874         ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
 875         if (ret < 0)
 876                 goto out;
 877
 878         /*
 879          * Workaround for FDSP code RAM corruption (needed for PG2.1
 880          * and newer; for older chips it's a NOP).  Change FDSP clock
 881          * settings so that it's muxed to the ATGP clock instead of
 882          * its own clock.
 883          */
 884
 885         ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 886         if (ret < 0)
 887                 goto out;
 888
 889         /* disable FDSP clock */
 890         ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
 891                              MEM_FDSP_CLK_120_DISABLE);
 892         if (ret < 0)
 893                 goto out;
 894
 895         /* set ATPG clock toward FDSP Code RAM rather than its own clock */
 896         ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
 897                              MEM_FDSP_CODERAM_FUNC_CLK_SEL);
 898         if (ret < 0)
 899                 goto out;
 900
 901         /* re-enable FDSP clock */
 902         ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
 903                              MEM_FDSP_CLK_120_ENABLE);
 904
 905 out:
 906         return ret;
 907 }
 908
 909 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
 910 {
 911         struct wl18xx_priv *priv = wl->priv;
 912         struct wl18xx_mac_and_phy_params *params;
 913         int ret;
 914
 915         params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
 916         if (!params) {
 917                 ret = -ENOMEM;
 918                 goto out;
 919         }
 920
 921         ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 922         if (ret < 0)
 923                 goto out;
 924
 925         ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
 926                            sizeof(*params), false);
 927
 928 out:
 929         kfree(params);
 930         return ret;
 931 }
 932
 933 static int wl18xx_enable_interrupts(struct wl1271 *wl)
 934 {
 935         u32 event_mask, intr_mask;
 936         int ret;
 937
 938         event_mask = WL18XX_ACX_EVENTS_VECTOR;
 939         intr_mask = WL18XX_INTR_MASK;
 940
 941         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
 942         if (ret < 0)
 943                 goto out;
 944
 945         wlcore_enable_interrupts(wl);
 946
 947         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
 948                                WL1271_ACX_INTR_ALL & ~intr_mask);
 949         if (ret < 0)
 950                 goto disable_interrupts;
 951
 952         return ret;
 953
 954 disable_interrupts:
 955         wlcore_disable_interrupts(wl);
 956
 957 out:
 958         return ret;
 959 }
 960
 961 static int wl18xx_boot(struct wl1271 *wl)
 962 {
 963         int ret;
 964
 965         ret = wl18xx_pre_boot(wl);
 966         if (ret < 0)
 967                 goto out;
 968
 969         ret = wl18xx_pre_upload(wl);
 970         if (ret < 0)
 971                 goto out;
 972
 973         ret = wlcore_boot_upload_firmware(wl);
 974         if (ret < 0)
 975                 goto out;
 976
 977         ret = wl18xx_set_mac_and_phy(wl);
 978         if (ret < 0)
 979                 goto out;
 980
 981         wl->event_mask = BSS_LOSS_EVENT_ID |
 982                 SCAN_COMPLETE_EVENT_ID |
 983                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 984                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
 985                 PERIODIC_SCAN_REPORT_EVENT_ID |
 986                 DUMMY_PACKET_EVENT_ID |
 987                 PEER_REMOVE_COMPLETE_EVENT_ID |
 988                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
 989                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
 990                 INACTIVE_STA_EVENT_ID |
 991                 MAX_TX_FAILURE_EVENT_ID |
 992                 CHANNEL_SWITCH_COMPLETE_EVENT_ID |
 993                 DFS_CHANNELS_CONFIG_COMPLETE_EVENT;
 994
 995         ret = wlcore_boot_run_firmware(wl);
 996         if (ret < 0)
 997                 goto out;
 998
 999         ret = wl18xx_enable_interrupts(wl);
1000
1001 out:
1002         return ret;
1003 }
1004
1005 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1006                                void *buf, size_t len)
1007 {
1008         struct wl18xx_priv *priv = wl->priv;
1009
1010         memcpy(priv->cmd_buf, buf, len);
1011         memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
1012
1013         return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
1014                             WL18XX_CMD_MAX_SIZE, false);
1015 }
1016
1017 static int wl18xx_ack_event(struct wl1271 *wl)
1018 {
1019         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1020                                 WL18XX_INTR_TRIG_EVENT_ACK);
1021 }
1022
1023 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1024 {
1025         u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
1026         return (len + blk_size - 1) / blk_size + spare_blks;
1027 }
1028
1029 static void
1030 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1031                           u32 blks, u32 spare_blks)
1032 {
1033         desc->wl18xx_mem.total_mem_blocks = blks;
1034 }
1035
1036 static void
1037 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1038                             struct sk_buff *skb)
1039 {
1040         desc->length = cpu_to_le16(skb->len);
1041
1042         /* if only the last frame is to be padded, we unset this bit on Tx */
1043         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
1044                 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
1045         else
1046                 desc->wl18xx_mem.ctrl = 0;
1047
1048         wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
1049                      "len: %d life: %d mem: %d", desc->hlid,
1050                      le16_to_cpu(desc->length),
1051                      le16_to_cpu(desc->life_time),
1052                      desc->wl18xx_mem.total_mem_blocks);
1053 }
1054
1055 static enum wl_rx_buf_align
1056 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1057 {
1058         if (rx_desc & RX_BUF_PADDED_PAYLOAD)
1059                 return WLCORE_RX_BUF_PADDED;
1060
1061         return WLCORE_RX_BUF_ALIGNED;
1062 }
1063
1064 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1065                                     u32 data_len)
1066 {
1067         struct wl1271_rx_descriptor *desc = rx_data;
1068
1069         /* invalid packet */
1070         if (data_len < sizeof(*desc))
1071                 return 0;
1072
1073         return data_len - sizeof(*desc);
1074 }
1075
1076 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
1077 {
1078         wl18xx_tx_immediate_complete(wl);
1079 }
1080
1081 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
1082 {
1083         int ret;
1084         u32 sdio_align_size = 0;
1085         u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
1086                               HOST_IF_CFG_ADD_RX_ALIGNMENT;
1087
1088         /* Enable Tx SDIO padding */
1089         if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
1090                 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1091                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1092         }
1093
1094         /* Enable Rx SDIO padding */
1095         if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1096                 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
1097                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1098         }
1099
1100         ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
1101                                             sdio_align_size, extra_mem_blk,
1102                                             WL18XX_HOST_IF_LEN_SIZE_FIELD);
1103         if (ret < 0)
1104                 return ret;
1105
1106         return 0;
1107 }
1108
1109 static int wl18xx_hw_init(struct wl1271 *wl)
1110 {
1111         int ret;
1112         struct wl18xx_priv *priv = wl->priv;
1113
1114         /* (re)init private structures. Relevant on recovery as well. */
1115         priv->last_fw_rls_idx = 0;
1116         priv->extra_spare_key_count = 0;
1117
1118         /* set the default amount of spare blocks in the bitmap */
1119         ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1120         if (ret < 0)
1121                 return ret;
1122
1123         if (checksum_param) {
1124                 ret = wl18xx_acx_set_checksum_state(wl);
1125                 if (ret != 0)
1126                         return ret;
1127         }
1128
1129         return ret;
1130 }
1131
1132 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1133                                     struct wl1271_tx_hw_descr *desc,
1134                                     struct sk_buff *skb)
1135 {
1136         u32 ip_hdr_offset;
1137         struct iphdr *ip_hdr;
1138
1139         if (!checksum_param) {
1140                 desc->wl18xx_checksum_data = 0;
1141                 return;
1142         }
1143
1144         if (skb->ip_summed != CHECKSUM_PARTIAL) {
1145                 desc->wl18xx_checksum_data = 0;
1146                 return;
1147         }
1148
1149         ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1150         if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1151                 desc->wl18xx_checksum_data = 0;
1152                 return;
1153         }
1154
1155         desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1156
1157         /* FW is interested only in the LSB of the protocol  TCP=0 UDP=1 */
1158         ip_hdr = (void *)skb_network_header(skb);
1159         desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1160 }
1161
1162 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1163                                struct wl1271_rx_descriptor *desc,
1164                                struct sk_buff *skb)
1165 {
1166         if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1167                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1168 }
1169
1170 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1171 {
1172         struct wl18xx_priv *priv = wl->priv;
1173
1174         /* only support MIMO with multiple antennas, and when SISO
1175          * is not forced through config
1176          */
1177         return (priv->conf.phy.number_of_assembled_ant2_4 >= 2) &&
1178                (priv->conf.ht.mode != HT_MODE_WIDE) &&
1179                (priv->conf.ht.mode != HT_MODE_SISO20);
1180 }
1181
1182 /*
1183  * TODO: instead of having these two functions to get the rate mask,
1184  * we should modify the wlvif->rate_set instead
1185  */
1186 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1187                                        struct wl12xx_vif *wlvif)
1188 {
1189         u32 hw_rate_set = wlvif->rate_set;
1190
1191         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1192             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1193                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1194                 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1195
1196                 /* we don't support MIMO in wide-channel mode */
1197                 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1198         } else if (wl18xx_is_mimo_supported(wl)) {
1199                 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1200                 hw_rate_set |= CONF_TX_MIMO_RATES;
1201         }
1202
1203         return hw_rate_set;
1204 }
1205
1206 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1207                                              struct wl12xx_vif *wlvif)
1208 {
1209         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1210             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1211                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1212
1213                 /* sanity check - we don't support this */
1214                 if (WARN_ON(wlvif->band != IEEE80211_BAND_5GHZ))
1215                         return 0;
1216
1217                 return CONF_TX_RATE_USE_WIDE_CHAN;
1218         } else if (wl18xx_is_mimo_supported(wl) &&
1219                    wlvif->band == IEEE80211_BAND_2GHZ) {
1220                 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1221                 /*
1222                  * we don't care about HT channel here - if a peer doesn't
1223                  * support MIMO, we won't enable it in its rates
1224                  */
1225                 return CONF_TX_MIMO_RATES;
1226         } else {
1227                 return 0;
1228         }
1229 }
1230
1231 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1232 {
1233         u32 fuse;
1234         s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0;
1235         int ret;
1236
1237         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1238         if (ret < 0)
1239                 goto out;
1240
1241         ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1242         if (ret < 0)
1243                 goto out;
1244
1245         pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1246         rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET;
1247
1248         if (rom <= 0xE)
1249                 metal = (fuse & WL18XX_METAL_VER_MASK) >>
1250                         WL18XX_METAL_VER_OFFSET;
1251         else
1252                 metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >>
1253                         WL18XX_NEW_METAL_VER_OFFSET;
1254
1255         ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1256         if (ret < 0)
1257                 goto out;
1258
1259         rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET;
1260         if (rdl_ver > RDL_MAX)
1261                 rdl_ver = RDL_NONE;
1262
1263         wl1271_info("wl18xx HW: RDL %d, %s, PG %x.%x (ROM %x)",
1264                     rdl_ver, rdl_names[rdl_ver], pg_ver, metal, rom);
1265
1266         if (ver)
1267                 *ver = pg_ver;
1268
1269         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1270
1271 out:
1272         return ret;
1273 }
1274
1275 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1276 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1277 {
1278         struct wl18xx_priv *priv = wl->priv;
1279         struct wlcore_conf_file *conf_file;
1280         const struct firmware *fw;
1281         int ret;
1282
1283         ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1284         if (ret < 0) {
1285                 wl1271_error("could not get configuration binary %s: %d",
1286                              WL18XX_CONF_FILE_NAME, ret);
1287                 goto out_fallback;
1288         }
1289
1290         if (fw->size != WL18XX_CONF_SIZE) {
1291                 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1292                              WL18XX_CONF_SIZE, fw->size);
1293                 ret = -EINVAL;
1294                 goto out;
1295         }
1296
1297         conf_file = (struct wlcore_conf_file *) fw->data;
1298
1299         if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1300                 wl1271_error("configuration binary file magic number mismatch, "
1301                              "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1302                              conf_file->header.magic);
1303                 ret = -EINVAL;
1304                 goto out;
1305         }
1306
1307         if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1308                 wl1271_error("configuration binary file version not supported, "
1309                              "expected 0x%08x got 0x%08x",
1310                              WL18XX_CONF_VERSION, conf_file->header.version);
1311                 ret = -EINVAL;
1312                 goto out;
1313         }
1314
1315         memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1316         memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1317
1318         goto out;
1319
1320 out_fallback:
1321         wl1271_warning("falling back to default config");
1322
1323         /* apply driver default configuration */
1324         memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1325         /* apply default private configuration */
1326         memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1327
1328         /* For now we just fallback */
1329         return 0;
1330
1331 out:
1332         release_firmware(fw);
1333         return ret;
1334 }
1335
1336 static int wl18xx_plt_init(struct wl1271 *wl)
1337 {
1338         int ret;
1339
1340         /* calibrator based auto/fem detect not supported for 18xx */
1341         if (wl->plt_mode == PLT_FEM_DETECT) {
1342                 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1343                 return -EINVAL;
1344         }
1345
1346         ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1347         if (ret < 0)
1348                 return ret;
1349
1350         return wl->ops->boot(wl);
1351 }
1352
1353 static int wl18xx_get_mac(struct wl1271 *wl)
1354 {
1355         u32 mac1, mac2;
1356         int ret;
1357
1358         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1359         if (ret < 0)
1360                 goto out;
1361
1362         ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1363         if (ret < 0)
1364                 goto out;
1365
1366         ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1367         if (ret < 0)
1368                 goto out;
1369
1370         /* these are the two parts of the BD_ADDR */
1371         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1372                 ((mac1 & 0xff000000) >> 24);
1373         wl->fuse_nic_addr = (mac1 & 0xffffff);
1374
1375         if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) {
1376                 u8 mac[ETH_ALEN];
1377
1378                 eth_random_addr(mac);
1379
1380                 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2];
1381                 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5];
1382                 wl1271_warning("MAC address from fuse not available, using random locally administered addresses.");
1383         }
1384
1385         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1386
1387 out:
1388         return ret;
1389 }
1390
1391 static int wl18xx_handle_static_data(struct wl1271 *wl,
1392                                      struct wl1271_static_data *static_data)
1393 {
1394         struct wl18xx_static_data_priv *static_data_priv =
1395                 (struct wl18xx_static_data_priv *) static_data->priv;
1396
1397         strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1398                 sizeof(wl->chip.phy_fw_ver_str));
1399
1400         /* make sure the string is NULL-terminated */
1401         wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0';
1402
1403         wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1404
1405         return 0;
1406 }
1407
1408 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1409 {
1410         struct wl18xx_priv *priv = wl->priv;
1411
1412         /* If we have keys requiring extra spare, indulge them */
1413         if (priv->extra_spare_key_count)
1414                 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1415
1416         return WL18XX_TX_HW_BLOCK_SPARE;
1417 }
1418
1419 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1420                           struct ieee80211_vif *vif,
1421                           struct ieee80211_sta *sta,
1422                           struct ieee80211_key_conf *key_conf)
1423 {
1424         struct wl18xx_priv *priv = wl->priv;
1425         bool change_spare = false, special_enc;
1426         int ret;
1427
1428         wl1271_debug(DEBUG_CRYPT, "extra spare keys before: %d",
1429                      priv->extra_spare_key_count);
1430
1431         special_enc = key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1432                       key_conf->cipher == WLAN_CIPHER_SUITE_TKIP;
1433
1434         ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1435         if (ret < 0)
1436                 goto out;
1437
1438         /*
1439          * when adding the first or removing the last GEM/TKIP key,
1440          * we have to adjust the number of spare blocks.
1441          */
1442         if (special_enc) {
1443                 if (cmd == SET_KEY) {
1444                         /* first key */
1445                         change_spare = (priv->extra_spare_key_count == 0);
1446                         priv->extra_spare_key_count++;
1447                 } else if (cmd == DISABLE_KEY) {
1448                         /* last key */
1449                         change_spare = (priv->extra_spare_key_count == 1);
1450                         priv->extra_spare_key_count--;
1451                 }
1452         }
1453
1454         wl1271_debug(DEBUG_CRYPT, "extra spare keys after: %d",
1455                      priv->extra_spare_key_count);
1456
1457         if (!change_spare)
1458                 goto out;
1459
1460         /* key is now set, change the spare blocks */
1461         if (priv->extra_spare_key_count)
1462                 ret = wl18xx_set_host_cfg_bitmap(wl,
1463                                         WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1464         else
1465                 ret = wl18xx_set_host_cfg_bitmap(wl,
1466                                         WL18XX_TX_HW_BLOCK_SPARE);
1467
1468 out:
1469         return ret;
1470 }
1471
1472 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1473                                u32 buf_offset, u32 last_len)
1474 {
1475         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1476                 struct wl1271_tx_hw_descr *last_desc;
1477
1478                 /* get the last TX HW descriptor written to the aggr buf */
1479                 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1480                                                         buf_offset - last_len);
1481
1482                 /* the last frame is padded up to an SDIO block */
1483                 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1484                 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1485         }
1486
1487         /* no modifications */
1488         return buf_offset;
1489 }
1490
1491 static void wl18xx_sta_rc_update(struct wl1271 *wl,
1492                                  struct wl12xx_vif *wlvif,
1493                                  struct ieee80211_sta *sta,
1494                                  u32 changed)
1495 {
1496         bool wide = sta->bandwidth >= IEEE80211_STA_RX_BW_40;
1497
1498         wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update wide %d", wide);
1499
1500         if (!(changed & IEEE80211_RC_BW_CHANGED))
1501                 return;
1502
1503         mutex_lock(&wl->mutex);
1504
1505         /* sanity */
1506         if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS))
1507                 goto out;
1508
1509         /* ignore the change before association */
1510         if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags))
1511                 goto out;
1512
1513         /*
1514          * If we started out as wide, we can change the operation mode. If we
1515          * thought this was a 20mhz AP, we have to reconnect
1516          */
1517         if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS ||
1518             wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS)
1519                 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1520         else
1521                 ieee80211_connection_loss(wl12xx_wlvif_to_vif(wlvif));
1522
1523 out:
1524         mutex_unlock(&wl->mutex);
1525 }
1526
1527 static int wl18xx_set_peer_cap(struct wl1271 *wl,
1528                                struct ieee80211_sta_ht_cap *ht_cap,
1529                                bool allow_ht_operation,
1530                                u32 rate_set, u8 hlid)
1531 {
1532         return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1533                                        rate_set, hlid);
1534 }
1535
1536 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1537                                  struct wl1271_link *lnk)
1538 {
1539         u8 thold;
1540         struct wl18xx_fw_status_priv *status_priv =
1541                 (struct wl18xx_fw_status_priv *)wl->fw_status_2->priv;
1542         u32 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1543
1544         /* suspended links are never high priority */
1545         if (test_bit(hlid, (unsigned long *)&suspend_bitmap))
1546                 return false;
1547
1548         /* the priority thresholds are taken from FW */
1549         if (test_bit(hlid, (unsigned long *)&wl->fw_fast_lnk_map) &&
1550             !test_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map))
1551                 thold = status_priv->tx_fast_link_prio_threshold;
1552         else
1553                 thold = status_priv->tx_slow_link_prio_threshold;
1554
1555         return lnk->allocated_pkts < thold;
1556 }
1557
1558 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1559                                 struct wl1271_link *lnk)
1560 {
1561         u8 thold;
1562         struct wl18xx_fw_status_priv *status_priv =
1563                 (struct wl18xx_fw_status_priv *)wl->fw_status_2->priv;
1564         u32 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1565
1566         if (test_bit(hlid, (unsigned long *)&suspend_bitmap))
1567                 thold = status_priv->tx_suspend_threshold;
1568         else if (test_bit(hlid, (unsigned long *)&wl->fw_fast_lnk_map) &&
1569                  !test_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map))
1570                 thold = status_priv->tx_fast_stop_threshold;
1571         else
1572                 thold = status_priv->tx_slow_stop_threshold;
1573
1574         return lnk->allocated_pkts < thold;
1575 }
1576
1577 static int wl18xx_setup(struct wl1271 *wl);
1578
1579 static struct wlcore_ops wl18xx_ops = {
1580         .setup          = wl18xx_setup,
1581         .identify_chip  = wl18xx_identify_chip,
1582         .boot           = wl18xx_boot,
1583         .plt_init       = wl18xx_plt_init,
1584         .trigger_cmd    = wl18xx_trigger_cmd,
1585         .ack_event      = wl18xx_ack_event,
1586         .wait_for_event = wl18xx_wait_for_event,
1587         .process_mailbox_events = wl18xx_process_mailbox_events,
1588         .calc_tx_blocks = wl18xx_calc_tx_blocks,
1589         .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1590         .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1591         .get_rx_buf_align = wl18xx_get_rx_buf_align,
1592         .get_rx_packet_len = wl18xx_get_rx_packet_len,
1593         .tx_immediate_compl = wl18xx_tx_immediate_completion,
1594         .tx_delayed_compl = NULL,
1595         .hw_init        = wl18xx_hw_init,
1596         .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1597         .get_pg_ver     = wl18xx_get_pg_ver,
1598         .set_rx_csum = wl18xx_set_rx_csum,
1599         .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1600         .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1601         .get_mac        = wl18xx_get_mac,
1602         .debugfs_init   = wl18xx_debugfs_add_files,
1603         .scan_start     = wl18xx_scan_start,
1604         .scan_stop      = wl18xx_scan_stop,
1605         .sched_scan_start       = wl18xx_sched_scan_start,
1606         .sched_scan_stop        = wl18xx_scan_sched_scan_stop,
1607         .handle_static_data     = wl18xx_handle_static_data,
1608         .get_spare_blocks = wl18xx_get_spare_blocks,
1609         .set_key        = wl18xx_set_key,
1610         .channel_switch = wl18xx_cmd_channel_switch,
1611         .pre_pkt_send   = wl18xx_pre_pkt_send,
1612         .sta_rc_update  = wl18xx_sta_rc_update,
1613         .set_peer_cap   = wl18xx_set_peer_cap,
1614         .lnk_high_prio  = wl18xx_lnk_high_prio,
1615         .lnk_low_prio   = wl18xx_lnk_low_prio,
1616 };
1617
1618 /* HT cap appropriate for wide channels in 2Ghz */
1619 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1620         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1621                IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40 |
1622                IEEE80211_HT_CAP_GRN_FLD,
1623         .ht_supported = true,
1624         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1625         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1626         .mcs = {
1627                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1628                 .rx_highest = cpu_to_le16(150),
1629                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1630                 },
1631 };
1632
1633 /* HT cap appropriate for wide channels in 5Ghz */
1634 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1635         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1636                IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1637                IEEE80211_HT_CAP_GRN_FLD,
1638         .ht_supported = true,
1639         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1640         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1641         .mcs = {
1642                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1643                 .rx_highest = cpu_to_le16(150),
1644                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1645                 },
1646 };
1647
1648 /* HT cap appropriate for SISO 20 */
1649 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1650         .cap = IEEE80211_HT_CAP_SGI_20 |
1651                IEEE80211_HT_CAP_GRN_FLD,
1652         .ht_supported = true,
1653         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1654         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1655         .mcs = {
1656                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1657                 .rx_highest = cpu_to_le16(72),
1658                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1659                 },
1660 };
1661
1662 /* HT cap appropriate for MIMO rates in 20mhz channel */
1663 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1664         .cap = IEEE80211_HT_CAP_SGI_20 |
1665                IEEE80211_HT_CAP_GRN_FLD,
1666         .ht_supported = true,
1667         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1668         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1669         .mcs = {
1670                 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1671                 .rx_highest = cpu_to_le16(144),
1672                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1673                 },
1674 };
1675
1676 static int wl18xx_setup(struct wl1271 *wl)
1677 {
1678         struct wl18xx_priv *priv = wl->priv;
1679         int ret;
1680
1681         wl->rtable = wl18xx_rtable;
1682         wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1683         wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS;
1684         wl->num_channels = 2;
1685         wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1686         wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1687         wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1688         wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1689         wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1690         wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1691         wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1692
1693         if (num_rx_desc_param != -1)
1694                 wl->num_rx_desc = num_rx_desc_param;
1695
1696         ret = wl18xx_conf_init(wl, wl->dev);
1697         if (ret < 0)
1698                 return ret;
1699
1700         /* If the module param is set, update it in conf */
1701         if (board_type_param) {
1702                 if (!strcmp(board_type_param, "fpga")) {
1703                         priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1704                 } else if (!strcmp(board_type_param, "hdk")) {
1705                         priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1706                 } else if (!strcmp(board_type_param, "dvp")) {
1707                         priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1708                 } else if (!strcmp(board_type_param, "evb")) {
1709                         priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1710                 } else if (!strcmp(board_type_param, "com8")) {
1711                         priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1712                 } else {
1713                         wl1271_error("invalid board type '%s'",
1714                                 board_type_param);
1715                         return -EINVAL;
1716                 }
1717         }
1718
1719         if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
1720                 wl1271_error("invalid board type '%d'",
1721                         priv->conf.phy.board_type);
1722                 return -EINVAL;
1723         }
1724
1725         if (low_band_component_param != -1)
1726                 priv->conf.phy.low_band_component = low_band_component_param;
1727         if (low_band_component_type_param != -1)
1728                 priv->conf.phy.low_band_component_type =
1729                         low_band_component_type_param;
1730         if (high_band_component_param != -1)
1731                 priv->conf.phy.high_band_component = high_band_component_param;
1732         if (high_band_component_type_param != -1)
1733                 priv->conf.phy.high_band_component_type =
1734                         high_band_component_type_param;
1735         if (pwr_limit_reference_11_abg_param != -1)
1736                 priv->conf.phy.pwr_limit_reference_11_abg =
1737                         pwr_limit_reference_11_abg_param;
1738         if (n_antennas_2_param != -1)
1739                 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1740         if (n_antennas_5_param != -1)
1741                 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1742         if (dc2dc_param != -1)
1743                 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1744
1745         if (ht_mode_param) {
1746                 if (!strcmp(ht_mode_param, "default"))
1747                         priv->conf.ht.mode = HT_MODE_DEFAULT;
1748                 else if (!strcmp(ht_mode_param, "wide"))
1749                         priv->conf.ht.mode = HT_MODE_WIDE;
1750                 else if (!strcmp(ht_mode_param, "siso20"))
1751                         priv->conf.ht.mode = HT_MODE_SISO20;
1752                 else {
1753                         wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1754                         return -EINVAL;
1755                 }
1756         }
1757
1758         if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
1759                 /*
1760                  * Only support mimo with multiple antennas. Fall back to
1761                  * siso40.
1762                  */
1763                 if (wl18xx_is_mimo_supported(wl))
1764                         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1765                                           &wl18xx_mimo_ht_cap_2ghz);
1766                 else
1767                         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1768                                           &wl18xx_siso40_ht_cap_2ghz);
1769
1770                 /* 5Ghz is always wide */
1771                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1772                                   &wl18xx_siso40_ht_cap_5ghz);
1773         } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
1774                 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1775                                   &wl18xx_siso40_ht_cap_2ghz);
1776                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1777                                   &wl18xx_siso40_ht_cap_5ghz);
1778         } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
1779                 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1780                                   &wl18xx_siso20_ht_cap);
1781                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1782                                   &wl18xx_siso20_ht_cap);
1783         }
1784
1785         if (!checksum_param) {
1786                 wl18xx_ops.set_rx_csum = NULL;
1787                 wl18xx_ops.init_vif = NULL;
1788         }
1789
1790         /* Enable 11a Band only if we have 5G antennas */
1791         wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
1792
1793         return 0;
1794 }
1795
1796 static int wl18xx_probe(struct platform_device *pdev)
1797 {
1798         struct wl1271 *wl;
1799         struct ieee80211_hw *hw;
1800         int ret;
1801
1802         hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
1803                              WL18XX_AGGR_BUFFER_SIZE,
1804                              sizeof(struct wl18xx_event_mailbox));
1805         if (IS_ERR(hw)) {
1806                 wl1271_error("can't allocate hw");
1807                 ret = PTR_ERR(hw);
1808                 goto out;
1809         }
1810
1811         wl = hw->priv;
1812         wl->ops = &wl18xx_ops;
1813         wl->ptable = wl18xx_ptable;
1814         ret = wlcore_probe(wl, pdev);
1815         if (ret)
1816                 goto out_free;
1817
1818         return ret;
1819
1820 out_free:
1821         wlcore_free_hw(wl);
1822 out:
1823         return ret;
1824 }
1825
1826 static const struct platform_device_id wl18xx_id_table[] = {
1827         { "wl18xx", 0 },
1828         {  } /* Terminating Entry */
1829 };
1830 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1831
1832 static struct platform_driver wl18xx_driver = {
1833         .probe          = wl18xx_probe,
1834         .remove         = wlcore_remove,
1835         .id_table       = wl18xx_id_table,
1836         .driver = {
1837                 .name   = "wl18xx_driver",
1838                 .owner  = THIS_MODULE,
1839         }
1840 };
1841
1842 module_platform_driver(wl18xx_driver);
1843 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1844 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1845
1846 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1847 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1848                  "dvp");
1849
1850 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1851 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1852
1853 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1854 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1855
1856 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1857 MODULE_PARM_DESC(n_antennas_2,
1858                  "Number of installed 2.4GHz antennas: 1 (default) or 2");
1859
1860 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1861 MODULE_PARM_DESC(n_antennas_5,
1862                  "Number of installed 5GHz antennas: 1 (default) or 2");
1863
1864 module_param_named(low_band_component, low_band_component_param, int,
1865                    S_IRUSR);
1866 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1867                  "(default is 0x01)");
1868
1869 module_param_named(low_band_component_type, low_band_component_type_param,
1870                    int, S_IRUSR);
1871 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1872                  "(default is 0x05 or 0x06 depending on the board_type)");
1873
1874 module_param_named(high_band_component, high_band_component_param, int,
1875                    S_IRUSR);
1876 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1877                  "(default is 0x01)");
1878
1879 module_param_named(high_band_component_type, high_band_component_type_param,
1880                    int, S_IRUSR);
1881 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1882                  "(default is 0x09)");
1883
1884 module_param_named(pwr_limit_reference_11_abg,
1885                    pwr_limit_reference_11_abg_param, int, S_IRUSR);
1886 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1887                  "(default is 0xc8)");
1888
1889 module_param_named(num_rx_desc,
1890                    num_rx_desc_param, int, S_IRUSR);
1891 MODULE_PARM_DESC(num_rx_desc_param,
1892                  "Number of Rx descriptors: u8 (default is 32)");
1893
1894 MODULE_LICENSE("GPL v2");
1895 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1896 MODULE_FIRMWARE(WL18XX_FW_NAME);