2 * Rockchip eFuse Driver
4 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
5 * Author: Caesar Wang <wxt@rock-chips.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/nvmem-provider.h>
23 #include <linux/slab.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/rockchip/rockchip_sip.h>
29 #define RK3288_A_SHIFT 6
30 #define RK3288_A_MASK 0x3ff
31 #define RK3288_PGENB BIT(3)
32 #define RK3288_LOAD BIT(2)
33 #define RK3288_STROBE BIT(1)
34 #define RK3288_CSB BIT(0)
36 #define RK3328_INT_STATUS 0x0018
37 #define RK3328_DOUT 0x0020
38 #define RK3328_AUTO_CTRL 0x0024
39 #define RK3328_INT_FINISH BIT(0)
40 #define RK3328_AUTO_ENB BIT(0)
41 #define RK3328_AUTO_RD BIT(1)
43 #define RK3366_A_SHIFT 6
44 #define RK3366_A_MASK 0x3ff
45 #define RK3366_RDEN BIT(2)
46 #define RK3366_AEN BIT(1)
48 #define RK3399_A_SHIFT 16
49 #define RK3399_A_MASK 0x3ff
50 #define RK3399_NBYTES 4
51 #define RK3399_STROBSFTSEL BIT(9)
52 #define RK3399_RSB BIT(7)
53 #define RK3399_PD BIT(5)
54 #define RK3399_PGENB BIT(3)
55 #define RK3399_LOAD BIT(2)
56 #define RK3399_STROBE BIT(1)
57 #define RK3399_CSB BIT(0)
59 #define REG_EFUSE_CTRL 0x0000
60 #define REG_EFUSE_DOUT 0x0004
62 struct rockchip_efuse_chip {
69 static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
70 void *val, size_t bytes)
72 struct rockchip_efuse_chip *efuse = context;
76 ret = clk_prepare_enable(efuse->clk);
78 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
82 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
85 writel(readl(efuse->base + REG_EFUSE_CTRL) &
86 (~(RK3288_A_MASK << RK3288_A_SHIFT)),
87 efuse->base + REG_EFUSE_CTRL);
88 writel(readl(efuse->base + REG_EFUSE_CTRL) |
89 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
90 efuse->base + REG_EFUSE_CTRL);
92 writel(readl(efuse->base + REG_EFUSE_CTRL) |
93 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
95 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
96 writel(readl(efuse->base + REG_EFUSE_CTRL) &
97 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
101 /* Switch to standby mode */
102 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
104 clk_disable_unprepare(efuse->clk);
109 static int rockchip_rk3288_efuse_secure_read(void *context,
111 void *val, size_t bytes)
113 struct rockchip_efuse_chip *efuse = context;
118 ret = clk_prepare_enable(efuse->clk);
120 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
124 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
125 RK3288_LOAD | RK3288_PGENB);
128 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
129 (~(RK3288_A_MASK << RK3288_A_SHIFT));
130 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
131 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
132 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
133 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
135 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
137 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
139 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
140 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
142 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
146 /* Switch to standby mode */
147 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
148 RK3288_PGENB | RK3288_CSB);
150 clk_disable_unprepare(efuse->clk);
155 static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
156 void *val, size_t bytes)
158 struct rockchip_efuse_chip *efuse = context;
159 unsigned int addr_start, addr_end, addr_offset, addr_len;
160 u32 out_value, status;
164 /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
166 ret = clk_prepare_enable(efuse->clk);
168 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
172 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
173 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
174 addr_offset = offset % RK3399_NBYTES;
175 addr_len = addr_end - addr_start;
177 buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL);
184 writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
185 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
186 efuse->base + RK3328_AUTO_CTRL);
188 status = readl(efuse->base + RK3328_INT_STATUS);
189 if (!(status & RK3328_INT_FINISH)) {
193 out_value = readl(efuse->base + RK3328_DOUT);
194 writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
196 memcpy(&buf[i], &out_value, RK3399_NBYTES);
199 memcpy(val, buf + addr_offset, bytes);
203 clk_disable_unprepare(efuse->clk);
208 static int rockchip_rk3366_efuse_read(void *context, unsigned int offset,
209 void *val, size_t bytes)
211 struct rockchip_efuse_chip *efuse = context;
215 ret = clk_prepare_enable(efuse->clk);
217 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
221 writel(RK3366_RDEN, efuse->base + REG_EFUSE_CTRL);
224 writel(readl(efuse->base + REG_EFUSE_CTRL) &
225 (~(RK3366_A_MASK << RK3366_A_SHIFT)),
226 efuse->base + REG_EFUSE_CTRL);
227 writel(readl(efuse->base + REG_EFUSE_CTRL) |
228 ((offset++ & RK3366_A_MASK) << RK3366_A_SHIFT),
229 efuse->base + REG_EFUSE_CTRL);
231 writel(readl(efuse->base + REG_EFUSE_CTRL) |
232 RK3366_AEN, efuse->base + REG_EFUSE_CTRL);
234 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
235 writel(readl(efuse->base + REG_EFUSE_CTRL) &
236 (~RK3366_AEN), efuse->base + REG_EFUSE_CTRL);
240 writel(readl(efuse->base + REG_EFUSE_CTRL) &
241 (~RK3366_RDEN), efuse->base + REG_EFUSE_CTRL);
243 clk_disable_unprepare(efuse->clk);
248 static int rockchip_rk3368_efuse_read(void *context, unsigned int offset,
249 void *val, size_t bytes)
251 struct rockchip_efuse_chip *efuse = context;
256 ret = clk_prepare_enable(efuse->clk);
258 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
262 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
263 RK3288_LOAD | RK3288_PGENB);
266 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
267 (~(RK3288_A_MASK << RK3288_A_SHIFT));
268 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
269 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
270 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
271 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
273 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
275 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
277 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
278 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
280 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
284 /* Switch to standby mode */
285 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
286 RK3288_PGENB | RK3288_CSB);
288 clk_disable_unprepare(efuse->clk);
293 static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
294 void *val, size_t bytes)
296 struct rockchip_efuse_chip *efuse = context;
297 unsigned int addr_start, addr_end, addr_offset, addr_len;
302 ret = clk_prepare_enable(efuse->clk);
304 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
308 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
309 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
310 addr_offset = offset % RK3399_NBYTES;
311 addr_len = addr_end - addr_start;
313 buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL);
315 clk_disable_unprepare(efuse->clk);
319 writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
320 efuse->base + REG_EFUSE_CTRL);
323 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
324 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
325 efuse->base + REG_EFUSE_CTRL);
327 out_value = readl(efuse->base + REG_EFUSE_DOUT);
328 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
329 efuse->base + REG_EFUSE_CTRL);
332 memcpy(&buf[i], &out_value, RK3399_NBYTES);
336 /* Switch to standby mode */
337 writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
339 memcpy(val, buf + addr_offset, bytes);
343 clk_disable_unprepare(efuse->clk);
348 static struct nvmem_config econfig = {
349 .name = "rockchip-efuse",
350 .owner = THIS_MODULE,
356 static const struct of_device_id rockchip_efuse_match[] = {
357 /* deprecated but kept around for dts binding compatibility */
359 .compatible = "rockchip,rockchip-efuse",
360 .data = (void *)&rockchip_rk3288_efuse_read,
363 .compatible = "rockchip,rk3066a-efuse",
364 .data = (void *)&rockchip_rk3288_efuse_read,
367 .compatible = "rockchip,rk3188-efuse",
368 .data = (void *)&rockchip_rk3288_efuse_read,
371 .compatible = "rockchip,rk3288-efuse",
372 .data = (void *)&rockchip_rk3288_efuse_read,
375 .compatible = "rockchip,rk3288-secure-efuse",
376 .data = (void *)&rockchip_rk3288_efuse_secure_read,
379 .compatible = "rockchip,rk3328-efuse",
380 .data = (void *)&rockchip_rk3328_efuse_read,
383 .compatible = "rockchip,rk3366-efuse",
384 .data = (void *)&rockchip_rk3366_efuse_read,
387 .compatible = "rockchip,rk3368-efuse",
388 .data = (void *)&rockchip_rk3368_efuse_read,
391 .compatible = "rockchip,rk3399-efuse",
392 .data = (void *)&rockchip_rk3399_efuse_read,
396 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
398 static int __init rockchip_efuse_probe(struct platform_device *pdev)
400 struct resource *res;
401 struct nvmem_device *nvmem;
402 struct rockchip_efuse_chip *efuse;
403 const struct of_device_id *match;
404 struct device *dev = &pdev->dev;
406 match = of_match_device(dev->driver->of_match_table, dev);
407 if (!match || !match->data) {
408 dev_err(dev, "failed to get match data\n");
412 efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
417 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
418 efuse->phys = res->start;
419 efuse->base = devm_ioremap_resource(&pdev->dev, res);
420 if (IS_ERR(efuse->base))
421 return PTR_ERR(efuse->base);
423 efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
424 if (IS_ERR(efuse->clk))
425 return PTR_ERR(efuse->clk);
427 efuse->dev = &pdev->dev;
428 if (of_property_read_u32_index(dev->of_node,
429 "rockchip,efuse-size",
432 econfig.size = resource_size(res);
434 econfig.reg_read = match->data;
435 econfig.priv = efuse;
436 econfig.dev = efuse->dev;
437 nvmem = nvmem_register(&econfig);
439 return PTR_ERR(nvmem);
441 platform_set_drvdata(pdev, nvmem);
446 static int rockchip_efuse_remove(struct platform_device *pdev)
448 struct nvmem_device *nvmem = platform_get_drvdata(pdev);
450 return nvmem_unregister(nvmem);
453 static struct platform_driver rockchip_efuse_driver = {
454 .remove = rockchip_efuse_remove,
456 .name = "rockchip-efuse",
457 .of_match_table = rockchip_efuse_match,
461 static int __init rockchip_efuse_module_init(void)
463 return platform_driver_probe(&rockchip_efuse_driver,
464 rockchip_efuse_probe);
467 subsys_initcall(rockchip_efuse_module_init);
469 MODULE_DESCRIPTION("rockchip_efuse driver");
470 MODULE_LICENSE("GPL v2");