drivers/nvmem/rockchip-efuse.c

   1 /*
   2  * Rockchip eFuse Driver
   3  *
   4  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   5  * Author: Caesar Wang <wxt@rock-chips.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14  * more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/nvmem-provider.h>
  23 #include <linux/slab.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/rockchip/rockchip_sip.h>
  28
  29 #define RK3288_A_SHIFT          6
  30 #define RK3288_A_MASK           0x3ff
  31 #define RK3288_PGENB            BIT(3)
  32 #define RK3288_LOAD             BIT(2)
  33 #define RK3288_STROBE           BIT(1)
  34 #define RK3288_CSB              BIT(0)
  35
  36 #define RK3328_INT_STATUS       0x0018
  37 #define RK3328_DOUT             0x0020
  38 #define RK3328_AUTO_CTRL        0x0024
  39 #define RK3328_INT_FINISH       BIT(0)
  40 #define RK3328_AUTO_ENB         BIT(0)
  41 #define RK3328_AUTO_RD          BIT(1)
  42
  43 #define RK3366_A_SHIFT          6
  44 #define RK3366_A_MASK           0x3ff
  45 #define RK3366_RDEN             BIT(2)
  46 #define RK3366_AEN              BIT(1)
  47
  48 #define RK3399_A_SHIFT          16
  49 #define RK3399_A_MASK           0x3ff
  50 #define RK3399_NBYTES           4
  51 #define RK3399_STROBSFTSEL      BIT(9)
  52 #define RK3399_RSB              BIT(7)
  53 #define RK3399_PD               BIT(5)
  54 #define RK3399_PGENB            BIT(3)
  55 #define RK3399_LOAD             BIT(2)
  56 #define RK3399_STROBE           BIT(1)
  57 #define RK3399_CSB              BIT(0)
  58
  59 #define REG_EFUSE_CTRL          0x0000
  60 #define REG_EFUSE_DOUT          0x0004
  61
  62 struct rockchip_efuse_chip {
  63         struct device *dev;
  64         void __iomem *base;
  65         struct clk *clk;
  66         phys_addr_t phys;
  67 };
  68
  69 static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
  70                                       void *val, size_t bytes)
  71 {
  72         struct rockchip_efuse_chip *efuse = context;
  73         u8 *buf = val;
  74         int ret;
  75
  76         ret = clk_prepare_enable(efuse->clk);
  77         if (ret < 0) {
  78                 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
  79                 return ret;
  80         }
  81
  82         writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
  83         udelay(1);
  84         while (bytes--) {
  85                 writel(readl(efuse->base + REG_EFUSE_CTRL) &
  86                              (~(RK3288_A_MASK << RK3288_A_SHIFT)),
  87                              efuse->base + REG_EFUSE_CTRL);
  88                 writel(readl(efuse->base + REG_EFUSE_CTRL) |
  89                              ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
  90                              efuse->base + REG_EFUSE_CTRL);
  91                 udelay(1);
  92                 writel(readl(efuse->base + REG_EFUSE_CTRL) |
  93                              RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
  94                 udelay(1);
  95                 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
  96                 writel(readl(efuse->base + REG_EFUSE_CTRL) &
  97                        (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
  98                 udelay(1);
  99         }
 100
 101         /* Switch to standby mode */
 102         writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
 103
 104         clk_disable_unprepare(efuse->clk);
 105
 106         return 0;
 107 }
 108
 109 static int rockchip_rk3288_efuse_secure_read(void *context,
 110                                              unsigned int offset,
 111                                              void *val, size_t bytes)
 112 {
 113         struct rockchip_efuse_chip *efuse = context;
 114         u8 *buf = val;
 115         u32 wr_val;
 116         int ret;
 117
 118         ret = clk_prepare_enable(efuse->clk);
 119         if (ret < 0) {
 120                 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 121                 return ret;
 122         }
 123
 124         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
 125                                  RK3288_LOAD | RK3288_PGENB);
 126         udelay(1);
 127         while (bytes--) {
 128                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
 129                          (~(RK3288_A_MASK << RK3288_A_SHIFT));
 130                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 131                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
 132                          ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
 133                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 134                 udelay(1);
 135                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
 136                          RK3288_STROBE;
 137                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 138                 udelay(1);
 139                 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
 140                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
 141                          (~RK3288_STROBE);
 142                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 143                 udelay(1);
 144         }
 145
 146         /* Switch to standby mode */
 147         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
 148                                  RK3288_PGENB | RK3288_CSB);
 149
 150         clk_disable_unprepare(efuse->clk);
 151
 152         return 0;
 153 }
 154
 155 static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
 156                                       void *val, size_t bytes)
 157 {
 158         struct rockchip_efuse_chip *efuse = context;
 159         unsigned int addr_start, addr_end, addr_offset, addr_len;
 160         u32 out_value, status;
 161         u8 *buf;
 162         int ret, i = 0;
 163
 164         /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
 165         offset += 96;
 166         ret = clk_prepare_enable(efuse->clk);
 167         if (ret < 0) {
 168                 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 169                 return ret;
 170         }
 171
 172         addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
 173         addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
 174         addr_offset = offset % RK3399_NBYTES;
 175         addr_len = addr_end - addr_start;
 176
 177         buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL);
 178         if (!buf) {
 179                 ret = -ENOMEM;
 180                 goto nomem;
 181         }
 182
 183         while (addr_len--) {
 184                 writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
 185                        ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
 186                        efuse->base + RK3328_AUTO_CTRL);
 187                 udelay(2);
 188                 status = readl(efuse->base + RK3328_INT_STATUS);
 189                 if (!(status & RK3328_INT_FINISH)) {
 190                         ret = -EIO;
 191                         goto err;
 192                 }
 193                 out_value = readl(efuse->base + RK3328_DOUT);
 194                 writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
 195
 196                 memcpy(&buf[i], &out_value, RK3399_NBYTES);
 197                 i += RK3399_NBYTES;
 198         }
 199         memcpy(val, buf + addr_offset, bytes);
 200 err:
 201         kfree(buf);
 202 nomem:
 203         clk_disable_unprepare(efuse->clk);
 204
 205         return ret;
 206 }
 207
 208 static int rockchip_rk3366_efuse_read(void *context, unsigned int offset,
 209                                       void *val, size_t bytes)
 210 {
 211         struct rockchip_efuse_chip *efuse = context;
 212         u8 *buf = val;
 213         int ret;
 214
 215         ret = clk_prepare_enable(efuse->clk);
 216         if (ret < 0) {
 217                 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 218                 return ret;
 219         }
 220
 221         writel(RK3366_RDEN, efuse->base + REG_EFUSE_CTRL);
 222         udelay(1);
 223         while (bytes--) {
 224                 writel(readl(efuse->base + REG_EFUSE_CTRL) &
 225                        (~(RK3366_A_MASK << RK3366_A_SHIFT)),
 226                        efuse->base + REG_EFUSE_CTRL);
 227                 writel(readl(efuse->base + REG_EFUSE_CTRL) |
 228                        ((offset++ & RK3366_A_MASK) << RK3366_A_SHIFT),
 229                        efuse->base + REG_EFUSE_CTRL);
 230                 udelay(1);
 231                 writel(readl(efuse->base + REG_EFUSE_CTRL) |
 232                        RK3366_AEN, efuse->base + REG_EFUSE_CTRL);
 233                 udelay(1);
 234                 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
 235                 writel(readl(efuse->base + REG_EFUSE_CTRL) &
 236                        (~RK3366_AEN), efuse->base + REG_EFUSE_CTRL);
 237                 udelay(1);
 238         }
 239
 240         writel(readl(efuse->base + REG_EFUSE_CTRL) &
 241                (~RK3366_RDEN), efuse->base + REG_EFUSE_CTRL);
 242
 243         clk_disable_unprepare(efuse->clk);
 244
 245         return 0;
 246 }
 247
 248 static int rockchip_rk3368_efuse_read(void *context, unsigned int offset,
 249                                       void *val, size_t bytes)
 250 {
 251         struct rockchip_efuse_chip *efuse = context;
 252         u8 *buf = val;
 253         u32 wr_val;
 254         int ret;
 255
 256         ret = clk_prepare_enable(efuse->clk);
 257         if (ret < 0) {
 258                 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 259                 return ret;
 260         }
 261
 262         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
 263                                  RK3288_LOAD | RK3288_PGENB);
 264         udelay(1);
 265         while (bytes--) {
 266                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
 267                          (~(RK3288_A_MASK << RK3288_A_SHIFT));
 268                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 269                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
 270                          ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
 271                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 272                 udelay(1);
 273                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
 274                          RK3288_STROBE;
 275                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 276                 udelay(1);
 277                 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
 278                 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
 279                          (~RK3288_STROBE);
 280                 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
 281                 udelay(1);
 282         }
 283
 284         /* Switch to standby mode */
 285         sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
 286                                  RK3288_PGENB | RK3288_CSB);
 287
 288         clk_disable_unprepare(efuse->clk);
 289
 290         return 0;
 291 }
 292
 293 static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
 294                                       void *val, size_t bytes)
 295 {
 296         struct rockchip_efuse_chip *efuse = context;
 297         unsigned int addr_start, addr_end, addr_offset, addr_len;
 298         u32 out_value;
 299         u8 *buf;
 300         int ret, i = 0;
 301
 302         ret = clk_prepare_enable(efuse->clk);
 303         if (ret < 0) {
 304                 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
 305                 return ret;
 306         }
 307
 308         addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
 309         addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
 310         addr_offset = offset % RK3399_NBYTES;
 311         addr_len = addr_end - addr_start;
 312
 313         buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL);
 314         if (!buf) {
 315                 clk_disable_unprepare(efuse->clk);
 316                 return -ENOMEM;
 317         }
 318
 319         writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
 320                efuse->base + REG_EFUSE_CTRL);
 321         udelay(1);
 322         while (addr_len--) {
 323                 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
 324                        ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
 325                        efuse->base + REG_EFUSE_CTRL);
 326                 udelay(1);
 327                 out_value = readl(efuse->base + REG_EFUSE_DOUT);
 328                 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
 329                        efuse->base + REG_EFUSE_CTRL);
 330                 udelay(1);
 331
 332                 memcpy(&buf[i], &out_value, RK3399_NBYTES);
 333                 i += RK3399_NBYTES;
 334         }
 335
 336         /* Switch to standby mode */
 337         writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
 338
 339         memcpy(val, buf + addr_offset, bytes);
 340
 341         kfree(buf);
 342
 343         clk_disable_unprepare(efuse->clk);
 344
 345         return 0;
 346 }
 347
 348 static struct nvmem_config econfig = {
 349         .name = "rockchip-efuse",
 350         .owner = THIS_MODULE,
 351         .stride = 1,
 352         .word_size = 1,
 353         .read_only = true,
 354 };
 355
 356 static const struct of_device_id rockchip_efuse_match[] = {
 357         /* deprecated but kept around for dts binding compatibility */
 358         {
 359                 .compatible = "rockchip,rockchip-efuse",
 360                 .data = (void *)&rockchip_rk3288_efuse_read,
 361         },
 362         {
 363                 .compatible = "rockchip,rk3066a-efuse",
 364                 .data = (void *)&rockchip_rk3288_efuse_read,
 365         },
 366         {
 367                 .compatible = "rockchip,rk3188-efuse",
 368                 .data = (void *)&rockchip_rk3288_efuse_read,
 369         },
 370         {
 371                 .compatible = "rockchip,rk3288-efuse",
 372                 .data = (void *)&rockchip_rk3288_efuse_read,
 373         },
 374         {
 375                 .compatible = "rockchip,rk3288-secure-efuse",
 376                 .data = (void *)&rockchip_rk3288_efuse_secure_read,
 377         },
 378         {
 379                 .compatible = "rockchip,rk3328-efuse",
 380                 .data = (void *)&rockchip_rk3328_efuse_read,
 381         },
 382         {
 383                 .compatible = "rockchip,rk3366-efuse",
 384                 .data = (void *)&rockchip_rk3366_efuse_read,
 385         },
 386         {
 387                 .compatible = "rockchip,rk3368-efuse",
 388                 .data = (void *)&rockchip_rk3368_efuse_read,
 389         },
 390         {
 391                 .compatible = "rockchip,rk3399-efuse",
 392                 .data = (void *)&rockchip_rk3399_efuse_read,
 393         },
 394         { /* sentinel */},
 395 };
 396 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
 397
 398 static int __init rockchip_efuse_probe(struct platform_device *pdev)
 399 {
 400         struct resource *res;
 401         struct nvmem_device *nvmem;
 402         struct rockchip_efuse_chip *efuse;
 403         const struct of_device_id *match;
 404         struct device *dev = &pdev->dev;
 405
 406         match = of_match_device(dev->driver->of_match_table, dev);
 407         if (!match || !match->data) {
 408                 dev_err(dev, "failed to get match data\n");
 409                 return -EINVAL;
 410         }
 411
 412         efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
 413                              GFP_KERNEL);
 414         if (!efuse)
 415                 return -ENOMEM;
 416
 417         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 418         efuse->phys = res->start;
 419         efuse->base = devm_ioremap_resource(&pdev->dev, res);
 420         if (IS_ERR(efuse->base))
 421                 return PTR_ERR(efuse->base);
 422
 423         efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
 424         if (IS_ERR(efuse->clk))
 425                 return PTR_ERR(efuse->clk);
 426
 427         efuse->dev = &pdev->dev;
 428         if (of_property_read_u32_index(dev->of_node,
 429                                        "rockchip,efuse-size",
 430                                        0,
 431                                        &econfig.size))
 432                 econfig.size = resource_size(res);
 433
 434         econfig.reg_read = match->data;
 435         econfig.priv = efuse;
 436         econfig.dev = efuse->dev;
 437         nvmem = nvmem_register(&econfig);
 438         if (IS_ERR(nvmem))
 439                 return PTR_ERR(nvmem);
 440
 441         platform_set_drvdata(pdev, nvmem);
 442
 443         return 0;
 444 }
 445
 446 static int rockchip_efuse_remove(struct platform_device *pdev)
 447 {
 448         struct nvmem_device *nvmem = platform_get_drvdata(pdev);
 449
 450         return nvmem_unregister(nvmem);
 451 }
 452
 453 static struct platform_driver rockchip_efuse_driver = {
 454         .remove = rockchip_efuse_remove,
 455         .driver = {
 456                 .name = "rockchip-efuse",
 457                 .of_match_table = rockchip_efuse_match,
 458         },
 459 };
 460
 461 static int __init rockchip_efuse_module_init(void)
 462 {
 463         return platform_driver_probe(&rockchip_efuse_driver,
 464                                      rockchip_efuse_probe);
 465 }
 466
 467 subsys_initcall(rockchip_efuse_module_init);
 468
 469 MODULE_DESCRIPTION("rockchip_efuse driver");
 470 MODULE_LICENSE("GPL v2");