drivers/pci/access.c

   1 #include <linux/delay.h>
   2 #include <linux/pci.h>
   3 #include <linux/module.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/wait.h>
   7
   8 #include "pci.h"
   9
  10 /*
  11  * This interrupt-safe spinlock protects all accesses to PCI
  12  * configuration space.
  13  */
  14
  15 static DEFINE_SPINLOCK(pci_lock);
  16
  17 /*
  18  *  Wrappers for all PCI configuration access functions.  They just check
  19  *  alignment, do locking and call the low-level functions pointed to
  20  *  by pci_dev->ops.
  21  */
  22
  23 #define PCI_byte_BAD 0
  24 #define PCI_word_BAD (pos & 1)
  25 #define PCI_dword_BAD (pos & 3)
  26
  27 #define PCI_OP_READ(size,type,len) \
  28 int pci_bus_read_config_##size \
  29         (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
  30 {                                                                       \
  31         int res;                                                        \
  32         unsigned long flags;                                            \
  33         u32 data = 0;                                                   \
  34         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
  35         spin_lock_irqsave(&pci_lock, flags);                            \
  36         res = bus->ops->read(bus, devfn, pos, len, &data);              \
  37         *value = (type)data;                                            \
  38         spin_unlock_irqrestore(&pci_lock, flags);                       \
  39         return res;                                                     \
  40 }
  41
  42 #define PCI_OP_WRITE(size,type,len) \
  43 int pci_bus_write_config_##size \
  44         (struct pci_bus *bus, unsigned int devfn, int pos, type value)  \
  45 {                                                                       \
  46         int res;                                                        \
  47         unsigned long flags;                                            \
  48         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
  49         spin_lock_irqsave(&pci_lock, flags);                            \
  50         res = bus->ops->write(bus, devfn, pos, len, value);             \
  51         spin_unlock_irqrestore(&pci_lock, flags);                       \
  52         return res;                                                     \
  53 }
  54
  55 PCI_OP_READ(byte, u8, 1)
  56 PCI_OP_READ(word, u16, 2)
  57 PCI_OP_READ(dword, u32, 4)
  58 PCI_OP_WRITE(byte, u8, 1)
  59 PCI_OP_WRITE(word, u16, 2)
  60 PCI_OP_WRITE(dword, u32, 4)
  61
  62 EXPORT_SYMBOL(pci_bus_read_config_byte);
  63 EXPORT_SYMBOL(pci_bus_read_config_word);
  64 EXPORT_SYMBOL(pci_bus_read_config_dword);
  65 EXPORT_SYMBOL(pci_bus_write_config_byte);
  66 EXPORT_SYMBOL(pci_bus_write_config_word);
  67 EXPORT_SYMBOL(pci_bus_write_config_dword);
  68
  69 /*
  70  * The following routines are to prevent the user from accessing PCI config
  71  * space when it's unsafe to do so.  Some devices require this during BIST and
  72  * we're required to prevent it during D-state transitions.
  73  *
  74  * We have a bit per device to indicate it's blocked and a global wait queue
  75  * for callers to sleep on until devices are unblocked.
  76  */
  77 static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
  78
  79 static noinline void pci_wait_ucfg(struct pci_dev *dev)
  80 {
  81         DECLARE_WAITQUEUE(wait, current);
  82
  83         __add_wait_queue(&pci_ucfg_wait, &wait);
  84         do {
  85                 set_current_state(TASK_UNINTERRUPTIBLE);
  86                 spin_unlock_irq(&pci_lock);
  87                 schedule();
  88                 spin_lock_irq(&pci_lock);
  89         } while (dev->block_ucfg_access);
  90         __remove_wait_queue(&pci_ucfg_wait, &wait);
  91 }
  92
  93 #define PCI_USER_READ_CONFIG(size,type)                                 \
  94 int pci_user_read_config_##size                                         \
  95         (struct pci_dev *dev, int pos, type *val)                       \
  96 {                                                                       \
  97         int ret = 0;                                                    \
  98         u32 data = -1;                                                  \
  99         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
 100         spin_lock_irq(&pci_lock);                                       \
 101         if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev);       \
 102         ret = dev->bus->ops->read(dev->bus, dev->devfn,                 \
 103                                         pos, sizeof(type), &data);      \
 104         spin_unlock_irq(&pci_lock);                                     \
 105         *val = (type)data;                                              \
 106         return ret;                                                     \
 107 }
 108
 109 #define PCI_USER_WRITE_CONFIG(size,type)                                \
 110 int pci_user_write_config_##size                                        \
 111         (struct pci_dev *dev, int pos, type val)                        \
 112 {                                                                       \
 113         int ret = -EIO;                                                 \
 114         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
 115         spin_lock_irq(&pci_lock);                                       \
 116         if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev);       \
 117         ret = dev->bus->ops->write(dev->bus, dev->devfn,                \
 118                                         pos, sizeof(type), val);        \
 119         spin_unlock_irq(&pci_lock);                                     \
 120         return ret;                                                     \
 121 }
 122
 123 PCI_USER_READ_CONFIG(byte, u8)
 124 PCI_USER_READ_CONFIG(word, u16)
 125 PCI_USER_READ_CONFIG(dword, u32)
 126 PCI_USER_WRITE_CONFIG(byte, u8)
 127 PCI_USER_WRITE_CONFIG(word, u16)
 128 PCI_USER_WRITE_CONFIG(dword, u32)
 129
 130 /* VPD access through PCI 2.2+ VPD capability */
 131
 132 #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
 133
 134 struct pci_vpd_pci22 {
 135         struct pci_vpd base;
 136         struct mutex lock;
 137         u16     flag;
 138         bool    busy;
 139         u8      cap;
 140 };
 141
 142 /*
 143  * Wait for last operation to complete.
 144  * This code has to spin since there is no other notification from the PCI
 145  * hardware. Since the VPD is often implemented by serial attachment to an
 146  * EEPROM, it may take many milliseconds to complete.
 147  */
 148 static int pci_vpd_pci22_wait(struct pci_dev *dev)
 149 {
 150         struct pci_vpd_pci22 *vpd =
 151                 container_of(dev->vpd, struct pci_vpd_pci22, base);
 152         unsigned long timeout = jiffies + HZ/20 + 2;
 153         u16 status;
 154         int ret;
 155
 156         if (!vpd->busy)
 157                 return 0;
 158
 159         for (;;) {
 160                 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
 161                                                 &status);
 162                 if (ret)
 163                         return ret;
 164
 165                 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
 166                         vpd->busy = false;
 167                         return 0;
 168                 }
 169
 170                 if (time_after(jiffies, timeout))
 171                         return -ETIMEDOUT;
 172                 if (fatal_signal_pending(current))
 173                         return -EINTR;
 174                 if (!cond_resched())
 175                         udelay(10);
 176         }
 177 }
 178
 179 static int pci_vpd_pci22_read(struct pci_dev *dev, int pos, int size,
 180                               char *buf)
 181 {
 182         struct pci_vpd_pci22 *vpd =
 183                 container_of(dev->vpd, struct pci_vpd_pci22, base);
 184         u32 val;
 185         int ret = 0;
 186         int begin, end, i;
 187
 188         if (pos < 0 || pos > vpd->base.len || size > vpd->base.len  - pos)
 189                 return -EINVAL;
 190         if (size == 0)
 191                 return 0;
 192
 193         if (mutex_lock_killable(&vpd->lock))
 194                 return -EINTR;
 195
 196         ret = pci_vpd_pci22_wait(dev);
 197         if (ret < 0)
 198                 goto out;
 199         ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
 200                                          pos & ~3);
 201         if (ret < 0)
 202                 goto out;
 203
 204         vpd->busy = true;
 205         vpd->flag = PCI_VPD_ADDR_F;
 206         ret = pci_vpd_pci22_wait(dev);
 207         if (ret < 0)
 208                 goto out;
 209         ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA,
 210                                          &val);
 211 out:
 212         mutex_unlock(&vpd->lock);
 213         if (ret < 0)
 214                 return ret;
 215
 216         /* Convert to bytes */
 217         begin = pos & 3;
 218         end = min(4, begin + size);
 219         for (i = 0; i < end; ++i) {
 220                 if (i >= begin)
 221                         *buf++ = val;
 222                 val >>= 8;
 223         }
 224         return end - begin;
 225 }
 226
 227 static int pci_vpd_pci22_write(struct pci_dev *dev, int pos, int size,
 228                                const char *buf)
 229 {
 230         struct pci_vpd_pci22 *vpd =
 231                 container_of(dev->vpd, struct pci_vpd_pci22, base);
 232         u32 val;
 233         int ret = 0;
 234
 235         if (pos < 0 || pos > vpd->base.len || pos & 3 ||
 236             size > vpd->base.len - pos || size < 4)
 237                 return -EINVAL;
 238
 239         val = (u8) *buf++;
 240         val |= ((u8) *buf++) << 8;
 241         val |= ((u8) *buf++) << 16;
 242         val |= ((u32)(u8) *buf++) << 24;
 243
 244         if (mutex_lock_killable(&vpd->lock))
 245                 return -EINTR;
 246         ret = pci_vpd_pci22_wait(dev);
 247         if (ret < 0)
 248                 goto out;
 249         ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
 250                                           val);
 251         if (ret < 0)
 252                 goto out;
 253         ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
 254                                          pos | PCI_VPD_ADDR_F);
 255         if (ret < 0)
 256                 goto out;
 257         vpd->busy = true;
 258         vpd->flag = 0;
 259         ret = pci_vpd_pci22_wait(dev);
 260 out:
 261         mutex_unlock(&vpd->lock);
 262         if (ret < 0)
 263                 return ret;
 264
 265         return 4;
 266 }
 267
 268 static void pci_vpd_pci22_release(struct pci_dev *dev)
 269 {
 270         kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
 271 }
 272
 273 static struct pci_vpd_ops pci_vpd_pci22_ops = {
 274         .read = pci_vpd_pci22_read,
 275         .write = pci_vpd_pci22_write,
 276         .release = pci_vpd_pci22_release,
 277 };
 278
 279 int pci_vpd_pci22_init(struct pci_dev *dev)
 280 {
 281         struct pci_vpd_pci22 *vpd;
 282         u8 cap;
 283
 284         cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
 285         if (!cap)
 286                 return -ENODEV;
 287         vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
 288         if (!vpd)
 289                 return -ENOMEM;
 290
 291         vpd->base.len = PCI_VPD_PCI22_SIZE;
 292         vpd->base.ops = &pci_vpd_pci22_ops;
 293         mutex_init(&vpd->lock);
 294         vpd->cap = cap;
 295         vpd->busy = false;
 296         dev->vpd = &vpd->base;
 297         return 0;
 298 }
 299
 300 /**
 301  * pci_block_user_cfg_access - Block userspace PCI config reads/writes
 302  * @dev:        pci device struct
 303  *
 304  * When user access is blocked, any reads or writes to config space will
 305  * sleep until access is unblocked again.  We don't allow nesting of
 306  * block/unblock calls.
 307  */
 308 void pci_block_user_cfg_access(struct pci_dev *dev)
 309 {
 310         unsigned long flags;
 311         int was_blocked;
 312
 313         spin_lock_irqsave(&pci_lock, flags);
 314         was_blocked = dev->block_ucfg_access;
 315         dev->block_ucfg_access = 1;
 316         spin_unlock_irqrestore(&pci_lock, flags);
 317
 318         /* If we BUG() inside the pci_lock, we're guaranteed to hose
 319          * the machine */
 320         BUG_ON(was_blocked);
 321 }
 322 EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
 323
 324 /**
 325  * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
 326  * @dev:        pci device struct
 327  *
 328  * This function allows userspace PCI config accesses to resume.
 329  */
 330 void pci_unblock_user_cfg_access(struct pci_dev *dev)
 331 {
 332         unsigned long flags;
 333
 334         spin_lock_irqsave(&pci_lock, flags);
 335
 336         /* This indicates a problem in the caller, but we don't need
 337          * to kill them, unlike a double-block above. */
 338         WARN_ON(!dev->block_ucfg_access);
 339
 340         dev->block_ucfg_access = 0;
 341         wake_up_all(&pci_ucfg_wait);
 342         spin_unlock_irqrestore(&pci_lock, flags);
 343 }
 344 EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);