2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
30 #include "pcie-designware.h"
32 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
40 struct regmap *iomuxc_gpr;
41 void __iomem *mem_base;
44 /* PCIe Root Complex registers (memory-mapped) */
45 #define PCIE_RC_LCR 0x7c
46 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
47 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
48 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
50 #define PCIE_RC_LCSR 0x80
52 /* PCIe Port Logic registers (memory-mapped) */
53 #define PL_OFFSET 0x700
54 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
55 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
56 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
57 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
58 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
59 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
60 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
62 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
63 #define PCIE_PHY_CTRL_DATA_LOC 0
64 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
65 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
66 #define PCIE_PHY_CTRL_WR_LOC 18
67 #define PCIE_PHY_CTRL_RD_LOC 19
69 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
70 #define PCIE_PHY_STAT_ACK_LOC 16
72 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
73 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
75 /* PHY registers (not memory-mapped) */
76 #define PCIE_PHY_RX_ASIC_OUT 0x100D
78 #define PHY_RX_OVRD_IN_LO 0x1005
79 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
80 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
82 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
85 u32 max_iterations = 10;
89 val = readl(dbi_base + PCIE_PHY_STAT);
90 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
97 } while (wait_counter < max_iterations);
102 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
107 val = addr << PCIE_PHY_CTRL_DATA_LOC;
108 writel(val, dbi_base + PCIE_PHY_CTRL);
110 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
111 writel(val, dbi_base + PCIE_PHY_CTRL);
113 ret = pcie_phy_poll_ack(dbi_base, 1);
117 val = addr << PCIE_PHY_CTRL_DATA_LOC;
118 writel(val, dbi_base + PCIE_PHY_CTRL);
120 ret = pcie_phy_poll_ack(dbi_base, 0);
127 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
128 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
133 ret = pcie_phy_wait_ack(dbi_base, addr);
137 /* assert Read signal */
138 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
139 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
141 ret = pcie_phy_poll_ack(dbi_base, 1);
145 val = readl(dbi_base + PCIE_PHY_STAT);
146 *data = val & 0xffff;
148 /* deassert Read signal */
149 writel(0x00, dbi_base + PCIE_PHY_CTRL);
151 ret = pcie_phy_poll_ack(dbi_base, 0);
158 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
165 ret = pcie_phy_wait_ack(dbi_base, addr);
169 var = data << PCIE_PHY_CTRL_DATA_LOC;
170 writel(var, dbi_base + PCIE_PHY_CTRL);
173 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
174 writel(var, dbi_base + PCIE_PHY_CTRL);
176 ret = pcie_phy_poll_ack(dbi_base, 1);
180 /* deassert cap data */
181 var = data << PCIE_PHY_CTRL_DATA_LOC;
182 writel(var, dbi_base + PCIE_PHY_CTRL);
184 /* wait for ack de-assertion */
185 ret = pcie_phy_poll_ack(dbi_base, 0);
189 /* assert wr signal */
190 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
191 writel(var, dbi_base + PCIE_PHY_CTRL);
194 ret = pcie_phy_poll_ack(dbi_base, 1);
198 /* deassert wr signal */
199 var = data << PCIE_PHY_CTRL_DATA_LOC;
200 writel(var, dbi_base + PCIE_PHY_CTRL);
202 /* wait for ack de-assertion */
203 ret = pcie_phy_poll_ack(dbi_base, 0);
207 writel(0x0, dbi_base + PCIE_PHY_CTRL);
212 /* Added for PCI abort handling */
213 static int imx6q_pcie_abort_handler(unsigned long addr,
214 unsigned int fsr, struct pt_regs *regs)
219 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
221 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
222 u32 val, gpr1, gpr12;
225 * If the bootloader already enabled the link we need some special
226 * handling to get the core back into a state where it is safe to
227 * touch it for configuration. As there is no dedicated reset signal
228 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
229 * state before completely disabling LTSSM, which is a prerequisite
230 * for core configuration.
232 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
233 * indication that the bootloader activated the link.
235 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
236 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
238 if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
239 (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
240 val = readl(pp->dbi_base + PCIE_PL_PFLR);
241 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
242 val |= PCIE_PL_PFLR_FORCE_LINK;
243 writel(val, pp->dbi_base + PCIE_PL_PFLR);
245 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
246 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
249 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
250 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
251 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
252 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
257 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
259 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
262 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
264 dev_err(pp->dev, "unable to enable pcie_phy clock\n");
268 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
270 dev_err(pp->dev, "unable to enable pcie_bus clock\n");
274 ret = clk_prepare_enable(imx6_pcie->pcie);
276 dev_err(pp->dev, "unable to enable pcie clock\n");
280 /* power up core phy and enable ref clock */
281 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
282 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
284 * the async reset input need ref clock to sync internally,
285 * when the ref clock comes after reset, internal synced
286 * reset time is too short, cannot meet the requirement.
287 * add one ~10us delay here.
290 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
291 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
293 /* allow the clocks to stabilize */
294 usleep_range(200, 500);
296 /* Some boards don't have PCIe reset GPIO. */
297 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
298 gpio_set_value(imx6_pcie->reset_gpio, 0);
300 gpio_set_value(imx6_pcie->reset_gpio, 1);
305 clk_disable_unprepare(imx6_pcie->pcie_bus);
307 clk_disable_unprepare(imx6_pcie->pcie_phy);
313 static void imx6_pcie_init_phy(struct pcie_port *pp)
315 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
317 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
318 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
320 /* configure constant input signal to the pcie ctrl and phy */
321 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
322 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
323 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
324 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
326 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
327 IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
328 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
329 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
330 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
331 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
332 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
333 IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
334 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
335 IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
338 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
340 unsigned int retries;
342 for (retries = 0; retries < 200; retries++) {
343 if (dw_pcie_link_up(pp))
345 usleep_range(100, 1000);
348 dev_err(pp->dev, "phy link never came up\n");
349 dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
350 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
351 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
355 static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
358 unsigned int retries;
360 for (retries = 0; retries < 200; retries++) {
361 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
362 /* Test if the speed change finished. */
363 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
365 usleep_range(100, 1000);
368 dev_err(pp->dev, "Speed change timeout\n");
372 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
374 struct pcie_port *pp = arg;
376 return dw_handle_msi_irq(pp);
379 static int imx6_pcie_establish_link(struct pcie_port *pp)
381 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
386 * Force Gen1 operation when starting the link. In case the link is
387 * started in Gen2 mode, there is a possibility the devices on the
388 * bus will not be detected at all. This happens with PCIe switches.
390 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
391 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
392 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
393 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
396 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
397 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
399 ret = imx6_pcie_wait_for_link(pp);
403 /* Allow Gen2 mode after the link is up. */
404 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
405 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
406 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
407 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
410 * Start Directed Speed Change so the best possible speed both link
411 * partners support can be negotiated.
413 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
414 tmp |= PORT_LOGIC_SPEED_CHANGE;
415 writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
417 ret = imx6_pcie_wait_for_speed_change(pp);
419 dev_err(pp->dev, "Failed to bring link up!\n");
423 /* Make sure link training is finished as well! */
424 ret = imx6_pcie_wait_for_link(pp);
426 dev_err(pp->dev, "Failed to bring link up!\n");
430 tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
431 dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
435 static void imx6_pcie_host_init(struct pcie_port *pp)
437 imx6_pcie_assert_core_reset(pp);
439 imx6_pcie_init_phy(pp);
441 imx6_pcie_deassert_core_reset(pp);
443 dw_pcie_setup_rc(pp);
445 imx6_pcie_establish_link(pp);
447 if (IS_ENABLED(CONFIG_PCI_MSI))
448 dw_pcie_msi_init(pp);
451 static void imx6_pcie_reset_phy(struct pcie_port *pp)
455 pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
456 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
457 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
458 pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
460 usleep_range(2000, 3000);
462 pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
463 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
464 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
465 pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
468 static int imx6_pcie_link_up(struct pcie_port *pp)
470 u32 rc, debug_r0, rx_valid;
474 * Test if the PHY reports that the link is up and also that the LTSSM
475 * training finished. There are three possible states of the link when
476 * this code is called:
477 * 1) The link is DOWN (unlikely)
478 * The link didn't come up yet for some reason. This usually means
479 * we have a real problem somewhere. Reset the PHY and exit. This
480 * state calls for inspection of the DEBUG registers.
481 * 2) The link is UP, but still in LTSSM training
482 * Wait for the training to finish, which should take a very short
483 * time. If the training does not finish, we have a problem and we
484 * need to inspect the DEBUG registers. If the training does finish,
485 * the link is up and operating correctly.
486 * 3) The link is UP and no longer in LTSSM training
487 * The link is up and operating correctly.
490 rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
491 if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
493 if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
497 dev_dbg(pp->dev, "Link is up, but still in training\n");
499 * Wait a little bit, then re-check if the link finished
502 usleep_range(1000, 2000);
505 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
506 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
507 * If (MAC/LTSSM.state == Recovery.RcvrLock)
508 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
511 pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
512 debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
517 if ((debug_r0 & 0x3f) != 0x0d)
520 dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
521 dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
523 imx6_pcie_reset_phy(pp);
528 static struct pcie_host_ops imx6_pcie_host_ops = {
529 .link_up = imx6_pcie_link_up,
530 .host_init = imx6_pcie_host_init,
533 static int __init imx6_add_pcie_port(struct pcie_port *pp,
534 struct platform_device *pdev)
538 if (IS_ENABLED(CONFIG_PCI_MSI)) {
539 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
540 if (pp->msi_irq <= 0) {
541 dev_err(&pdev->dev, "failed to get MSI irq\n");
545 ret = devm_request_irq(&pdev->dev, pp->msi_irq,
546 imx6_pcie_msi_handler,
547 IRQF_SHARED, "mx6-pcie-msi", pp);
549 dev_err(&pdev->dev, "failed to request MSI irq\n");
554 pp->root_bus_nr = -1;
555 pp->ops = &imx6_pcie_host_ops;
557 ret = dw_pcie_host_init(pp);
559 dev_err(&pdev->dev, "failed to initialize host\n");
566 static int __init imx6_pcie_probe(struct platform_device *pdev)
568 struct imx6_pcie *imx6_pcie;
569 struct pcie_port *pp;
570 struct device_node *np = pdev->dev.of_node;
571 struct resource *dbi_base;
574 imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
579 pp->dev = &pdev->dev;
581 /* Added for PCI abort handling */
582 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
583 "imprecise external abort");
585 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
586 pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
587 if (IS_ERR(pp->dbi_base))
588 return PTR_ERR(pp->dbi_base);
591 imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
592 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
593 ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
594 GPIOF_OUT_INIT_LOW, "PCIe reset");
596 dev_err(&pdev->dev, "unable to get reset gpio\n");
602 imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
603 if (IS_ERR(imx6_pcie->pcie_phy)) {
605 "pcie_phy clock source missing or invalid\n");
606 return PTR_ERR(imx6_pcie->pcie_phy);
609 imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
610 if (IS_ERR(imx6_pcie->pcie_bus)) {
612 "pcie_bus clock source missing or invalid\n");
613 return PTR_ERR(imx6_pcie->pcie_bus);
616 imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
617 if (IS_ERR(imx6_pcie->pcie)) {
619 "pcie clock source missing or invalid\n");
620 return PTR_ERR(imx6_pcie->pcie);
623 /* Grab GPR config register range */
624 imx6_pcie->iomuxc_gpr =
625 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
626 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
627 dev_err(&pdev->dev, "unable to find iomuxc registers\n");
628 return PTR_ERR(imx6_pcie->iomuxc_gpr);
631 ret = imx6_add_pcie_port(pp, pdev);
635 platform_set_drvdata(pdev, imx6_pcie);
639 static void imx6_pcie_shutdown(struct platform_device *pdev)
641 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
643 /* bring down link, so bootloader gets clean state in case of reboot */
644 imx6_pcie_assert_core_reset(&imx6_pcie->pp);
647 static const struct of_device_id imx6_pcie_of_match[] = {
648 { .compatible = "fsl,imx6q-pcie", },
651 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
653 static struct platform_driver imx6_pcie_driver = {
655 .name = "imx6q-pcie",
656 .of_match_table = imx6_pcie_of_match,
658 .shutdown = imx6_pcie_shutdown,
661 /* Freescale PCIe driver does not allow module unload */
663 static int __init imx6_pcie_init(void)
665 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
667 module_init(imx6_pcie_init);
669 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
670 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
671 MODULE_LICENSE("GPL v2");