2 * PCIe host controller driver for Texas Instruments Keystone SoCs
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 * Implementation based on pci-exynos.c and pcie-designware.c
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/irqdomain.h>
19 #include <linux/module.h>
20 #include <linux/msi.h>
21 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy/phy.h>
26 #include <linux/resource.h>
27 #include <linux/signal.h>
29 #include "pcie-designware.h"
30 #include "pci-keystone.h"
32 #define DRIVER_NAME "keystone-pcie"
34 /* driver specific constants */
35 #define MAX_MSI_HOST_IRQS 8
36 #define MAX_LEGACY_HOST_IRQS 4
39 #define PCIE_CAP_BASE 0x70
41 /* PCIE controller device IDs */
42 #define PCIE_RC_K2HK 0xb008
43 #define PCIE_RC_K2E 0xb009
44 #define PCIE_RC_K2L 0xb00a
46 #define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
48 static void quirk_limit_mrrs(struct pci_dev *dev)
50 struct pci_bus *bus = dev->bus;
51 struct pci_dev *bridge = bus->self;
52 static const struct pci_device_id rc_pci_devids[] = {
53 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
54 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
55 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
56 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
57 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
58 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
62 if (pci_is_root_bus(bus))
65 /* look for the host bridge */
66 while (!pci_is_root_bus(bus)) {
73 * Keystone PCI controller has a h/w limitation of
74 * 256 bytes maximum read request size. It can't handle
75 * anything higher than this. So force this limit on
76 * all downstream devices.
78 if (pci_match_id(rc_pci_devids, bridge)) {
79 if (pcie_get_readrq(dev) > 256) {
80 dev_info(&dev->dev, "limiting MRRS to 256\n");
81 pcie_set_readrq(dev, 256);
86 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
88 static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
90 struct pcie_port *pp = &ks_pcie->pp;
95 if (dw_pcie_link_up(pp)) {
96 dev_err(pp->dev, "Link already up\n");
100 ks_dw_pcie_initiate_link_train(ks_pcie);
101 /* check if the link is up or not */
102 for (retries = 0; retries < 200; retries++) {
103 if (dw_pcie_link_up(pp))
105 usleep_range(100, 1000);
106 ks_dw_pcie_initiate_link_train(ks_pcie);
109 dev_err(pp->dev, "phy link never came up\n");
113 static void ks_pcie_msi_irq_handler(unsigned int __irq, struct irq_desc *desc)
115 unsigned int irq = irq_desc_get_irq(desc);
116 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
117 u32 offset = irq - ks_pcie->msi_host_irqs[0];
118 struct pcie_port *pp = &ks_pcie->pp;
119 struct irq_chip *chip = irq_desc_get_chip(desc);
121 dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
124 * The chained irq handler installation would have replaced normal
125 * interrupt driver handler so we need to take care of mask/unmask and
128 chained_irq_enter(chip, desc);
129 ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
130 chained_irq_exit(chip, desc);
134 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
135 * @irq: IRQ line for legacy interrupts
136 * @desc: Pointer to irq descriptor
138 * Traverse through pending legacy interrupts and invoke handler for each. Also
139 * takes care of interrupt controller level mask/ack operation.
141 static void ks_pcie_legacy_irq_handler(unsigned int __irq,
142 struct irq_desc *desc)
144 unsigned int irq = irq_desc_get_irq(desc);
145 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
146 struct pcie_port *pp = &ks_pcie->pp;
147 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
148 struct irq_chip *chip = irq_desc_get_chip(desc);
150 dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
153 * The chained irq handler installation would have replaced normal
154 * interrupt driver handler so we need to take care of mask/unmask and
157 chained_irq_enter(chip, desc);
158 ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
159 chained_irq_exit(chip, desc);
162 static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
163 char *controller, int *num_irqs)
165 int temp, max_host_irqs, legacy = 1, *host_irqs, ret = -EINVAL;
166 struct device *dev = ks_pcie->pp.dev;
167 struct device_node *np_pcie = dev->of_node, **np_temp;
169 if (!strcmp(controller, "msi-interrupt-controller"))
173 np_temp = &ks_pcie->legacy_intc_np;
174 max_host_irqs = MAX_LEGACY_HOST_IRQS;
175 host_irqs = &ks_pcie->legacy_host_irqs[0];
177 np_temp = &ks_pcie->msi_intc_np;
178 max_host_irqs = MAX_MSI_HOST_IRQS;
179 host_irqs = &ks_pcie->msi_host_irqs[0];
182 /* interrupt controller is in a child node */
183 *np_temp = of_find_node_by_name(np_pcie, controller);
185 dev_err(dev, "Node for %s is absent\n", controller);
188 temp = of_irq_count(*np_temp);
191 if (temp > max_host_irqs)
192 dev_warn(dev, "Too many %s interrupts defined %u\n",
193 (legacy ? "legacy" : "MSI"), temp);
196 * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
199 for (temp = 0; temp < max_host_irqs; temp++) {
200 host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
201 if (!host_irqs[temp])
212 static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
217 for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
218 irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
219 ks_pcie_legacy_irq_handler,
222 ks_dw_pcie_enable_legacy_irqs(ks_pcie);
225 if (IS_ENABLED(CONFIG_PCI_MSI)) {
226 for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
227 irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
228 ks_pcie_msi_irq_handler,
235 * When a PCI device does not exist during config cycles, keystone host gets a
236 * bus error instead of returning 0xffffffff. This handler always returns 0
237 * for this kind of faults.
239 static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
240 struct pt_regs *regs)
242 unsigned long instr = *(unsigned long *) instruction_pointer(regs);
244 if ((instr & 0x0e100090) == 0x00100090) {
245 int reg = (instr >> 12) & 15;
247 regs->uregs[reg] = -1;
254 static void __init ks_pcie_host_init(struct pcie_port *pp)
256 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
259 ks_pcie_establish_link(ks_pcie);
260 ks_dw_pcie_setup_rc_app_regs(ks_pcie);
261 ks_pcie_setup_interrupts(ks_pcie);
262 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
263 pp->dbi_base + PCI_IO_BASE);
265 /* update the Vendor ID */
266 writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
268 /* update the DEV_STAT_CTRL to publish right mrrs */
269 val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
270 val &= ~PCI_EXP_DEVCTL_READRQ;
271 /* set the mrrs to 256 bytes */
273 writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
276 * PCIe access errors that result into OCP errors are caught by ARM as
279 hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
280 "Asynchronous external abort");
283 static struct pcie_host_ops keystone_pcie_host_ops = {
284 .rd_other_conf = ks_dw_pcie_rd_other_conf,
285 .wr_other_conf = ks_dw_pcie_wr_other_conf,
286 .link_up = ks_dw_pcie_link_up,
287 .host_init = ks_pcie_host_init,
288 .msi_set_irq = ks_dw_pcie_msi_set_irq,
289 .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
290 .get_msi_addr = ks_dw_pcie_get_msi_addr,
291 .msi_host_init = ks_dw_pcie_msi_host_init,
292 .scan_bus = ks_dw_pcie_v3_65_scan_bus,
295 static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
296 struct platform_device *pdev)
298 struct pcie_port *pp = &ks_pcie->pp;
301 ret = ks_pcie_get_irq_controller_info(ks_pcie,
302 "legacy-interrupt-controller",
303 &ks_pcie->num_legacy_host_irqs);
307 if (IS_ENABLED(CONFIG_PCI_MSI)) {
308 ret = ks_pcie_get_irq_controller_info(ks_pcie,
309 "msi-interrupt-controller",
310 &ks_pcie->num_msi_host_irqs);
315 pp->root_bus_nr = -1;
316 pp->ops = &keystone_pcie_host_ops;
317 ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
319 dev_err(&pdev->dev, "failed to initialize host\n");
326 static const struct of_device_id ks_pcie_of_match[] = {
329 .compatible = "ti,keystone-pcie",
333 MODULE_DEVICE_TABLE(of, ks_pcie_of_match);
335 static int __exit ks_pcie_remove(struct platform_device *pdev)
337 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
339 clk_disable_unprepare(ks_pcie->clk);
344 static int __init ks_pcie_probe(struct platform_device *pdev)
346 struct device *dev = &pdev->dev;
347 struct keystone_pcie *ks_pcie;
348 struct pcie_port *pp;
349 struct resource *res;
354 ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
361 /* initialize SerDes Phy if present */
362 phy = devm_phy_get(dev, "pcie-phy");
363 if (!IS_ERR_OR_NULL(phy)) {
369 /* index 2 is to read PCI DEVICE_ID */
370 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
371 reg_p = devm_ioremap_resource(dev, res);
373 return PTR_ERR(reg_p);
374 ks_pcie->device_id = readl(reg_p) >> 16;
375 devm_iounmap(dev, reg_p);
376 devm_release_mem_region(dev, res->start, resource_size(res));
379 platform_set_drvdata(pdev, ks_pcie);
380 ks_pcie->clk = devm_clk_get(dev, "pcie");
381 if (IS_ERR(ks_pcie->clk)) {
382 dev_err(dev, "Failed to get pcie rc clock\n");
383 return PTR_ERR(ks_pcie->clk);
385 ret = clk_prepare_enable(ks_pcie->clk);
389 ret = ks_add_pcie_port(ks_pcie, pdev);
395 clk_disable_unprepare(ks_pcie->clk);
400 static struct platform_driver ks_pcie_driver __refdata = {
401 .probe = ks_pcie_probe,
402 .remove = __exit_p(ks_pcie_remove),
404 .name = "keystone-pcie",
405 .of_match_table = of_match_ptr(ks_pcie_of_match),
409 module_platform_driver(ks_pcie_driver);
411 MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
412 MODULE_DESCRIPTION("Keystone PCIe host controller driver");
413 MODULE_LICENSE("GPL v2");