2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/mbus.h>
14 #include <linux/slab.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
22 * PCIe unit register offsets.
24 #define PCIE_DEV_ID_OFF 0x0000
25 #define PCIE_CMD_OFF 0x0004
26 #define PCIE_DEV_REV_OFF 0x0008
27 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
28 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
29 #define PCIE_HEADER_LOG_4_OFF 0x0128
30 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
31 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
32 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
33 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
34 #define PCIE_WIN5_CTRL_OFF 0x1880
35 #define PCIE_WIN5_BASE_OFF 0x1884
36 #define PCIE_WIN5_REMAP_OFF 0x188c
37 #define PCIE_CONF_ADDR_OFF 0x18f8
38 #define PCIE_CONF_ADDR_EN 0x80000000
39 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
40 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
41 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
42 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
43 #define PCIE_CONF_ADDR(bus, devfn, where) \
44 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
45 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
47 #define PCIE_CONF_DATA_OFF 0x18fc
48 #define PCIE_MASK_OFF 0x1910
49 #define PCIE_MASK_ENABLE_INTS 0x0f000000
50 #define PCIE_CTRL_OFF 0x1a00
51 #define PCIE_CTRL_X1_MODE 0x0001
52 #define PCIE_STAT_OFF 0x1a04
53 #define PCIE_STAT_BUS 0xff00
54 #define PCIE_STAT_DEV 0x1f0000
55 #define PCIE_STAT_LINK_DOWN BIT(0)
56 #define PCIE_DEBUG_CTRL 0x1a60
57 #define PCIE_DEBUG_SOFT_RESET BIT(20)
60 * This product ID is registered by Marvell, and used when the Marvell
61 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
62 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
65 #define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
67 /* PCI configuration space of a PCI-to-PCI bridge */
68 struct mvebu_sw_pci_bridge {
83 u8 secondary_latency_timer;
100 struct mvebu_pcie_port;
102 /* Structure representing all PCIe interfaces */
104 struct platform_device *pdev;
105 struct mvebu_pcie_port *ports;
107 struct resource realio;
109 struct resource busn;
113 /* Structure representing one PCIe interface */
114 struct mvebu_pcie_port {
117 spinlock_t conf_lock;
122 unsigned int mem_target;
123 unsigned int mem_attr;
124 unsigned int io_target;
125 unsigned int io_attr;
127 struct mvebu_sw_pci_bridge bridge;
128 struct device_node *dn;
129 struct mvebu_pcie *pcie;
130 phys_addr_t memwin_base;
132 phys_addr_t iowin_base;
136 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
138 return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
141 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
145 stat = readl(port->base + PCIE_STAT_OFF);
146 stat &= ~PCIE_STAT_BUS;
148 writel(stat, port->base + PCIE_STAT_OFF);
151 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
155 stat = readl(port->base + PCIE_STAT_OFF);
156 stat &= ~PCIE_STAT_DEV;
158 writel(stat, port->base + PCIE_STAT_OFF);
162 * Setup PCIE BARs and Address Decode Wins:
163 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
164 * WIN[0-3] -> DRAM bank[0-3]
166 static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
168 const struct mbus_dram_target_info *dram;
172 dram = mv_mbus_dram_info();
174 /* First, disable and clear BARs and windows. */
175 for (i = 1; i < 3; i++) {
176 writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
177 writel(0, port->base + PCIE_BAR_LO_OFF(i));
178 writel(0, port->base + PCIE_BAR_HI_OFF(i));
181 for (i = 0; i < 5; i++) {
182 writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
183 writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
184 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
187 writel(0, port->base + PCIE_WIN5_CTRL_OFF);
188 writel(0, port->base + PCIE_WIN5_BASE_OFF);
189 writel(0, port->base + PCIE_WIN5_REMAP_OFF);
191 /* Setup windows for DDR banks. Count total DDR size on the fly. */
193 for (i = 0; i < dram->num_cs; i++) {
194 const struct mbus_dram_window *cs = dram->cs + i;
196 writel(cs->base & 0xffff0000,
197 port->base + PCIE_WIN04_BASE_OFF(i));
198 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
199 writel(((cs->size - 1) & 0xffff0000) |
200 (cs->mbus_attr << 8) |
201 (dram->mbus_dram_target_id << 4) | 1,
202 port->base + PCIE_WIN04_CTRL_OFF(i));
207 /* Round up 'size' to the nearest power of two. */
208 if ((size & (size - 1)) != 0)
209 size = 1 << fls(size);
211 /* Setup BAR[1] to all DRAM banks. */
212 writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
213 writel(0, port->base + PCIE_BAR_HI_OFF(1));
214 writel(((size - 1) & 0xffff0000) | 1,
215 port->base + PCIE_BAR_CTRL_OFF(1));
218 static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
223 /* Point PCIe unit MBUS decode windows to DRAM space. */
224 mvebu_pcie_setup_wins(port);
226 /* Master + slave enable. */
227 cmd = readw(port->base + PCIE_CMD_OFF);
228 cmd |= PCI_COMMAND_IO;
229 cmd |= PCI_COMMAND_MEMORY;
230 cmd |= PCI_COMMAND_MASTER;
231 writew(cmd, port->base + PCIE_CMD_OFF);
233 /* Enable interrupt lines A-D. */
234 mask = readl(port->base + PCIE_MASK_OFF);
235 mask |= PCIE_MASK_ENABLE_INTS;
236 writel(mask, port->base + PCIE_MASK_OFF);
239 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
241 u32 devfn, int where, int size, u32 *val)
243 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
244 port->base + PCIE_CONF_ADDR_OFF);
246 *val = readl(port->base + PCIE_CONF_DATA_OFF);
249 *val = (*val >> (8 * (where & 3))) & 0xff;
251 *val = (*val >> (8 * (where & 3))) & 0xffff;
253 return PCIBIOS_SUCCESSFUL;
256 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
258 u32 devfn, int where, int size, u32 val)
260 int ret = PCIBIOS_SUCCESSFUL;
262 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
263 port->base + PCIE_CONF_ADDR_OFF);
266 writel(val, port->base + PCIE_CONF_DATA_OFF);
268 writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
270 writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
272 ret = PCIBIOS_BAD_REGISTER_NUMBER;
277 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
281 /* Are the new iobase/iolimit values invalid? */
282 if (port->bridge.iolimit < port->bridge.iobase ||
283 port->bridge.iolimitupper < port->bridge.iobaseupper) {
285 /* If a window was configured, remove it */
286 if (port->iowin_base) {
287 mvebu_mbus_del_window(port->iowin_base,
289 port->iowin_base = 0;
290 port->iowin_size = 0;
297 * We read the PCI-to-PCI bridge emulated registers, and
298 * calculate the base address and size of the address decoding
299 * window to setup, according to the PCI-to-PCI bridge
300 * specifications. iobase is the bus address, port->iowin_base
301 * is the CPU address.
303 iobase = ((port->bridge.iobase & 0xF0) << 8) |
304 (port->bridge.iobaseupper << 16);
305 port->iowin_base = port->pcie->io.start + iobase;
306 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
307 (port->bridge.iolimitupper << 16)) -
310 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
311 port->iowin_base, port->iowin_size,
314 pci_ioremap_io(iobase, port->iowin_base);
317 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
319 /* Are the new membase/memlimit values invalid? */
320 if (port->bridge.memlimit < port->bridge.membase) {
322 /* If a window was configured, remove it */
323 if (port->memwin_base) {
324 mvebu_mbus_del_window(port->memwin_base,
326 port->memwin_base = 0;
327 port->memwin_size = 0;
334 * We read the PCI-to-PCI bridge emulated registers, and
335 * calculate the base address and size of the address decoding
336 * window to setup, according to the PCI-to-PCI bridge
339 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
341 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
344 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
345 port->memwin_base, port->memwin_size);
349 * Initialize the configuration space of the PCI-to-PCI bridge
350 * associated with the given PCIe interface.
352 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
354 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
356 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
358 bridge->class = PCI_CLASS_BRIDGE_PCI;
359 bridge->vendor = PCI_VENDOR_ID_MARVELL;
360 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
361 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
362 bridge->cache_line_size = 0x10;
364 /* We support 32 bits I/O addressing */
365 bridge->iobase = PCI_IO_RANGE_TYPE_32;
366 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
370 * Read the configuration space of the PCI-to-PCI bridge associated to
371 * the given PCIe interface.
373 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
374 unsigned int where, int size, u32 *value)
376 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
378 switch (where & ~3) {
380 *value = bridge->device << 16 | bridge->vendor;
384 *value = bridge->command;
387 case PCI_CLASS_REVISION:
388 *value = bridge->class << 16 | bridge->interface << 8 |
392 case PCI_CACHE_LINE_SIZE:
393 *value = bridge->bist << 24 | bridge->header_type << 16 |
394 bridge->latency_timer << 8 | bridge->cache_line_size;
397 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
398 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
401 case PCI_PRIMARY_BUS:
402 *value = (bridge->secondary_latency_timer << 24 |
403 bridge->subordinate_bus << 16 |
404 bridge->secondary_bus << 8 |
405 bridge->primary_bus);
409 *value = (bridge->secondary_status << 16 |
410 bridge->iolimit << 8 |
414 case PCI_MEMORY_BASE:
415 *value = (bridge->memlimit << 16 | bridge->membase);
418 case PCI_PREF_MEMORY_BASE:
422 case PCI_IO_BASE_UPPER16:
423 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
426 case PCI_ROM_ADDRESS1:
432 return PCIBIOS_BAD_REGISTER_NUMBER;
436 *value = (*value >> (8 * (where & 3))) & 0xffff;
438 *value = (*value >> (8 * (where & 3))) & 0xff;
440 return PCIBIOS_SUCCESSFUL;
443 /* Write to the PCI-to-PCI bridge configuration space */
444 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
445 unsigned int where, int size, u32 value)
447 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
454 mask = ~(0xffff << ((where & 3) * 8));
456 mask = ~(0xff << ((where & 3) * 8));
458 return PCIBIOS_BAD_REGISTER_NUMBER;
460 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
464 value = (reg & mask) | value << ((where & 3) * 8);
466 switch (where & ~3) {
468 bridge->command = value & 0xffff;
471 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
472 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
477 * We also keep bit 1 set, it is a read-only bit that
478 * indicates we support 32 bits addressing for the
481 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
482 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
483 bridge->secondary_status = value >> 16;
484 mvebu_pcie_handle_iobase_change(port);
487 case PCI_MEMORY_BASE:
488 bridge->membase = value & 0xffff;
489 bridge->memlimit = value >> 16;
490 mvebu_pcie_handle_membase_change(port);
493 case PCI_IO_BASE_UPPER16:
494 bridge->iobaseupper = value & 0xffff;
495 bridge->iolimitupper = value >> 16;
496 mvebu_pcie_handle_iobase_change(port);
499 case PCI_PRIMARY_BUS:
500 bridge->primary_bus = value & 0xff;
501 bridge->secondary_bus = (value >> 8) & 0xff;
502 bridge->subordinate_bus = (value >> 16) & 0xff;
503 bridge->secondary_latency_timer = (value >> 24) & 0xff;
504 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
511 return PCIBIOS_SUCCESSFUL;
514 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
516 return sys->private_data;
519 static struct mvebu_pcie_port *
520 mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
525 for (i = 0; i < pcie->nports; i++) {
526 struct mvebu_pcie_port *port = &pcie->ports[i];
527 if (bus->number == 0 && port->devfn == devfn)
529 if (bus->number != 0 &&
530 bus->number >= port->bridge.secondary_bus &&
531 bus->number <= port->bridge.subordinate_bus)
538 /* PCI configuration space write function */
539 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
540 int where, int size, u32 val)
542 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
543 struct mvebu_pcie_port *port;
547 port = mvebu_pcie_find_port(pcie, bus, devfn);
549 return PCIBIOS_DEVICE_NOT_FOUND;
551 /* Access the emulated PCI-to-PCI bridge */
552 if (bus->number == 0)
553 return mvebu_sw_pci_bridge_write(port, where, size, val);
556 return PCIBIOS_DEVICE_NOT_FOUND;
559 * On the secondary bus, we don't want to expose any other
560 * device than the device physically connected in the PCIe
561 * slot, visible in slot 0. In slot 1, there's a special
562 * Marvell device that only makes sense when the Armada is
563 * used as a PCIe endpoint.
565 if (bus->number == port->bridge.secondary_bus &&
566 PCI_SLOT(devfn) != 0)
567 return PCIBIOS_DEVICE_NOT_FOUND;
569 /* Access the real PCIe interface */
570 spin_lock_irqsave(&port->conf_lock, flags);
571 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
573 spin_unlock_irqrestore(&port->conf_lock, flags);
578 /* PCI configuration space read function */
579 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
582 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
583 struct mvebu_pcie_port *port;
587 port = mvebu_pcie_find_port(pcie, bus, devfn);
590 return PCIBIOS_DEVICE_NOT_FOUND;
593 /* Access the emulated PCI-to-PCI bridge */
594 if (bus->number == 0)
595 return mvebu_sw_pci_bridge_read(port, where, size, val);
597 if (!port->haslink) {
599 return PCIBIOS_DEVICE_NOT_FOUND;
603 * On the secondary bus, we don't want to expose any other
604 * device than the device physically connected in the PCIe
605 * slot, visible in slot 0. In slot 1, there's a special
606 * Marvell device that only makes sense when the Armada is
607 * used as a PCIe endpoint.
609 if (bus->number == port->bridge.secondary_bus &&
610 PCI_SLOT(devfn) != 0) {
612 return PCIBIOS_DEVICE_NOT_FOUND;
615 /* Access the real PCIe interface */
616 spin_lock_irqsave(&port->conf_lock, flags);
617 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
619 spin_unlock_irqrestore(&port->conf_lock, flags);
624 static struct pci_ops mvebu_pcie_ops = {
625 .read = mvebu_pcie_rd_conf,
626 .write = mvebu_pcie_wr_conf,
629 static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
631 struct mvebu_pcie *pcie = sys_to_pcie(sys);
634 pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
635 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
636 pci_add_resource(&sys->resources, &pcie->busn);
638 for (i = 0; i < pcie->nports; i++) {
639 struct mvebu_pcie_port *port = &pcie->ports[i];
642 mvebu_pcie_setup_hw(port);
648 static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
653 ret = of_irq_map_pci(dev, &oirq);
657 return irq_create_of_mapping(oirq.controller, oirq.specifier,
661 static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
663 struct mvebu_pcie *pcie = sys_to_pcie(sys);
666 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
667 &mvebu_pcie_ops, sys, &sys->resources);
671 pci_scan_child_bus(bus);
676 resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
677 const struct resource *res,
678 resource_size_t start,
679 resource_size_t size,
680 resource_size_t align)
682 if (dev->bus->number != 0)
686 * On the PCI-to-PCI bridge side, the I/O windows must have at
687 * least a 64 KB size and be aligned on their size, and the
688 * memory windows must have at least a 1 MB size and be
689 * aligned on their size
691 if (res->flags & IORESOURCE_IO)
692 return round_up(start, max((resource_size_t)SZ_64K, size));
693 else if (res->flags & IORESOURCE_MEM)
694 return round_up(start, max((resource_size_t)SZ_1M, size));
699 static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
703 memset(&hw, 0, sizeof(hw));
705 hw.nr_controllers = 1;
706 hw.private_data = (void **)&pcie;
707 hw.setup = mvebu_pcie_setup;
708 hw.scan = mvebu_pcie_scan_bus;
709 hw.map_irq = mvebu_pcie_map_irq;
710 hw.ops = &mvebu_pcie_ops;
711 hw.align_resource = mvebu_pcie_align_resource;
713 pci_common_init(&hw);
717 * Looks up the list of register addresses encoded into the reg =
718 * <...> property for one that matches the given port/lane. Once
721 static void __iomem * __init
722 mvebu_pcie_map_registers(struct platform_device *pdev,
723 struct device_node *np,
724 struct mvebu_pcie_port *port)
726 struct resource regs;
729 ret = of_address_to_resource(np, 0, ®s);
733 return devm_ioremap_resource(&pdev->dev, ®s);
736 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
737 #define DT_TYPE_IO 0x1
738 #define DT_TYPE_MEM32 0x2
739 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
740 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
742 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
743 unsigned long type, int *tgt, int *attr)
745 const int na = 3, ns = 2;
747 int rlen, nranges, rangesz, pna, i;
749 range = of_get_property(np, "ranges", &rlen);
753 pna = of_n_addr_cells(np);
754 rangesz = pna + na + ns;
755 nranges = rlen / sizeof(__be32) / rangesz;
757 for (i = 0; i < nranges; i++) {
758 u32 flags = of_read_number(range, 1);
759 u32 slot = of_read_number(range, 2);
760 u64 cpuaddr = of_read_number(range + na, pna);
763 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
764 rtype = IORESOURCE_IO;
765 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
766 rtype = IORESOURCE_MEM;
768 if (slot == PCI_SLOT(devfn) && type == rtype) {
769 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
770 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
780 static int __init mvebu_pcie_probe(struct platform_device *pdev)
782 struct mvebu_pcie *pcie;
783 struct device_node *np = pdev->dev.of_node;
784 struct device_node *child;
787 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
794 /* Get the PCIe memory and I/O aperture */
795 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
796 if (resource_size(&pcie->mem) == 0) {
797 dev_err(&pdev->dev, "invalid memory aperture size\n");
801 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
802 if (resource_size(&pcie->io) == 0) {
803 dev_err(&pdev->dev, "invalid I/O aperture size\n");
807 pcie->realio.flags = pcie->io.flags;
808 pcie->realio.start = PCIBIOS_MIN_IO;
809 pcie->realio.end = min_t(resource_size_t,
811 resource_size(&pcie->io));
813 /* Get the bus range */
814 ret = of_pci_parse_bus_range(np, &pcie->busn);
816 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
821 for_each_child_of_node(pdev->dev.of_node, child) {
822 if (!of_device_is_available(child))
827 pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
828 sizeof(struct mvebu_pcie_port),
834 for_each_child_of_node(pdev->dev.of_node, child) {
835 struct mvebu_pcie_port *port = &pcie->ports[i];
837 if (!of_device_is_available(child))
842 if (of_property_read_u32(child, "marvell,pcie-port",
845 "ignoring PCIe DT node, missing pcie-port property\n");
849 if (of_property_read_u32(child, "marvell,pcie-lane",
853 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
854 port->port, port->lane);
856 port->devfn = of_pci_get_devfn(child);
860 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
861 &port->mem_target, &port->mem_attr);
863 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
864 port->port, port->lane);
868 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
869 &port->io_target, &port->io_attr);
871 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
872 port->port, port->lane);
876 port->base = mvebu_pcie_map_registers(pdev, child, port);
877 if (IS_ERR(port->base)) {
878 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
879 port->port, port->lane);
884 mvebu_pcie_set_local_dev_nr(port, 1);
886 if (mvebu_pcie_link_up(port)) {
888 dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
889 port->port, port->lane);
892 dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
893 port->port, port->lane);
896 port->clk = of_clk_get_by_name(child, NULL);
897 if (IS_ERR(port->clk)) {
898 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
899 port->port, port->lane);
907 clk_prepare_enable(port->clk);
908 spin_lock_init(&port->conf_lock);
910 mvebu_sw_pci_bridge_init(port);
915 mvebu_pcie_enable(pcie);
920 static const struct of_device_id mvebu_pcie_of_match_table[] = {
921 { .compatible = "marvell,armada-xp-pcie", },
922 { .compatible = "marvell,armada-370-pcie", },
923 { .compatible = "marvell,kirkwood-pcie", },
926 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
928 static struct platform_driver mvebu_pcie_driver = {
930 .owner = THIS_MODULE,
931 .name = "mvebu-pcie",
933 of_match_ptr(mvebu_pcie_of_match_table),
937 static int __init mvebu_pcie_init(void)
939 return platform_driver_probe(&mvebu_pcie_driver,
943 subsys_initcall(mvebu_pcie_init);
945 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
946 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
947 MODULE_LICENSE("GPLv2");