2 * PCIe host controller driver for Tegra SoCs
4 * Copyright (c) 2010, CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
7 * Based on NVIDIA PCIe driver
8 * Copyright (c) 2008-2009, NVIDIA Corporation.
10 * Bits taken from arch/arm/mach-dove/pcie.c
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 #include <linux/clk.h>
28 #include <linux/debugfs.h>
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/irqdomain.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/msi.h>
37 #include <linux/of_address.h>
38 #include <linux/of_pci.h>
39 #include <linux/of_platform.h>
40 #include <linux/pci.h>
41 #include <linux/phy/phy.h>
42 #include <linux/platform_device.h>
43 #include <linux/reset.h>
44 #include <linux/sizes.h>
45 #include <linux/slab.h>
46 #include <linux/vmalloc.h>
47 #include <linux/regulator/consumer.h>
49 #include <soc/tegra/cpuidle.h>
50 #include <soc/tegra/pmc.h>
52 #include <asm/mach/irq.h>
53 #include <asm/mach/map.h>
54 #include <asm/mach/pci.h>
56 #define INT_PCI_MSI_NR (8 * 32)
58 /* register definitions */
60 #define AFI_AXI_BAR0_SZ 0x00
61 #define AFI_AXI_BAR1_SZ 0x04
62 #define AFI_AXI_BAR2_SZ 0x08
63 #define AFI_AXI_BAR3_SZ 0x0c
64 #define AFI_AXI_BAR4_SZ 0x10
65 #define AFI_AXI_BAR5_SZ 0x14
67 #define AFI_AXI_BAR0_START 0x18
68 #define AFI_AXI_BAR1_START 0x1c
69 #define AFI_AXI_BAR2_START 0x20
70 #define AFI_AXI_BAR3_START 0x24
71 #define AFI_AXI_BAR4_START 0x28
72 #define AFI_AXI_BAR5_START 0x2c
74 #define AFI_FPCI_BAR0 0x30
75 #define AFI_FPCI_BAR1 0x34
76 #define AFI_FPCI_BAR2 0x38
77 #define AFI_FPCI_BAR3 0x3c
78 #define AFI_FPCI_BAR4 0x40
79 #define AFI_FPCI_BAR5 0x44
81 #define AFI_CACHE_BAR0_SZ 0x48
82 #define AFI_CACHE_BAR0_ST 0x4c
83 #define AFI_CACHE_BAR1_SZ 0x50
84 #define AFI_CACHE_BAR1_ST 0x54
86 #define AFI_MSI_BAR_SZ 0x60
87 #define AFI_MSI_FPCI_BAR_ST 0x64
88 #define AFI_MSI_AXI_BAR_ST 0x68
90 #define AFI_MSI_VEC0 0x6c
91 #define AFI_MSI_VEC1 0x70
92 #define AFI_MSI_VEC2 0x74
93 #define AFI_MSI_VEC3 0x78
94 #define AFI_MSI_VEC4 0x7c
95 #define AFI_MSI_VEC5 0x80
96 #define AFI_MSI_VEC6 0x84
97 #define AFI_MSI_VEC7 0x88
99 #define AFI_MSI_EN_VEC0 0x8c
100 #define AFI_MSI_EN_VEC1 0x90
101 #define AFI_MSI_EN_VEC2 0x94
102 #define AFI_MSI_EN_VEC3 0x98
103 #define AFI_MSI_EN_VEC4 0x9c
104 #define AFI_MSI_EN_VEC5 0xa0
105 #define AFI_MSI_EN_VEC6 0xa4
106 #define AFI_MSI_EN_VEC7 0xa8
108 #define AFI_CONFIGURATION 0xac
109 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
111 #define AFI_FPCI_ERROR_MASKS 0xb0
113 #define AFI_INTR_MASK 0xb4
114 #define AFI_INTR_MASK_INT_MASK (1 << 0)
115 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
117 #define AFI_INTR_CODE 0xb8
118 #define AFI_INTR_CODE_MASK 0xf
119 #define AFI_INTR_INI_SLAVE_ERROR 1
120 #define AFI_INTR_INI_DECODE_ERROR 2
121 #define AFI_INTR_TARGET_ABORT 3
122 #define AFI_INTR_MASTER_ABORT 4
123 #define AFI_INTR_INVALID_WRITE 5
124 #define AFI_INTR_LEGACY 6
125 #define AFI_INTR_FPCI_DECODE_ERROR 7
126 #define AFI_INTR_AXI_DECODE_ERROR 8
127 #define AFI_INTR_FPCI_TIMEOUT 9
128 #define AFI_INTR_PE_PRSNT_SENSE 10
129 #define AFI_INTR_PE_CLKREQ_SENSE 11
130 #define AFI_INTR_CLKCLAMP_SENSE 12
131 #define AFI_INTR_RDY4PD_SENSE 13
132 #define AFI_INTR_P2P_ERROR 14
134 #define AFI_INTR_SIGNATURE 0xbc
135 #define AFI_UPPER_FPCI_ADDRESS 0xc0
136 #define AFI_SM_INTR_ENABLE 0xc4
137 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
138 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
139 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
140 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
141 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
142 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
143 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
144 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
146 #define AFI_AFI_INTR_ENABLE 0xc8
147 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
148 #define AFI_INTR_EN_INI_DECERR (1 << 1)
149 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
150 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
151 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
152 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
153 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
154 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
155 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
157 #define AFI_PCIE_CONFIG 0x0f8
158 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
159 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
160 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
161 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
162 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
163 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
164 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
165 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
166 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
167 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
169 #define AFI_FUSE 0x104
170 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
172 #define AFI_PEX0_CTRL 0x110
173 #define AFI_PEX1_CTRL 0x118
174 #define AFI_PEX2_CTRL 0x128
175 #define AFI_PEX_CTRL_RST (1 << 0)
176 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
177 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
178 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
180 #define AFI_PLLE_CONTROL 0x160
181 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
182 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
184 #define AFI_PEXBIAS_CTRL_0 0x168
186 #define RP_VEND_XP 0x00000F00
187 #define RP_VEND_XP_DL_UP (1 << 30)
189 #define RP_PRIV_MISC 0x00000FE0
190 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
191 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
193 #define RP_LINK_CONTROL_STATUS 0x00000090
194 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
195 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
197 #define PADS_CTL_SEL 0x0000009C
199 #define PADS_CTL 0x000000A0
200 #define PADS_CTL_IDDQ_1L (1 << 0)
201 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
202 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
204 #define PADS_PLL_CTL_TEGRA20 0x000000B8
205 #define PADS_PLL_CTL_TEGRA30 0x000000B4
206 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
207 #define PADS_PLL_CTL_LOCKDET (1 << 8)
208 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
209 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
210 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
211 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
212 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
213 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
214 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
215 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
217 #define PADS_REFCLK_CFG0 0x000000C8
218 #define PADS_REFCLK_CFG1 0x000000CC
219 #define PADS_REFCLK_BIAS 0x000000D0
222 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
223 * entries, one entry per PCIe port. These field definitions and desired
224 * values aren't in the TRM, but do come from NVIDIA.
226 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
227 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
228 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
229 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
231 /* Default value provided by HW engineering is 0xfa5c */
232 #define PADS_REFCLK_CFG_VALUE \
234 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
235 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
236 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
237 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
241 struct msi_controller chip;
242 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
243 struct irq_domain *domain;
249 /* used to differentiate between Tegra SoC generations */
250 struct tegra_pcie_soc_data {
251 unsigned int num_ports;
252 unsigned int msi_base_shift;
255 bool has_pex_clkreq_en;
256 bool has_pex_bias_ctrl;
257 bool has_intr_prsnt_sense;
262 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
264 return container_of(chip, struct tegra_msi, chip);
274 struct list_head buses;
281 struct resource prefetch;
282 struct resource busn;
289 struct reset_control *pex_rst;
290 struct reset_control *afi_rst;
291 struct reset_control *pcie_xrst;
295 struct tegra_msi msi;
297 struct list_head ports;
298 unsigned int num_ports;
301 struct regulator_bulk_data *supplies;
302 unsigned int num_supplies;
304 const struct tegra_pcie_soc_data *soc_data;
305 struct dentry *debugfs;
308 struct tegra_pcie_port {
309 struct tegra_pcie *pcie;
310 struct list_head list;
311 struct resource regs;
317 struct tegra_pcie_bus {
318 struct vm_struct *area;
319 struct list_head list;
323 static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys)
325 return sys->private_data;
328 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
329 unsigned long offset)
331 writel(value, pcie->afi + offset);
334 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
336 return readl(pcie->afi + offset);
339 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
340 unsigned long offset)
342 writel(value, pcie->pads + offset);
345 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
347 return readl(pcie->pads + offset);
351 * The configuration space mapping on Tegra is somewhat similar to the ECAM
352 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
353 * register accesses are mapped:
355 * [27:24] extended register number
357 * [15:11] device number
358 * [10: 8] function number
359 * [ 7: 0] register number
361 * Mapping the whole extended configuration space would require 256 MiB of
362 * virtual address space, only a small part of which will actually be used.
363 * To work around this, a 1 MiB of virtual addresses are allocated per bus
364 * when the bus is first accessed. When the physical range is mapped, the
365 * the bus number bits are hidden so that the extended register number bits
366 * appear as bits [19:16]. Therefore the virtual mapping looks like this:
368 * [19:16] extended register number
369 * [15:11] device number
370 * [10: 8] function number
371 * [ 7: 0] register number
373 * This is achieved by stitching together 16 chunks of 64 KiB of physical
374 * address space via the MMU.
376 static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
378 return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
379 (PCI_FUNC(devfn) << 8) | (where & 0xfc);
382 static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
385 pgprot_t prot = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_XN |
386 L_PTE_MT_DEV_SHARED | L_PTE_SHARED;
387 phys_addr_t cs = pcie->cs->start;
388 struct tegra_pcie_bus *bus;
392 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
394 return ERR_PTR(-ENOMEM);
396 INIT_LIST_HEAD(&bus->list);
399 /* allocate 1 MiB of virtual addresses */
400 bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
406 /* map each of the 16 chunks of 64 KiB each */
407 for (i = 0; i < 16; i++) {
408 unsigned long virt = (unsigned long)bus->area->addr +
410 phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
412 err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
414 dev_err(pcie->dev, "ioremap_page_range() failed: %d\n",
423 vunmap(bus->area->addr);
430 * Look up a virtual address mapping for the specified bus number. If no such
431 * mapping exists, try to create one.
433 static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie,
436 struct tegra_pcie_bus *bus;
438 list_for_each_entry(bus, &pcie->buses, list)
439 if (bus->nr == busnr)
440 return (void __iomem *)bus->area->addr;
442 bus = tegra_pcie_bus_alloc(pcie, busnr);
446 list_add_tail(&bus->list, &pcie->buses);
448 return (void __iomem *)bus->area->addr;
451 static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
455 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
456 void __iomem *addr = NULL;
458 if (bus->number == 0) {
459 unsigned int slot = PCI_SLOT(devfn);
460 struct tegra_pcie_port *port;
462 list_for_each_entry(port, &pcie->ports, list) {
463 if (port->index + 1 == slot) {
464 addr = port->base + (where & ~3);
469 addr = tegra_pcie_bus_map(pcie, bus->number);
472 "failed to map cfg. space for bus %u\n",
477 addr += tegra_pcie_conf_offset(devfn, where);
483 static struct pci_ops tegra_pcie_ops = {
484 .map_bus = tegra_pcie_conf_address,
485 .read = pci_generic_config_read32,
486 .write = pci_generic_config_write32,
489 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
491 unsigned long ret = 0;
493 switch (port->index) {
510 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
512 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
515 /* pulse reset signal */
516 value = afi_readl(port->pcie, ctrl);
517 value &= ~AFI_PEX_CTRL_RST;
518 afi_writel(port->pcie, value, ctrl);
520 usleep_range(1000, 2000);
522 value = afi_readl(port->pcie, ctrl);
523 value |= AFI_PEX_CTRL_RST;
524 afi_writel(port->pcie, value, ctrl);
527 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
529 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
530 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
533 /* enable reference clock */
534 value = afi_readl(port->pcie, ctrl);
535 value |= AFI_PEX_CTRL_REFCLK_EN;
537 if (soc->has_pex_clkreq_en)
538 value |= AFI_PEX_CTRL_CLKREQ_EN;
540 value |= AFI_PEX_CTRL_OVERRIDE_EN;
542 afi_writel(port->pcie, value, ctrl);
544 tegra_pcie_port_reset(port);
547 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
549 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
550 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
553 /* assert port reset */
554 value = afi_readl(port->pcie, ctrl);
555 value &= ~AFI_PEX_CTRL_RST;
556 afi_writel(port->pcie, value, ctrl);
558 /* disable reference clock */
559 value = afi_readl(port->pcie, ctrl);
561 if (soc->has_pex_clkreq_en)
562 value &= ~AFI_PEX_CTRL_CLKREQ_EN;
564 value &= ~AFI_PEX_CTRL_REFCLK_EN;
565 afi_writel(port->pcie, value, ctrl);
568 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
570 struct tegra_pcie *pcie = port->pcie;
572 devm_iounmap(pcie->dev, port->base);
573 devm_release_mem_region(pcie->dev, port->regs.start,
574 resource_size(&port->regs));
575 list_del(&port->list);
576 devm_kfree(pcie->dev, port);
579 /* Tegra PCIE root complex wrongly reports device class */
580 static void tegra_pcie_fixup_class(struct pci_dev *dev)
582 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
587 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
589 /* Tegra PCIE requires relaxed ordering */
590 static void tegra_pcie_relax_enable(struct pci_dev *dev)
592 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
594 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
596 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
598 struct tegra_pcie *pcie = sys_to_pcie(sys);
601 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem);
605 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->prefetch);
609 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
610 pci_add_resource_offset(&sys->resources, &pcie->prefetch,
612 pci_add_resource(&sys->resources, &pcie->busn);
614 pci_ioremap_io(pcie->pio.start, pcie->io.start);
619 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
621 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
624 tegra_cpuidle_pcie_irqs_in_use();
626 irq = of_irq_parse_and_map_pci(pdev, slot, pin);
633 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
635 const char *err_msg[] = {
643 "Response decoding error",
644 "AXI response decoding error",
645 "Transaction timeout",
646 "Slot present pin change",
647 "Slot clock request change",
648 "TMS clock ramp change",
649 "TMS ready for power down",
652 struct tegra_pcie *pcie = arg;
655 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
656 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
657 afi_writel(pcie, 0, AFI_INTR_CODE);
659 if (code == AFI_INTR_LEGACY)
662 if (code >= ARRAY_SIZE(err_msg))
666 * do not pollute kernel log with master abort reports since they
667 * happen a lot during enumeration
669 if (code == AFI_INTR_MASTER_ABORT)
670 dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
673 dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
676 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
677 code == AFI_INTR_FPCI_DECODE_ERROR) {
678 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
679 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
681 if (code == AFI_INTR_MASTER_ABORT)
682 dev_dbg(pcie->dev, " FPCI address: %10llx\n", address);
684 dev_err(pcie->dev, " FPCI address: %10llx\n", address);
691 * FPCI map is as follows:
692 * - 0xfdfc000000: I/O space
693 * - 0xfdfe000000: type 0 configuration space
694 * - 0xfdff000000: type 1 configuration space
695 * - 0xfe00000000: type 0 extended configuration space
696 * - 0xfe10000000: type 1 extended configuration space
698 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
700 u32 fpci_bar, size, axi_address;
702 /* Bar 0: type 1 extended configuration space */
703 fpci_bar = 0xfe100000;
704 size = resource_size(pcie->cs);
705 axi_address = pcie->cs->start;
706 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
707 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
708 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
710 /* Bar 1: downstream IO bar */
711 fpci_bar = 0xfdfc0000;
712 size = resource_size(&pcie->io);
713 axi_address = pcie->io.start;
714 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
715 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
716 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
718 /* Bar 2: prefetchable memory BAR */
719 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
720 size = resource_size(&pcie->prefetch);
721 axi_address = pcie->prefetch.start;
722 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
723 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
724 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
726 /* Bar 3: non prefetchable memory BAR */
727 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
728 size = resource_size(&pcie->mem);
729 axi_address = pcie->mem.start;
730 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
731 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
732 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
734 /* NULL out the remaining BARs as they are not used */
735 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
736 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
737 afi_writel(pcie, 0, AFI_FPCI_BAR4);
739 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
740 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
741 afi_writel(pcie, 0, AFI_FPCI_BAR5);
743 /* map all upstream transactions as uncached */
744 afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST);
745 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
746 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
747 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
749 /* MSI translations are setup only when needed */
750 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
751 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
752 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
753 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
756 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
758 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
761 timeout = jiffies + msecs_to_jiffies(timeout);
763 while (time_before(jiffies, timeout)) {
764 value = pads_readl(pcie, soc->pads_pll_ctl);
765 if (value & PADS_PLL_CTL_LOCKDET)
772 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
774 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
778 /* initialize internal PHY, enable up to 16 PCIE lanes */
779 pads_writel(pcie, 0x0, PADS_CTL_SEL);
781 /* override IDDQ to 1 on all 4 lanes */
782 value = pads_readl(pcie, PADS_CTL);
783 value |= PADS_CTL_IDDQ_1L;
784 pads_writel(pcie, value, PADS_CTL);
787 * Set up PHY PLL inputs select PLLE output as refclock,
788 * set TX ref sel to div10 (not div5).
790 value = pads_readl(pcie, soc->pads_pll_ctl);
791 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
792 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
793 pads_writel(pcie, value, soc->pads_pll_ctl);
796 value = pads_readl(pcie, soc->pads_pll_ctl);
797 value &= ~PADS_PLL_CTL_RST_B4SM;
798 pads_writel(pcie, value, soc->pads_pll_ctl);
800 usleep_range(20, 100);
802 /* take PLL out of reset */
803 value = pads_readl(pcie, soc->pads_pll_ctl);
804 value |= PADS_PLL_CTL_RST_B4SM;
805 pads_writel(pcie, value, soc->pads_pll_ctl);
807 /* Configure the reference clock driver */
808 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
809 pads_writel(pcie, value, PADS_REFCLK_CFG0);
810 if (soc->num_ports > 2)
811 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
813 /* wait for the PLL to lock */
814 err = tegra_pcie_pll_wait(pcie, 500);
816 dev_err(pcie->dev, "PLL failed to lock: %d\n", err);
820 /* turn off IDDQ override */
821 value = pads_readl(pcie, PADS_CTL);
822 value &= ~PADS_CTL_IDDQ_1L;
823 pads_writel(pcie, value, PADS_CTL);
825 /* enable TX/RX data */
826 value = pads_readl(pcie, PADS_CTL);
827 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
828 pads_writel(pcie, value, PADS_CTL);
833 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
835 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
836 struct tegra_pcie_port *port;
840 /* enable PLL power down */
842 value = afi_readl(pcie, AFI_PLLE_CONTROL);
843 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
844 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
845 afi_writel(pcie, value, AFI_PLLE_CONTROL);
848 /* power down PCIe slot clock bias pad */
849 if (soc->has_pex_bias_ctrl)
850 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
852 /* configure mode and disable all ports */
853 value = afi_readl(pcie, AFI_PCIE_CONFIG);
854 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
855 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
857 list_for_each_entry(port, &pcie->ports, list)
858 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
860 afi_writel(pcie, value, AFI_PCIE_CONFIG);
863 value = afi_readl(pcie, AFI_FUSE);
864 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
865 afi_writel(pcie, value, AFI_FUSE);
867 value = afi_readl(pcie, AFI_FUSE);
868 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
869 afi_writel(pcie, value, AFI_FUSE);
873 err = tegra_pcie_phy_enable(pcie);
875 err = phy_power_on(pcie->phy);
878 dev_err(pcie->dev, "failed to power on PHY: %d\n", err);
882 /* take the PCIe interface module out of reset */
883 reset_control_deassert(pcie->pcie_xrst);
885 /* finally enable PCIe */
886 value = afi_readl(pcie, AFI_CONFIGURATION);
887 value |= AFI_CONFIGURATION_EN_FPCI;
888 afi_writel(pcie, value, AFI_CONFIGURATION);
890 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
891 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
892 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
894 if (soc->has_intr_prsnt_sense)
895 value |= AFI_INTR_EN_PRSNT_SENSE;
897 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
898 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
900 /* don't enable MSI for now, only when needed */
901 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
903 /* disable all exceptions */
904 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
909 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
913 /* TODO: disable and unprepare clocks? */
915 err = phy_power_off(pcie->phy);
917 dev_warn(pcie->dev, "failed to power off PHY: %d\n", err);
919 reset_control_assert(pcie->pcie_xrst);
920 reset_control_assert(pcie->afi_rst);
921 reset_control_assert(pcie->pex_rst);
923 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
925 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
927 dev_warn(pcie->dev, "failed to disable regulators: %d\n", err);
930 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
932 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
935 reset_control_assert(pcie->pcie_xrst);
936 reset_control_assert(pcie->afi_rst);
937 reset_control_assert(pcie->pex_rst);
939 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
941 /* enable regulators */
942 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
944 dev_err(pcie->dev, "failed to enable regulators: %d\n", err);
946 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
950 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
954 reset_control_deassert(pcie->afi_rst);
956 err = clk_prepare_enable(pcie->afi_clk);
958 dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);
962 if (soc->has_cml_clk) {
963 err = clk_prepare_enable(pcie->cml_clk);
965 dev_err(pcie->dev, "failed to enable CML clock: %d\n",
971 err = clk_prepare_enable(pcie->pll_e);
973 dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
980 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
982 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
984 pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
985 if (IS_ERR(pcie->pex_clk))
986 return PTR_ERR(pcie->pex_clk);
988 pcie->afi_clk = devm_clk_get(pcie->dev, "afi");
989 if (IS_ERR(pcie->afi_clk))
990 return PTR_ERR(pcie->afi_clk);
992 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
993 if (IS_ERR(pcie->pll_e))
994 return PTR_ERR(pcie->pll_e);
996 if (soc->has_cml_clk) {
997 pcie->cml_clk = devm_clk_get(pcie->dev, "cml");
998 if (IS_ERR(pcie->cml_clk))
999 return PTR_ERR(pcie->cml_clk);
1005 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1007 pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
1008 if (IS_ERR(pcie->pex_rst))
1009 return PTR_ERR(pcie->pex_rst);
1011 pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
1012 if (IS_ERR(pcie->afi_rst))
1013 return PTR_ERR(pcie->afi_rst);
1015 pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
1016 if (IS_ERR(pcie->pcie_xrst))
1017 return PTR_ERR(pcie->pcie_xrst);
1022 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1024 struct platform_device *pdev = to_platform_device(pcie->dev);
1025 struct resource *pads, *afi, *res;
1028 err = tegra_pcie_clocks_get(pcie);
1030 dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
1034 err = tegra_pcie_resets_get(pcie);
1036 dev_err(&pdev->dev, "failed to get resets: %d\n", err);
1040 pcie->phy = devm_phy_optional_get(pcie->dev, "pcie");
1041 if (IS_ERR(pcie->phy)) {
1042 err = PTR_ERR(pcie->phy);
1043 dev_err(&pdev->dev, "failed to get PHY: %d\n", err);
1047 err = phy_init(pcie->phy);
1049 dev_err(&pdev->dev, "failed to initialize PHY: %d\n", err);
1053 err = tegra_pcie_power_on(pcie);
1055 dev_err(&pdev->dev, "failed to power up: %d\n", err);
1059 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1060 pcie->pads = devm_ioremap_resource(&pdev->dev, pads);
1061 if (IS_ERR(pcie->pads)) {
1062 err = PTR_ERR(pcie->pads);
1066 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1067 pcie->afi = devm_ioremap_resource(&pdev->dev, afi);
1068 if (IS_ERR(pcie->afi)) {
1069 err = PTR_ERR(pcie->afi);
1073 /* request configuration space, but remap later, on demand */
1074 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
1076 err = -EADDRNOTAVAIL;
1080 pcie->cs = devm_request_mem_region(pcie->dev, res->start,
1081 resource_size(res), res->name);
1083 err = -EADDRNOTAVAIL;
1087 /* request interrupt */
1088 err = platform_get_irq_byname(pdev, "intr");
1090 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1096 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1098 dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
1105 tegra_pcie_power_off(pcie);
1109 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1114 free_irq(pcie->irq, pcie);
1116 tegra_pcie_power_off(pcie);
1118 err = phy_exit(pcie->phy);
1120 dev_err(pcie->dev, "failed to teardown PHY: %d\n", err);
1125 static int tegra_msi_alloc(struct tegra_msi *chip)
1129 mutex_lock(&chip->lock);
1131 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1132 if (msi < INT_PCI_MSI_NR)
1133 set_bit(msi, chip->used);
1137 mutex_unlock(&chip->lock);
1142 static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1144 struct device *dev = chip->chip.dev;
1146 mutex_lock(&chip->lock);
1148 if (!test_bit(irq, chip->used))
1149 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1151 clear_bit(irq, chip->used);
1153 mutex_unlock(&chip->lock);
1156 static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1158 struct tegra_pcie *pcie = data;
1159 struct tegra_msi *msi = &pcie->msi;
1160 unsigned int i, processed = 0;
1162 for (i = 0; i < 8; i++) {
1163 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1166 unsigned int offset = find_first_bit(®, 32);
1167 unsigned int index = i * 32 + offset;
1170 /* clear the interrupt */
1171 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1173 irq = irq_find_mapping(msi->domain, index);
1175 if (test_bit(index, msi->used))
1176 generic_handle_irq(irq);
1178 dev_info(pcie->dev, "unhandled MSI\n");
1181 * that's weird who triggered this?
1184 dev_info(pcie->dev, "unexpected MSI\n");
1187 /* see if there's any more pending in this vector */
1188 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1194 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1197 static int tegra_msi_setup_irq(struct msi_controller *chip,
1198 struct pci_dev *pdev, struct msi_desc *desc)
1200 struct tegra_msi *msi = to_tegra_msi(chip);
1205 hwirq = tegra_msi_alloc(msi);
1209 irq = irq_create_mapping(msi->domain, hwirq);
1211 tegra_msi_free(msi, hwirq);
1215 irq_set_msi_desc(irq, desc);
1217 msg.address_lo = virt_to_phys((void *)msi->pages);
1218 /* 32 bit address only */
1222 pci_write_msi_msg(irq, &msg);
1227 static void tegra_msi_teardown_irq(struct msi_controller *chip,
1230 struct tegra_msi *msi = to_tegra_msi(chip);
1231 struct irq_data *d = irq_get_irq_data(irq);
1232 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1234 irq_dispose_mapping(irq);
1235 tegra_msi_free(msi, hwirq);
1238 static struct irq_chip tegra_msi_irq_chip = {
1239 .name = "Tegra PCIe MSI",
1240 .irq_enable = pci_msi_unmask_irq,
1241 .irq_disable = pci_msi_mask_irq,
1242 .irq_mask = pci_msi_mask_irq,
1243 .irq_unmask = pci_msi_unmask_irq,
1246 static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1247 irq_hw_number_t hwirq)
1249 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1250 irq_set_chip_data(irq, domain->host_data);
1251 set_irq_flags(irq, IRQF_VALID);
1253 tegra_cpuidle_pcie_irqs_in_use();
1258 static const struct irq_domain_ops msi_domain_ops = {
1259 .map = tegra_msi_map,
1262 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1264 struct platform_device *pdev = to_platform_device(pcie->dev);
1265 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1266 struct tegra_msi *msi = &pcie->msi;
1271 mutex_init(&msi->lock);
1273 msi->chip.dev = pcie->dev;
1274 msi->chip.setup_irq = tegra_msi_setup_irq;
1275 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1277 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
1278 &msi_domain_ops, &msi->chip);
1280 dev_err(&pdev->dev, "failed to create IRQ domain\n");
1284 err = platform_get_irq_byname(pdev, "msi");
1286 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1292 err = request_irq(msi->irq, tegra_pcie_msi_irq, 0,
1293 tegra_msi_irq_chip.name, pcie);
1295 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1299 /* setup AFI/FPCI range */
1300 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1301 base = virt_to_phys((void *)msi->pages);
1303 afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1304 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
1305 /* this register is in 4K increments */
1306 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1308 /* enable all MSI vectors */
1309 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1310 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1311 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1312 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1313 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1314 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1315 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1316 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1318 /* and unmask the MSI interrupt */
1319 reg = afi_readl(pcie, AFI_INTR_MASK);
1320 reg |= AFI_INTR_MASK_MSI_MASK;
1321 afi_writel(pcie, reg, AFI_INTR_MASK);
1326 irq_domain_remove(msi->domain);
1330 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1332 struct tegra_msi *msi = &pcie->msi;
1333 unsigned int i, irq;
1336 /* mask the MSI interrupt */
1337 value = afi_readl(pcie, AFI_INTR_MASK);
1338 value &= ~AFI_INTR_MASK_MSI_MASK;
1339 afi_writel(pcie, value, AFI_INTR_MASK);
1341 /* disable all MSI vectors */
1342 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1343 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1344 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1345 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1346 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1347 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1348 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1349 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1351 free_pages(msi->pages, 0);
1354 free_irq(msi->irq, pcie);
1356 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1357 irq = irq_find_mapping(msi->domain, i);
1359 irq_dispose_mapping(irq);
1362 irq_domain_remove(msi->domain);
1367 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1370 struct device_node *np = pcie->dev->of_node;
1372 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1375 dev_info(pcie->dev, "4x1, 1x1 configuration\n");
1376 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
1380 dev_info(pcie->dev, "2x1, 1x1 configuration\n");
1381 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
1384 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1387 dev_info(pcie->dev, "4x1, 2x1 configuration\n");
1388 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
1392 dev_info(pcie->dev, "2x3 configuration\n");
1393 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
1397 dev_info(pcie->dev, "4x1, 1x2 configuration\n");
1398 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
1401 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1404 dev_info(pcie->dev, "single-mode configuration\n");
1405 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1409 dev_info(pcie->dev, "dual-mode configuration\n");
1410 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1419 * Check whether a given set of supplies is available in a device tree node.
1420 * This is used to check whether the new or the legacy device tree bindings
1423 static bool of_regulator_bulk_available(struct device_node *np,
1424 struct regulator_bulk_data *supplies,
1425 unsigned int num_supplies)
1430 for (i = 0; i < num_supplies; i++) {
1431 snprintf(property, 32, "%s-supply", supplies[i].supply);
1433 if (of_find_property(np, property, NULL) == NULL)
1441 * Old versions of the device tree binding for this device used a set of power
1442 * supplies that didn't match the hardware inputs. This happened to work for a
1443 * number of cases but is not future proof. However to preserve backwards-
1444 * compatibility with old device trees, this function will try to use the old
1447 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1449 struct device_node *np = pcie->dev->of_node;
1451 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1452 pcie->num_supplies = 3;
1453 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1454 pcie->num_supplies = 2;
1456 if (pcie->num_supplies == 0) {
1457 dev_err(pcie->dev, "device %s not supported in legacy mode\n",
1462 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1463 sizeof(*pcie->supplies),
1465 if (!pcie->supplies)
1468 pcie->supplies[0].supply = "pex-clk";
1469 pcie->supplies[1].supply = "vdd";
1471 if (pcie->num_supplies > 2)
1472 pcie->supplies[2].supply = "avdd";
1474 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1479 * Obtains the list of regulators required for a particular generation of the
1482 * This would've been nice to do simply by providing static tables for use
1483 * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky
1484 * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB)
1485 * and either seems to be optional depending on which ports are being used.
1487 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
1489 struct device_node *np = pcie->dev->of_node;
1492 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1493 pcie->num_supplies = 7;
1495 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1496 sizeof(*pcie->supplies),
1498 if (!pcie->supplies)
1501 pcie->supplies[i++].supply = "avddio-pex";
1502 pcie->supplies[i++].supply = "dvddio-pex";
1503 pcie->supplies[i++].supply = "avdd-pex-pll";
1504 pcie->supplies[i++].supply = "hvdd-pex";
1505 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1506 pcie->supplies[i++].supply = "vddio-pex-ctl";
1507 pcie->supplies[i++].supply = "avdd-pll-erefe";
1508 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1509 bool need_pexa = false, need_pexb = false;
1511 /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */
1512 if (lane_mask & 0x0f)
1515 /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */
1516 if (lane_mask & 0x30)
1519 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
1520 (need_pexb ? 2 : 0);
1522 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1523 sizeof(*pcie->supplies),
1525 if (!pcie->supplies)
1528 pcie->supplies[i++].supply = "avdd-pex-pll";
1529 pcie->supplies[i++].supply = "hvdd-pex";
1530 pcie->supplies[i++].supply = "vddio-pex-ctl";
1531 pcie->supplies[i++].supply = "avdd-plle";
1534 pcie->supplies[i++].supply = "avdd-pexa";
1535 pcie->supplies[i++].supply = "vdd-pexa";
1539 pcie->supplies[i++].supply = "avdd-pexb";
1540 pcie->supplies[i++].supply = "vdd-pexb";
1542 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1543 pcie->num_supplies = 5;
1545 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1546 sizeof(*pcie->supplies),
1548 if (!pcie->supplies)
1551 pcie->supplies[0].supply = "avdd-pex";
1552 pcie->supplies[1].supply = "vdd-pex";
1553 pcie->supplies[2].supply = "avdd-pex-pll";
1554 pcie->supplies[3].supply = "avdd-plle";
1555 pcie->supplies[4].supply = "vddio-pex-clk";
1558 if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies,
1559 pcie->num_supplies))
1560 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1564 * If not all regulators are available for this new scheme, assume
1565 * that the device tree complies with an older version of the device
1568 dev_info(pcie->dev, "using legacy DT binding for power supplies\n");
1570 devm_kfree(pcie->dev, pcie->supplies);
1571 pcie->num_supplies = 0;
1573 return tegra_pcie_get_legacy_regulators(pcie);
1576 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1578 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1579 struct device_node *np = pcie->dev->of_node, *port;
1580 struct of_pci_range_parser parser;
1581 struct of_pci_range range;
1582 u32 lanes = 0, mask = 0;
1583 unsigned int lane = 0;
1584 struct resource res;
1587 memset(&pcie->all, 0, sizeof(pcie->all));
1588 pcie->all.flags = IORESOURCE_MEM;
1589 pcie->all.name = np->full_name;
1590 pcie->all.start = ~0;
1593 if (of_pci_range_parser_init(&parser, np)) {
1594 dev_err(pcie->dev, "missing \"ranges\" property\n");
1598 for_each_of_pci_range(&parser, &range) {
1599 err = of_pci_range_to_resource(&range, np, &res);
1603 switch (res.flags & IORESOURCE_TYPE_BITS) {
1605 memcpy(&pcie->pio, &res, sizeof(res));
1606 pcie->pio.name = np->full_name;
1609 * The Tegra PCIe host bridge uses this to program the
1610 * mapping of the I/O space to the physical address,
1611 * so we override the .start and .end fields here that
1612 * of_pci_range_to_resource() converted to I/O space.
1613 * We also set the IORESOURCE_MEM type to clarify that
1614 * the resource is in the physical memory space.
1616 pcie->io.start = range.cpu_addr;
1617 pcie->io.end = range.cpu_addr + range.size - 1;
1618 pcie->io.flags = IORESOURCE_MEM;
1619 pcie->io.name = "I/O";
1621 memcpy(&res, &pcie->io, sizeof(res));
1624 case IORESOURCE_MEM:
1625 if (res.flags & IORESOURCE_PREFETCH) {
1626 memcpy(&pcie->prefetch, &res, sizeof(res));
1627 pcie->prefetch.name = "prefetchable";
1629 memcpy(&pcie->mem, &res, sizeof(res));
1630 pcie->mem.name = "non-prefetchable";
1635 if (res.start <= pcie->all.start)
1636 pcie->all.start = res.start;
1638 if (res.end >= pcie->all.end)
1639 pcie->all.end = res.end;
1642 err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->all);
1646 err = of_pci_parse_bus_range(np, &pcie->busn);
1648 dev_err(pcie->dev, "failed to parse ranges property: %d\n",
1650 pcie->busn.name = np->name;
1651 pcie->busn.start = 0;
1652 pcie->busn.end = 0xff;
1653 pcie->busn.flags = IORESOURCE_BUS;
1656 /* parse root ports */
1657 for_each_child_of_node(np, port) {
1658 struct tegra_pcie_port *rp;
1662 err = of_pci_get_devfn(port);
1664 dev_err(pcie->dev, "failed to parse address: %d\n",
1669 index = PCI_SLOT(err);
1671 if (index < 1 || index > soc->num_ports) {
1672 dev_err(pcie->dev, "invalid port number: %d\n", index);
1678 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1680 dev_err(pcie->dev, "failed to parse # of lanes: %d\n",
1686 dev_err(pcie->dev, "invalid # of lanes: %u\n", value);
1690 lanes |= value << (index << 3);
1692 if (!of_device_is_available(port)) {
1697 mask |= ((1 << value) - 1) << lane;
1700 rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
1704 err = of_address_to_resource(port, 0, &rp->regs);
1706 dev_err(pcie->dev, "failed to parse address: %d\n",
1711 INIT_LIST_HEAD(&rp->list);
1716 rp->base = devm_ioremap_resource(pcie->dev, &rp->regs);
1717 if (IS_ERR(rp->base))
1718 return PTR_ERR(rp->base);
1720 list_add_tail(&rp->list, &pcie->ports);
1723 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1725 dev_err(pcie->dev, "invalid lane configuration\n");
1729 err = tegra_pcie_get_regulators(pcie, mask);
1737 * FIXME: If there are no PCIe cards attached, then calling this function
1738 * can result in the increase of the bootup time as there are big timeout
1741 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1742 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1744 unsigned int retries = 3;
1745 unsigned long value;
1747 /* override presence detection */
1748 value = readl(port->base + RP_PRIV_MISC);
1749 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
1750 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
1751 writel(value, port->base + RP_PRIV_MISC);
1754 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1757 value = readl(port->base + RP_VEND_XP);
1759 if (value & RP_VEND_XP_DL_UP)
1762 usleep_range(1000, 2000);
1763 } while (--timeout);
1766 dev_err(port->pcie->dev, "link %u down, retrying\n",
1771 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1774 value = readl(port->base + RP_LINK_CONTROL_STATUS);
1776 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1779 usleep_range(1000, 2000);
1780 } while (--timeout);
1783 tegra_pcie_port_reset(port);
1784 } while (--retries);
1789 static int tegra_pcie_enable(struct tegra_pcie *pcie)
1791 struct tegra_pcie_port *port, *tmp;
1794 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1795 dev_info(pcie->dev, "probing port %u, using %u lanes\n",
1796 port->index, port->lanes);
1798 tegra_pcie_port_enable(port);
1800 if (tegra_pcie_port_check_link(port))
1803 dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
1805 tegra_pcie_port_disable(port);
1806 tegra_pcie_port_free(port);
1809 memset(&hw, 0, sizeof(hw));
1811 #ifdef CONFIG_PCI_MSI
1812 hw.msi_ctrl = &pcie->msi.chip;
1815 hw.nr_controllers = 1;
1816 hw.private_data = (void **)&pcie;
1817 hw.setup = tegra_pcie_setup;
1818 hw.map_irq = tegra_pcie_map_irq;
1819 hw.ops = &tegra_pcie_ops;
1821 pci_common_init_dev(pcie->dev, &hw);
1826 static const struct tegra_pcie_soc_data tegra20_pcie_data = {
1828 .msi_base_shift = 0,
1829 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1830 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1831 .has_pex_clkreq_en = false,
1832 .has_pex_bias_ctrl = false,
1833 .has_intr_prsnt_sense = false,
1834 .has_cml_clk = false,
1838 static const struct tegra_pcie_soc_data tegra30_pcie_data = {
1840 .msi_base_shift = 8,
1841 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1842 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1843 .has_pex_clkreq_en = true,
1844 .has_pex_bias_ctrl = true,
1845 .has_intr_prsnt_sense = true,
1846 .has_cml_clk = true,
1850 static const struct tegra_pcie_soc_data tegra124_pcie_data = {
1852 .msi_base_shift = 8,
1853 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1854 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1855 .has_pex_clkreq_en = true,
1856 .has_pex_bias_ctrl = true,
1857 .has_intr_prsnt_sense = true,
1858 .has_cml_clk = true,
1862 static const struct of_device_id tegra_pcie_of_match[] = {
1863 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data },
1864 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
1865 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
1868 MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
1870 static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos)
1872 struct tegra_pcie *pcie = s->private;
1874 if (list_empty(&pcie->ports))
1877 seq_printf(s, "Index Status\n");
1879 return seq_list_start(&pcie->ports, *pos);
1882 static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos)
1884 struct tegra_pcie *pcie = s->private;
1886 return seq_list_next(v, &pcie->ports, pos);
1889 static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v)
1893 static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v)
1895 bool up = false, active = false;
1896 struct tegra_pcie_port *port;
1899 port = list_entry(v, struct tegra_pcie_port, list);
1901 value = readl(port->base + RP_VEND_XP);
1903 if (value & RP_VEND_XP_DL_UP)
1906 value = readl(port->base + RP_LINK_CONTROL_STATUS);
1908 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1911 seq_printf(s, "%2u ", port->index);
1914 seq_printf(s, "up");
1918 seq_printf(s, ", ");
1920 seq_printf(s, "active");
1923 seq_printf(s, "\n");
1927 static const struct seq_operations tegra_pcie_ports_seq_ops = {
1928 .start = tegra_pcie_ports_seq_start,
1929 .next = tegra_pcie_ports_seq_next,
1930 .stop = tegra_pcie_ports_seq_stop,
1931 .show = tegra_pcie_ports_seq_show,
1934 static int tegra_pcie_ports_open(struct inode *inode, struct file *file)
1936 struct tegra_pcie *pcie = inode->i_private;
1940 err = seq_open(file, &tegra_pcie_ports_seq_ops);
1944 s = file->private_data;
1950 static const struct file_operations tegra_pcie_ports_ops = {
1951 .owner = THIS_MODULE,
1952 .open = tegra_pcie_ports_open,
1954 .llseek = seq_lseek,
1955 .release = seq_release,
1958 static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
1960 struct dentry *file;
1962 pcie->debugfs = debugfs_create_dir("pcie", NULL);
1966 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs,
1967 pcie, &tegra_pcie_ports_ops);
1974 debugfs_remove_recursive(pcie->debugfs);
1975 pcie->debugfs = NULL;
1979 static int tegra_pcie_probe(struct platform_device *pdev)
1981 const struct of_device_id *match;
1982 struct tegra_pcie *pcie;
1985 match = of_match_device(tegra_pcie_of_match, &pdev->dev);
1989 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1993 INIT_LIST_HEAD(&pcie->buses);
1994 INIT_LIST_HEAD(&pcie->ports);
1995 pcie->soc_data = match->data;
1996 pcie->dev = &pdev->dev;
1998 err = tegra_pcie_parse_dt(pcie);
2002 pcibios_min_mem = 0;
2004 err = tegra_pcie_get_resources(pcie);
2006 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
2010 err = tegra_pcie_enable_controller(pcie);
2014 /* setup the AFI address translations */
2015 tegra_pcie_setup_translations(pcie);
2017 if (IS_ENABLED(CONFIG_PCI_MSI)) {
2018 err = tegra_pcie_enable_msi(pcie);
2021 "failed to enable MSI support: %d\n",
2027 err = tegra_pcie_enable(pcie);
2029 dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err);
2033 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2034 err = tegra_pcie_debugfs_init(pcie);
2036 dev_err(&pdev->dev, "failed to setup debugfs: %d\n",
2040 platform_set_drvdata(pdev, pcie);
2044 if (IS_ENABLED(CONFIG_PCI_MSI))
2045 tegra_pcie_disable_msi(pcie);
2047 tegra_pcie_put_resources(pcie);
2051 static struct platform_driver tegra_pcie_driver = {
2053 .name = "tegra-pcie",
2054 .of_match_table = tegra_pcie_of_match,
2055 .suppress_bind_attrs = true,
2057 .probe = tegra_pcie_probe,
2059 module_platform_driver(tegra_pcie_driver);
2061 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2062 MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver");
2063 MODULE_LICENSE("GPL v2");