2 * APM X-Gene PCIe Driver
4 * Copyright (c) 2014 Applied Micro Circuits Corporation.
6 * Author: Tanmay Inamdar <tinamdar@apm.com>.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/delay.h>
22 #include <linux/jiffies.h>
23 #include <linux/memblock.h>
24 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_pci.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
33 #define PCIECORE_CTLANDSTATUS 0x50
41 #define OMR1BARL 0x100
42 #define OMR2BARL 0x118
43 #define OMR3BARL 0x130
48 #define BRIDGE_CFG_0 0x2000
49 #define BRIDGE_CFG_4 0x2010
50 #define BRIDGE_STATUS_0 0x2600
52 #define LINK_UP_MASK 0x00000100
53 #define AXI_EP_CFG_ACCESS 0x10000
54 #define EN_COHERENCY 0xF0000000
55 #define EN_REG 0x00000001
56 #define OB_LO_IO 0x00000002
57 #define XGENE_PCIE_VENDORID 0x10E8
58 #define XGENE_PCIE_DEVICEID 0xE004
59 #define SZ_1T (SZ_1G*1024ULL)
60 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
62 #define ROOT_CAP_AND_CTRL 0x5C
65 #define XGENE_PCIE_IP_VER_UNKN 0
66 #define XGENE_PCIE_IP_VER_1 1
68 struct xgene_pcie_port {
69 struct device_node *node;
72 void __iomem *csr_base;
73 void __iomem *cfg_base;
74 unsigned long cfg_addr;
79 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
81 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
85 * When the address bit [17:16] is 2'b01, the Configuration access will be
86 * treated as Type 1 and it will be forwarded to external PCIe device.
88 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
90 struct xgene_pcie_port *port = bus->sysdata;
92 if (bus->number >= (bus->primary + 1))
93 return port->cfg_base + AXI_EP_CFG_ACCESS;
95 return port->cfg_base;
99 * For Configuration request, RTDID register is used as Bus Number,
100 * Device Number and Function number of the header fields.
102 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
104 struct xgene_pcie_port *port = bus->sysdata;
105 unsigned int b, d, f;
112 if (!pci_is_root_bus(bus))
113 rtdid_val = (b << 8) | (d << 3) | f;
115 writel(rtdid_val, port->csr_base + RTDID);
116 /* read the register back to ensure flush */
117 readl(port->csr_base + RTDID);
121 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
122 * the translation from PCI bus to native BUS. Entire DDR region
123 * is mapped into PCIe space using these registers, so it can be
124 * reached by DMA from EP devices. The BAR0/1 of bridge should be
125 * hidden during enumeration to avoid the sizing and resource allocation
128 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
130 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
131 (offset == PCI_BASE_ADDRESS_1)))
137 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
140 if ((pci_is_root_bus(bus) && devfn != 0) ||
141 xgene_pcie_hide_rc_bars(bus, offset))
144 xgene_pcie_set_rtdid_reg(bus, devfn);
145 return xgene_pcie_get_cfg_base(bus) + offset;
148 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
149 int where, int size, u32 *val)
151 struct xgene_pcie_port *port = bus->sysdata;
153 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
155 return PCIBIOS_DEVICE_NOT_FOUND;
158 * The v1 controller has a bug in its Configuration Request
159 * Retry Status (CRS) logic: when CRS is enabled and we read the
160 * Vendor and Device ID of a non-existent device, the controller
161 * fabricates return data of 0xFFFF0001 ("device exists but is not
162 * ready") instead of 0xFFFFFFFF ("device does not exist"). This
163 * causes the PCI core to retry the read until it times out.
164 * Avoid this by not claiming to support CRS.
166 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
167 ((where & ~0x3) == ROOT_CAP_AND_CTRL))
168 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
171 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
173 return PCIBIOS_SUCCESSFUL;
176 static struct pci_ops xgene_pcie_ops = {
177 .map_bus = xgene_pcie_map_bus,
178 .read = xgene_pcie_config_read32,
179 .write = pci_generic_config_write32,
182 static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
185 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
189 val32 = readl(csr_base + addr);
190 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
191 writel(val, csr_base + addr);
193 val32 = readl(csr_base + addr + 0x04);
194 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
195 writel(val, csr_base + addr + 0x04);
197 val32 = readl(csr_base + addr + 0x04);
198 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
199 writel(val, csr_base + addr + 0x04);
201 val32 = readl(csr_base + addr + 0x08);
202 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
203 writel(val, csr_base + addr + 0x08);
208 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
209 u32 *lanes, u32 *speed)
211 void __iomem *csr_base = port->csr_base;
214 port->link_up = false;
215 val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
216 if (val32 & LINK_UP_MASK) {
217 port->link_up = true;
218 *speed = PIPE_PHY_RATE_RD(val32);
219 val32 = readl(csr_base + BRIDGE_STATUS_0);
220 *lanes = val32 >> 26;
224 static int xgene_pcie_init_port(struct xgene_pcie_port *port)
228 port->clk = clk_get(port->dev, NULL);
229 if (IS_ERR(port->clk)) {
230 dev_err(port->dev, "clock not available\n");
234 rc = clk_prepare_enable(port->clk);
236 dev_err(port->dev, "clock enable failed\n");
243 static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
244 struct platform_device *pdev)
246 struct resource *res;
248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
249 port->csr_base = devm_ioremap_resource(port->dev, res);
250 if (IS_ERR(port->csr_base))
251 return PTR_ERR(port->csr_base);
253 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
254 port->cfg_base = devm_ioremap_resource(port->dev, res);
255 if (IS_ERR(port->cfg_base))
256 return PTR_ERR(port->cfg_base);
257 port->cfg_addr = res->start;
262 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
263 struct resource *res, u32 offset,
264 u64 cpu_addr, u64 pci_addr)
266 void __iomem *base = port->csr_base + offset;
267 resource_size_t size = resource_size(res);
268 u64 restype = resource_type(res);
273 if (restype == IORESOURCE_MEM) {
280 if (size >= min_size)
281 mask = ~(size - 1) | flag;
283 dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n",
284 (u64)size, min_size);
286 writel(lower_32_bits(cpu_addr), base);
287 writel(upper_32_bits(cpu_addr), base + 0x04);
288 writel(lower_32_bits(mask), base + 0x08);
289 writel(upper_32_bits(mask), base + 0x0c);
290 writel(lower_32_bits(pci_addr), base + 0x10);
291 writel(upper_32_bits(pci_addr), base + 0x14);
294 static void xgene_pcie_setup_cfg_reg(void __iomem *csr_base, u64 addr)
296 writel(lower_32_bits(addr), csr_base + CFGBARL);
297 writel(upper_32_bits(addr), csr_base + CFGBARH);
298 writel(EN_REG, csr_base + CFGCTL);
301 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
302 struct list_head *res,
303 resource_size_t io_base)
305 struct resource_entry *window;
306 struct device *dev = port->dev;
309 resource_list_for_each_entry(window, res) {
310 struct resource *res = window->res;
311 u64 restype = resource_type(res);
313 dev_dbg(port->dev, "%pR\n", res);
317 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
318 res->start - window->offset);
319 ret = pci_remap_iospace(res, io_base);
324 xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start,
325 res->start - window->offset);
330 dev_err(dev, "invalid resource %pR\n", res);
334 xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr);
339 static void xgene_pcie_setup_pims(void *addr, u64 pim, u64 size)
341 writel(lower_32_bits(pim), addr);
342 writel(upper_32_bits(pim) | EN_COHERENCY, addr + 0x04);
343 writel(lower_32_bits(size), addr + 0x10);
344 writel(upper_32_bits(size), addr + 0x14);
348 * X-Gene PCIe support maximum 3 inbound memory regions
349 * This function helps to select a region based on size of region
351 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
353 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
354 *ib_reg_mask |= (1 << 1);
358 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
359 *ib_reg_mask |= (1 << 0);
363 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
364 *ib_reg_mask |= (1 << 2);
371 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
372 struct of_pci_range *range, u8 *ib_reg_mask)
374 void __iomem *csr_base = port->csr_base;
375 void __iomem *cfg_base = port->cfg_base;
378 u64 cpu_addr = range->cpu_addr;
379 u64 pci_addr = range->pci_addr;
380 u64 size = range->size;
381 u64 mask = ~(size - 1) | EN_REG;
382 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
386 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
388 dev_warn(port->dev, "invalid pcie dma-range config\n");
392 if (range->flags & IORESOURCE_PREFETCH)
393 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
395 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
398 xgene_pcie_set_ib_mask(csr_base, BRIDGE_CFG_4, flags, size);
399 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
400 writel(bar_low, bar_addr);
401 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
402 pim_addr = csr_base + PIM1_1L;
405 bar_addr = csr_base + IBAR2;
406 writel(bar_low, bar_addr);
407 writel(lower_32_bits(mask), csr_base + IR2MSK);
408 pim_addr = csr_base + PIM2_1L;
411 bar_addr = csr_base + IBAR3L;
412 writel(bar_low, bar_addr);
413 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
414 writel(lower_32_bits(mask), csr_base + IR3MSKL);
415 writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
416 pim_addr = csr_base + PIM3_1L;
420 xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1));
423 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
424 struct device_node *node)
426 const int na = 3, ns = 2;
430 parser->pna = of_n_addr_cells(node);
431 parser->np = parser->pna + na + ns;
433 parser->range = of_get_property(node, "dma-ranges", &rlen);
436 parser->end = parser->range + rlen / sizeof(__be32);
441 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
443 struct device_node *np = port->node;
444 struct of_pci_range range;
445 struct of_pci_range_parser parser;
446 struct device *dev = port->dev;
449 if (pci_dma_range_parser_init(&parser, np)) {
450 dev_err(dev, "missing dma-ranges property\n");
454 /* Get the dma-ranges from DT */
455 for_each_of_pci_range(&parser, &range) {
456 u64 end = range.cpu_addr + range.size - 1;
458 dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
459 range.flags, range.cpu_addr, end, range.pci_addr);
460 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
465 /* clear BAR configuration which was done by firmware */
466 static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
470 for (i = PIM1_1L; i <= CFGCTL; i += 4)
471 writel(0x0, port->csr_base + i);
474 static int xgene_pcie_setup(struct xgene_pcie_port *port,
475 struct list_head *res,
476 resource_size_t io_base)
478 u32 val, lanes = 0, speed = 0;
481 xgene_pcie_clear_config(port);
483 /* setup the vendor and device IDs correctly */
484 val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
485 writel(val, port->csr_base + BRIDGE_CFG_0);
487 ret = xgene_pcie_map_ranges(port, res, io_base);
491 ret = xgene_pcie_parse_map_dma_ranges(port);
495 xgene_pcie_linkup(port, &lanes, &speed);
497 dev_info(port->dev, "(rc) link down\n");
499 dev_info(port->dev, "(rc) x%d gen-%d link up\n",
504 static int xgene_pcie_msi_enable(struct pci_bus *bus)
506 struct device_node *msi_node;
508 msi_node = of_parse_phandle(bus->dev.of_node,
513 bus->msi = of_pci_find_msi_chip_by_node(msi_node);
517 bus->msi->dev = &bus->dev;
521 static int xgene_pcie_probe_bridge(struct platform_device *pdev)
523 struct device_node *dn = pdev->dev.of_node;
524 struct xgene_pcie_port *port;
525 resource_size_t iobase = 0;
530 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
533 port->node = of_node_get(pdev->dev.of_node);
534 port->dev = &pdev->dev;
536 port->version = XGENE_PCIE_IP_VER_UNKN;
537 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
538 port->version = XGENE_PCIE_IP_VER_1;
540 ret = xgene_pcie_map_reg(port, pdev);
544 ret = xgene_pcie_init_port(port);
548 ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
552 ret = xgene_pcie_setup(port, &res, iobase);
556 bus = pci_create_root_bus(&pdev->dev, 0,
557 &xgene_pcie_ops, port, &res);
561 if (IS_ENABLED(CONFIG_PCI_MSI))
562 if (xgene_pcie_msi_enable(bus))
563 dev_info(port->dev, "failed to enable MSI\n");
565 pci_scan_child_bus(bus);
566 pci_assign_unassigned_bus_resources(bus);
567 pci_bus_add_devices(bus);
569 platform_set_drvdata(pdev, port);
573 static const struct of_device_id xgene_pcie_match_table[] = {
574 {.compatible = "apm,xgene-pcie",},
578 static struct platform_driver xgene_pcie_driver = {
580 .name = "xgene-pcie",
581 .of_match_table = of_match_ptr(xgene_pcie_match_table),
583 .probe = xgene_pcie_probe_bridge,
585 module_platform_driver(xgene_pcie_driver);
587 MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>");
588 MODULE_DESCRIPTION("APM X-Gene PCIe driver");
589 MODULE_LICENSE("GPL v2");