2 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqchip/chained_irq.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
28 #define RP_TX_REG0 0x2000
29 #define RP_TX_REG1 0x2004
30 #define RP_TX_CNTRL 0x2008
33 #define RP_RXCPL_STATUS 0x2010
34 #define RP_RXCPL_EOP 0x2
35 #define RP_RXCPL_SOP 0x1
36 #define RP_RXCPL_REG0 0x2014
37 #define RP_RXCPL_REG1 0x2018
38 #define P2A_INT_STATUS 0x3060
39 #define P2A_INT_STS_ALL 0xf
40 #define P2A_INT_ENABLE 0x3070
41 #define P2A_INT_ENA_ALL 0xf
42 #define RP_LTSSM 0x3c64
45 /* TLP configuration type 0 and 1 */
46 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
47 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
48 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
49 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
50 #define TLP_PAYLOAD_SIZE 0x01
51 #define TLP_READ_TAG 0x1d
52 #define TLP_WRITE_TAG 0x10
53 #define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
54 #define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be))
55 #define TLP_CFG_DW2(bus, devfn, offset) \
56 (((bus) << 24) | ((devfn) << 16) | (offset))
57 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
58 #define TLP_HDR_SIZE 3
67 struct platform_device *pdev;
68 void __iomem *cra_base;
71 struct irq_domain *irq_domain;
72 struct resource bus_range;
73 struct list_head resources;
76 struct tlp_rp_regpair_t {
82 static void altera_pcie_retrain(struct pci_dev *dev)
84 u16 linkcap, linkstat;
87 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
88 * current speed is 2.5 GB/s.
90 pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
92 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
95 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
96 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
97 pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
100 DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
103 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
104 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
105 * using these registers, so it can be reached by DMA from EP devices.
106 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
107 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
108 * should be hidden during enumeration to avoid the sizing and resource
109 * allocation by PCIe core.
111 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
114 if (pci_is_root_bus(bus) && (devfn == 0) &&
115 (offset == PCI_BASE_ADDRESS_0))
121 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
124 writel_relaxed(value, pcie->cra_base + reg);
127 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
129 return readl_relaxed(pcie->cra_base + reg);
132 static void tlp_write_tx(struct altera_pcie *pcie,
133 struct tlp_rp_regpair_t *tlp_rp_regdata)
135 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
136 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
137 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
140 static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
142 return !!(cra_readl(pcie, RP_LTSSM) & LTSSM_L0);
145 static bool altera_pcie_valid_config(struct altera_pcie *pcie,
146 struct pci_bus *bus, int dev)
148 /* If there is no link, then there is no device */
149 if (bus->number != pcie->root_bus_nr) {
150 if (!altera_pcie_link_is_up(pcie))
154 /* access only one slot on each root port */
155 if (bus->number == pcie->root_bus_nr && dev > 0)
159 * Do not read more than one device on the bus directly attached
160 * to root port, root port can only attach to one downstream port.
162 if (bus->primary == pcie->root_bus_nr && dev > 0)
168 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
176 * Minimum 2 loops to read TLP headers and 1 loop to read data
179 for (i = 0; i < TLP_LOOP; i++) {
180 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
181 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
182 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
183 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
185 if (ctrl & RP_RXCPL_SOP)
188 if (ctrl & RP_RXCPL_EOP) {
191 return PCIBIOS_SUCCESSFUL;
200 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
201 u32 data, bool align)
203 struct tlp_rp_regpair_t tlp_rp_regdata;
205 tlp_rp_regdata.reg0 = headers[0];
206 tlp_rp_regdata.reg1 = headers[1];
207 tlp_rp_regdata.ctrl = RP_TX_SOP;
208 tlp_write_tx(pcie, &tlp_rp_regdata);
211 tlp_rp_regdata.reg0 = headers[2];
212 tlp_rp_regdata.reg1 = 0;
213 tlp_rp_regdata.ctrl = 0;
214 tlp_write_tx(pcie, &tlp_rp_regdata);
216 tlp_rp_regdata.reg0 = data;
217 tlp_rp_regdata.reg1 = 0;
219 tlp_rp_regdata.reg0 = headers[2];
220 tlp_rp_regdata.reg1 = data;
223 tlp_rp_regdata.ctrl = RP_TX_EOP;
224 tlp_write_tx(pcie, &tlp_rp_regdata);
227 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
228 int where, u8 byte_en, u32 *value)
230 u32 headers[TLP_HDR_SIZE];
232 if (bus == pcie->root_bus_nr)
233 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
235 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
237 headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
238 TLP_READ_TAG, byte_en);
239 headers[2] = TLP_CFG_DW2(bus, devfn, where);
241 tlp_write_packet(pcie, headers, 0, false);
243 return tlp_read_packet(pcie, value);
246 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
247 int where, u8 byte_en, u32 value)
249 u32 headers[TLP_HDR_SIZE];
252 if (bus == pcie->root_bus_nr)
253 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
255 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
257 headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
258 TLP_WRITE_TAG, byte_en);
259 headers[2] = TLP_CFG_DW2(bus, devfn, where);
261 /* check alignment to Qword */
262 if ((where & 0x7) == 0)
263 tlp_write_packet(pcie, headers, value, true);
265 tlp_write_packet(pcie, headers, value, false);
267 ret = tlp_read_packet(pcie, NULL);
268 if (ret != PCIBIOS_SUCCESSFUL)
272 * Monitor changes to PCI_PRIMARY_BUS register on root port
273 * and update local copy of root bus number accordingly.
275 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
276 pcie->root_bus_nr = (u8)(value);
278 return PCIBIOS_SUCCESSFUL;
281 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
282 int where, int size, u32 *value)
284 struct altera_pcie *pcie = bus->sysdata;
289 if (altera_pcie_hide_rc_bar(bus, devfn, where))
290 return PCIBIOS_BAD_REGISTER_NUMBER;
292 if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
294 return PCIBIOS_DEVICE_NOT_FOUND;
299 byte_en = 1 << (where & 3);
302 byte_en = 3 << (where & 3);
309 ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
310 (where & ~DWORD_MASK), byte_en, &data);
311 if (ret != PCIBIOS_SUCCESSFUL)
316 *value = (data >> (8 * (where & 0x3))) & 0xff;
319 *value = (data >> (8 * (where & 0x2))) & 0xffff;
326 return PCIBIOS_SUCCESSFUL;
329 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
330 int where, int size, u32 value)
332 struct altera_pcie *pcie = bus->sysdata;
334 u32 shift = 8 * (where & 3);
337 if (altera_pcie_hide_rc_bar(bus, devfn, where))
338 return PCIBIOS_BAD_REGISTER_NUMBER;
340 if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
341 return PCIBIOS_DEVICE_NOT_FOUND;
345 data32 = (value & 0xff) << shift;
346 byte_en = 1 << (where & 3);
349 data32 = (value & 0xffff) << shift;
350 byte_en = 3 << (where & 3);
358 return tlp_cfg_dword_write(pcie, bus->number, devfn,
359 (where & ~DWORD_MASK), byte_en, data32);
362 static struct pci_ops altera_pcie_ops = {
363 .read = altera_pcie_cfg_read,
364 .write = altera_pcie_cfg_write,
367 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
368 irq_hw_number_t hwirq)
370 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
371 irq_set_chip_data(irq, domain->host_data);
376 static const struct irq_domain_ops intx_domain_ops = {
377 .map = altera_pcie_intx_map,
380 static void altera_pcie_isr(struct irq_desc *desc)
382 struct irq_chip *chip = irq_desc_get_chip(desc);
383 struct altera_pcie *pcie;
384 unsigned long status;
388 chained_irq_enter(chip, desc);
389 pcie = irq_desc_get_handler_data(desc);
391 while ((status = cra_readl(pcie, P2A_INT_STATUS)
392 & P2A_INT_STS_ALL) != 0) {
393 for_each_set_bit(bit, &status, INTX_NUM) {
394 /* clear interrupts */
395 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
397 virq = irq_find_mapping(pcie->irq_domain, bit + 1);
399 generic_handle_irq(virq);
401 dev_err(&pcie->pdev->dev,
402 "unexpected IRQ, INT%d\n", bit);
406 chained_irq_exit(chip, desc);
409 static void altera_pcie_release_of_pci_ranges(struct altera_pcie *pcie)
411 pci_free_resource_list(&pcie->resources);
414 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
416 int err, res_valid = 0;
417 struct device *dev = &pcie->pdev->dev;
418 struct device_node *np = dev->of_node;
419 struct resource_entry *win;
421 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
426 resource_list_for_each_entry(win, &pcie->resources) {
427 struct resource *parent, *res = win->res;
429 switch (resource_type(res)) {
431 parent = &iomem_resource;
432 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
438 err = devm_request_resource(dev, parent, res);
440 goto out_release_res;
444 dev_err(dev, "non-prefetchable memory resource required\n");
446 goto out_release_res;
452 altera_pcie_release_of_pci_ranges(pcie);
456 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
458 struct device *dev = &pcie->pdev->dev;
459 struct device_node *node = dev->of_node;
462 pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM,
463 &intx_domain_ops, pcie);
464 if (!pcie->irq_domain) {
465 dev_err(dev, "Failed to get a INTx IRQ domain\n");
472 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
474 struct resource *cra;
475 struct platform_device *pdev = pcie->pdev;
477 cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
479 dev_err(&pdev->dev, "no Cra memory resource defined\n");
483 pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
484 if (IS_ERR(pcie->cra_base)) {
485 dev_err(&pdev->dev, "failed to map cra memory\n");
486 return PTR_ERR(pcie->cra_base);
490 pcie->irq = platform_get_irq(pdev, 0);
491 if (pcie->irq <= 0) {
492 dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
496 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
501 static int altera_pcie_probe(struct platform_device *pdev)
503 struct altera_pcie *pcie;
505 struct pci_bus *child;
508 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
514 ret = altera_pcie_parse_dt(pcie);
516 dev_err(&pdev->dev, "Parsing DT failed\n");
520 INIT_LIST_HEAD(&pcie->resources);
522 ret = altera_pcie_parse_request_of_pci_ranges(pcie);
524 dev_err(&pdev->dev, "Failed add resources\n");
528 ret = altera_pcie_init_irq_domain(pcie);
530 dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
534 /* clear all interrupts */
535 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
536 /* enable all interrupts */
537 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
539 bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
540 pcie, &pcie->resources);
544 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
545 pci_assign_unassigned_bus_resources(bus);
547 /* Configure PCI Express setting. */
548 list_for_each_entry(child, &bus->children, node)
549 pcie_bus_configure_settings(child);
551 pci_bus_add_devices(bus);
553 platform_set_drvdata(pdev, pcie);
557 static const struct of_device_id altera_pcie_of_match[] = {
558 { .compatible = "altr,pcie-root-port-1.0", },
561 MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
563 static struct platform_driver altera_pcie_driver = {
564 .probe = altera_pcie_probe,
566 .name = "altera-pcie",
567 .of_match_table = altera_pcie_of_match,
568 .suppress_bind_attrs = true,
572 static int altera_pcie_init(void)
574 return platform_driver_register(&altera_pcie_driver);
576 module_init(altera_pcie_init);
578 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
579 MODULE_DESCRIPTION("Altera PCIe host controller driver");
580 MODULE_LICENSE("GPL v2");