2 * PCIe host controller driver for HiSilicon Hip05 SoC
4 * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
6 * Author: Zhou Wang <wangzhou1@hisilicon.com>
7 * Dacai Zhu <zhudacai@hisilicon.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
21 #include "pcie-designware.h"
23 #define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
24 #define PCIE_LTSSM_LINKUP_STATE 0x11
25 #define PCIE_LTSSM_STATE_MASK 0x3F
27 #define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
30 struct regmap *subctrl;
31 void __iomem *reg_base;
36 static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
39 writel(val, pcie->reg_base + reg);
42 static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
44 return readl(pcie->reg_base + reg);
47 /* Hip05 PCIe host only supports 32-bit config access */
48 static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
53 struct hisi_pcie *pcie = to_hisi_pcie(pp);
54 void *walker = ®_val;
56 walker += (where & 0x3);
58 reg_val = hisi_pcie_apb_readl(pcie, reg);
61 *val = *(u8 __force *) walker;
63 *val = *(u16 __force *) walker;
65 return PCIBIOS_BAD_REGISTER_NUMBER;
67 return PCIBIOS_SUCCESSFUL;
70 /* Hip05 PCIe host only supports 32-bit config access */
71 static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
76 struct hisi_pcie *pcie = to_hisi_pcie(pp);
77 void *walker = ®_val;
79 walker += (where & 0x3);
82 hisi_pcie_apb_writel(pcie, val, reg);
84 reg_val = hisi_pcie_apb_readl(pcie, reg);
85 *(u16 __force *) walker = val;
86 hisi_pcie_apb_writel(pcie, reg_val, reg);
87 } else if (size == 1) {
88 reg_val = hisi_pcie_apb_readl(pcie, reg);
89 *(u8 __force *) walker = val;
90 hisi_pcie_apb_writel(pcie, reg_val, reg);
92 return PCIBIOS_BAD_REGISTER_NUMBER;
94 return PCIBIOS_SUCCESSFUL;
97 static int hisi_pcie_link_up(struct pcie_port *pp)
100 struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
102 regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
103 0x100 * hisi_pcie->port_id, &val);
105 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
108 static struct pcie_host_ops hisi_pcie_host_ops = {
109 .rd_own_conf = hisi_pcie_cfg_read,
110 .wr_own_conf = hisi_pcie_cfg_write,
111 .link_up = hisi_pcie_link_up,
114 static int hisi_add_pcie_port(struct pcie_port *pp,
115 struct platform_device *pdev)
119 struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
121 if (of_property_read_u32(pdev->dev.of_node, "port-id", &port_id)) {
122 dev_err(&pdev->dev, "failed to read port-id\n");
126 dev_err(&pdev->dev, "Invalid port-id: %d\n", port_id);
129 hisi_pcie->port_id = port_id;
131 pp->ops = &hisi_pcie_host_ops;
133 ret = dw_pcie_host_init(pp);
135 dev_err(&pdev->dev, "failed to initialize host\n");
142 static int hisi_pcie_probe(struct platform_device *pdev)
144 struct hisi_pcie *hisi_pcie;
145 struct pcie_port *pp;
146 struct resource *reg;
149 hisi_pcie = devm_kzalloc(&pdev->dev, sizeof(*hisi_pcie), GFP_KERNEL);
154 pp->dev = &pdev->dev;
157 syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
158 if (IS_ERR(hisi_pcie->subctrl)) {
159 dev_err(pp->dev, "cannot get subctrl base\n");
160 return PTR_ERR(hisi_pcie->subctrl);
163 reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
164 hisi_pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg);
165 if (IS_ERR(hisi_pcie->reg_base)) {
166 dev_err(pp->dev, "cannot get rc_dbi base\n");
167 return PTR_ERR(hisi_pcie->reg_base);
170 hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
172 ret = hisi_add_pcie_port(pp, pdev);
176 platform_set_drvdata(pdev, hisi_pcie);
178 dev_warn(pp->dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
183 static const struct of_device_id hisi_pcie_of_match[] = {
184 {.compatible = "hisilicon,hip05-pcie",},
188 MODULE_DEVICE_TABLE(of, hisi_pcie_of_match);
190 static struct platform_driver hisi_pcie_driver = {
191 .probe = hisi_pcie_probe,
194 .of_match_table = hisi_pcie_of_match,
198 module_platform_driver(hisi_pcie_driver);