2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
31 #define DRV_NAME "rcar-pcie"
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
66 /* PCIe address reg & mask */
67 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
97 #define INT_PCI_MSI_NR 32
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
108 #define RCAR_PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_controller chip;
121 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
123 return container_of(chip, struct rcar_msi, chip);
126 /* Structure representing the PCIe interface */
130 struct resource res[RCAR_PCI_MAX_RESOURCES];
131 struct resource busn;
138 static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
140 return sys->private_data;
143 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
146 writel(val, pcie->base + reg);
149 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
152 return readl(pcie->base + reg);
156 RCAR_PCI_ACCESS_READ,
157 RCAR_PCI_ACCESS_WRITE,
160 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
162 int shift = 8 * (where & 3);
163 u32 val = rcar_pci_read_reg(pcie, where & ~3);
165 val &= ~(mask << shift);
166 val |= data << shift;
167 rcar_pci_write_reg(pcie, val, where & ~3);
170 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
178 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
179 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
180 unsigned char access_type, struct pci_bus *bus,
181 unsigned int devfn, int where, u32 *data)
183 int dev, func, reg, index;
185 dev = PCI_SLOT(devfn);
186 func = PCI_FUNC(devfn);
191 * While each channel has its own memory-mapped extended config
192 * space, it's generally only accessible when in endpoint mode.
193 * When in root complex mode, the controller is unable to target
194 * itself with either type 0 or type 1 accesses, and indeed, any
195 * controller initiated target transfer to its own config space
196 * result in a completer abort.
198 * Each channel effectively only supports a single device, but as
199 * the same channel <-> device access works for any PCI_SLOT()
200 * value, we cheat a bit here and bind the controller's config
201 * space to devfn 0 in order to enable self-enumeration. In this
202 * case the regular ECAR/ECDR path is sidelined and the mangled
203 * config access itself is initiated as an internal bus transaction.
205 if (pci_is_root_bus(bus)) {
207 return PCIBIOS_DEVICE_NOT_FOUND;
209 if (access_type == RCAR_PCI_ACCESS_READ) {
210 *data = rcar_pci_read_reg(pcie, PCICONF(index));
212 /* Keep an eye out for changes to the root bus number */
213 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
214 pcie->root_bus_nr = *data & 0xff;
216 rcar_pci_write_reg(pcie, *data, PCICONF(index));
219 return PCIBIOS_SUCCESSFUL;
222 if (pcie->root_bus_nr < 0)
223 return PCIBIOS_DEVICE_NOT_FOUND;
226 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
228 /* Set the PIO address */
229 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
230 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
232 /* Enable the configuration access */
233 if (bus->parent->number == pcie->root_bus_nr)
234 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
238 /* Check for errors */
239 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
240 return PCIBIOS_DEVICE_NOT_FOUND;
242 /* Check for master and target aborts */
243 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
244 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
245 return PCIBIOS_DEVICE_NOT_FOUND;
247 if (access_type == RCAR_PCI_ACCESS_READ)
248 *data = rcar_pci_read_reg(pcie, PCIECDR);
250 rcar_pci_write_reg(pcie, *data, PCIECDR);
252 /* Disable the configuration access */
253 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
255 return PCIBIOS_SUCCESSFUL;
258 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
261 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
264 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
265 bus, devfn, where, val);
266 if (ret != PCIBIOS_SUCCESSFUL) {
272 *val = (*val >> (8 * (where & 3))) & 0xff;
274 *val = (*val >> (8 * (where & 2))) & 0xffff;
276 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
277 bus->number, devfn, where, size, (unsigned long)*val);
282 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
283 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 val)
286 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
290 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
291 bus, devfn, where, &data);
292 if (ret != PCIBIOS_SUCCESSFUL)
295 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
296 bus->number, devfn, where, size, (unsigned long)val);
299 shift = 8 * (where & 3);
300 data &= ~(0xff << shift);
301 data |= ((val & 0xff) << shift);
302 } else if (size == 2) {
303 shift = 8 * (where & 2);
304 data &= ~(0xffff << shift);
305 data |= ((val & 0xffff) << shift);
309 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
310 bus, devfn, where, &data);
315 static struct pci_ops rcar_pcie_ops = {
316 .read = rcar_pcie_read_conf,
317 .write = rcar_pcie_write_conf,
320 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
322 struct resource *res = &pcie->res[win];
324 /* Setup PCIe address space mappings for each resource */
325 resource_size_t size;
326 resource_size_t res_start;
329 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
332 * The PAMR mask is calculated in units of 128Bytes, which
333 * keeps things pretty simple.
335 size = resource_size(res);
336 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
337 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
339 if (res->flags & IORESOURCE_IO)
340 res_start = pci_pio_to_address(res->start);
342 res_start = res->start;
344 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
345 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
348 /* First resource is for IO */
350 if (res->flags & IORESOURCE_IO)
353 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
356 static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
358 struct rcar_pcie *pcie = sys_to_pcie(sys);
359 struct resource *res;
362 pcie->root_bus_nr = -1;
364 /* Setup PCI resources */
365 for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
371 rcar_pcie_setup_window(i, pcie);
373 if (res->flags & IORESOURCE_IO) {
374 phys_addr_t io_start = pci_pio_to_address(res->start);
375 pci_ioremap_io(nr * SZ_64K, io_start);
377 pci_add_resource(&sys->resources, res);
379 pci_add_resource(&sys->resources, &pcie->busn);
384 static struct hw_pci rcar_pci = {
385 .setup = rcar_pcie_setup,
386 .map_irq = of_irq_parse_and_map_pci,
387 .ops = &rcar_pcie_ops,
390 static void rcar_pcie_enable(struct rcar_pcie *pcie)
392 struct platform_device *pdev = to_platform_device(pcie->dev);
394 rcar_pci.nr_controllers = 1;
395 rcar_pci.private_data = (void **)&pcie;
396 #ifdef CONFIG_PCI_MSI
397 rcar_pci.msi_ctrl = &pcie->msi.chip;
400 pci_common_init_dev(&pdev->dev, &rcar_pci);
403 static int phy_wait_for_ack(struct rcar_pcie *pcie)
405 unsigned int timeout = 100;
408 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
414 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
419 static void phy_write_reg(struct rcar_pcie *pcie,
420 unsigned int rate, unsigned int addr,
421 unsigned int lane, unsigned int data)
423 unsigned long phyaddr;
425 phyaddr = WRITE_CMD |
426 ((rate & 1) << RATE_POS) |
427 ((lane & 0xf) << LANE_POS) |
428 ((addr & 0xff) << ADR_POS);
431 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
432 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
434 /* Ignore errors as they will be dealt with if the data link is down */
435 phy_wait_for_ack(pcie);
438 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
439 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
441 /* Ignore errors as they will be dealt with if the data link is down */
442 phy_wait_for_ack(pcie);
445 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
447 unsigned int timeout = 10;
450 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
459 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
463 /* Begin initialization */
464 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
467 rcar_pci_write_reg(pcie, 1, PCIEMSR);
470 * Initial header for port config space is type 1, set the device
471 * class to match. Hardware takes care of propagating the IDSETR
472 * settings, so there is no need to bother with a quirk.
474 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
477 * Setup Secondary Bus Number & Subordinate Bus Number, even though
478 * they aren't used, to avoid bridge being detected as broken.
480 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
481 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
483 /* Initialize default capabilities. */
484 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
485 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
486 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
487 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
488 PCI_HEADER_TYPE_BRIDGE);
490 /* Enable data link layer active state reporting */
491 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
492 PCI_EXP_LNKCAP_DLLLARC);
494 /* Write out the physical slot number = 0 */
495 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
497 /* Set the completion timer timeout to the maximum 50ms. */
498 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
500 /* Terminate list of capabilities (Next Capability Offset=0) */
501 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
504 if (IS_ENABLED(CONFIG_PCI_MSI))
505 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
507 /* Finish initialization - establish a PCI Express link */
508 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
510 /* This will timeout if we don't have a link. */
511 err = rcar_pcie_wait_for_dl(pcie);
515 /* Enable INTx interrupts */
516 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
523 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
525 unsigned int timeout = 10;
527 /* Initialize the phy */
528 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
529 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
530 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
531 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
532 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
533 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
534 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
535 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
536 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
537 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
538 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
539 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
541 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
542 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
543 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
546 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
547 return rcar_pcie_hw_init(pcie);
555 static int rcar_msi_alloc(struct rcar_msi *chip)
559 mutex_lock(&chip->lock);
561 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
562 if (msi < INT_PCI_MSI_NR)
563 set_bit(msi, chip->used);
567 mutex_unlock(&chip->lock);
572 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
574 mutex_lock(&chip->lock);
575 clear_bit(irq, chip->used);
576 mutex_unlock(&chip->lock);
579 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
581 struct rcar_pcie *pcie = data;
582 struct rcar_msi *msi = &pcie->msi;
585 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
587 /* MSI & INTx share an interrupt - we only handle MSI here */
592 unsigned int index = find_first_bit(®, 32);
595 /* clear the interrupt */
596 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
598 irq = irq_find_mapping(msi->domain, index);
600 if (test_bit(index, msi->used))
601 generic_handle_irq(irq);
603 dev_info(pcie->dev, "unhandled MSI\n");
605 /* Unknown MSI, just clear it */
606 dev_dbg(pcie->dev, "unexpected MSI\n");
609 /* see if there's any more pending in this vector */
610 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
616 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
617 struct msi_desc *desc)
619 struct rcar_msi *msi = to_rcar_msi(chip);
620 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
625 hwirq = rcar_msi_alloc(msi);
629 irq = irq_create_mapping(msi->domain, hwirq);
631 rcar_msi_free(msi, hwirq);
635 irq_set_msi_desc(irq, desc);
637 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
638 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
641 pci_write_msi_msg(irq, &msg);
646 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
648 struct rcar_msi *msi = to_rcar_msi(chip);
649 struct irq_data *d = irq_get_irq_data(irq);
651 rcar_msi_free(msi, d->hwirq);
654 static struct irq_chip rcar_msi_irq_chip = {
655 .name = "R-Car PCIe MSI",
656 .irq_enable = pci_msi_unmask_irq,
657 .irq_disable = pci_msi_mask_irq,
658 .irq_mask = pci_msi_mask_irq,
659 .irq_unmask = pci_msi_unmask_irq,
662 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
663 irq_hw_number_t hwirq)
665 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
666 irq_set_chip_data(irq, domain->host_data);
667 set_irq_flags(irq, IRQF_VALID);
672 static const struct irq_domain_ops msi_domain_ops = {
676 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
678 struct platform_device *pdev = to_platform_device(pcie->dev);
679 struct rcar_msi *msi = &pcie->msi;
683 mutex_init(&msi->lock);
685 msi->chip.dev = pcie->dev;
686 msi->chip.setup_irq = rcar_msi_setup_irq;
687 msi->chip.teardown_irq = rcar_msi_teardown_irq;
689 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
690 &msi_domain_ops, &msi->chip);
692 dev_err(&pdev->dev, "failed to create IRQ domain\n");
696 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
697 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
698 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
700 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
704 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
705 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
707 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
711 /* setup MSI data target */
712 msi->pages = __get_free_pages(GFP_KERNEL, 0);
713 base = virt_to_phys((void *)msi->pages);
715 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
716 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
718 /* enable all MSI interrupts */
719 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
724 irq_domain_remove(msi->domain);
728 static int rcar_pcie_get_resources(struct platform_device *pdev,
729 struct rcar_pcie *pcie)
734 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
738 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
739 if (IS_ERR(pcie->clk)) {
740 dev_err(pcie->dev, "cannot get platform clock\n");
741 return PTR_ERR(pcie->clk);
743 err = clk_prepare_enable(pcie->clk);
747 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
748 if (IS_ERR(pcie->bus_clk)) {
749 dev_err(pcie->dev, "cannot get pcie bus clock\n");
750 err = PTR_ERR(pcie->bus_clk);
753 err = clk_prepare_enable(pcie->bus_clk);
757 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
759 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
765 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
767 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
773 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
774 if (IS_ERR(pcie->base)) {
775 err = PTR_ERR(pcie->base);
782 clk_disable_unprepare(pcie->bus_clk);
784 clk_disable_unprepare(pcie->clk);
789 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
790 struct of_pci_range *range,
793 u64 restype = range->flags;
794 u64 cpu_addr = range->cpu_addr;
795 u64 cpu_end = range->cpu_addr + range->size;
796 u64 pci_addr = range->pci_addr;
797 u32 flags = LAM_64BIT | LAR_ENABLE;
802 if (restype & IORESOURCE_PREFETCH)
803 flags |= LAM_PREFETCH;
806 * If the size of the range is larger than the alignment of the start
807 * address, we have to use multiple entries to perform the mapping.
810 unsigned long nr_zeros = __ffs64(cpu_addr);
811 u64 alignment = 1ULL << nr_zeros;
813 size = min(range->size, alignment);
817 /* Hardware supports max 4GiB inbound region */
818 size = min(size, 1ULL << 32);
820 mask = roundup_pow_of_two(size) - 1;
823 while (cpu_addr < cpu_end) {
825 * Set up 64-bit inbound regions as the range parser doesn't
826 * distinguish between 32 and 64-bit types.
828 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
829 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
830 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
832 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
833 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
834 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
840 if (idx > MAX_NR_INBOUND_MAPS) {
841 dev_err(pcie->dev, "Failed to map inbound regions!\n");
850 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
851 struct device_node *node)
853 const int na = 3, ns = 2;
857 parser->pna = of_n_addr_cells(node);
858 parser->np = parser->pna + na + ns;
860 parser->range = of_get_property(node, "dma-ranges", &rlen);
864 parser->end = parser->range + rlen / sizeof(__be32);
868 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
869 struct device_node *np)
871 struct of_pci_range range;
872 struct of_pci_range_parser parser;
876 if (pci_dma_range_parser_init(&parser, np))
879 /* Get the dma-ranges from DT */
880 for_each_of_pci_range(&parser, &range) {
881 u64 end = range.cpu_addr + range.size - 1;
882 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
883 range.flags, range.cpu_addr, end, range.pci_addr);
885 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
893 static const struct of_device_id rcar_pcie_of_match[] = {
894 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
895 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
896 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
899 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
901 static int rcar_pcie_probe(struct platform_device *pdev)
903 struct rcar_pcie *pcie;
905 struct of_pci_range range;
906 struct of_pci_range_parser parser;
907 const struct of_device_id *of_id;
909 int (*hw_init_fn)(struct rcar_pcie *);
911 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
915 pcie->dev = &pdev->dev;
916 platform_set_drvdata(pdev, pcie);
918 /* Get the bus range */
919 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
920 dev_err(&pdev->dev, "failed to parse bus-range property\n");
924 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
925 dev_err(&pdev->dev, "missing ranges property\n");
929 err = rcar_pcie_get_resources(pdev, pcie);
931 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
935 for_each_of_pci_range(&parser, &range) {
936 err = of_pci_range_to_resource(&range, pdev->dev.of_node,
941 if (win > RCAR_PCI_MAX_RESOURCES)
945 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
949 if (IS_ENABLED(CONFIG_PCI_MSI)) {
950 err = rcar_pcie_enable_msi(pcie);
953 "failed to enable MSI support: %d\n",
959 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
960 if (!of_id || !of_id->data)
962 hw_init_fn = of_id->data;
964 /* Failure to get a link might just be that no cards are inserted */
965 err = hw_init_fn(pcie);
967 dev_info(&pdev->dev, "PCIe link down\n");
971 data = rcar_pci_read_reg(pcie, MACSR);
972 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
974 rcar_pcie_enable(pcie);
979 static struct platform_driver rcar_pcie_driver = {
982 .of_match_table = rcar_pcie_of_match,
983 .suppress_bind_attrs = true,
985 .probe = rcar_pcie_probe,
987 module_platform_driver(rcar_pcie_driver);
989 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
990 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
991 MODULE_LICENSE("GPL v2");