2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Based on the xilinx PCIe driver
8 * Bits taken from Synopsys Designware Host controller driver and
9 * ARM PCI Host generic driver.
11 * This program is free software: you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or
14 * (at your option) any later version.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/msi.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/of_pci.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_irq.h>
31 #include <linux/pci.h>
32 #include <linux/platform_device.h>
33 #include <linux/reset.h>
34 #include <linux/regmap.h>
36 #define REF_CLK_100MHZ (100 * 1000 * 1000)
37 #define PCIE_CLIENT_BASE 0x0
38 #define PCIE_RC_CONFIG_BASE 0xa00000
39 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
40 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
41 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
43 #define PCIE_CLIENT_BASIC_STATUS0 0x44
44 #define PCIE_CLIENT_BASIC_STATUS1 0x48
45 #define PCIE_CLIENT_INT_MASK 0x4c
46 #define PCIE_CLIENT_INT_STATUS 0x50
47 #define PCIE_CORE_INT_MASK 0x900210
48 #define PCIE_CORE_INT_STATUS 0x90020c
50 /** Size of one AXI Region (not Region 0) */
51 #define AXI_REGION_SIZE (0x1 << 20)
52 /** Overall size of AXI area */
53 #define AXI_OVERALL_SIZE (64 * (0x1 << 20))
54 /** Size of Region 0, equal to sum of sizes of other regions */
55 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
56 #define OB_REG_SIZE_SHIFT 5
57 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
59 #define AXI_WRAPPER_IO_WRITE 0x6
60 #define AXI_WRAPPER_MEM_WRITE 0x2
61 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
62 #define MIN_AXI_ADDR_BITS_PASSED 8
64 #define ROCKCHIP_PCIE_RPIFR1_INTR_MASK GENMASK(8, 5)
65 #define ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT 5
66 #define CLIENT_INTERRUPTS \
67 (LOC_INT | INTA | INTB | INTC | INTD |\
68 CORR_ERR | NFATAL_ERR | FATAL_ERR | DPA_INT | \
69 HOT_RESET | MSG_DONE | LEGACY_DONE)
70 #define CORE_INTERRUPTS \
71 (PRFPE | CRFPE | RRPE | CRFO | RT | RTR | \
72 PE | MTR | UCR | FCE | CT | UTC | MMVC)
73 #define PWR_STCG BIT(0)
74 #define HOT_PLUG BIT(1)
75 #define PHY_INT BIT(2)
76 #define UDMA_INT BIT(3)
77 #define LOC_INT BIT(4)
82 #define CORR_ERR BIT(9)
83 #define NFATAL_ERR BIT(10)
84 #define FATAL_ERR BIT(11)
85 #define DPA_INT BIT(12)
86 #define HOT_RESET BIT(13)
87 #define MSG_DONE BIT(14)
88 #define LEGACY_DONE BIT(15)
104 #define PCIE_ECAM_BUS(x) (((x) & 0xFF) << 20)
105 #define PCIE_ECAM_DEV(x) (((x) & 0x1F) << 15)
106 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
107 #define PCIE_ECAM_REG(x) (((x) & 0xFFF) << 0)
108 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
109 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
110 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
112 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
113 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
114 #define RC_REGION_0_PASS_BITS (25 - 1)
115 #define RC_REGION_1_ADDR_TRANS_H 0x00000000
116 #define RC_REGION_1_ADDR_TRANS_L 0x00400000
117 #define RC_REGION_1_PASS_BITS (20 - 1)
118 #define MAX_AXI_WRAPPER_REGION_NUM 33
119 #define PCIE_CLIENT_CONF_ENABLE BIT(0)
120 #define PCIE_CLIENT_CONF_LANE_NUM(x) ((x / 2) << 4)
121 #define PCIE_CLIENT_MODE_RC BIT(6)
122 #define PCIE_CLIENT_GEN_SEL_2 BIT(7)
123 #define PCIE_CLIENT_GEN_SEL_1 0x0
125 struct rockchip_pcie_port {
126 void __iomem *reg_base;
127 void __iomem *apb_base;
129 unsigned int pcie_conf;
130 unsigned int pcie_status;
131 unsigned int pcie_laneoff;
132 struct reset_control *phy_rst;
133 struct reset_control *core_rst;
134 struct reset_control *mgmt_rst;
135 struct reset_control *mgmt_sticky_rst;
136 struct reset_control *pipe_rst;
137 struct clk *aclk_pcie;
138 struct clk *aclk_perf_pcie;
139 struct clk *hclk_pcie;
140 struct clk *clk_pciephy_ref;
141 struct gpio_desc *ep_gpio;
143 resource_size_t io_base;
144 struct resource *cfg;
146 struct resource *mem;
147 struct resource *busn;
148 phys_addr_t io_bus_addr;
150 phys_addr_t mem_bus_addr;
154 struct msi_controller *msi;
157 struct irq_domain *irq_domain;
160 static inline u32 pcie_read(struct rockchip_pcie_port *port, u32 reg)
162 return readl(port->apb_base + reg);
165 static inline void pcie_write(struct rockchip_pcie_port *port,
168 writel(val, port->apb_base + reg);
171 static inline void pcie_pb_wr_cfg(struct rockchip_pcie_port *port,
174 regmap_write(port->grf, port->pcie_conf,
175 (0x3ff << 17) | (data << 7) | (addr << 1));
177 regmap_write(port->grf, port->pcie_conf,
178 (0x1 << 16) | (0x1 << 0));
180 regmap_write(port->grf, port->pcie_conf,
181 (0x1 << 16) | (0x0 << 0));
184 static inline u32 pcie_pb_rd_cfg(struct rockchip_pcie_port *port,
189 regmap_write(port->grf, port->pcie_conf,
190 (0x3ff << 17) | (addr << 1));
191 regmap_read(port->grf, port->pcie_status, &val);
195 static int rockchip_pcie_valid_config(struct rockchip_pcie_port *pp,
196 struct pci_bus *bus, int dev)
198 /* access only one slot on each root port */
199 if (bus->number == pp->root_bus_nr && dev > 0)
203 * do not read more than one device on the bus directly attached
204 * to RC's (Virtual Bridge's) DS side.
206 if (bus->primary == pp->root_bus_nr && dev > 0)
212 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *pp,
216 void __iomem *addr = pp->apb_base + PCIE_RC_CONFIG_BASE + where;
218 if ((uintptr_t)addr & (size - 1)) {
220 return PCIBIOS_BAD_REGISTER_NUMBER;
225 } else if (size == 2) {
227 } else if (size == 1) {
231 return PCIBIOS_BAD_REGISTER_NUMBER;
233 return PCIBIOS_SUCCESSFUL;
236 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
237 int where, int size, u32 val)
242 offset = (where & (~0x3));
243 tmp = readl(pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
245 writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + where);
246 } else if (size == 2) {
248 tmp = ((tmp & 0xffff) | (val << 16));
250 tmp = ((tmp & 0xffff0000) | val);
252 writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
253 } else if (size == 1) {
254 if ((where & 0x3) == 0)
255 tmp = ((tmp & (~0xff)) | val);
256 else if ((where & 0x3) == 1)
257 tmp = ((tmp & (~0xff00)) | (val << 8));
258 else if ((where & 0x3) == 2)
259 tmp = ((tmp & (~0xff0000)) | (val << 16));
260 else if ((where & 0x3) == 3)
261 tmp = ((tmp & (~0xff000000)) | (val << 24));
263 writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
265 return PCIBIOS_BAD_REGISTER_NUMBER;
267 return PCIBIOS_SUCCESSFUL;
270 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
271 struct pci_bus *bus, u32 devfn,
272 int where, int size, u32 *val)
276 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
277 PCI_FUNC(devfn), where);
279 if (busdev & (size - 1)) {
281 return PCIBIOS_BAD_REGISTER_NUMBER;
285 *val = readl(pp->reg_base + busdev);
286 } else if (size == 2) {
287 *val = readw(pp->reg_base + busdev);
288 } else if (size == 1) {
289 *val = readb(pp->reg_base + busdev);
292 return PCIBIOS_BAD_REGISTER_NUMBER;
294 return PCIBIOS_SUCCESSFUL;
297 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *pp,
298 struct pci_bus *bus, u32 devfn,
299 int where, int size, u32 val)
303 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
304 PCI_FUNC(devfn), where);
305 if (busdev & (size - 1))
306 return PCIBIOS_BAD_REGISTER_NUMBER;
309 writel(val, pp->reg_base + busdev);
311 writew(val, pp->reg_base + busdev);
313 writeb(val, pp->reg_base + busdev);
315 return PCIBIOS_BAD_REGISTER_NUMBER;
317 return PCIBIOS_SUCCESSFUL;
320 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
323 struct rockchip_pcie_port *pp = bus->sysdata;
326 if (rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
328 return PCIBIOS_DEVICE_NOT_FOUND;
331 if (bus->number != pp->root_bus_nr)
332 ret = rockchip_pcie_rd_other_conf(pp, bus, devfn,
335 ret = rockchip_pcie_rd_own_conf(pp, where, size, val);
340 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
341 int where, int size, u32 val)
343 struct rockchip_pcie_port *pp = bus->sysdata;
346 if (rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
347 return PCIBIOS_DEVICE_NOT_FOUND;
349 if (bus->number != pp->root_bus_nr)
350 ret = rockchip_pcie_wr_other_conf(pp, bus, devfn,
353 ret = rockchip_pcie_wr_own_conf(pp, where, size, val);
358 static struct pci_ops rockchip_pcie_ops = {
359 .read = rockchip_pcie_rd_conf,
360 .write = rockchip_pcie_wr_conf,
364 * rockchip_pcie_init_port - Initialize hardware
365 * @port: PCIe port information
367 static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
371 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
373 gpiod_set_value(port->ep_gpio, 0);
375 /* Make sure PCIe relate block is in reset state */
376 err = reset_control_assert(port->phy_rst);
378 dev_err(port->dev, "assert phy_rst err %d\n", err);
381 err = reset_control_assert(port->core_rst);
383 dev_err(port->dev, "assert core_rst err %d\n", err);
386 err = reset_control_assert(port->mgmt_rst);
388 dev_err(port->dev, "assert mgmt_rst err %d\n", err);
391 err = reset_control_assert(port->mgmt_sticky_rst);
393 dev_err(port->dev, "assert mgmt_sticky_rst err %d\n", err);
396 err = reset_control_assert(port->pipe_rst);
398 dev_err(port->dev, "assert pipe_rst err %d\n", err);
402 pcie_write(port, (0xf << 20) | (0x1 << 16) | PCIE_CLIENT_GEN_SEL_2 |
403 (0x1 << 19) | (0x1 << 3) |
404 PCIE_CLIENT_MODE_RC |
405 PCIE_CLIENT_CONF_LANE_NUM(port->lanes) |
406 PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_BASE);
408 err = reset_control_deassert(port->phy_rst);
410 dev_err(port->dev, "deassert phy_rst err %d\n", err);
413 regmap_write(port->grf, port->pcie_conf,
414 (0x3f << 17) | (0x10 << 1));
416 while (time_before(jiffies, timeout)) {
417 regmap_read(port->grf, port->pcie_status, &status);
418 if ((status & (1 << 9))) {
419 dev_info(port->dev, "pll locked!\n");
425 dev_err(port->dev, "pll lock timeout!\n");
428 pcie_pb_wr_cfg(port, 0x10, 0x8);
429 pcie_pb_wr_cfg(port, 0x12, 0x8);
432 while (time_before(jiffies, timeout)) {
433 regmap_read(port->grf, port->pcie_status, &status);
434 if (!(status & (1 << 10))) {
435 dev_info(port->dev, "pll output enable done!\n");
442 dev_err(port->dev, "pll output enable timeout!\n");
446 regmap_write(port->grf, port->pcie_conf,
447 (0x3f << 17) | (0x10 << 1));
449 while (time_before(jiffies, timeout)) {
450 regmap_read(port->grf, port->pcie_status, &status);
451 if ((status & (1 << 9))) {
452 dev_info(port->dev, "pll relocked!\n");
458 dev_err(port->dev, "pll relock timeout!\n");
462 err = reset_control_deassert(port->core_rst);
464 dev_err(port->dev, "deassert core_rst err %d\n", err);
467 err = reset_control_deassert(port->mgmt_rst);
469 dev_err(port->dev, "deassert mgmt_rst err %d\n", err);
472 err = reset_control_deassert(port->mgmt_sticky_rst);
474 dev_err(port->dev, "deassert mgmt_sticky_rst err %d\n", err);
477 err = reset_control_deassert(port->pipe_rst);
479 dev_err(port->dev, "deassert pipe_rst err %d\n", err);
483 pcie_write(port, 1 << 17 | 1 << 1, PCIE_CLIENT_BASE);
485 gpiod_set_value(port->ep_gpio, 1);
487 while (time_before(jiffies, timeout)) {
488 status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
489 if (((status >> 20) & 0x3) == 0x3) {
490 dev_info(port->dev, "pcie link training gen1 pass!\n");
496 dev_err(port->dev, "pcie link training gen1 timeout!\n");
500 status = pcie_read(port, 0x9000d0);
502 pcie_write(port, status, 0x9000d0);
504 while (time_before(jiffies, timeout)) {
505 status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
506 if (((status >> 3) & 0x3) == 0x1) {
507 dev_info(port->dev, "pcie link training gen2 pass!\n");
513 dev_dbg(port->dev, "pcie link training gen2 timeout, force to gen1!\n");
515 if (((status >> 3) & 0x3) == 0x0)
516 dev_info(port->dev, "pcie link 2.5!\n");
517 if (((status >> 3) & 0x3) == 0x1)
518 dev_info(port->dev, "pcie link 5.0!\n");
520 status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
521 status = 0x1 << ((status >> 1) & 0x3);
522 dev_info(port->dev, "current link width is x%d\n", status);
524 status = pcie_pb_rd_cfg(port, 0x30);
525 if (!((status >> 11) & 0x1))
526 dev_dbg(port->dev, "lane A is used\n");
528 regmap_write(port->grf, port->pcie_laneoff,
529 (0x1 << 19) | (0x1 << 3));
531 status = pcie_pb_rd_cfg(port, 0x31);
532 if (!((status >> 11) & 0x1))
533 dev_dbg(port->dev, "lane B is used\n");
535 regmap_write(port->grf, port->pcie_laneoff,
536 (0x2 << 19) | (0x2 << 3));
538 status = pcie_pb_rd_cfg(port, 0x32);
539 if (!((status >> 11) & 0x1))
540 dev_dbg(port->dev, "lane C is used\n");
542 regmap_write(port->grf, port->pcie_laneoff,
543 (0x4 << 19) | (0x4 << 3));
545 status = pcie_pb_rd_cfg(port, 0x33);
546 if (!((status >> 11) & 0x1))
547 dev_dbg(port->dev, "lane D is used\n");
549 regmap_write(port->grf, port->pcie_laneoff,
550 (0x8 << 19) | (0x8 << 3));
555 * rockchip_pcie_parse_dt - Parse Device tree
556 * @port: PCIe port information
558 * Return: '0' on success and error value on failure
560 static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
562 struct device *dev = port->dev;
563 struct device_node *node = dev->of_node;
564 struct resource regs;
565 unsigned int pcie_conf;
566 unsigned int pcie_status;
567 unsigned int pcie_laneoff;
570 err = of_address_to_resource(node, 0, ®s);
572 dev_err(dev, "missing \"reg\" property\n");
576 port->reg_base = devm_ioremap_resource(dev, ®s);
577 if (IS_ERR(port->reg_base))
578 return PTR_ERR(port->reg_base);
580 err = of_address_to_resource(node, 1, ®s);
582 dev_err(dev, "missing \"reg\" property\n");
586 port->apb_base = devm_ioremap_resource(dev, ®s);
587 if (IS_ERR(port->apb_base))
588 return PTR_ERR(port->apb_base);
590 port->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
592 if (IS_ERR(port->grf)) {
593 dev_err(dev, "Missing rockchip,grf property\n");
594 return PTR_ERR(port->grf);
597 if (of_property_read_u32(node, "pcie-conf", &pcie_conf)) {
598 dev_err(dev, "missing pcie-conf property in node %s\n",
603 port->pcie_conf = pcie_conf;
605 if (of_property_read_u32(node, "pcie-status", &pcie_status)) {
606 dev_err(dev, "missing pcie-status property in node %s\n",
611 port->pcie_status = pcie_status;
613 if (of_property_read_u32(node, "pcie-laneoff", &pcie_laneoff)) {
614 dev_err(dev, "missing pcie-laneoff property in node %s\n",
619 port->pcie_laneoff = pcie_laneoff;
622 err = of_property_read_u32(node, "num-lanes", &port->lanes);
623 if (!err && ((port->lanes == 0) ||
624 (port->lanes == 3) ||
625 (port->lanes > 4))) {
626 dev_info(dev, "invalid num-lanes, default use one lane\n");
630 port->phy_rst = devm_reset_control_get(dev, "phy-rst");
631 if (IS_ERR(port->phy_rst)) {
632 if (PTR_ERR(port->phy_rst) != -EPROBE_DEFER)
633 dev_err(dev, "missing phy-rst property in node %s\n",
635 err = PTR_ERR(port->phy_rst);
639 port->core_rst = devm_reset_control_get(dev, "core-rst");
640 if (IS_ERR(port->core_rst)) {
641 if (PTR_ERR(port->core_rst) != -EPROBE_DEFER)
642 dev_err(dev, "missing core-rst property in node %s\n",
644 err = PTR_ERR(port->core_rst);
648 port->mgmt_rst = devm_reset_control_get(dev, "mgmt-rst");
649 if (IS_ERR(port->mgmt_rst)) {
650 if (PTR_ERR(port->mgmt_rst) != -EPROBE_DEFER)
651 dev_err(dev, "missing mgmt-rst property in node %s\n",
653 err = PTR_ERR(port->mgmt_rst);
657 port->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky-rst");
658 if (IS_ERR(port->mgmt_sticky_rst)) {
659 if (PTR_ERR(port->mgmt_sticky_rst) != -EPROBE_DEFER)
660 dev_err(dev, "missing mgmt-sticky-rst property in node %s\n",
662 err = PTR_ERR(port->mgmt_sticky_rst);
666 port->pipe_rst = devm_reset_control_get(dev, "pipe-rst");
667 if (IS_ERR(port->pipe_rst)) {
668 if (PTR_ERR(port->pipe_rst) != -EPROBE_DEFER)
669 dev_err(dev, "missing pipe-rst property in node %s\n",
671 err = PTR_ERR(port->pipe_rst);
675 port->ep_gpio = gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
676 if (IS_ERR(port->ep_gpio)) {
677 dev_err(dev, "missing ep-gpios property in node %s\n",
679 return PTR_ERR(port->ep_gpio);
682 port->aclk_pcie = devm_clk_get(dev, "aclk_pcie");
683 if (IS_ERR(port->aclk_pcie)) {
684 dev_err(dev, "aclk_pcie clock not found.\n");
685 return PTR_ERR(port->aclk_pcie);
688 port->aclk_perf_pcie = devm_clk_get(dev, "aclk_perf_pcie");
689 if (IS_ERR(port->aclk_perf_pcie)) {
690 dev_err(dev, "aclk_perf_pcie clock not found.\n");
691 return PTR_ERR(port->aclk_perf_pcie);
694 port->hclk_pcie = devm_clk_get(dev, "hclk_pcie");
695 if (IS_ERR(port->hclk_pcie)) {
696 dev_err(dev, "hclk_pcie clock not found.\n");
697 return PTR_ERR(port->hclk_pcie);
700 port->clk_pciephy_ref = devm_clk_get(dev, "clk_pciephy_ref");
701 if (IS_ERR(port->clk_pciephy_ref)) {
702 dev_err(dev, "clk_pciephy_ref clock not found.\n");
703 return PTR_ERR(port->clk_pciephy_ref);
706 err = clk_prepare_enable(port->aclk_pcie);
708 dev_err(dev, "Unable to enable aclk_pcie clock.\n");
712 err = clk_prepare_enable(port->aclk_perf_pcie);
714 dev_err(dev, "Unable to enable aclk_perf_pcie clock.\n");
715 goto err_aclk_perf_pcie;
718 err = clk_prepare_enable(port->hclk_pcie);
720 dev_err(dev, "Unable to enable hclk_pcie clock.\n");
724 err = clk_prepare_enable(port->clk_pciephy_ref);
726 dev_err(dev, "Unable to enable hclk_pcie clock.\n");
727 goto err_pciephy_ref;
733 clk_disable_unprepare(port->hclk_pcie);
735 clk_disable_unprepare(port->aclk_perf_pcie);
737 clk_disable_unprepare(port->aclk_pcie);
742 static void rockchip_pcie_msi_enable(struct rockchip_pcie_port *pp)
744 struct device_node *msi_node;
746 msi_node = of_parse_phandle(pp->dev->of_node,
751 pp->msi = of_pci_find_msi_chip_by_node(msi_node);
752 of_node_put(msi_node);
755 pp->msi->dev = pp->dev;
758 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *pp)
760 pcie_write(pp, (CLIENT_INTERRUPTS << 16) &
761 (~CLIENT_INTERRUPTS), PCIE_CLIENT_INT_MASK);
762 pcie_write(pp, CORE_INTERRUPTS, PCIE_CORE_INT_MASK);
765 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
766 irq_hw_number_t hwirq)
768 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
769 irq_set_chip_data(irq, domain->host_data);
774 static const struct irq_domain_ops intx_domain_ops = {
775 .map = rockchip_pcie_intx_map,
778 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *pp)
780 struct device *dev = pp->dev;
781 struct device_node *node = dev->of_node;
782 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
784 if (!pcie_intc_node) {
785 dev_err(dev, "No PCIe Intc node found\n");
786 return PTR_ERR(pcie_intc_node);
788 pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
789 &intx_domain_ops, pp);
790 if (!pp->irq_domain) {
791 dev_err(dev, "Failed to get a INTx IRQ domain\n");
792 return PTR_ERR(pp->irq_domain);
798 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
800 struct rockchip_pcie_port *pp = arg;
804 reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
806 dev_dbg(pp->dev, "local interrupt recived\n");
807 sub_reg = pcie_read(pp, PCIE_CORE_INT_STATUS);
809 dev_dbg(pp->dev, "Parity error detected while reading from the PNP Receive FIFO RAM\n");
812 dev_dbg(pp->dev, "Parity error detected while reading from the Completion Receive FIFO RAM\n");
815 dev_dbg(pp->dev, "Parity error detected while reading from Replay Buffer RAM\n");
818 dev_dbg(pp->dev, "Overflow occurred in the PNP Receive FIFO\n");
821 dev_dbg(pp->dev, "Overflow occurred in the Completion Receive FIFO\n");
824 dev_dbg(pp->dev, "Replay timer timed out\n");
827 dev_dbg(pp->dev, "Replay timer rolled over after 4 transmissions of the same TLP\n");
830 dev_dbg(pp->dev, "Phy error detected on receive side\n");
833 dev_dbg(pp->dev, "Malformed TLP received from the link\n");
836 dev_dbg(pp->dev, "Malformed TLP received from the link\n");
839 dev_dbg(pp->dev, "An error was observed in the flow control advertisements from the other side\n");
842 dev_dbg(pp->dev, "A request timed out waiting for completion\n");
845 dev_dbg(pp->dev, "Unmapped TC error\n");
848 dev_dbg(pp->dev, "MSI mask register changes\n");
850 pcie_write(pp, sub_reg, PCIE_CORE_INT_STATUS);
853 pcie_write(pp, reg, PCIE_CLIENT_INT_STATUS);
858 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
860 struct rockchip_pcie_port *pp = arg;
863 reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
864 if (reg & LEGACY_DONE)
865 dev_dbg(pp->dev, "legacy done interrupt recived\n");
868 dev_dbg(pp->dev, "message done interrupt recived\n");
871 dev_dbg(pp->dev, "hot reset interrupt recived\n");
874 dev_dbg(pp->dev, "dpa interrupt recived\n");
877 dev_dbg(pp->dev, "fatal error interrupt recived\n");
880 dev_dbg(pp->dev, "no fatal error interrupt recived\n");
883 dev_dbg(pp->dev, "correctable error interrupt recived\n");
885 pcie_write(pp, reg, PCIE_CLIENT_INT_STATUS);
890 static irqreturn_t rockchip_pcie_legacy_int_handler(int irq, void *arg)
892 struct rockchip_pcie_port *pp = arg;
895 reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
896 reg = (reg & ROCKCHIP_PCIE_RPIFR1_INTR_MASK) >>
897 ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT;
898 generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
900 pcie_write(pp, reg, PCIE_CLIENT_INT_STATUS);
904 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *pp,
906 int type, u8 num_pass_bits,
907 u32 lower_addr, u32 upper_addr)
913 void __iomem *aw_base;
917 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
919 if ((num_pass_bits + 1) < 8)
921 if (num_pass_bits > 63)
923 if (region_no == 0) {
924 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
927 if (region_no != 0) {
928 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
931 aw_base = pp->apb_base + PCIE_CORE_AXI_CONF_BASE;
932 aw_base += (region_no << OB_REG_SIZE_SHIFT);
934 ob_addr_0 = (ob_addr_0 &
935 ~0x0000003fU) | (num_pass_bits &
937 ob_addr_0 = (ob_addr_0 &
938 ~0xffffff00U) | (lower_addr & 0xffffff00U);
939 ob_addr_1 = upper_addr;
940 ob_desc_0 = (1 << 23 | type);
942 writel(ob_addr_0, aw_base);
943 writel(ob_addr_1, aw_base + 0x4);
944 writel(ob_desc_0, aw_base + 0x8);
945 writel(ob_desc_1, aw_base + 0xc);
950 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *pp,
958 void __iomem *aw_base;
962 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
964 if ((num_pass_bits + 1) < MIN_AXI_ADDR_BITS_PASSED)
966 if (num_pass_bits > 63)
968 aw_base = pp->apb_base + PCIE_CORE_AXI_INBOUND_BASE;
969 aw_base += (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
970 ib_addr_0 = (ib_addr_0 &
971 ~0x0000003fU) | (num_pass_bits &
974 ib_addr_0 = (ib_addr_0 & ~0xffffff00U) |
975 ((lower_addr << 8) & 0xffffff00U);
976 ib_addr_1 = upper_addr;
977 writel(ib_addr_0, aw_base);
978 writel(ib_addr_1, aw_base + 0x4);
983 static int rockchip_pcie_probe(struct platform_device *pdev)
985 struct rockchip_pcie_port *port;
986 struct device *dev = &pdev->dev;
987 struct pci_bus *bus, *child;
988 struct resource_entry *win;
997 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1001 irq = platform_get_irq_byname(pdev, "pcie-sys");
1003 dev_err(dev, "missing pcie_sys IRQ resource\n");
1006 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
1007 IRQF_SHARED, "pcie-sys", port);
1009 dev_err(dev, "failed to request pcie subsystem irq\n");
1013 port->irq = platform_get_irq_byname(pdev, "pcie-legacy");
1014 if (port->irq < 0) {
1015 dev_err(dev, "missing pcie_legacy IRQ resource\n");
1018 err = devm_request_irq(dev, port->irq,
1019 rockchip_pcie_legacy_int_handler,
1024 dev_err(&pdev->dev, "failed to request pcie-legacy irq\n");
1028 irq = platform_get_irq_byname(pdev, "pcie-client");
1030 dev_err(dev, "missing pcie-client IRQ resource\n");
1033 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
1034 IRQF_SHARED, "pcie-client", port);
1036 dev_err(dev, "failed to request pcie client irq\n");
1041 err = rockchip_pcie_parse_dt(port);
1043 dev_err(dev, "Parsing DT failed\n");
1047 err = rockchip_pcie_init_port(port);
1051 platform_set_drvdata(pdev, port);
1053 rockchip_pcie_enable_interrupts(port);
1054 if (!IS_ENABLED(CONFIG_PCI_MSI)) {
1055 err = rockchip_pcie_init_irq_domain(port);
1060 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1061 &res, &port->io_base);
1064 /* Get the I/O and memory ranges from DT */
1065 resource_list_for_each_entry(win, &res) {
1066 switch (resource_type(win->res)) {
1068 port->io = win->res;
1069 port->io->name = "I/O";
1070 port->io_size = resource_size(port->io);
1071 port->io_bus_addr = port->io->start - win->offset;
1072 err = pci_remap_iospace(port->io, port->io_base);
1074 dev_warn(port->dev, "error %d: failed to map resource %pR\n",
1079 case IORESOURCE_MEM:
1080 port->mem = win->res;
1081 port->mem->name = "MEM";
1082 port->mem_size = resource_size(port->mem);
1083 port->mem_bus_addr = port->mem->start - win->offset;
1086 port->cfg = win->res;
1088 case IORESOURCE_BUS:
1089 port->busn = win->res;
1096 pcie_write(port, 0x6040000, PCIE_RC_CONFIG_BASE + 0x8);
1097 pcie_write(port, 0x0, PCIE_CORE_CTRL_MGMT_BASE + 0x300);
1099 pcie_write(port, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
1100 PCIE_CORE_AXI_CONF_BASE);
1101 pcie_write(port, RC_REGION_0_ADDR_TRANS_H,
1102 PCIE_CORE_AXI_CONF_BASE + 0x4);
1103 pcie_write(port, 0x0080000a, PCIE_CORE_AXI_CONF_BASE + 0x8);
1104 pcie_write(port, 0x00000000, PCIE_CORE_AXI_CONF_BASE + 0xc);
1106 for (reg_no = 0; reg_no < (port->mem_size >> 20); reg_no++) {
1107 err = rockchip_pcie_prog_ob_atu(port, reg_no + 1,
1108 AXI_WRAPPER_MEM_WRITE,
1110 port->mem_bus_addr +
1114 dev_err(dev, "Program RC outbound atu failed\n");
1119 err = rockchip_pcie_prog_ib_atu(port, 2, 32 - 1, 0x0, 0);
1121 dev_err(dev, "Program RC inbound atu failed\n");
1125 rockchip_pcie_msi_enable(port);
1127 port->root_bus_nr = port->busn->start;
1128 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1129 bus = pci_scan_root_bus_msi(port->dev, port->root_bus_nr,
1130 &rockchip_pcie_ops, port, &res,
1133 bus = pci_scan_root_bus(&pdev->dev, 0,
1134 &rockchip_pcie_ops, port, &res);
1139 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1140 pci_bus_size_bridges(bus);
1141 pci_bus_assign_resources(bus);
1142 list_for_each_entry(child, &bus->children, node)
1143 pcie_bus_configure_settings(child);
1146 pci_bus_add_devices(bus);
1151 static int rockchip_pcie_remove(struct platform_device *pdev)
1153 struct rockchip_pcie_port *port = platform_get_drvdata(pdev);
1155 clk_disable_unprepare(port->hclk_pcie);
1156 clk_disable_unprepare(port->aclk_perf_pcie);
1157 clk_disable_unprepare(port->aclk_pcie);
1158 clk_disable_unprepare(port->clk_pciephy_ref);
1163 static const struct of_device_id rockchip_pcie_of_match[] = {
1164 { .compatible = "rockchip,rk3399-pcie", },
1168 static struct platform_driver rockchip_pcie_driver = {
1170 .name = "rockchip-pcie",
1171 .of_match_table = rockchip_pcie_of_match,
1172 .suppress_bind_attrs = true,
1174 .probe = rockchip_pcie_probe,
1175 .remove = rockchip_pcie_remove,
1177 module_platform_driver(rockchip_pcie_driver);
1179 MODULE_AUTHOR("Rockchip Inc");
1180 MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
1181 MODULE_LICENSE("GPL v2");