3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
25 static int pci_msi_enable = 1;
29 #ifndef arch_msi_check_device
30 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
36 #ifndef arch_setup_msi_irqs
37 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
39 struct msi_desc *entry;
43 * If an architecture wants to support multiple MSI, it needs to
44 * override arch_setup_msi_irqs()
46 if (type == PCI_CAP_ID_MSI && nvec > 1)
49 list_for_each_entry(entry, &dev->msi_list, list) {
50 ret = arch_setup_msi_irq(dev, entry);
61 #ifndef arch_teardown_msi_irqs
62 void arch_teardown_msi_irqs(struct pci_dev *dev)
64 struct msi_desc *entry;
66 list_for_each_entry(entry, &dev->msi_list, list) {
70 nvec = 1 << entry->msi_attrib.multiple;
71 for (i = 0; i < nvec; i++)
72 arch_teardown_msi_irq(entry->irq + i);
77 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
83 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
84 control &= ~PCI_MSI_FLAGS_ENABLE;
86 control |= PCI_MSI_FLAGS_ENABLE;
87 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
90 static void msix_set_enable(struct pci_dev *dev, int enable)
95 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
97 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
98 control &= ~PCI_MSIX_FLAGS_ENABLE;
100 control |= PCI_MSIX_FLAGS_ENABLE;
101 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
105 static inline __attribute_const__ u32 msi_mask(unsigned x)
107 /* Don't shift by >= width of type */
110 return (1 << (1 << x)) - 1;
113 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
115 return msi_mask((control >> 1) & 7);
118 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
120 return msi_mask((control >> 4) & 7);
124 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
125 * mask all MSI interrupts by clearing the MSI enable bit does not work
126 * reliably as devices without an INTx disable bit will then generate a
127 * level IRQ which will never be cleared.
129 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
131 u32 mask_bits = desc->masked;
133 if (!desc->msi_attrib.maskbit)
138 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
143 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
145 desc->masked = __msi_mask_irq(desc, mask, flag);
149 * This internal function does not flush PCI writes to the device.
150 * All users must ensure that they read from the device before either
151 * assuming that the device state is up to date, or returning out of this
152 * file. This saves a few milliseconds when initialising devices with lots
153 * of MSI-X interrupts.
155 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
157 u32 mask_bits = desc->masked;
158 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
159 PCI_MSIX_ENTRY_VECTOR_CTRL;
162 writel(mask_bits, desc->mask_base + offset);
167 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
169 desc->masked = __msix_mask_irq(desc, flag);
172 static void msi_set_mask_bit(unsigned irq, u32 flag)
174 struct msi_desc *desc = get_irq_msi(irq);
176 if (desc->msi_attrib.is_msix) {
177 msix_mask_irq(desc, flag);
178 readl(desc->mask_base); /* Flush write to device */
180 unsigned offset = irq - desc->dev->irq;
181 msi_mask_irq(desc, 1 << offset, flag << offset);
185 void mask_msi_irq(unsigned int irq)
187 msi_set_mask_bit(irq, 1);
190 void unmask_msi_irq(unsigned int irq)
192 msi_set_mask_bit(irq, 0);
195 void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
197 struct msi_desc *entry = get_irq_desc_msi(desc);
199 /* We do not touch the hardware (which may not even be
200 * accessible at the moment) but return the last message
201 * written. Assert that this is valid, assuming that
202 * valid messages are not all-zeroes. */
203 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
209 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
211 struct irq_desc *desc = irq_to_desc(irq);
213 read_msi_msg_desc(desc, msg);
216 void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
218 struct msi_desc *entry = get_irq_desc_msi(desc);
220 if (entry->dev->current_state != PCI_D0) {
221 /* Don't touch the hardware now */
222 } else if (entry->msi_attrib.is_msix) {
224 base = entry->mask_base +
225 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
227 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
228 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
229 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
231 struct pci_dev *dev = entry->dev;
232 int pos = entry->msi_attrib.pos;
235 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
236 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
237 msgctl |= entry->msi_attrib.multiple << 4;
238 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
240 pci_write_config_dword(dev, msi_lower_address_reg(pos),
242 if (entry->msi_attrib.is_64) {
243 pci_write_config_dword(dev, msi_upper_address_reg(pos),
245 pci_write_config_word(dev, msi_data_reg(pos, 1),
248 pci_write_config_word(dev, msi_data_reg(pos, 0),
255 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
257 struct irq_desc *desc = irq_to_desc(irq);
259 write_msi_msg_desc(desc, msg);
262 static void free_msi_irqs(struct pci_dev *dev)
264 struct msi_desc *entry, *tmp;
266 list_for_each_entry(entry, &dev->msi_list, list) {
270 nvec = 1 << entry->msi_attrib.multiple;
271 for (i = 0; i < nvec; i++)
272 BUG_ON(irq_has_action(entry->irq + i));
275 arch_teardown_msi_irqs(dev);
277 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
278 if (entry->msi_attrib.is_msix) {
279 if (list_is_last(&entry->list, &dev->msi_list))
280 iounmap(entry->mask_base);
282 list_del(&entry->list);
287 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
289 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
293 INIT_LIST_HEAD(&desc->list);
299 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
301 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
302 pci_intx(dev, enable);
305 static void __pci_restore_msi_state(struct pci_dev *dev)
309 struct msi_desc *entry;
311 if (!dev->msi_enabled)
314 entry = get_irq_msi(dev->irq);
315 pos = entry->msi_attrib.pos;
317 pci_intx_for_msi(dev, 0);
318 msi_set_enable(dev, pos, 0);
319 write_msi_msg(dev->irq, &entry->msg);
321 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
322 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
323 control &= ~PCI_MSI_FLAGS_QSIZE;
324 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
325 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
328 static void __pci_restore_msix_state(struct pci_dev *dev)
331 struct msi_desc *entry;
334 if (!dev->msix_enabled)
336 BUG_ON(list_empty(&dev->msi_list));
337 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
338 pos = entry->msi_attrib.pos;
339 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
341 /* route the table */
342 pci_intx_for_msi(dev, 0);
343 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
344 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
346 list_for_each_entry(entry, &dev->msi_list, list) {
347 write_msi_msg(entry->irq, &entry->msg);
348 msix_mask_irq(entry, entry->masked);
351 control &= ~PCI_MSIX_FLAGS_MASKALL;
352 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
355 void pci_restore_msi_state(struct pci_dev *dev)
357 __pci_restore_msi_state(dev);
358 __pci_restore_msix_state(dev);
360 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
363 * msi_capability_init - configure device's MSI capability structure
364 * @dev: pointer to the pci_dev data structure of MSI device function
365 * @nvec: number of interrupts to allocate
367 * Setup the MSI capability structure of the device with the requested
368 * number of interrupts. A return value of zero indicates the successful
369 * setup of an entry with the new MSI irq. A negative return value indicates
370 * an error, and a positive return value indicates the number of interrupts
371 * which could have been allocated.
373 static int msi_capability_init(struct pci_dev *dev, int nvec)
375 struct msi_desc *entry;
380 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
381 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
383 pci_read_config_word(dev, msi_control_reg(pos), &control);
384 /* MSI Entry Initialization */
385 entry = alloc_msi_entry(dev);
389 entry->msi_attrib.is_msix = 0;
390 entry->msi_attrib.is_64 = is_64bit_address(control);
391 entry->msi_attrib.entry_nr = 0;
392 entry->msi_attrib.maskbit = is_mask_bit_support(control);
393 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
394 entry->msi_attrib.pos = pos;
396 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
397 /* All MSIs are unmasked by default, Mask them all */
398 if (entry->msi_attrib.maskbit)
399 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
400 mask = msi_capable_mask(control);
401 msi_mask_irq(entry, mask, mask);
403 list_add_tail(&entry->list, &dev->msi_list);
405 /* Configure MSI capability structure */
406 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
408 msi_mask_irq(entry, mask, ~mask);
413 /* Set MSI enabled bits */
414 pci_intx_for_msi(dev, 0);
415 msi_set_enable(dev, pos, 1);
416 dev->msi_enabled = 1;
418 dev->irq = entry->irq;
422 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
425 unsigned long phys_addr;
429 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
430 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
431 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
432 phys_addr = pci_resource_start(dev, bir) + table_offset;
434 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
437 static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
438 void __iomem *base, struct msix_entry *entries,
441 struct msi_desc *entry;
444 for (i = 0; i < nvec; i++) {
445 entry = alloc_msi_entry(dev);
451 /* No enough memory. Don't try again */
455 entry->msi_attrib.is_msix = 1;
456 entry->msi_attrib.is_64 = 1;
457 entry->msi_attrib.entry_nr = entries[i].entry;
458 entry->msi_attrib.default_irq = dev->irq;
459 entry->msi_attrib.pos = pos;
460 entry->mask_base = base;
462 list_add_tail(&entry->list, &dev->msi_list);
468 static void msix_program_entries(struct pci_dev *dev,
469 struct msix_entry *entries)
471 struct msi_desc *entry;
474 list_for_each_entry(entry, &dev->msi_list, list) {
475 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
476 PCI_MSIX_ENTRY_VECTOR_CTRL;
478 entries[i].vector = entry->irq;
479 set_irq_msi(entry->irq, entry);
480 entry->masked = readl(entry->mask_base + offset);
481 msix_mask_irq(entry, 1);
487 * msix_capability_init - configure device's MSI-X capability
488 * @dev: pointer to the pci_dev data structure of MSI-X device function
489 * @entries: pointer to an array of struct msix_entry entries
490 * @nvec: number of @entries
492 * Setup the MSI-X capability structure of device function with a
493 * single MSI-X irq. A return of zero indicates the successful setup of
494 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
496 static int msix_capability_init(struct pci_dev *dev,
497 struct msix_entry *entries, int nvec)
503 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
504 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
506 /* Ensure MSI-X is disabled while it is set up */
507 control &= ~PCI_MSIX_FLAGS_ENABLE;
508 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
510 /* Request & Map MSI-X table region */
511 base = msix_map_region(dev, pos, multi_msix_capable(control));
515 ret = msix_setup_entries(dev, pos, base, entries, nvec);
519 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
524 * Some devices require MSI-X to be enabled before we can touch the
525 * MSI-X registers. We need to mask all the vectors to prevent
526 * interrupts coming in before they're fully set up.
528 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
529 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
531 msix_program_entries(dev, entries);
533 /* Set MSI-X enabled bits and unmask the function */
534 pci_intx_for_msi(dev, 0);
535 dev->msix_enabled = 1;
537 control &= ~PCI_MSIX_FLAGS_MASKALL;
538 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
545 * If we had some success, report the number of irqs
546 * we succeeded in setting up.
548 struct msi_desc *entry;
551 list_for_each_entry(entry, &dev->msi_list, list) {
565 * pci_msi_check_device - check whether MSI may be enabled on a device
566 * @dev: pointer to the pci_dev data structure of MSI device function
567 * @nvec: how many MSIs have been requested ?
568 * @type: are we checking for MSI or MSI-X ?
570 * Look at global flags, the device itself, and its parent busses
571 * to determine if MSI/-X are supported for the device. If MSI/-X is
572 * supported return 0, else return an error code.
574 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
579 /* MSI must be globally enabled and supported by the device */
580 if (!pci_msi_enable || !dev || dev->no_msi)
584 * You can't ask to have 0 or less MSIs configured.
586 * b) the list manipulation code assumes nvec >= 1.
592 * Any bridge which does NOT route MSI transactions from its
593 * secondary bus to its primary bus must set NO_MSI flag on
594 * the secondary pci_bus.
595 * We expect only arch-specific PCI host bus controller driver
596 * or quirks for specific PCI bridges to be setting NO_MSI.
598 for (bus = dev->bus; bus; bus = bus->parent)
599 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
602 ret = arch_msi_check_device(dev, nvec, type);
606 if (!pci_find_capability(dev, type))
613 * pci_enable_msi_block - configure device's MSI capability structure
614 * @dev: device to configure
615 * @nvec: number of interrupts to configure
617 * Allocate IRQs for a device with the MSI capability.
618 * This function returns a negative errno if an error occurs. If it
619 * is unable to allocate the number of interrupts requested, it returns
620 * the number of interrupts it might be able to allocate. If it successfully
621 * allocates at least the number of interrupts requested, it returns 0 and
622 * updates the @dev's irq member to the lowest new interrupt number; the
623 * other interrupt numbers allocated to this device are consecutive.
625 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
627 int status, pos, maxvec;
630 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
633 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
634 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
638 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
642 WARN_ON(!!dev->msi_enabled);
644 /* Check whether driver already requested MSI-X irqs */
645 if (dev->msix_enabled) {
646 dev_info(&dev->dev, "can't enable MSI "
647 "(MSI-X already enabled)\n");
651 status = msi_capability_init(dev, nvec);
654 EXPORT_SYMBOL(pci_enable_msi_block);
656 void pci_msi_shutdown(struct pci_dev *dev)
658 struct msi_desc *desc;
663 if (!pci_msi_enable || !dev || !dev->msi_enabled)
666 BUG_ON(list_empty(&dev->msi_list));
667 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
668 pos = desc->msi_attrib.pos;
670 msi_set_enable(dev, pos, 0);
671 pci_intx_for_msi(dev, 1);
672 dev->msi_enabled = 0;
674 /* Return the device with MSI unmasked as initial states */
675 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
676 mask = msi_capable_mask(ctrl);
677 /* Keep cached state to be restored */
678 __msi_mask_irq(desc, mask, ~mask);
680 /* Restore dev->irq to its default pin-assertion irq */
681 dev->irq = desc->msi_attrib.default_irq;
684 void pci_disable_msi(struct pci_dev *dev)
686 if (!pci_msi_enable || !dev || !dev->msi_enabled)
689 pci_msi_shutdown(dev);
692 EXPORT_SYMBOL(pci_disable_msi);
695 * pci_msix_table_size - return the number of device's MSI-X table entries
696 * @dev: pointer to the pci_dev data structure of MSI-X device function
698 int pci_msix_table_size(struct pci_dev *dev)
703 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
707 pci_read_config_word(dev, msi_control_reg(pos), &control);
708 return multi_msix_capable(control);
712 * pci_enable_msix - configure device's MSI-X capability structure
713 * @dev: pointer to the pci_dev data structure of MSI-X device function
714 * @entries: pointer to an array of MSI-X entries
715 * @nvec: number of MSI-X irqs requested for allocation by device driver
717 * Setup the MSI-X capability structure of device function with the number
718 * of requested irqs upon its software driver call to request for
719 * MSI-X mode enabled on its hardware device function. A return of zero
720 * indicates the successful configuration of MSI-X capability structure
721 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
722 * Or a return of > 0 indicates that driver request is exceeding the number
723 * of irqs or MSI-X vectors available. Driver should use the returned value to
724 * re-send its request.
726 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
728 int status, nr_entries;
734 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
738 nr_entries = pci_msix_table_size(dev);
739 if (nvec > nr_entries)
742 /* Check for any invalid entries */
743 for (i = 0; i < nvec; i++) {
744 if (entries[i].entry >= nr_entries)
745 return -EINVAL; /* invalid entry */
746 for (j = i + 1; j < nvec; j++) {
747 if (entries[i].entry == entries[j].entry)
748 return -EINVAL; /* duplicate entry */
751 WARN_ON(!!dev->msix_enabled);
753 /* Check whether driver already requested for MSI irq */
754 if (dev->msi_enabled) {
755 dev_info(&dev->dev, "can't enable MSI-X "
756 "(MSI IRQ already assigned)\n");
759 status = msix_capability_init(dev, entries, nvec);
762 EXPORT_SYMBOL(pci_enable_msix);
764 void pci_msix_shutdown(struct pci_dev *dev)
766 struct msi_desc *entry;
768 if (!pci_msi_enable || !dev || !dev->msix_enabled)
771 /* Return the device with MSI-X masked as initial states */
772 list_for_each_entry(entry, &dev->msi_list, list) {
773 /* Keep cached states to be restored */
774 __msix_mask_irq(entry, 1);
777 msix_set_enable(dev, 0);
778 pci_intx_for_msi(dev, 1);
779 dev->msix_enabled = 0;
782 void pci_disable_msix(struct pci_dev *dev)
784 if (!pci_msi_enable || !dev || !dev->msix_enabled)
787 pci_msix_shutdown(dev);
790 EXPORT_SYMBOL(pci_disable_msix);
793 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
794 * @dev: pointer to the pci_dev data structure of MSI(X) device function
796 * Being called during hotplug remove, from which the device function
797 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
798 * allocated for this device function, are reclaimed to unused state,
799 * which may be used later on.
801 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
803 if (!pci_msi_enable || !dev)
806 if (dev->msi_enabled || dev->msix_enabled)
810 void pci_no_msi(void)
816 * pci_msi_enabled - is MSI enabled?
818 * Returns true if MSI has not been disabled by the command-line option
821 int pci_msi_enabled(void)
823 return pci_msi_enable;
825 EXPORT_SYMBOL(pci_msi_enabled);
827 void pci_msi_init_pci_dev(struct pci_dev *dev)
829 INIT_LIST_HEAD(&dev->msi_list);