3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
26 static int pci_msi_enable = 1;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 #if defined(CONFIG_GENERIC_HARDIRQS)
34 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
36 struct msi_chip *chip = dev->bus->msi;
39 if (!chip || !chip->setup_irq)
42 err = chip->setup_irq(chip, dev, desc);
46 irq_set_chip_data(desc->irq, chip);
51 void __weak arch_teardown_msi_irq(unsigned int irq)
53 struct msi_chip *chip = irq_get_chip_data(irq);
55 if (!chip || !chip->teardown_irq)
58 chip->teardown_irq(chip, irq);
61 int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
63 struct msi_chip *chip = dev->bus->msi;
65 if (!chip || !chip->check_device)
68 return chip->check_device(chip, dev, nvec, type);
71 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
76 void __weak arch_teardown_msi_irq(unsigned int irq)
80 int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
84 #endif /* CONFIG_GENERIC_HARDIRQS */
86 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
88 struct msi_desc *entry;
92 * If an architecture wants to support multiple MSI, it needs to
93 * override arch_setup_msi_irqs()
95 if (type == PCI_CAP_ID_MSI && nvec > 1)
98 list_for_each_entry(entry, &dev->msi_list, list) {
99 ret = arch_setup_msi_irq(dev, entry);
110 * We have a default implementation available as a separate non-weak
111 * function, as it is used by the Xen x86 PCI code
113 void default_teardown_msi_irqs(struct pci_dev *dev)
115 struct msi_desc *entry;
117 list_for_each_entry(entry, &dev->msi_list, list) {
121 if (entry->nvec_used)
122 nvec = entry->nvec_used;
124 nvec = 1 << entry->msi_attrib.multiple;
125 for (i = 0; i < nvec; i++)
126 arch_teardown_msi_irq(entry->irq + i);
130 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
132 return default_teardown_msi_irqs(dev);
135 void default_restore_msi_irqs(struct pci_dev *dev, int irq)
137 struct msi_desc *entry;
140 if (dev->msix_enabled) {
141 list_for_each_entry(entry, &dev->msi_list, list) {
142 if (irq == entry->irq)
145 } else if (dev->msi_enabled) {
146 entry = irq_get_msi_desc(irq);
150 write_msi_msg(irq, &entry->msg);
153 void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq)
155 return default_restore_msi_irqs(dev, irq);
158 static void msi_set_enable(struct pci_dev *dev, int enable)
162 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
163 control &= ~PCI_MSI_FLAGS_ENABLE;
165 control |= PCI_MSI_FLAGS_ENABLE;
166 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
169 static void msix_set_enable(struct pci_dev *dev, int enable)
173 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
174 control &= ~PCI_MSIX_FLAGS_ENABLE;
176 control |= PCI_MSIX_FLAGS_ENABLE;
177 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
180 static inline __attribute_const__ u32 msi_mask(unsigned x)
182 /* Don't shift by >= width of type */
185 return (1 << (1 << x)) - 1;
188 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
190 return msi_mask((control >> 1) & 7);
193 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
195 return msi_mask((control >> 4) & 7);
199 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
200 * mask all MSI interrupts by clearing the MSI enable bit does not work
201 * reliably as devices without an INTx disable bit will then generate a
202 * level IRQ which will never be cleared.
204 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
206 u32 mask_bits = desc->masked;
208 if (!desc->msi_attrib.maskbit)
213 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
218 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
220 desc->masked = __msi_mask_irq(desc, mask, flag);
224 * This internal function does not flush PCI writes to the device.
225 * All users must ensure that they read from the device before either
226 * assuming that the device state is up to date, or returning out of this
227 * file. This saves a few milliseconds when initialising devices with lots
228 * of MSI-X interrupts.
230 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
232 u32 mask_bits = desc->masked;
233 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
234 PCI_MSIX_ENTRY_VECTOR_CTRL;
235 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
237 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
238 writel(mask_bits, desc->mask_base + offset);
243 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
245 desc->masked = __msix_mask_irq(desc, flag);
248 #ifdef CONFIG_GENERIC_HARDIRQS
250 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
252 struct msi_desc *desc = irq_data_get_msi(data);
254 if (desc->msi_attrib.is_msix) {
255 msix_mask_irq(desc, flag);
256 readl(desc->mask_base); /* Flush write to device */
258 unsigned offset = data->irq - desc->dev->irq;
259 msi_mask_irq(desc, 1 << offset, flag << offset);
263 void mask_msi_irq(struct irq_data *data)
265 msi_set_mask_bit(data, 1);
268 void unmask_msi_irq(struct irq_data *data)
270 msi_set_mask_bit(data, 0);
273 #endif /* CONFIG_GENERIC_HARDIRQS */
275 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
277 BUG_ON(entry->dev->current_state != PCI_D0);
279 if (entry->msi_attrib.is_msix) {
280 void __iomem *base = entry->mask_base +
281 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
283 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
284 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
285 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
287 struct pci_dev *dev = entry->dev;
288 int pos = dev->msi_cap;
291 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
293 if (entry->msi_attrib.is_64) {
294 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
296 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
299 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
305 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
307 struct msi_desc *entry = irq_get_msi_desc(irq);
309 __read_msi_msg(entry, msg);
312 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
314 /* Assert that the cache is valid, assuming that
315 * valid messages are not all-zeroes. */
316 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
322 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
324 struct msi_desc *entry = irq_get_msi_desc(irq);
326 __get_cached_msi_msg(entry, msg);
329 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
331 if (entry->dev->current_state != PCI_D0) {
332 /* Don't touch the hardware now */
333 } else if (entry->msi_attrib.is_msix) {
335 base = entry->mask_base +
336 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
338 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
339 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
340 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
342 struct pci_dev *dev = entry->dev;
343 int pos = dev->msi_cap;
346 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
347 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
348 msgctl |= entry->msi_attrib.multiple << 4;
349 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
351 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
353 if (entry->msi_attrib.is_64) {
354 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
356 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
359 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
366 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
368 struct msi_desc *entry = irq_get_msi_desc(irq);
370 __write_msi_msg(entry, msg);
373 static void free_msi_irqs(struct pci_dev *dev)
375 struct msi_desc *entry, *tmp;
377 list_for_each_entry(entry, &dev->msi_list, list) {
381 if (entry->nvec_used)
382 nvec = entry->nvec_used;
384 nvec = 1 << entry->msi_attrib.multiple;
385 #ifdef CONFIG_GENERIC_HARDIRQS
386 for (i = 0; i < nvec; i++)
387 BUG_ON(irq_has_action(entry->irq + i));
391 arch_teardown_msi_irqs(dev);
393 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
394 if (entry->msi_attrib.is_msix) {
395 if (list_is_last(&entry->list, &dev->msi_list))
396 iounmap(entry->mask_base);
400 * Its possible that we get into this path
401 * When populate_msi_sysfs fails, which means the entries
402 * were not registered with sysfs. In that case don't
405 if (entry->kobj.parent) {
406 kobject_del(&entry->kobj);
407 kobject_put(&entry->kobj);
410 list_del(&entry->list);
415 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
417 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
421 INIT_LIST_HEAD(&desc->list);
427 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
429 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
430 pci_intx(dev, enable);
433 static void __pci_restore_msi_state(struct pci_dev *dev)
436 struct msi_desc *entry;
438 if (!dev->msi_enabled)
441 entry = irq_get_msi_desc(dev->irq);
443 pci_intx_for_msi(dev, 0);
444 msi_set_enable(dev, 0);
445 arch_restore_msi_irqs(dev, dev->irq);
447 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
448 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
449 control &= ~PCI_MSI_FLAGS_QSIZE;
450 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
451 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
454 static void __pci_restore_msix_state(struct pci_dev *dev)
456 struct msi_desc *entry;
459 if (!dev->msix_enabled)
461 BUG_ON(list_empty(&dev->msi_list));
462 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
463 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
465 /* route the table */
466 pci_intx_for_msi(dev, 0);
467 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
468 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
470 list_for_each_entry(entry, &dev->msi_list, list) {
471 arch_restore_msi_irqs(dev, entry->irq);
472 msix_mask_irq(entry, entry->masked);
475 control &= ~PCI_MSIX_FLAGS_MASKALL;
476 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
479 void pci_restore_msi_state(struct pci_dev *dev)
481 __pci_restore_msi_state(dev);
482 __pci_restore_msix_state(dev);
484 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
487 #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
488 #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
490 struct msi_attribute {
491 struct attribute attr;
492 ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
494 ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
495 const char *buf, size_t count);
498 static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
501 return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
504 static ssize_t msi_irq_attr_show(struct kobject *kobj,
505 struct attribute *attr, char *buf)
507 struct msi_attribute *attribute = to_msi_attr(attr);
508 struct msi_desc *entry = to_msi_desc(kobj);
510 if (!attribute->show)
513 return attribute->show(entry, attribute, buf);
516 static const struct sysfs_ops msi_irq_sysfs_ops = {
517 .show = msi_irq_attr_show,
520 static struct msi_attribute mode_attribute =
521 __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
524 static struct attribute *msi_irq_default_attrs[] = {
525 &mode_attribute.attr,
529 static void msi_kobj_release(struct kobject *kobj)
531 struct msi_desc *entry = to_msi_desc(kobj);
533 pci_dev_put(entry->dev);
536 static struct kobj_type msi_irq_ktype = {
537 .release = msi_kobj_release,
538 .sysfs_ops = &msi_irq_sysfs_ops,
539 .default_attrs = msi_irq_default_attrs,
542 static int populate_msi_sysfs(struct pci_dev *pdev)
544 struct msi_desc *entry;
545 struct kobject *kobj;
549 pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
553 list_for_each_entry(entry, &pdev->msi_list, list) {
555 kobj->kset = pdev->msi_kset;
557 ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
568 list_for_each_entry(entry, &pdev->msi_list, list) {
571 kobject_del(&entry->kobj);
572 kobject_put(&entry->kobj);
579 * msi_capability_init - configure device's MSI capability structure
580 * @dev: pointer to the pci_dev data structure of MSI device function
581 * @nvec: number of interrupts to allocate
583 * Setup the MSI capability structure of the device with the requested
584 * number of interrupts. A return value of zero indicates the successful
585 * setup of an entry with the new MSI irq. A negative return value indicates
586 * an error, and a positive return value indicates the number of interrupts
587 * which could have been allocated.
589 static int msi_capability_init(struct pci_dev *dev, int nvec)
591 struct msi_desc *entry;
596 msi_set_enable(dev, 0); /* Disable MSI during set up */
598 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
599 /* MSI Entry Initialization */
600 entry = alloc_msi_entry(dev);
604 entry->msi_attrib.is_msix = 0;
605 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
606 entry->msi_attrib.entry_nr = 0;
607 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
608 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
609 entry->msi_attrib.pos = dev->msi_cap;
611 if (control & PCI_MSI_FLAGS_64BIT)
612 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
614 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
615 /* All MSIs are unmasked by default, Mask them all */
616 if (entry->msi_attrib.maskbit)
617 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
618 mask = msi_capable_mask(control);
619 msi_mask_irq(entry, mask, mask);
621 list_add_tail(&entry->list, &dev->msi_list);
623 /* Configure MSI capability structure */
624 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
626 msi_mask_irq(entry, mask, ~mask);
631 ret = populate_msi_sysfs(dev);
633 msi_mask_irq(entry, mask, ~mask);
638 /* Set MSI enabled bits */
639 pci_intx_for_msi(dev, 0);
640 msi_set_enable(dev, 1);
641 dev->msi_enabled = 1;
643 dev->irq = entry->irq;
647 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
649 resource_size_t phys_addr;
653 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
655 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
656 table_offset &= PCI_MSIX_TABLE_OFFSET;
657 phys_addr = pci_resource_start(dev, bir) + table_offset;
659 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
662 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
663 struct msix_entry *entries, int nvec)
665 struct msi_desc *entry;
668 for (i = 0; i < nvec; i++) {
669 entry = alloc_msi_entry(dev);
675 /* No enough memory. Don't try again */
679 entry->msi_attrib.is_msix = 1;
680 entry->msi_attrib.is_64 = 1;
681 entry->msi_attrib.entry_nr = entries[i].entry;
682 entry->msi_attrib.default_irq = dev->irq;
683 entry->msi_attrib.pos = dev->msix_cap;
684 entry->mask_base = base;
686 list_add_tail(&entry->list, &dev->msi_list);
692 static void msix_program_entries(struct pci_dev *dev,
693 struct msix_entry *entries)
695 struct msi_desc *entry;
698 list_for_each_entry(entry, &dev->msi_list, list) {
699 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
700 PCI_MSIX_ENTRY_VECTOR_CTRL;
702 entries[i].vector = entry->irq;
703 irq_set_msi_desc(entry->irq, entry);
704 entry->masked = readl(entry->mask_base + offset);
705 msix_mask_irq(entry, 1);
711 * msix_capability_init - configure device's MSI-X capability
712 * @dev: pointer to the pci_dev data structure of MSI-X device function
713 * @entries: pointer to an array of struct msix_entry entries
714 * @nvec: number of @entries
716 * Setup the MSI-X capability structure of device function with a
717 * single MSI-X irq. A return of zero indicates the successful setup of
718 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
720 static int msix_capability_init(struct pci_dev *dev,
721 struct msix_entry *entries, int nvec)
727 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
729 /* Ensure MSI-X is disabled while it is set up */
730 control &= ~PCI_MSIX_FLAGS_ENABLE;
731 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
733 /* Request & Map MSI-X table region */
734 base = msix_map_region(dev, msix_table_size(control));
738 ret = msix_setup_entries(dev, base, entries, nvec);
742 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
747 * Some devices require MSI-X to be enabled before we can touch the
748 * MSI-X registers. We need to mask all the vectors to prevent
749 * interrupts coming in before they're fully set up.
751 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
752 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
754 msix_program_entries(dev, entries);
756 ret = populate_msi_sysfs(dev);
762 /* Set MSI-X enabled bits and unmask the function */
763 pci_intx_for_msi(dev, 0);
764 dev->msix_enabled = 1;
766 control &= ~PCI_MSIX_FLAGS_MASKALL;
767 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
774 * If we had some success, report the number of irqs
775 * we succeeded in setting up.
777 struct msi_desc *entry;
780 list_for_each_entry(entry, &dev->msi_list, list) {
794 * pci_msi_check_device - check whether MSI may be enabled on a device
795 * @dev: pointer to the pci_dev data structure of MSI device function
796 * @nvec: how many MSIs have been requested ?
797 * @type: are we checking for MSI or MSI-X ?
799 * Look at global flags, the device itself, and its parent busses
800 * to determine if MSI/-X are supported for the device. If MSI/-X is
801 * supported return 0, else return an error code.
803 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
808 /* MSI must be globally enabled and supported by the device */
809 if (!pci_msi_enable || !dev || dev->no_msi)
813 * You can't ask to have 0 or less MSIs configured.
815 * b) the list manipulation code assumes nvec >= 1.
821 * Any bridge which does NOT route MSI transactions from its
822 * secondary bus to its primary bus must set NO_MSI flag on
823 * the secondary pci_bus.
824 * We expect only arch-specific PCI host bus controller driver
825 * or quirks for specific PCI bridges to be setting NO_MSI.
827 for (bus = dev->bus; bus; bus = bus->parent)
828 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
831 ret = arch_msi_check_device(dev, nvec, type);
839 * pci_enable_msi_block - configure device's MSI capability structure
840 * @dev: device to configure
841 * @nvec: number of interrupts to configure
843 * Allocate IRQs for a device with the MSI capability.
844 * This function returns a negative errno if an error occurs. If it
845 * is unable to allocate the number of interrupts requested, it returns
846 * the number of interrupts it might be able to allocate. If it successfully
847 * allocates at least the number of interrupts requested, it returns 0 and
848 * updates the @dev's irq member to the lowest new interrupt number; the
849 * other interrupt numbers allocated to this device are consecutive.
851 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
859 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
860 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
864 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
868 WARN_ON(!!dev->msi_enabled);
870 /* Check whether driver already requested MSI-X irqs */
871 if (dev->msix_enabled) {
872 dev_info(&dev->dev, "can't enable MSI "
873 "(MSI-X already enabled)\n");
877 status = msi_capability_init(dev, nvec);
880 EXPORT_SYMBOL(pci_enable_msi_block);
882 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
890 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
891 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
898 ret = pci_enable_msi_block(dev, nvec);
905 EXPORT_SYMBOL(pci_enable_msi_block_auto);
907 void pci_msi_shutdown(struct pci_dev *dev)
909 struct msi_desc *desc;
913 if (!pci_msi_enable || !dev || !dev->msi_enabled)
916 BUG_ON(list_empty(&dev->msi_list));
917 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
919 msi_set_enable(dev, 0);
920 pci_intx_for_msi(dev, 1);
921 dev->msi_enabled = 0;
923 /* Return the device with MSI unmasked as initial states */
924 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
925 mask = msi_capable_mask(ctrl);
926 /* Keep cached state to be restored */
927 __msi_mask_irq(desc, mask, ~mask);
929 /* Restore dev->irq to its default pin-assertion irq */
930 dev->irq = desc->msi_attrib.default_irq;
933 void pci_disable_msi(struct pci_dev *dev)
935 if (!pci_msi_enable || !dev || !dev->msi_enabled)
938 pci_msi_shutdown(dev);
940 kset_unregister(dev->msi_kset);
941 dev->msi_kset = NULL;
943 EXPORT_SYMBOL(pci_disable_msi);
946 * pci_msix_table_size - return the number of device's MSI-X table entries
947 * @dev: pointer to the pci_dev data structure of MSI-X device function
949 int pci_msix_table_size(struct pci_dev *dev)
956 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
957 return msix_table_size(control);
961 * pci_enable_msix - configure device's MSI-X capability structure
962 * @dev: pointer to the pci_dev data structure of MSI-X device function
963 * @entries: pointer to an array of MSI-X entries
964 * @nvec: number of MSI-X irqs requested for allocation by device driver
966 * Setup the MSI-X capability structure of device function with the number
967 * of requested irqs upon its software driver call to request for
968 * MSI-X mode enabled on its hardware device function. A return of zero
969 * indicates the successful configuration of MSI-X capability structure
970 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
971 * Or a return of > 0 indicates that driver request is exceeding the number
972 * of irqs or MSI-X vectors available. Driver should use the returned value to
973 * re-send its request.
975 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
977 int status, nr_entries;
980 if (!entries || !dev->msix_cap)
983 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
987 nr_entries = pci_msix_table_size(dev);
988 if (nvec > nr_entries)
991 /* Check for any invalid entries */
992 for (i = 0; i < nvec; i++) {
993 if (entries[i].entry >= nr_entries)
994 return -EINVAL; /* invalid entry */
995 for (j = i + 1; j < nvec; j++) {
996 if (entries[i].entry == entries[j].entry)
997 return -EINVAL; /* duplicate entry */
1000 WARN_ON(!!dev->msix_enabled);
1002 /* Check whether driver already requested for MSI irq */
1003 if (dev->msi_enabled) {
1004 dev_info(&dev->dev, "can't enable MSI-X "
1005 "(MSI IRQ already assigned)\n");
1008 status = msix_capability_init(dev, entries, nvec);
1011 EXPORT_SYMBOL(pci_enable_msix);
1013 void pci_msix_shutdown(struct pci_dev *dev)
1015 struct msi_desc *entry;
1017 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1020 /* Return the device with MSI-X masked as initial states */
1021 list_for_each_entry(entry, &dev->msi_list, list) {
1022 /* Keep cached states to be restored */
1023 __msix_mask_irq(entry, 1);
1026 msix_set_enable(dev, 0);
1027 pci_intx_for_msi(dev, 1);
1028 dev->msix_enabled = 0;
1031 void pci_disable_msix(struct pci_dev *dev)
1033 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1036 pci_msix_shutdown(dev);
1038 kset_unregister(dev->msi_kset);
1039 dev->msi_kset = NULL;
1041 EXPORT_SYMBOL(pci_disable_msix);
1044 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
1045 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1047 * Being called during hotplug remove, from which the device function
1048 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
1049 * allocated for this device function, are reclaimed to unused state,
1050 * which may be used later on.
1052 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1054 if (!pci_msi_enable || !dev)
1057 if (dev->msi_enabled || dev->msix_enabled)
1061 void pci_no_msi(void)
1067 * pci_msi_enabled - is MSI enabled?
1069 * Returns true if MSI has not been disabled by the command-line option
1072 int pci_msi_enabled(void)
1074 return pci_msi_enable;
1076 EXPORT_SYMBOL(pci_msi_enabled);
1078 void pci_msi_init_pci_dev(struct pci_dev *dev)
1080 INIT_LIST_HEAD(&dev->msi_list);
1082 /* Disable the msi hardware to avoid screaming interrupts
1083 * during boot. This is the power on reset default so
1084 * usually this should be a noop.
1086 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1088 msi_set_enable(dev, 0);
1090 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1092 msix_set_enable(dev, 0);