3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
20 #include <asm/errno.h>
27 static DEFINE_SPINLOCK(msi_lock);
28 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
29 static struct kmem_cache* msi_cachep;
31 static int pci_msi_enable = 1;
33 static int msi_cache_init(void)
35 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
36 0, SLAB_HWCACHE_ALIGN, NULL, NULL);
43 static void msi_set_mask_bit(unsigned int irq, int flag)
45 struct msi_desc *entry;
47 entry = msi_desc[irq];
48 BUG_ON(!entry || !entry->dev);
49 switch (entry->msi_attrib.type) {
51 if (entry->msi_attrib.maskbit) {
55 pos = (long)entry->mask_base;
56 pci_read_config_dword(entry->dev, pos, &mask_bits);
59 pci_write_config_dword(entry->dev, pos, mask_bits);
64 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
65 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
66 writel(flag, entry->mask_base + offset);
75 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
77 struct msi_desc *entry = get_irq_data(irq);
78 switch(entry->msi_attrib.type) {
81 struct pci_dev *dev = entry->dev;
82 int pos = entry->msi_attrib.pos;
85 pci_read_config_dword(dev, msi_lower_address_reg(pos),
87 if (entry->msi_attrib.is_64) {
88 pci_read_config_dword(dev, msi_upper_address_reg(pos),
90 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
93 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
101 base = entry->mask_base +
102 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
104 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
105 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
106 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
114 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
116 struct msi_desc *entry = get_irq_data(irq);
117 switch (entry->msi_attrib.type) {
120 struct pci_dev *dev = entry->dev;
121 int pos = entry->msi_attrib.pos;
123 pci_write_config_dword(dev, msi_lower_address_reg(pos),
125 if (entry->msi_attrib.is_64) {
126 pci_write_config_dword(dev, msi_upper_address_reg(pos),
128 pci_write_config_word(dev, msi_data_reg(pos, 1),
131 pci_write_config_word(dev, msi_data_reg(pos, 0),
136 case PCI_CAP_ID_MSIX:
139 base = entry->mask_base +
140 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
142 writel(msg->address_lo,
143 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
144 writel(msg->address_hi,
145 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
146 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
154 void mask_msi_irq(unsigned int irq)
156 msi_set_mask_bit(irq, 1);
159 void unmask_msi_irq(unsigned int irq)
161 msi_set_mask_bit(irq, 0);
164 static int msi_free_irq(struct pci_dev* dev, int irq);
166 static int msi_init(void)
168 static int status = -ENOMEM;
173 status = msi_cache_init();
176 printk(KERN_WARNING "PCI: MSI cache init failed\n");
183 static struct msi_desc* alloc_msi_entry(void)
185 struct msi_desc *entry;
187 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
191 entry->link.tail = entry->link.head = 0; /* single message */
197 static void attach_msi_entry(struct msi_desc *entry, int irq)
201 spin_lock_irqsave(&msi_lock, flags);
202 msi_desc[irq] = entry;
203 spin_unlock_irqrestore(&msi_lock, flags);
206 static int create_msi_irq(void)
208 struct msi_desc *entry;
211 entry = alloc_msi_entry();
217 kmem_cache_free(msi_cachep, entry);
221 set_irq_data(irq, entry);
226 static void destroy_msi_irq(unsigned int irq)
228 struct msi_desc *entry;
230 entry = get_irq_data(irq);
231 set_irq_chip(irq, NULL);
232 set_irq_data(irq, NULL);
234 kmem_cache_free(msi_cachep, entry);
237 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
241 pci_read_config_word(dev, msi_control_reg(pos), &control);
242 if (type == PCI_CAP_ID_MSI) {
243 /* Set enabled bits to single MSI & enable MSI_enable bit */
244 msi_enable(control, 1);
245 pci_write_config_word(dev, msi_control_reg(pos), control);
246 dev->msi_enabled = 1;
248 msix_enable(control);
249 pci_write_config_word(dev, msi_control_reg(pos), control);
250 dev->msix_enabled = 1;
253 pci_intx(dev, 0); /* disable intx */
256 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
260 pci_read_config_word(dev, msi_control_reg(pos), &control);
261 if (type == PCI_CAP_ID_MSI) {
262 /* Set enabled bits to single MSI & enable MSI_enable bit */
263 msi_disable(control);
264 pci_write_config_word(dev, msi_control_reg(pos), control);
265 dev->msi_enabled = 0;
267 msix_disable(control);
268 pci_write_config_word(dev, msi_control_reg(pos), control);
269 dev->msix_enabled = 0;
272 pci_intx(dev, 1); /* enable intx */
276 static int __pci_save_msi_state(struct pci_dev *dev)
280 struct pci_cap_saved_state *save_state;
283 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
284 if (pos <= 0 || dev->no_msi)
287 pci_read_config_word(dev, msi_control_reg(pos), &control);
288 if (!(control & PCI_MSI_FLAGS_ENABLE))
291 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
294 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
297 cap = &save_state->data[0];
299 pci_read_config_dword(dev, pos, &cap[i++]);
300 control = cap[0] >> 16;
301 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
302 if (control & PCI_MSI_FLAGS_64BIT) {
303 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
304 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
306 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
307 if (control & PCI_MSI_FLAGS_MASKBIT)
308 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
309 save_state->cap_nr = PCI_CAP_ID_MSI;
310 pci_add_saved_cap(dev, save_state);
314 static void __pci_restore_msi_state(struct pci_dev *dev)
318 struct pci_cap_saved_state *save_state;
321 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
322 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
323 if (!save_state || pos <= 0)
325 cap = &save_state->data[0];
327 control = cap[i++] >> 16;
328 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
329 if (control & PCI_MSI_FLAGS_64BIT) {
330 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
331 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
333 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
334 if (control & PCI_MSI_FLAGS_MASKBIT)
335 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
336 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
337 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
338 pci_remove_saved_cap(save_state);
342 static int __pci_save_msix_state(struct pci_dev *dev)
345 int irq, head, tail = 0;
347 struct pci_cap_saved_state *save_state;
349 if (!dev->msix_enabled)
352 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
353 if (pos <= 0 || dev->no_msi)
356 /* save the capability */
357 pci_read_config_word(dev, msi_control_reg(pos), &control);
358 if (!(control & PCI_MSIX_FLAGS_ENABLE))
360 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
363 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
366 *((u16 *)&save_state->data[0]) = control;
369 irq = head = dev->first_msi_irq;
370 while (head != tail) {
371 struct msi_desc *entry;
373 entry = msi_desc[irq];
374 read_msi_msg(irq, &entry->msg_save);
376 tail = msi_desc[irq]->link.tail;
380 save_state->cap_nr = PCI_CAP_ID_MSIX;
381 pci_add_saved_cap(dev, save_state);
385 int pci_save_msi_state(struct pci_dev *dev)
389 rc = __pci_save_msi_state(dev);
393 rc = __pci_save_msix_state(dev);
398 static void __pci_restore_msix_state(struct pci_dev *dev)
402 int irq, head, tail = 0;
403 struct msi_desc *entry;
404 struct pci_cap_saved_state *save_state;
406 if (!dev->msix_enabled)
409 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
412 save = *((u16 *)&save_state->data[0]);
413 pci_remove_saved_cap(save_state);
416 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
420 /* route the table */
421 irq = head = dev->first_msi_irq;
422 while (head != tail) {
423 entry = msi_desc[irq];
424 write_msi_msg(irq, &entry->msg_save);
426 tail = msi_desc[irq]->link.tail;
430 pci_write_config_word(dev, msi_control_reg(pos), save);
431 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
434 void pci_restore_msi_state(struct pci_dev *dev)
436 __pci_restore_msi_state(dev);
437 __pci_restore_msix_state(dev);
439 #endif /* CONFIG_PM */
442 * msi_capability_init - configure device's MSI capability structure
443 * @dev: pointer to the pci_dev data structure of MSI device function
445 * Setup the MSI capability structure of device function with a single
446 * MSI irq, regardless of device function is capable of handling
447 * multiple messages. A return of zero indicates the successful setup
448 * of an entry zero with the new MSI irq or non-zero for otherwise.
450 static int msi_capability_init(struct pci_dev *dev)
453 struct msi_desc *entry;
457 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
458 pci_read_config_word(dev, msi_control_reg(pos), &control);
459 /* MSI Entry Initialization */
460 irq = create_msi_irq();
464 entry = get_irq_data(irq);
465 entry->link.head = irq;
466 entry->link.tail = irq;
467 entry->msi_attrib.type = PCI_CAP_ID_MSI;
468 entry->msi_attrib.is_64 = is_64bit_address(control);
469 entry->msi_attrib.entry_nr = 0;
470 entry->msi_attrib.maskbit = is_mask_bit_support(control);
471 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
472 entry->msi_attrib.pos = pos;
473 if (is_mask_bit_support(control)) {
474 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
475 is_64bit_address(control));
478 if (entry->msi_attrib.maskbit) {
479 unsigned int maskbits, temp;
480 /* All MSIs are unmasked by default, Mask them all */
481 pci_read_config_dword(dev,
482 msi_mask_bits_reg(pos, is_64bit_address(control)),
484 temp = (1 << multi_msi_capable(control));
485 temp = ((temp - 1) & ~temp);
487 pci_write_config_dword(dev,
488 msi_mask_bits_reg(pos, is_64bit_address(control)),
491 /* Configure MSI capability structure */
492 status = arch_setup_msi_irq(irq, dev);
494 destroy_msi_irq(irq);
498 dev->first_msi_irq = irq;
499 attach_msi_entry(entry, irq);
500 /* Set MSI enabled bits */
501 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
508 * msix_capability_init - configure device's MSI-X capability
509 * @dev: pointer to the pci_dev data structure of MSI-X device function
510 * @entries: pointer to an array of struct msix_entry entries
511 * @nvec: number of @entries
513 * Setup the MSI-X capability structure of device function with a
514 * single MSI-X irq. A return of zero indicates the successful setup of
515 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
517 static int msix_capability_init(struct pci_dev *dev,
518 struct msix_entry *entries, int nvec)
520 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
522 int irq, pos, i, j, nr_entries, temp = 0;
523 unsigned long phys_addr;
529 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
530 /* Request & Map MSI-X table region */
531 pci_read_config_word(dev, msi_control_reg(pos), &control);
532 nr_entries = multi_msix_capable(control);
534 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
535 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
536 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
537 phys_addr = pci_resource_start (dev, bir) + table_offset;
538 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
542 /* MSI-X Table Initialization */
543 for (i = 0; i < nvec; i++) {
544 irq = create_msi_irq();
548 entry = get_irq_data(irq);
549 j = entries[i].entry;
550 entries[i].vector = irq;
551 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
552 entry->msi_attrib.is_64 = 1;
553 entry->msi_attrib.entry_nr = j;
554 entry->msi_attrib.maskbit = 1;
555 entry->msi_attrib.default_irq = dev->irq;
556 entry->msi_attrib.pos = pos;
558 entry->mask_base = base;
560 entry->link.head = irq;
561 entry->link.tail = irq;
564 entry->link.head = temp;
565 entry->link.tail = tail->link.tail;
566 tail->link.tail = irq;
567 head->link.head = irq;
571 /* Configure MSI-X capability structure */
572 status = arch_setup_msi_irq(irq, dev);
574 destroy_msi_irq(irq);
578 attach_msi_entry(entry, irq);
583 for (; i >= 0; i--) {
584 irq = (entries + i)->vector;
585 msi_free_irq(dev, irq);
586 (entries + i)->vector = 0;
588 /* If we had some success report the number of irqs
589 * we succeeded in setting up.
595 dev->first_msi_irq = entries[0].vector;
596 /* Set MSI-X enabled bits */
597 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
603 * pci_msi_supported - check whether MSI may be enabled on device
604 * @dev: pointer to the pci_dev data structure of MSI device function
606 * Look at global flags, the device itself, and its parent busses
607 * to return 0 if MSI are supported for the device.
610 int pci_msi_supported(struct pci_dev * dev)
614 /* MSI must be globally enabled and supported by the device */
615 if (!pci_msi_enable || !dev || dev->no_msi)
618 /* Any bridge which does NOT route MSI transactions from it's
619 * secondary bus to it's primary bus must set NO_MSI flag on
620 * the secondary pci_bus.
621 * We expect only arch-specific PCI host bus controller driver
622 * or quirks for specific PCI bridges to be setting NO_MSI.
624 for (bus = dev->bus; bus; bus = bus->parent)
625 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
632 * pci_enable_msi - configure device's MSI capability structure
633 * @dev: pointer to the pci_dev data structure of MSI device function
635 * Setup the MSI capability structure of device function with
636 * a single MSI irq upon its software driver call to request for
637 * MSI mode enabled on its hardware device function. A return of zero
638 * indicates the successful setup of an entry zero with the new MSI
639 * irq or non-zero for otherwise.
641 int pci_enable_msi(struct pci_dev* dev)
645 if (pci_msi_supported(dev) < 0)
652 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
656 WARN_ON(!!dev->msi_enabled);
658 /* Check whether driver already requested for MSI-X irqs */
659 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
660 if (pos > 0 && dev->msix_enabled) {
661 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
662 "Device already has MSI-X enabled\n",
666 status = msi_capability_init(dev);
670 void pci_disable_msi(struct pci_dev* dev)
672 struct msi_desc *entry;
673 int pos, default_irq;
682 if (!dev->msi_enabled)
685 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
689 pci_read_config_word(dev, msi_control_reg(pos), &control);
690 if (!(control & PCI_MSI_FLAGS_ENABLE))
694 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
696 spin_lock_irqsave(&msi_lock, flags);
697 entry = msi_desc[dev->first_msi_irq];
698 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
699 spin_unlock_irqrestore(&msi_lock, flags);
702 if (irq_has_action(dev->first_msi_irq)) {
703 spin_unlock_irqrestore(&msi_lock, flags);
704 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
705 "free_irq() on MSI irq %d\n",
706 pci_name(dev), dev->first_msi_irq);
707 BUG_ON(irq_has_action(dev->first_msi_irq));
709 default_irq = entry->msi_attrib.default_irq;
710 spin_unlock_irqrestore(&msi_lock, flags);
711 msi_free_irq(dev, dev->first_msi_irq);
713 /* Restore dev->irq to its default pin-assertion irq */
714 dev->irq = default_irq;
716 dev->first_msi_irq = 0;
719 static int msi_free_irq(struct pci_dev* dev, int irq)
721 struct msi_desc *entry;
722 int head, entry_nr, type;
726 arch_teardown_msi_irq(irq);
728 spin_lock_irqsave(&msi_lock, flags);
729 entry = msi_desc[irq];
730 if (!entry || entry->dev != dev) {
731 spin_unlock_irqrestore(&msi_lock, flags);
734 type = entry->msi_attrib.type;
735 entry_nr = entry->msi_attrib.entry_nr;
736 head = entry->link.head;
737 base = entry->mask_base;
738 msi_desc[entry->link.head]->link.tail = entry->link.tail;
739 msi_desc[entry->link.tail]->link.head = entry->link.head;
741 msi_desc[irq] = NULL;
742 spin_unlock_irqrestore(&msi_lock, flags);
744 destroy_msi_irq(irq);
746 if (type == PCI_CAP_ID_MSIX) {
747 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
748 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
758 * pci_enable_msix - configure device's MSI-X capability structure
759 * @dev: pointer to the pci_dev data structure of MSI-X device function
760 * @entries: pointer to an array of MSI-X entries
761 * @nvec: number of MSI-X irqs requested for allocation by device driver
763 * Setup the MSI-X capability structure of device function with the number
764 * of requested irqs upon its software driver call to request for
765 * MSI-X mode enabled on its hardware device function. A return of zero
766 * indicates the successful configuration of MSI-X capability structure
767 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
768 * Or a return of > 0 indicates that driver request is exceeding the number
769 * of irqs available. Driver should use the returned value to re-send
772 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
774 int status, pos, nr_entries;
778 if (!entries || pci_msi_supported(dev) < 0)
785 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
789 pci_read_config_word(dev, msi_control_reg(pos), &control);
790 nr_entries = multi_msix_capable(control);
791 if (nvec > nr_entries)
794 /* Check for any invalid entries */
795 for (i = 0; i < nvec; i++) {
796 if (entries[i].entry >= nr_entries)
797 return -EINVAL; /* invalid entry */
798 for (j = i + 1; j < nvec; j++) {
799 if (entries[i].entry == entries[j].entry)
800 return -EINVAL; /* duplicate entry */
803 WARN_ON(!!dev->msix_enabled);
805 /* Check whether driver already requested for MSI irq */
806 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
808 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
809 "Device already has an MSI irq assigned\n",
813 status = msix_capability_init(dev, entries, nvec);
817 void pci_disable_msix(struct pci_dev* dev)
819 int irq, head, tail = 0, warning = 0;
829 if (!dev->msix_enabled)
832 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
836 pci_read_config_word(dev, msi_control_reg(pos), &control);
837 if (!(control & PCI_MSIX_FLAGS_ENABLE))
840 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
842 irq = head = dev->first_msi_irq;
843 while (head != tail) {
844 spin_lock_irqsave(&msi_lock, flags);
845 tail = msi_desc[irq]->link.tail;
846 spin_unlock_irqrestore(&msi_lock, flags);
847 if (irq_has_action(irq))
849 else if (irq != head) /* Release MSI-X irq */
850 msi_free_irq(dev, irq);
853 msi_free_irq(dev, irq);
855 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
856 "free_irq() on all MSI-X irqs\n",
860 dev->first_msi_irq = 0;
864 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
865 * @dev: pointer to the pci_dev data structure of MSI(X) device function
867 * Being called during hotplug remove, from which the device function
868 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
869 * allocated for this device function, are reclaimed to unused state,
870 * which may be used later on.
872 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
877 if (!pci_msi_enable || !dev)
880 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
881 if (pos > 0 && dev->msi_enabled) {
882 if (irq_has_action(dev->first_msi_irq)) {
883 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
884 "called without free_irq() on MSI irq %d\n",
885 pci_name(dev), dev->first_msi_irq);
886 BUG_ON(irq_has_action(dev->first_msi_irq));
887 } else /* Release MSI irq assigned to this device */
888 msi_free_irq(dev, dev->first_msi_irq);
890 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
891 if (pos > 0 && dev->msix_enabled) {
892 int irq, head, tail = 0, warning = 0;
893 void __iomem *base = NULL;
895 irq = head = dev->first_msi_irq;
896 while (head != tail) {
897 spin_lock_irqsave(&msi_lock, flags);
898 tail = msi_desc[irq]->link.tail;
899 base = msi_desc[irq]->mask_base;
900 spin_unlock_irqrestore(&msi_lock, flags);
901 if (irq_has_action(irq))
903 else if (irq != head) /* Release MSI-X irq */
904 msi_free_irq(dev, irq);
907 msi_free_irq(dev, irq);
910 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
911 "called without free_irq() on all MSI-X irqs\n",
918 void pci_no_msi(void)
923 EXPORT_SYMBOL(pci_enable_msi);
924 EXPORT_SYMBOL(pci_disable_msi);
925 EXPORT_SYMBOL(pci_enable_msix);
926 EXPORT_SYMBOL(pci_disable_msix);