3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
20 #include <asm/errno.h>
26 static int pci_msi_enable = 1;
30 #ifndef arch_msi_check_device
31 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
37 #ifndef arch_setup_msi_irqs
38 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
40 struct msi_desc *entry;
44 * If an architecture wants to support multiple MSI, it needs to
45 * override arch_setup_msi_irqs()
47 if (type == PCI_CAP_ID_MSI && nvec > 1)
50 list_for_each_entry(entry, &dev->msi_list, list) {
51 ret = arch_setup_msi_irq(dev, entry);
62 #ifndef arch_teardown_msi_irqs
63 void arch_teardown_msi_irqs(struct pci_dev *dev)
65 struct msi_desc *entry;
67 list_for_each_entry(entry, &dev->msi_list, list) {
71 nvec = 1 << entry->msi_attrib.multiple;
72 for (i = 0; i < nvec; i++)
73 arch_teardown_msi_irq(entry->irq + i);
78 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
84 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
85 control &= ~PCI_MSI_FLAGS_ENABLE;
87 control |= PCI_MSI_FLAGS_ENABLE;
88 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
91 static void msix_set_enable(struct pci_dev *dev, int enable)
96 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
98 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
99 control &= ~PCI_MSIX_FLAGS_ENABLE;
101 control |= PCI_MSIX_FLAGS_ENABLE;
102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
106 static inline __attribute_const__ u32 msi_mask(unsigned x)
108 /* Don't shift by >= width of type */
111 return (1 << (1 << x)) - 1;
114 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
116 return msi_mask((control >> 1) & 7);
119 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
121 return msi_mask((control >> 4) & 7);
125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
126 * mask all MSI interrupts by clearing the MSI enable bit does not work
127 * reliably as devices without an INTx disable bit will then generate a
128 * level IRQ which will never be cleared.
130 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
132 u32 mask_bits = desc->masked;
134 if (!desc->msi_attrib.maskbit)
139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
140 desc->masked = mask_bits;
144 * This internal function does not flush PCI writes to the device.
145 * All users must ensure that they read from the device before either
146 * assuming that the device state is up to date, or returning out of this
147 * file. This saves a few milliseconds when initialising devices with lots
148 * of MSI-X interrupts.
150 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
152 u32 mask_bits = desc->masked;
153 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
154 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
157 writel(mask_bits, desc->mask_base + offset);
158 desc->masked = mask_bits;
161 static void msi_set_mask_bit(unsigned irq, u32 flag)
163 struct msi_desc *desc = get_irq_msi(irq);
165 if (desc->msi_attrib.is_msix) {
166 msix_mask_irq(desc, flag);
167 readl(desc->mask_base); /* Flush write to device */
169 unsigned offset = irq - desc->dev->irq;
170 msi_mask_irq(desc, 1 << offset, flag << offset);
174 void mask_msi_irq(unsigned int irq)
176 msi_set_mask_bit(irq, 1);
179 void unmask_msi_irq(unsigned int irq)
181 msi_set_mask_bit(irq, 0);
184 void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
186 struct msi_desc *entry = get_irq_desc_msi(desc);
187 if (entry->msi_attrib.is_msix) {
188 void __iomem *base = entry->mask_base +
189 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
191 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
192 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
193 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
195 struct pci_dev *dev = entry->dev;
196 int pos = entry->msi_attrib.pos;
199 pci_read_config_dword(dev, msi_lower_address_reg(pos),
201 if (entry->msi_attrib.is_64) {
202 pci_read_config_dword(dev, msi_upper_address_reg(pos),
204 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
207 pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
213 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
215 struct irq_desc *desc = irq_to_desc(irq);
217 read_msi_msg_desc(desc, msg);
220 void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
222 struct msi_desc *entry = get_irq_desc_msi(desc);
223 if (entry->msi_attrib.is_msix) {
225 base = entry->mask_base +
226 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
228 writel(msg->address_lo,
229 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
230 writel(msg->address_hi,
231 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
232 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
234 struct pci_dev *dev = entry->dev;
235 int pos = entry->msi_attrib.pos;
238 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
239 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
240 msgctl |= entry->msi_attrib.multiple << 4;
241 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
243 pci_write_config_dword(dev, msi_lower_address_reg(pos),
245 if (entry->msi_attrib.is_64) {
246 pci_write_config_dword(dev, msi_upper_address_reg(pos),
248 pci_write_config_word(dev, msi_data_reg(pos, 1),
251 pci_write_config_word(dev, msi_data_reg(pos, 0),
258 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
260 struct irq_desc *desc = irq_to_desc(irq);
262 write_msi_msg_desc(desc, msg);
265 static int msi_free_irqs(struct pci_dev* dev);
267 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
269 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
273 INIT_LIST_HEAD(&desc->list);
279 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
281 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
282 pci_intx(dev, enable);
285 static void __pci_restore_msi_state(struct pci_dev *dev)
289 struct msi_desc *entry;
291 if (!dev->msi_enabled)
294 entry = get_irq_msi(dev->irq);
295 pos = entry->msi_attrib.pos;
297 pci_intx_for_msi(dev, 0);
298 msi_set_enable(dev, pos, 0);
299 write_msi_msg(dev->irq, &entry->msg);
301 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
302 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
303 control &= ~PCI_MSI_FLAGS_QSIZE;
304 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
305 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
308 static void __pci_restore_msix_state(struct pci_dev *dev)
311 struct msi_desc *entry;
314 if (!dev->msix_enabled)
316 BUG_ON(list_empty(&dev->msi_list));
317 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
318 pos = entry->msi_attrib.pos;
319 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
321 /* route the table */
322 pci_intx_for_msi(dev, 0);
323 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
324 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
326 list_for_each_entry(entry, &dev->msi_list, list) {
327 write_msi_msg(entry->irq, &entry->msg);
328 msix_mask_irq(entry, entry->masked);
331 control &= ~PCI_MSIX_FLAGS_MASKALL;
332 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
335 void pci_restore_msi_state(struct pci_dev *dev)
337 __pci_restore_msi_state(dev);
338 __pci_restore_msix_state(dev);
340 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
343 * msi_capability_init - configure device's MSI capability structure
344 * @dev: pointer to the pci_dev data structure of MSI device function
345 * @nvec: number of interrupts to allocate
347 * Setup the MSI capability structure of the device with the requested
348 * number of interrupts. A return value of zero indicates the successful
349 * setup of an entry with the new MSI irq. A negative return value indicates
350 * an error, and a positive return value indicates the number of interrupts
351 * which could have been allocated.
353 static int msi_capability_init(struct pci_dev *dev, int nvec)
355 struct msi_desc *entry;
360 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
361 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
363 pci_read_config_word(dev, msi_control_reg(pos), &control);
364 /* MSI Entry Initialization */
365 entry = alloc_msi_entry(dev);
369 entry->msi_attrib.is_msix = 0;
370 entry->msi_attrib.is_64 = is_64bit_address(control);
371 entry->msi_attrib.entry_nr = 0;
372 entry->msi_attrib.maskbit = is_mask_bit_support(control);
373 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
374 entry->msi_attrib.pos = pos;
376 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
377 /* All MSIs are unmasked by default, Mask them all */
378 if (entry->msi_attrib.maskbit)
379 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
380 mask = msi_capable_mask(control);
381 msi_mask_irq(entry, mask, mask);
383 list_add_tail(&entry->list, &dev->msi_list);
385 /* Configure MSI capability structure */
386 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
392 /* Set MSI enabled bits */
393 pci_intx_for_msi(dev, 0);
394 msi_set_enable(dev, pos, 1);
395 dev->msi_enabled = 1;
397 dev->irq = entry->irq;
402 * msix_capability_init - configure device's MSI-X capability
403 * @dev: pointer to the pci_dev data structure of MSI-X device function
404 * @entries: pointer to an array of struct msix_entry entries
405 * @nvec: number of @entries
407 * Setup the MSI-X capability structure of device function with a
408 * single MSI-X irq. A return of zero indicates the successful setup of
409 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
411 static int msix_capability_init(struct pci_dev *dev,
412 struct msix_entry *entries, int nvec)
414 struct msi_desc *entry;
415 int pos, i, j, nr_entries, ret;
416 unsigned long phys_addr;
422 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
423 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
425 /* Ensure MSI-X is disabled while it is set up */
426 control &= ~PCI_MSIX_FLAGS_ENABLE;
427 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
429 /* Request & Map MSI-X table region */
430 nr_entries = multi_msix_capable(control);
432 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
433 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
434 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
435 phys_addr = pci_resource_start (dev, bir) + table_offset;
436 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
440 for (i = 0; i < nvec; i++) {
441 entry = alloc_msi_entry(dev);
447 /* No enough memory. Don't try again */
451 j = entries[i].entry;
452 entry->msi_attrib.is_msix = 1;
453 entry->msi_attrib.is_64 = 1;
454 entry->msi_attrib.entry_nr = j;
455 entry->msi_attrib.default_irq = dev->irq;
456 entry->msi_attrib.pos = pos;
457 entry->mask_base = base;
459 list_add_tail(&entry->list, &dev->msi_list);
462 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
464 /* If we had some success report the number of irqs
465 * we succeeded in setting up. */
467 list_for_each_entry(entry, &dev->msi_list, list) {
468 if (entry->irq != 0) {
483 * Some devices require MSI-X to be enabled before we can touch the
484 * MSI-X registers. We need to mask all the vectors to prevent
485 * interrupts coming in before they're fully set up.
487 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
488 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
491 list_for_each_entry(entry, &dev->msi_list, list) {
492 entries[i].vector = entry->irq;
493 set_irq_msi(entry->irq, entry);
494 j = entries[i].entry;
495 entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
496 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
497 msix_mask_irq(entry, 1);
501 /* Set MSI-X enabled bits and unmask the function */
502 pci_intx_for_msi(dev, 0);
503 dev->msix_enabled = 1;
505 control &= ~PCI_MSIX_FLAGS_MASKALL;
506 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
512 * pci_msi_check_device - check whether MSI may be enabled on a device
513 * @dev: pointer to the pci_dev data structure of MSI device function
514 * @nvec: how many MSIs have been requested ?
515 * @type: are we checking for MSI or MSI-X ?
517 * Look at global flags, the device itself, and its parent busses
518 * to determine if MSI/-X are supported for the device. If MSI/-X is
519 * supported return 0, else return an error code.
521 static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type)
526 /* MSI must be globally enabled and supported by the device */
527 if (!pci_msi_enable || !dev || dev->no_msi)
531 * You can't ask to have 0 or less MSIs configured.
533 * b) the list manipulation code assumes nvec >= 1.
538 /* Any bridge which does NOT route MSI transactions from it's
539 * secondary bus to it's primary bus must set NO_MSI flag on
540 * the secondary pci_bus.
541 * We expect only arch-specific PCI host bus controller driver
542 * or quirks for specific PCI bridges to be setting NO_MSI.
544 for (bus = dev->bus; bus; bus = bus->parent)
545 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
548 ret = arch_msi_check_device(dev, nvec, type);
552 if (!pci_find_capability(dev, type))
559 * pci_enable_msi_block - configure device's MSI capability structure
560 * @dev: device to configure
561 * @nvec: number of interrupts to configure
563 * Allocate IRQs for a device with the MSI capability.
564 * This function returns a negative errno if an error occurs. If it
565 * is unable to allocate the number of interrupts requested, it returns
566 * the number of interrupts it might be able to allocate. If it successfully
567 * allocates at least the number of interrupts requested, it returns 0 and
568 * updates the @dev's irq member to the lowest new interrupt number; the
569 * other interrupt numbers allocated to this device are consecutive.
571 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
573 int status, pos, maxvec;
576 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
579 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
580 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
584 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
588 WARN_ON(!!dev->msi_enabled);
590 /* Check whether driver already requested MSI-X irqs */
591 if (dev->msix_enabled) {
592 dev_info(&dev->dev, "can't enable MSI "
593 "(MSI-X already enabled)\n");
597 status = msi_capability_init(dev, nvec);
600 EXPORT_SYMBOL(pci_enable_msi_block);
602 void pci_msi_shutdown(struct pci_dev *dev)
604 struct msi_desc *desc;
609 if (!pci_msi_enable || !dev || !dev->msi_enabled)
612 BUG_ON(list_empty(&dev->msi_list));
613 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
614 pos = desc->msi_attrib.pos;
616 msi_set_enable(dev, pos, 0);
617 pci_intx_for_msi(dev, 1);
618 dev->msi_enabled = 0;
620 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
621 mask = msi_capable_mask(ctrl);
622 msi_mask_irq(desc, mask, ~mask);
624 /* Restore dev->irq to its default pin-assertion irq */
625 dev->irq = desc->msi_attrib.default_irq;
628 void pci_disable_msi(struct pci_dev* dev)
630 struct msi_desc *entry;
632 if (!pci_msi_enable || !dev || !dev->msi_enabled)
635 pci_msi_shutdown(dev);
637 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
638 if (entry->msi_attrib.is_msix)
643 EXPORT_SYMBOL(pci_disable_msi);
645 static int msi_free_irqs(struct pci_dev* dev)
647 struct msi_desc *entry, *tmp;
649 list_for_each_entry(entry, &dev->msi_list, list) {
653 nvec = 1 << entry->msi_attrib.multiple;
654 for (i = 0; i < nvec; i++)
655 BUG_ON(irq_has_action(entry->irq + i));
658 arch_teardown_msi_irqs(dev);
660 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
661 if (entry->msi_attrib.is_msix) {
662 msix_mask_irq(entry, 1);
663 if (list_is_last(&entry->list, &dev->msi_list))
664 iounmap(entry->mask_base);
666 list_del(&entry->list);
674 * pci_msix_table_size - return the number of device's MSI-X table entries
675 * @dev: pointer to the pci_dev data structure of MSI-X device function
677 int pci_msix_table_size(struct pci_dev *dev)
682 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
686 pci_read_config_word(dev, msi_control_reg(pos), &control);
687 return multi_msix_capable(control);
691 * pci_enable_msix - configure device's MSI-X capability structure
692 * @dev: pointer to the pci_dev data structure of MSI-X device function
693 * @entries: pointer to an array of MSI-X entries
694 * @nvec: number of MSI-X irqs requested for allocation by device driver
696 * Setup the MSI-X capability structure of device function with the number
697 * of requested irqs upon its software driver call to request for
698 * MSI-X mode enabled on its hardware device function. A return of zero
699 * indicates the successful configuration of MSI-X capability structure
700 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
701 * Or a return of > 0 indicates that driver request is exceeding the number
702 * of irqs or MSI-X vectors available. Driver should use the returned value to
703 * re-send its request.
705 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
707 int status, nr_entries;
713 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
717 nr_entries = pci_msix_table_size(dev);
718 if (nvec > nr_entries)
721 /* Check for any invalid entries */
722 for (i = 0; i < nvec; i++) {
723 if (entries[i].entry >= nr_entries)
724 return -EINVAL; /* invalid entry */
725 for (j = i + 1; j < nvec; j++) {
726 if (entries[i].entry == entries[j].entry)
727 return -EINVAL; /* duplicate entry */
730 WARN_ON(!!dev->msix_enabled);
732 /* Check whether driver already requested for MSI irq */
733 if (dev->msi_enabled) {
734 dev_info(&dev->dev, "can't enable MSI-X "
735 "(MSI IRQ already assigned)\n");
738 status = msix_capability_init(dev, entries, nvec);
741 EXPORT_SYMBOL(pci_enable_msix);
743 static void msix_free_all_irqs(struct pci_dev *dev)
748 void pci_msix_shutdown(struct pci_dev* dev)
750 if (!pci_msi_enable || !dev || !dev->msix_enabled)
753 msix_set_enable(dev, 0);
754 pci_intx_for_msi(dev, 1);
755 dev->msix_enabled = 0;
757 void pci_disable_msix(struct pci_dev* dev)
759 if (!pci_msi_enable || !dev || !dev->msix_enabled)
762 pci_msix_shutdown(dev);
764 msix_free_all_irqs(dev);
766 EXPORT_SYMBOL(pci_disable_msix);
769 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
770 * @dev: pointer to the pci_dev data structure of MSI(X) device function
772 * Being called during hotplug remove, from which the device function
773 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
774 * allocated for this device function, are reclaimed to unused state,
775 * which may be used later on.
777 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
779 if (!pci_msi_enable || !dev)
782 if (dev->msi_enabled)
785 if (dev->msix_enabled)
786 msix_free_all_irqs(dev);
789 void pci_no_msi(void)
795 * pci_msi_enabled - is MSI enabled?
797 * Returns true if MSI has not been disabled by the command-line option
800 int pci_msi_enabled(void)
802 return pci_msi_enable;
804 EXPORT_SYMBOL(pci_msi_enabled);
806 void pci_msi_init_pci_dev(struct pci_dev *dev)
808 INIT_LIST_HEAD(&dev->msi_list);