3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/irqdomain.h>
23 #include <linux/of_irq.h>
27 static int pci_msi_enable = 1;
28 int pci_msi_ignore_mask;
30 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
32 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
33 static struct irq_domain *pci_msi_default_domain;
34 static DEFINE_MUTEX(pci_msi_domain_lock);
36 struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
38 return pci_msi_default_domain;
41 static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
43 struct irq_domain *domain;
45 domain = dev_get_msi_domain(&dev->dev);
49 return arch_get_pci_msi_domain(dev);
52 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
54 struct irq_domain *domain;
56 domain = pci_msi_get_domain(dev);
58 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
60 return arch_setup_msi_irqs(dev, nvec, type);
63 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
65 struct irq_domain *domain;
67 domain = pci_msi_get_domain(dev);
69 pci_msi_domain_free_irqs(domain, dev);
71 arch_teardown_msi_irqs(dev);
74 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
75 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
80 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
82 struct msi_controller *chip = dev->bus->msi;
85 if (!chip || !chip->setup_irq)
88 err = chip->setup_irq(chip, dev, desc);
92 irq_set_chip_data(desc->irq, chip);
97 void __weak arch_teardown_msi_irq(unsigned int irq)
99 struct msi_controller *chip = irq_get_chip_data(irq);
101 if (!chip || !chip->teardown_irq)
104 chip->teardown_irq(chip, irq);
107 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
109 struct msi_desc *entry;
113 * If an architecture wants to support multiple MSI, it needs to
114 * override arch_setup_msi_irqs()
116 if (type == PCI_CAP_ID_MSI && nvec > 1)
119 for_each_pci_msi_entry(entry, dev) {
120 ret = arch_setup_msi_irq(dev, entry);
131 * We have a default implementation available as a separate non-weak
132 * function, as it is used by the Xen x86 PCI code
134 void default_teardown_msi_irqs(struct pci_dev *dev)
137 struct msi_desc *entry;
139 for_each_pci_msi_entry(entry, dev)
141 for (i = 0; i < entry->nvec_used; i++)
142 arch_teardown_msi_irq(entry->irq + i);
145 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
147 return default_teardown_msi_irqs(dev);
150 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
152 struct msi_desc *entry;
155 if (dev->msix_enabled) {
156 for_each_pci_msi_entry(entry, dev) {
157 if (irq == entry->irq)
160 } else if (dev->msi_enabled) {
161 entry = irq_get_msi_desc(irq);
165 __pci_write_msi_msg(entry, &entry->msg);
168 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
170 return default_restore_msi_irqs(dev);
173 static inline __attribute_const__ u32 msi_mask(unsigned x)
175 /* Don't shift by >= width of type */
178 return (1 << (1 << x)) - 1;
182 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
183 * mask all MSI interrupts by clearing the MSI enable bit does not work
184 * reliably as devices without an INTx disable bit will then generate a
185 * level IRQ which will never be cleared.
187 u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
189 u32 mask_bits = desc->masked;
191 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
196 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
202 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
204 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
208 * This internal function does not flush PCI writes to the device.
209 * All users must ensure that they read from the device before either
210 * assuming that the device state is up to date, or returning out of this
211 * file. This saves a few milliseconds when initialising devices with lots
212 * of MSI-X interrupts.
214 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
216 u32 mask_bits = desc->masked;
217 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
218 PCI_MSIX_ENTRY_VECTOR_CTRL;
220 if (pci_msi_ignore_mask)
223 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
225 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
226 writel(mask_bits, desc->mask_base + offset);
231 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
233 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
236 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
238 struct msi_desc *desc = irq_data_get_msi_desc(data);
240 if (desc->msi_attrib.is_msix) {
241 msix_mask_irq(desc, flag);
242 readl(desc->mask_base); /* Flush write to device */
244 unsigned offset = data->irq - desc->irq;
245 msi_mask_irq(desc, 1 << offset, flag << offset);
250 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
251 * @data: pointer to irqdata associated to that interrupt
253 void pci_msi_mask_irq(struct irq_data *data)
255 msi_set_mask_bit(data, 1);
259 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
260 * @data: pointer to irqdata associated to that interrupt
262 void pci_msi_unmask_irq(struct irq_data *data)
264 msi_set_mask_bit(data, 0);
267 void default_restore_msi_irqs(struct pci_dev *dev)
269 struct msi_desc *entry;
271 for_each_pci_msi_entry(entry, dev)
272 default_restore_msi_irq(dev, entry->irq);
275 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
277 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
279 BUG_ON(dev->current_state != PCI_D0);
281 if (entry->msi_attrib.is_msix) {
282 void __iomem *base = entry->mask_base +
283 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
285 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
286 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
287 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
289 int pos = dev->msi_cap;
292 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
294 if (entry->msi_attrib.is_64) {
295 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
297 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
300 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
306 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
308 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
310 if (dev->current_state != PCI_D0) {
311 /* Don't touch the hardware now */
312 } else if (entry->msi_attrib.is_msix) {
314 base = entry->mask_base +
315 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
317 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
318 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
319 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
321 int pos = dev->msi_cap;
324 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
325 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
326 msgctl |= entry->msi_attrib.multiple << 4;
327 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
329 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
331 if (entry->msi_attrib.is_64) {
332 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
334 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
337 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
344 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
346 struct msi_desc *entry = irq_get_msi_desc(irq);
348 __pci_write_msi_msg(entry, msg);
350 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
352 static void free_msi_irqs(struct pci_dev *dev)
354 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
355 struct msi_desc *entry, *tmp;
356 struct attribute **msi_attrs;
357 struct device_attribute *dev_attr;
360 for_each_pci_msi_entry(entry, dev)
362 for (i = 0; i < entry->nvec_used; i++)
363 BUG_ON(irq_has_action(entry->irq + i));
365 pci_msi_teardown_msi_irqs(dev);
367 list_for_each_entry_safe(entry, tmp, msi_list, list) {
368 if (entry->msi_attrib.is_msix) {
369 if (list_is_last(&entry->list, msi_list))
370 iounmap(entry->mask_base);
373 list_del(&entry->list);
377 if (dev->msi_irq_groups) {
378 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
379 msi_attrs = dev->msi_irq_groups[0]->attrs;
380 while (msi_attrs[count]) {
381 dev_attr = container_of(msi_attrs[count],
382 struct device_attribute, attr);
383 kfree(dev_attr->attr.name);
388 kfree(dev->msi_irq_groups[0]);
389 kfree(dev->msi_irq_groups);
390 dev->msi_irq_groups = NULL;
394 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
396 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
397 pci_intx(dev, enable);
400 static void __pci_restore_msi_state(struct pci_dev *dev)
403 struct msi_desc *entry;
405 if (!dev->msi_enabled)
408 entry = irq_get_msi_desc(dev->irq);
410 pci_intx_for_msi(dev, 0);
411 pci_msi_set_enable(dev, 0);
412 arch_restore_msi_irqs(dev);
414 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
415 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
417 control &= ~PCI_MSI_FLAGS_QSIZE;
418 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
419 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
422 static void __pci_restore_msix_state(struct pci_dev *dev)
424 struct msi_desc *entry;
426 if (!dev->msix_enabled)
428 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
430 /* route the table */
431 pci_intx_for_msi(dev, 0);
432 pci_msix_clear_and_set_ctrl(dev, 0,
433 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
435 arch_restore_msi_irqs(dev);
436 for_each_pci_msi_entry(entry, dev)
437 msix_mask_irq(entry, entry->masked);
439 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
442 void pci_restore_msi_state(struct pci_dev *dev)
444 __pci_restore_msi_state(dev);
445 __pci_restore_msix_state(dev);
447 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
449 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
452 struct msi_desc *entry;
456 retval = kstrtoul(attr->attr.name, 10, &irq);
460 entry = irq_get_msi_desc(irq);
462 return sprintf(buf, "%s\n",
463 entry->msi_attrib.is_msix ? "msix" : "msi");
468 static int populate_msi_sysfs(struct pci_dev *pdev)
470 struct attribute **msi_attrs;
471 struct attribute *msi_attr;
472 struct device_attribute *msi_dev_attr;
473 struct attribute_group *msi_irq_group;
474 const struct attribute_group **msi_irq_groups;
475 struct msi_desc *entry;
480 /* Determine how many msi entries we have */
481 for_each_pci_msi_entry(entry, pdev)
486 /* Dynamically create the MSI attributes for the PCI device */
487 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
490 for_each_pci_msi_entry(entry, pdev) {
491 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
494 msi_attrs[count] = &msi_dev_attr->attr;
496 sysfs_attr_init(&msi_dev_attr->attr);
497 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
499 if (!msi_dev_attr->attr.name)
501 msi_dev_attr->attr.mode = S_IRUGO;
502 msi_dev_attr->show = msi_mode_show;
506 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
509 msi_irq_group->name = "msi_irqs";
510 msi_irq_group->attrs = msi_attrs;
512 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
514 goto error_irq_group;
515 msi_irq_groups[0] = msi_irq_group;
517 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
519 goto error_irq_groups;
520 pdev->msi_irq_groups = msi_irq_groups;
525 kfree(msi_irq_groups);
527 kfree(msi_irq_group);
530 msi_attr = msi_attrs[count];
532 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
533 kfree(msi_attr->name);
536 msi_attr = msi_attrs[count];
542 static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
545 struct msi_desc *entry;
547 /* MSI Entry Initialization */
548 entry = alloc_msi_entry(&dev->dev);
552 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
554 entry->msi_attrib.is_msix = 0;
555 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
556 entry->msi_attrib.entry_nr = 0;
557 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
558 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
559 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
560 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
561 entry->nvec_used = nvec;
563 if (control & PCI_MSI_FLAGS_64BIT)
564 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
566 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
568 /* Save the initial mask status */
569 if (entry->msi_attrib.maskbit)
570 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
575 static int msi_verify_entries(struct pci_dev *dev)
577 struct msi_desc *entry;
579 for_each_pci_msi_entry(entry, dev) {
580 if (!dev->no_64bit_msi || !entry->msg.address_hi)
582 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
583 " tried to assign one above 4G\n");
590 * msi_capability_init - configure device's MSI capability structure
591 * @dev: pointer to the pci_dev data structure of MSI device function
592 * @nvec: number of interrupts to allocate
594 * Setup the MSI capability structure of the device with the requested
595 * number of interrupts. A return value of zero indicates the successful
596 * setup of an entry with the new MSI irq. A negative return value indicates
597 * an error, and a positive return value indicates the number of interrupts
598 * which could have been allocated.
600 static int msi_capability_init(struct pci_dev *dev, int nvec)
602 struct msi_desc *entry;
606 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
608 entry = msi_setup_entry(dev, nvec);
612 /* All MSIs are unmasked by default, Mask them all */
613 mask = msi_mask(entry->msi_attrib.multi_cap);
614 msi_mask_irq(entry, mask, mask);
616 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
618 /* Configure MSI capability structure */
619 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
621 msi_mask_irq(entry, mask, ~mask);
626 ret = msi_verify_entries(dev);
628 msi_mask_irq(entry, mask, ~mask);
633 ret = populate_msi_sysfs(dev);
635 msi_mask_irq(entry, mask, ~mask);
640 /* Set MSI enabled bits */
641 pci_intx_for_msi(dev, 0);
642 pci_msi_set_enable(dev, 1);
643 dev->msi_enabled = 1;
645 pcibios_free_irq(dev);
646 dev->irq = entry->irq;
650 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
652 resource_size_t phys_addr;
657 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
659 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
660 flags = pci_resource_flags(dev, bir);
661 if (!flags || (flags & IORESOURCE_UNSET))
664 table_offset &= PCI_MSIX_TABLE_OFFSET;
665 phys_addr = pci_resource_start(dev, bir) + table_offset;
667 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
670 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
671 struct msix_entry *entries, int nvec)
673 struct msi_desc *entry;
676 for (i = 0; i < nvec; i++) {
677 entry = alloc_msi_entry(&dev->dev);
683 /* No enough memory. Don't try again */
687 entry->msi_attrib.is_msix = 1;
688 entry->msi_attrib.is_64 = 1;
689 entry->msi_attrib.entry_nr = entries[i].entry;
690 entry->msi_attrib.default_irq = dev->irq;
691 entry->mask_base = base;
692 entry->nvec_used = 1;
694 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
700 static void msix_program_entries(struct pci_dev *dev,
701 struct msix_entry *entries)
703 struct msi_desc *entry;
706 for_each_pci_msi_entry(entry, dev) {
707 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
708 PCI_MSIX_ENTRY_VECTOR_CTRL;
710 entries[i].vector = entry->irq;
711 entry->masked = readl(entry->mask_base + offset);
712 msix_mask_irq(entry, 1);
718 * msix_capability_init - configure device's MSI-X capability
719 * @dev: pointer to the pci_dev data structure of MSI-X device function
720 * @entries: pointer to an array of struct msix_entry entries
721 * @nvec: number of @entries
723 * Setup the MSI-X capability structure of device function with a
724 * single MSI-X irq. A return of zero indicates the successful setup of
725 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
727 static int msix_capability_init(struct pci_dev *dev,
728 struct msix_entry *entries, int nvec)
734 /* Ensure MSI-X is disabled while it is set up */
735 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
737 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
738 /* Request & Map MSI-X table region */
739 base = msix_map_region(dev, msix_table_size(control));
743 ret = msix_setup_entries(dev, base, entries, nvec);
747 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
751 /* Check if all MSI entries honor device restrictions */
752 ret = msi_verify_entries(dev);
757 * Some devices require MSI-X to be enabled before we can touch the
758 * MSI-X registers. We need to mask all the vectors to prevent
759 * interrupts coming in before they're fully set up.
761 pci_msix_clear_and_set_ctrl(dev, 0,
762 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
764 msix_program_entries(dev, entries);
766 ret = populate_msi_sysfs(dev);
770 /* Set MSI-X enabled bits and unmask the function */
771 pci_intx_for_msi(dev, 0);
772 dev->msix_enabled = 1;
773 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
775 pcibios_free_irq(dev);
781 * If we had some success, report the number of irqs
782 * we succeeded in setting up.
784 struct msi_desc *entry;
787 for_each_pci_msi_entry(entry, dev) {
802 * pci_msi_supported - check whether MSI may be enabled on a device
803 * @dev: pointer to the pci_dev data structure of MSI device function
804 * @nvec: how many MSIs have been requested ?
806 * Look at global flags, the device itself, and its parent buses
807 * to determine if MSI/-X are supported for the device. If MSI/-X is
808 * supported return 1, else return 0.
810 static int pci_msi_supported(struct pci_dev *dev, int nvec)
814 /* MSI must be globally enabled and supported by the device */
818 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
822 * You can't ask to have 0 or less MSIs configured.
824 * b) the list manipulation code assumes nvec >= 1.
830 * Any bridge which does NOT route MSI transactions from its
831 * secondary bus to its primary bus must set NO_MSI flag on
832 * the secondary pci_bus.
833 * We expect only arch-specific PCI host bus controller driver
834 * or quirks for specific PCI bridges to be setting NO_MSI.
836 for (bus = dev->bus; bus; bus = bus->parent)
837 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
844 * pci_msi_vec_count - Return the number of MSI vectors a device can send
845 * @dev: device to report about
847 * This function returns the number of MSI vectors a device requested via
848 * Multiple Message Capable register. It returns a negative errno if the
849 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
850 * and returns a power of two, up to a maximum of 2^5 (32), according to the
853 int pci_msi_vec_count(struct pci_dev *dev)
861 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
862 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
866 EXPORT_SYMBOL(pci_msi_vec_count);
868 void pci_msi_shutdown(struct pci_dev *dev)
870 struct msi_desc *desc;
873 if (!pci_msi_enable || !dev || !dev->msi_enabled)
876 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
877 desc = first_pci_msi_entry(dev);
879 pci_msi_set_enable(dev, 0);
880 pci_intx_for_msi(dev, 1);
881 dev->msi_enabled = 0;
883 /* Return the device with MSI unmasked as initial states */
884 mask = msi_mask(desc->msi_attrib.multi_cap);
885 /* Keep cached state to be restored */
886 __pci_msi_desc_mask_irq(desc, mask, ~mask);
888 /* Restore dev->irq to its default pin-assertion irq */
889 dev->irq = desc->msi_attrib.default_irq;
890 pcibios_alloc_irq(dev);
893 void pci_disable_msi(struct pci_dev *dev)
895 if (!pci_msi_enable || !dev || !dev->msi_enabled)
898 pci_msi_shutdown(dev);
901 EXPORT_SYMBOL(pci_disable_msi);
904 * pci_msix_vec_count - return the number of device's MSI-X table entries
905 * @dev: pointer to the pci_dev data structure of MSI-X device function
906 * This function returns the number of device's MSI-X table entries and
907 * therefore the number of MSI-X vectors device is capable of sending.
908 * It returns a negative errno if the device is not capable of sending MSI-X
911 int pci_msix_vec_count(struct pci_dev *dev)
918 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
919 return msix_table_size(control);
921 EXPORT_SYMBOL(pci_msix_vec_count);
924 * pci_enable_msix - configure device's MSI-X capability structure
925 * @dev: pointer to the pci_dev data structure of MSI-X device function
926 * @entries: pointer to an array of MSI-X entries
927 * @nvec: number of MSI-X irqs requested for allocation by device driver
929 * Setup the MSI-X capability structure of device function with the number
930 * of requested irqs upon its software driver call to request for
931 * MSI-X mode enabled on its hardware device function. A return of zero
932 * indicates the successful configuration of MSI-X capability structure
933 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
934 * Or a return of > 0 indicates that driver request is exceeding the number
935 * of irqs or MSI-X vectors available. Driver should use the returned value to
936 * re-send its request.
938 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
943 if (!pci_msi_supported(dev, nvec))
949 nr_entries = pci_msix_vec_count(dev);
952 if (nvec > nr_entries)
955 /* Check for any invalid entries */
956 for (i = 0; i < nvec; i++) {
957 if (entries[i].entry >= nr_entries)
958 return -EINVAL; /* invalid entry */
959 for (j = i + 1; j < nvec; j++) {
960 if (entries[i].entry == entries[j].entry)
961 return -EINVAL; /* duplicate entry */
964 WARN_ON(!!dev->msix_enabled);
966 /* Check whether driver already requested for MSI irq */
967 if (dev->msi_enabled) {
968 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
971 return msix_capability_init(dev, entries, nvec);
973 EXPORT_SYMBOL(pci_enable_msix);
975 void pci_msix_shutdown(struct pci_dev *dev)
977 struct msi_desc *entry;
979 if (!pci_msi_enable || !dev || !dev->msix_enabled)
982 /* Return the device with MSI-X masked as initial states */
983 for_each_pci_msi_entry(entry, dev) {
984 /* Keep cached states to be restored */
985 __pci_msix_desc_mask_irq(entry, 1);
988 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
989 pci_intx_for_msi(dev, 1);
990 dev->msix_enabled = 0;
991 pcibios_alloc_irq(dev);
994 void pci_disable_msix(struct pci_dev *dev)
996 if (!pci_msi_enable || !dev || !dev->msix_enabled)
999 pci_msix_shutdown(dev);
1002 EXPORT_SYMBOL(pci_disable_msix);
1004 void pci_no_msi(void)
1010 * pci_msi_enabled - is MSI enabled?
1012 * Returns true if MSI has not been disabled by the command-line option
1015 int pci_msi_enabled(void)
1017 return pci_msi_enable;
1019 EXPORT_SYMBOL(pci_msi_enabled);
1021 void pci_msi_init_pci_dev(struct pci_dev *dev)
1026 * pci_enable_msi_range - configure device's MSI capability structure
1027 * @dev: device to configure
1028 * @minvec: minimal number of interrupts to configure
1029 * @maxvec: maximum number of interrupts to configure
1031 * This function tries to allocate a maximum possible number of interrupts in a
1032 * range between @minvec and @maxvec. It returns a negative errno if an error
1033 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1034 * and updates the @dev's irq member to the lowest new interrupt number;
1035 * the other interrupt numbers allocated to this device are consecutive.
1037 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1042 if (!pci_msi_supported(dev, minvec))
1045 WARN_ON(!!dev->msi_enabled);
1047 /* Check whether driver already requested MSI-X irqs */
1048 if (dev->msix_enabled) {
1050 "can't enable MSI (MSI-X already enabled)\n");
1054 if (maxvec < minvec)
1057 nvec = pci_msi_vec_count(dev);
1060 else if (nvec < minvec)
1062 else if (nvec > maxvec)
1066 rc = msi_capability_init(dev, nvec);
1069 } else if (rc > 0) {
1078 EXPORT_SYMBOL(pci_enable_msi_range);
1081 * pci_enable_msix_range - configure device's MSI-X capability structure
1082 * @dev: pointer to the pci_dev data structure of MSI-X device function
1083 * @entries: pointer to an array of MSI-X entries
1084 * @minvec: minimum number of MSI-X irqs requested
1085 * @maxvec: maximum number of MSI-X irqs requested
1087 * Setup the MSI-X capability structure of device function with a maximum
1088 * possible number of interrupts in the range between @minvec and @maxvec
1089 * upon its software driver call to request for MSI-X mode enabled on its
1090 * hardware device function. It returns a negative errno if an error occurs.
1091 * If it succeeds, it returns the actual number of interrupts allocated and
1092 * indicates the successful configuration of MSI-X capability structure
1093 * with new allocated MSI-X interrupts.
1095 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1096 int minvec, int maxvec)
1101 if (maxvec < minvec)
1105 rc = pci_enable_msix(dev, entries, nvec);
1108 } else if (rc > 0) {
1117 EXPORT_SYMBOL(pci_enable_msix_range);
1119 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1121 return to_pci_dev(desc->dev);
1124 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1126 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1128 return dev->bus->sysdata;
1130 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1132 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1134 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1135 * @irq_data: Pointer to interrupt data of the MSI interrupt
1136 * @msg: Pointer to the message
1138 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1140 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1143 * For MSI-X desc->irq is always equal to irq_data->irq. For
1144 * MSI only the first interrupt of MULTI MSI passes the test.
1146 if (desc->irq == irq_data->irq)
1147 __pci_write_msi_msg(desc, msg);
1151 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1152 * @dev: Pointer to the PCI device
1153 * @desc: Pointer to the msi descriptor
1155 * The ID number is only used within the irqdomain.
1157 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1158 struct msi_desc *desc)
1160 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1161 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1162 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1165 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1167 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1171 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1172 * @domain: The interrupt domain to check
1173 * @info: The domain info for verification
1174 * @dev: The device to check
1177 * 0 if the functionality is supported
1178 * 1 if Multi MSI is requested, but the domain does not support it
1179 * -ENOTSUPP otherwise
1181 int pci_msi_domain_check_cap(struct irq_domain *domain,
1182 struct msi_domain_info *info, struct device *dev)
1184 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1186 /* Special handling to support pci_enable_msi_range() */
1187 if (pci_msi_desc_is_multi_msi(desc) &&
1188 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1190 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1196 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1197 struct msi_desc *desc, int error)
1199 /* Special handling to support pci_enable_msi_range() */
1200 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1206 #ifdef GENERIC_MSI_DOMAIN_OPS
1207 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1208 struct msi_desc *desc)
1211 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1215 #define pci_msi_domain_set_desc NULL
1218 static struct msi_domain_ops pci_msi_domain_ops_default = {
1219 .set_desc = pci_msi_domain_set_desc,
1220 .msi_check = pci_msi_domain_check_cap,
1221 .handle_error = pci_msi_domain_handle_error,
1224 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1226 struct msi_domain_ops *ops = info->ops;
1229 info->ops = &pci_msi_domain_ops_default;
1231 if (ops->set_desc == NULL)
1232 ops->set_desc = pci_msi_domain_set_desc;
1233 if (ops->msi_check == NULL)
1234 ops->msi_check = pci_msi_domain_check_cap;
1235 if (ops->handle_error == NULL)
1236 ops->handle_error = pci_msi_domain_handle_error;
1240 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1242 struct irq_chip *chip = info->chip;
1245 if (!chip->irq_write_msi_msg)
1246 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1247 if (!chip->irq_mask)
1248 chip->irq_mask = pci_msi_mask_irq;
1249 if (!chip->irq_unmask)
1250 chip->irq_unmask = pci_msi_unmask_irq;
1254 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1255 * @fwnode: Optional fwnode of the interrupt controller
1256 * @info: MSI domain info
1257 * @parent: Parent irq domain
1259 * Updates the domain and chip ops and creates a MSI interrupt domain.
1262 * A domain pointer or NULL in case of failure.
1264 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1265 struct msi_domain_info *info,
1266 struct irq_domain *parent)
1268 struct irq_domain *domain;
1270 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1271 pci_msi_domain_update_dom_ops(info);
1272 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1273 pci_msi_domain_update_chip_ops(info);
1275 domain = msi_create_irq_domain(fwnode, info, parent);
1279 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1284 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1285 * @domain: The interrupt domain to allocate from
1286 * @dev: The device for which to allocate
1287 * @nvec: The number of interrupts to allocate
1288 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1291 * A virtual interrupt number or an error code in case of failure
1293 int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1296 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1300 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1301 * @domain: The interrupt domain
1302 * @dev: The device for which to free interrupts
1304 void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1306 msi_domain_free_irqs(domain, &dev->dev);
1310 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1311 * @fwnode: Optional fwnode of the interrupt controller
1312 * @info: MSI domain info
1313 * @parent: Parent irq domain
1315 * Returns: A domain pointer or NULL in case of failure. If successful
1316 * the default PCI/MSI irqdomain pointer is updated.
1318 struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
1319 struct msi_domain_info *info, struct irq_domain *parent)
1321 struct irq_domain *domain;
1323 mutex_lock(&pci_msi_domain_lock);
1324 if (pci_msi_default_domain) {
1325 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1328 domain = pci_msi_create_irq_domain(fwnode, info, parent);
1329 pci_msi_default_domain = domain;
1331 mutex_unlock(&pci_msi_domain_lock);
1336 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1344 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1345 * @domain: The interrupt domain
1346 * @pdev: The PCI device.
1348 * The RID for a device is formed from the alias, with a firmware
1349 * supplied mapping applied
1353 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1355 struct device_node *of_node;
1358 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1360 of_node = irq_domain_get_of_node(domain);
1362 rid = of_msi_map_rid(&pdev->dev, of_node, rid);
1368 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1369 * @pdev: The PCI device
1371 * Use the firmware data to find a device-specific MSI domain
1372 * (i.e. not one that is ste as a default).
1374 * Returns: The coresponding MSI domain or NULL if none has been found.
1376 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1380 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1381 return of_msi_map_get_device_domain(&pdev->dev, rid);
1383 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */