2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm-generic/pci-bridge.h>
26 #include <asm/setup.h>
29 const char *pci_power_names[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
32 EXPORT_SYMBOL_GPL(pci_power_names);
34 int isa_dma_bridge_buggy;
35 EXPORT_SYMBOL(isa_dma_bridge_buggy);
38 EXPORT_SYMBOL(pci_pci_problems);
40 unsigned int pci_pm_d3_delay;
42 static void pci_pme_list_scan(struct work_struct *work);
44 static LIST_HEAD(pci_pme_list);
45 static DEFINE_MUTEX(pci_pme_list_mutex);
46 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
48 struct pci_pme_device {
49 struct list_head list;
53 #define PME_TIMEOUT 1000 /* How long between PME checks */
55 static void pci_dev_d3_sleep(struct pci_dev *dev)
57 unsigned int delay = dev->d3_delay;
59 if (delay < pci_pm_d3_delay)
60 delay = pci_pm_d3_delay;
65 #ifdef CONFIG_PCI_DOMAINS
66 int pci_domains_supported = 1;
69 #define DEFAULT_CARDBUS_IO_SIZE (256)
70 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
72 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
73 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
75 #define DEFAULT_HOTPLUG_IO_SIZE (256)
76 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
78 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
79 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
84 * The default CLS is used if arch didn't set CLS explicitly and not
85 * all pci devices agree on the same value. Arch can override either
86 * the dfl or actual value as it sees fit. Don't forget this is
87 * measured in 32-bit words, not bytes.
89 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
90 u8 pci_cache_line_size;
93 * If we set up a device for bus mastering, we need to check the latency
94 * timer as certain BIOSes forget to set it properly.
96 unsigned int pcibios_max_latency = 255;
98 /* If set, the PCIe ARI capability will not be used. */
99 static bool pcie_ari_disabled;
102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
103 * @bus: pointer to PCI bus structure to search
105 * Given a PCI bus, returns the highest PCI bus number present in the set
106 * including the given PCI bus and its list of child PCI buses.
108 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
110 struct list_head *tmp;
111 unsigned char max, n;
113 max = bus->busn_res.end;
114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp));
121 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
123 #ifdef CONFIG_HAS_IOMEM
124 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
127 * Make sure the BAR is actually a memory resource, not an IO resource
129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
133 return ioremap_nocache(pci_resource_start(pdev, bar),
134 pci_resource_len(pdev, bar));
136 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
139 #define PCI_FIND_CAP_TTL 48
141 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
142 u8 pos, int cap, int *ttl)
147 pci_bus_read_config_byte(bus, devfn, pos, &pos);
151 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
157 pos += PCI_CAP_LIST_NEXT;
162 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
165 int ttl = PCI_FIND_CAP_TTL;
167 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
170 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
172 return __pci_find_next_cap(dev->bus, dev->devfn,
173 pos + PCI_CAP_LIST_NEXT, cap);
175 EXPORT_SYMBOL_GPL(pci_find_next_capability);
177 static int __pci_bus_find_cap_start(struct pci_bus *bus,
178 unsigned int devfn, u8 hdr_type)
182 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
183 if (!(status & PCI_STATUS_CAP_LIST))
187 case PCI_HEADER_TYPE_NORMAL:
188 case PCI_HEADER_TYPE_BRIDGE:
189 return PCI_CAPABILITY_LIST;
190 case PCI_HEADER_TYPE_CARDBUS:
191 return PCI_CB_CAPABILITY_LIST;
200 * pci_find_capability - query for devices' capabilities
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Tell if a device supports a given PCI capability.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
207 * support it. Possible values for @cap:
209 * %PCI_CAP_ID_PM Power Management
210 * %PCI_CAP_ID_AGP Accelerated Graphics Port
211 * %PCI_CAP_ID_VPD Vital Product Data
212 * %PCI_CAP_ID_SLOTID Slot Identification
213 * %PCI_CAP_ID_MSI Message Signalled Interrupts
214 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
215 * %PCI_CAP_ID_PCIX PCI-X
216 * %PCI_CAP_ID_EXP PCI Express
218 int pci_find_capability(struct pci_dev *dev, int cap)
222 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
224 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
230 * pci_bus_find_capability - query for devices' capabilities
231 * @bus: the PCI bus to query
232 * @devfn: PCI device to query
233 * @cap: capability code
235 * Like pci_find_capability() but works for pci devices that do not have a
236 * pci_dev structure set up yet.
238 * Returns the address of the requested capability structure within the
239 * device's PCI configuration space or 0 in case the device does not
242 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
247 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
249 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
251 pos = __pci_find_next_cap(bus, devfn, pos, cap);
257 * pci_find_next_ext_capability - Find an extended capability
258 * @dev: PCI device to query
259 * @start: address at which to start looking (0 to start at beginning of list)
260 * @cap: capability code
262 * Returns the address of the next matching extended capability structure
263 * within the device's PCI configuration space or 0 if the device does
264 * not support it. Some capabilities can occur several times, e.g., the
265 * vendor-specific capability, and this provides a way to find them all.
267 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
271 int pos = PCI_CFG_SPACE_SIZE;
273 /* minimum 8 bytes per capability */
274 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
286 * If we have no capabilities, this is indicated by cap ID,
287 * cap version and next pointer all being 0.
293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
296 pos = PCI_EXT_CAP_NEXT(header);
297 if (pos < PCI_CFG_SPACE_SIZE)
300 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
306 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
309 * pci_find_ext_capability - Find an extended capability
310 * @dev: PCI device to query
311 * @cap: capability code
313 * Returns the address of the requested extended capability structure
314 * within the device's PCI configuration space or 0 if the device does
315 * not support it. Possible values for @cap:
317 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
318 * %PCI_EXT_CAP_ID_VC Virtual Channel
319 * %PCI_EXT_CAP_ID_DSN Device Serial Number
320 * %PCI_EXT_CAP_ID_PWR Power Budgeting
322 int pci_find_ext_capability(struct pci_dev *dev, int cap)
324 return pci_find_next_ext_capability(dev, 0, cap);
326 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
328 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
330 int rc, ttl = PCI_FIND_CAP_TTL;
333 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
334 mask = HT_3BIT_CAP_MASK;
336 mask = HT_5BIT_CAP_MASK;
338 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
339 PCI_CAP_ID_HT, &ttl);
341 rc = pci_read_config_byte(dev, pos + 3, &cap);
342 if (rc != PCIBIOS_SUCCESSFUL)
345 if ((cap & mask) == ht_cap)
348 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
349 pos + PCI_CAP_LIST_NEXT,
350 PCI_CAP_ID_HT, &ttl);
356 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
357 * @dev: PCI device to query
358 * @pos: Position from which to continue searching
359 * @ht_cap: Hypertransport capability code
361 * To be used in conjunction with pci_find_ht_capability() to search for
362 * all capabilities matching @ht_cap. @pos should always be a value returned
363 * from pci_find_ht_capability().
365 * NB. To be 100% safe against broken PCI devices, the caller should take
366 * steps to avoid an infinite loop.
368 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
370 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
372 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
375 * pci_find_ht_capability - query a device's Hypertransport capabilities
376 * @dev: PCI device to query
377 * @ht_cap: Hypertransport capability code
379 * Tell if a device supports a given Hypertransport capability.
380 * Returns an address within the device's PCI configuration space
381 * or 0 in case the device does not support the request capability.
382 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
383 * which has a Hypertransport capability matching @ht_cap.
385 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
389 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
391 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
395 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
398 * pci_find_parent_resource - return resource region of parent bus of given region
399 * @dev: PCI device structure contains resources to be searched
400 * @res: child resource record for which parent is sought
402 * For given resource region of given device, return the resource
403 * region of parent bus the given region is contained in or where
404 * it should be allocated from.
407 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
409 const struct pci_bus *bus = dev->bus;
411 struct resource *best = NULL, *r;
413 pci_bus_for_each_resource(bus, r, i) {
416 if (res->start && !(res->start >= r->start && res->end <= r->end))
417 continue; /* Not contained */
418 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
419 continue; /* Wrong type */
420 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
421 return r; /* Exact match */
422 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
423 if (r->flags & IORESOURCE_PREFETCH)
425 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
433 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
434 * @dev: PCI device to have its BARs restored
436 * Restore the BAR values for a given device, so as to make it
437 * accessible by its driver.
440 pci_restore_bars(struct pci_dev *dev)
444 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
445 pci_update_resource(dev, i);
448 static struct pci_platform_pm_ops *pci_platform_pm;
450 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
452 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
455 pci_platform_pm = ops;
459 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
461 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
464 static inline int platform_pci_set_power_state(struct pci_dev *dev,
467 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
470 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
472 return pci_platform_pm ?
473 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
476 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
478 return pci_platform_pm ?
479 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
482 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
484 return pci_platform_pm ?
485 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
489 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
491 * @dev: PCI device to handle.
492 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
495 * -EINVAL if the requested state is invalid.
496 * -EIO if device does not support PCI PM or its PM capabilities register has a
497 * wrong version, or device doesn't support the requested state.
498 * 0 if device already is in the requested state.
499 * 0 if device's power state has been successfully changed.
501 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
504 bool need_restore = false;
506 /* Check if we're already there */
507 if (dev->current_state == state)
513 if (state < PCI_D0 || state > PCI_D3hot)
516 /* Validate current state:
517 * Can enter D0 from any state, but if we can only go deeper
518 * to sleep if we're already in a low power state
520 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
521 && dev->current_state > state) {
522 dev_err(&dev->dev, "invalid power transition "
523 "(from state %d to %d)\n", dev->current_state, state);
527 /* check if this device supports the desired state */
528 if ((state == PCI_D1 && !dev->d1_support)
529 || (state == PCI_D2 && !dev->d2_support))
532 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
534 /* If we're (effectively) in D3, force entire word to 0.
535 * This doesn't affect PME_Status, disables PME_En, and
536 * sets PowerState to 0.
538 switch (dev->current_state) {
542 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
547 case PCI_UNKNOWN: /* Boot-up */
548 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
549 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
551 /* Fall-through: force to D0 */
557 /* enter specified state */
558 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
560 /* Mandatory power management transition delays */
561 /* see PCI PM 1.1 5.6.1 table 18 */
562 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
563 pci_dev_d3_sleep(dev);
564 else if (state == PCI_D2 || dev->current_state == PCI_D2)
565 udelay(PCI_PM_D2_DELAY);
567 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
568 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
569 if (dev->current_state != state && printk_ratelimit())
570 dev_info(&dev->dev, "Refused to change power state, "
571 "currently in D%d\n", dev->current_state);
574 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
575 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
576 * from D3hot to D0 _may_ perform an internal reset, thereby
577 * going to "D0 Uninitialized" rather than "D0 Initialized".
578 * For example, at least some versions of the 3c905B and the
579 * 3c556B exhibit this behaviour.
581 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
582 * devices in a D3hot state at boot. Consequently, we need to
583 * restore at least the BARs so that the device will be
584 * accessible to its driver.
587 pci_restore_bars(dev);
590 pcie_aspm_pm_state_change(dev->bus->self);
596 * pci_update_current_state - Read PCI power state of given device from its
597 * PCI PM registers and cache it
598 * @dev: PCI device to handle.
599 * @state: State to cache in case the device doesn't have the PM capability
601 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
607 * Configuration space is not accessible for device in
608 * D3cold, so just keep or set D3cold for safety
610 if (dev->current_state == PCI_D3cold)
612 if (state == PCI_D3cold) {
613 dev->current_state = PCI_D3cold;
616 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
617 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
619 dev->current_state = state;
624 * pci_power_up - Put the given device into D0 forcibly
625 * @dev: PCI device to power up
627 void pci_power_up(struct pci_dev *dev)
629 if (platform_pci_power_manageable(dev))
630 platform_pci_set_power_state(dev, PCI_D0);
632 pci_raw_set_power_state(dev, PCI_D0);
633 pci_update_current_state(dev, PCI_D0);
637 * pci_platform_power_transition - Use platform to change device power state
638 * @dev: PCI device to handle.
639 * @state: State to put the device into.
641 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
645 if (platform_pci_power_manageable(dev)) {
646 error = platform_pci_set_power_state(dev, state);
648 pci_update_current_state(dev, state);
649 /* Fall back to PCI_D0 if native PM is not supported */
651 dev->current_state = PCI_D0;
654 /* Fall back to PCI_D0 if native PM is not supported */
656 dev->current_state = PCI_D0;
663 * __pci_start_power_transition - Start power transition of a PCI device
664 * @dev: PCI device to handle.
665 * @state: State to put the device into.
667 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
669 if (state == PCI_D0) {
670 pci_platform_power_transition(dev, PCI_D0);
672 * Mandatory power management transition delays, see
673 * PCI Express Base Specification Revision 2.0 Section
674 * 6.6.1: Conventional Reset. Do not delay for
675 * devices powered on/off by corresponding bridge,
676 * because have already delayed for the bridge.
678 if (dev->runtime_d3cold) {
679 msleep(dev->d3cold_delay);
681 * When powering on a bridge from D3cold, the
682 * whole hierarchy may be powered on into
683 * D0uninitialized state, resume them to give
684 * them a chance to suspend again
686 pci_wakeup_bus(dev->subordinate);
692 * __pci_dev_set_current_state - Set current state of a PCI device
693 * @dev: Device to handle
694 * @data: pointer to state to be set
696 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
698 pci_power_t state = *(pci_power_t *)data;
700 dev->current_state = state;
705 * __pci_bus_set_current_state - Walk given bus and set current state of devices
706 * @bus: Top bus of the subtree to walk.
707 * @state: state to be set
709 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
712 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
716 * __pci_complete_power_transition - Complete power transition of a PCI device
717 * @dev: PCI device to handle.
718 * @state: State to put the device into.
720 * This function should not be called directly by device drivers.
722 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
728 ret = pci_platform_power_transition(dev, state);
729 /* Power off the bridge may power off the whole hierarchy */
730 if (!ret && state == PCI_D3cold)
731 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
734 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
737 * pci_set_power_state - Set the power state of a PCI device
738 * @dev: PCI device to handle.
739 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
741 * Transition a device to a new power state, using the platform firmware and/or
742 * the device's PCI PM registers.
745 * -EINVAL if the requested state is invalid.
746 * -EIO if device does not support PCI PM or its PM capabilities register has a
747 * wrong version, or device doesn't support the requested state.
748 * 0 if device already is in the requested state.
749 * 0 if device's power state has been successfully changed.
751 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
755 /* bound the state we're entering */
756 if (state > PCI_D3cold)
758 else if (state < PCI_D0)
760 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
762 * If the device or the parent bridge do not support PCI PM,
763 * ignore the request if we're doing anything other than putting
764 * it into D0 (which would only happen on boot).
768 /* Check if we're already there */
769 if (dev->current_state == state)
772 __pci_start_power_transition(dev, state);
774 /* This device is quirked not to be put into D3, so
775 don't put it in D3 */
776 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
780 * To put device in D3cold, we put device into D3hot in native
781 * way, then put device into D3cold with platform ops
783 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
786 if (!__pci_complete_power_transition(dev, state))
789 * When aspm_policy is "powersave" this call ensures
790 * that ASPM is configured.
792 if (!error && dev->bus->self)
793 pcie_aspm_powersave_config_link(dev->bus->self);
799 * pci_choose_state - Choose the power state of a PCI device
800 * @dev: PCI device to be suspended
801 * @state: target sleep state for the whole system. This is the value
802 * that is passed to suspend() function.
804 * Returns PCI power state suitable for given device and given system
808 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
812 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
815 ret = platform_pci_choose_state(dev);
816 if (ret != PCI_POWER_ERROR)
819 switch (state.event) {
822 case PM_EVENT_FREEZE:
823 case PM_EVENT_PRETHAW:
824 /* REVISIT both freeze and pre-thaw "should" use D0 */
825 case PM_EVENT_SUSPEND:
826 case PM_EVENT_HIBERNATE:
829 dev_info(&dev->dev, "unrecognized suspend event %d\n",
836 EXPORT_SYMBOL(pci_choose_state);
838 #define PCI_EXP_SAVE_REGS 7
841 static struct pci_cap_saved_state *pci_find_saved_cap(
842 struct pci_dev *pci_dev, char cap)
844 struct pci_cap_saved_state *tmp;
845 struct hlist_node *pos;
847 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
848 if (tmp->cap.cap_nr == cap)
854 static int pci_save_pcie_state(struct pci_dev *dev)
857 struct pci_cap_saved_state *save_state;
860 if (!pci_is_pcie(dev))
863 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
865 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
869 cap = (u16 *)&save_state->cap.data[0];
870 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
872 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
873 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
874 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
875 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
876 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
881 static void pci_restore_pcie_state(struct pci_dev *dev)
884 struct pci_cap_saved_state *save_state;
887 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
891 cap = (u16 *)&save_state->cap.data[0];
892 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
894 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
895 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
896 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
897 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
898 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
902 static int pci_save_pcix_state(struct pci_dev *dev)
905 struct pci_cap_saved_state *save_state;
907 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
911 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
913 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
917 pci_read_config_word(dev, pos + PCI_X_CMD,
918 (u16 *)save_state->cap.data);
923 static void pci_restore_pcix_state(struct pci_dev *dev)
926 struct pci_cap_saved_state *save_state;
929 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
930 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
931 if (!save_state || pos <= 0)
933 cap = (u16 *)&save_state->cap.data[0];
935 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
940 * pci_save_state - save the PCI configuration space of a device before suspending
941 * @dev: - PCI device that we're dealing with
944 pci_save_state(struct pci_dev *dev)
947 /* XXX: 100% dword access ok here? */
948 for (i = 0; i < 16; i++)
949 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
950 dev->state_saved = true;
951 if ((i = pci_save_pcie_state(dev)) != 0)
953 if ((i = pci_save_pcix_state(dev)) != 0)
958 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
959 u32 saved_val, int retry)
963 pci_read_config_dword(pdev, offset, &val);
964 if (val == saved_val)
968 dev_dbg(&pdev->dev, "restoring config space at offset "
969 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
970 pci_write_config_dword(pdev, offset, saved_val);
974 pci_read_config_dword(pdev, offset, &val);
975 if (val == saved_val)
982 static void pci_restore_config_space_range(struct pci_dev *pdev,
983 int start, int end, int retry)
987 for (index = end; index >= start; index--)
988 pci_restore_config_dword(pdev, 4 * index,
989 pdev->saved_config_space[index],
993 static void pci_restore_config_space(struct pci_dev *pdev)
995 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
996 pci_restore_config_space_range(pdev, 10, 15, 0);
997 /* Restore BARs before the command register. */
998 pci_restore_config_space_range(pdev, 4, 9, 10);
999 pci_restore_config_space_range(pdev, 0, 3, 0);
1001 pci_restore_config_space_range(pdev, 0, 15, 0);
1006 * pci_restore_state - Restore the saved state of a PCI device
1007 * @dev: - PCI device that we're dealing with
1009 void pci_restore_state(struct pci_dev *dev)
1011 if (!dev->state_saved)
1014 /* PCI Express register must be restored first */
1015 pci_restore_pcie_state(dev);
1016 pci_restore_ats_state(dev);
1018 pci_restore_config_space(dev);
1020 pci_restore_pcix_state(dev);
1021 pci_restore_msi_state(dev);
1022 pci_restore_iov_state(dev);
1024 dev->state_saved = false;
1027 struct pci_saved_state {
1028 u32 config_space[16];
1029 struct pci_cap_saved_data cap[0];
1033 * pci_store_saved_state - Allocate and return an opaque struct containing
1034 * the device saved state.
1035 * @dev: PCI device that we're dealing with
1037 * Rerturn NULL if no state or error.
1039 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1041 struct pci_saved_state *state;
1042 struct pci_cap_saved_state *tmp;
1043 struct pci_cap_saved_data *cap;
1044 struct hlist_node *pos;
1047 if (!dev->state_saved)
1050 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1052 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1053 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1055 state = kzalloc(size, GFP_KERNEL);
1059 memcpy(state->config_space, dev->saved_config_space,
1060 sizeof(state->config_space));
1063 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1064 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1065 memcpy(cap, &tmp->cap, len);
1066 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1068 /* Empty cap_save terminates list */
1072 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1075 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1076 * @dev: PCI device that we're dealing with
1077 * @state: Saved state returned from pci_store_saved_state()
1079 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1081 struct pci_cap_saved_data *cap;
1083 dev->state_saved = false;
1088 memcpy(dev->saved_config_space, state->config_space,
1089 sizeof(state->config_space));
1093 struct pci_cap_saved_state *tmp;
1095 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1096 if (!tmp || tmp->cap.size != cap->size)
1099 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1100 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1101 sizeof(struct pci_cap_saved_data) + cap->size);
1104 dev->state_saved = true;
1107 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1110 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1111 * and free the memory allocated for it.
1112 * @dev: PCI device that we're dealing with
1113 * @state: Pointer to saved state returned from pci_store_saved_state()
1115 int pci_load_and_free_saved_state(struct pci_dev *dev,
1116 struct pci_saved_state **state)
1118 int ret = pci_load_saved_state(dev, *state);
1123 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1125 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1129 err = pci_set_power_state(dev, PCI_D0);
1130 if (err < 0 && err != -EIO)
1132 err = pcibios_enable_device(dev, bars);
1135 pci_fixup_device(pci_fixup_enable, dev);
1141 * pci_reenable_device - Resume abandoned device
1142 * @dev: PCI device to be resumed
1144 * Note this function is a backend of pci_default_resume and is not supposed
1145 * to be called by normal code, write proper resume handler and use it instead.
1147 int pci_reenable_device(struct pci_dev *dev)
1149 if (pci_is_enabled(dev))
1150 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1154 static int __pci_enable_device_flags(struct pci_dev *dev,
1155 resource_size_t flags)
1161 * Power state could be unknown at this point, either due to a fresh
1162 * boot or a device removal call. So get the current power state
1163 * so that things like MSI message writing will behave as expected
1164 * (e.g. if the device really is in D0 at enable time).
1168 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1169 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1172 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1173 return 0; /* already enabled */
1175 /* only skip sriov related */
1176 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1177 if (dev->resource[i].flags & flags)
1179 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1180 if (dev->resource[i].flags & flags)
1183 err = do_pci_enable_device(dev, bars);
1185 atomic_dec(&dev->enable_cnt);
1190 * pci_enable_device_io - Initialize a device for use with IO space
1191 * @dev: PCI device to be initialized
1193 * Initialize device before it's used by a driver. Ask low-level code
1194 * to enable I/O resources. Wake up the device if it was suspended.
1195 * Beware, this function can fail.
1197 int pci_enable_device_io(struct pci_dev *dev)
1199 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1203 * pci_enable_device_mem - Initialize a device for use with Memory space
1204 * @dev: PCI device to be initialized
1206 * Initialize device before it's used by a driver. Ask low-level code
1207 * to enable Memory resources. Wake up the device if it was suspended.
1208 * Beware, this function can fail.
1210 int pci_enable_device_mem(struct pci_dev *dev)
1212 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1216 * pci_enable_device - Initialize device before it's used by a driver.
1217 * @dev: PCI device to be initialized
1219 * Initialize device before it's used by a driver. Ask low-level code
1220 * to enable I/O and memory. Wake up the device if it was suspended.
1221 * Beware, this function can fail.
1223 * Note we don't actually enable the device many times if we call
1224 * this function repeatedly (we just increment the count).
1226 int pci_enable_device(struct pci_dev *dev)
1228 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1232 * Managed PCI resources. This manages device on/off, intx/msi/msix
1233 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1234 * there's no need to track it separately. pci_devres is initialized
1235 * when a device is enabled using managed PCI device enable interface.
1238 unsigned int enabled:1;
1239 unsigned int pinned:1;
1240 unsigned int orig_intx:1;
1241 unsigned int restore_intx:1;
1245 static void pcim_release(struct device *gendev, void *res)
1247 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1248 struct pci_devres *this = res;
1251 if (dev->msi_enabled)
1252 pci_disable_msi(dev);
1253 if (dev->msix_enabled)
1254 pci_disable_msix(dev);
1256 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1257 if (this->region_mask & (1 << i))
1258 pci_release_region(dev, i);
1260 if (this->restore_intx)
1261 pci_intx(dev, this->orig_intx);
1263 if (this->enabled && !this->pinned)
1264 pci_disable_device(dev);
1267 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1269 struct pci_devres *dr, *new_dr;
1271 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1275 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1278 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1281 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1283 if (pci_is_managed(pdev))
1284 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1289 * pcim_enable_device - Managed pci_enable_device()
1290 * @pdev: PCI device to be initialized
1292 * Managed pci_enable_device().
1294 int pcim_enable_device(struct pci_dev *pdev)
1296 struct pci_devres *dr;
1299 dr = get_pci_dr(pdev);
1305 rc = pci_enable_device(pdev);
1307 pdev->is_managed = 1;
1314 * pcim_pin_device - Pin managed PCI device
1315 * @pdev: PCI device to pin
1317 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1318 * driver detach. @pdev must have been enabled with
1319 * pcim_enable_device().
1321 void pcim_pin_device(struct pci_dev *pdev)
1323 struct pci_devres *dr;
1325 dr = find_pci_dr(pdev);
1326 WARN_ON(!dr || !dr->enabled);
1332 * pcibios_add_device - provide arch specific hooks when adding device dev
1333 * @dev: the PCI device being added
1335 * Permits the platform to provide architecture specific functionality when
1336 * devices are added. This is the default implementation. Architecture
1337 * implementations can override this.
1339 int __weak pcibios_add_device (struct pci_dev *dev)
1345 * pcibios_disable_device - disable arch specific PCI resources for device dev
1346 * @dev: the PCI device to disable
1348 * Disables architecture specific PCI resources for the device. This
1349 * is the default implementation. Architecture implementations can
1352 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1354 static void do_pci_disable_device(struct pci_dev *dev)
1358 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1359 if (pci_command & PCI_COMMAND_MASTER) {
1360 pci_command &= ~PCI_COMMAND_MASTER;
1361 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1364 pcibios_disable_device(dev);
1368 * pci_disable_enabled_device - Disable device without updating enable_cnt
1369 * @dev: PCI device to disable
1371 * NOTE: This function is a backend of PCI power management routines and is
1372 * not supposed to be called drivers.
1374 void pci_disable_enabled_device(struct pci_dev *dev)
1376 if (pci_is_enabled(dev))
1377 do_pci_disable_device(dev);
1381 * pci_disable_device - Disable PCI device after use
1382 * @dev: PCI device to be disabled
1384 * Signal to the system that the PCI device is not in use by the system
1385 * anymore. This only involves disabling PCI bus-mastering, if active.
1387 * Note we don't actually disable the device until all callers of
1388 * pci_enable_device() have called pci_disable_device().
1391 pci_disable_device(struct pci_dev *dev)
1393 struct pci_devres *dr;
1395 dr = find_pci_dr(dev);
1399 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1402 do_pci_disable_device(dev);
1404 dev->is_busmaster = 0;
1408 * pcibios_set_pcie_reset_state - set reset state for device dev
1409 * @dev: the PCIe device reset
1410 * @state: Reset state to enter into
1413 * Sets the PCIe reset state for the device. This is the default
1414 * implementation. Architecture implementations can override this.
1416 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1417 enum pcie_reset_state state)
1423 * pci_set_pcie_reset_state - set reset state for device dev
1424 * @dev: the PCIe device reset
1425 * @state: Reset state to enter into
1428 * Sets the PCI reset state for the device.
1430 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1432 return pcibios_set_pcie_reset_state(dev, state);
1436 * pci_check_pme_status - Check if given device has generated PME.
1437 * @dev: Device to check.
1439 * Check the PME status of the device and if set, clear it and clear PME enable
1440 * (if set). Return 'true' if PME status and PME enable were both set or
1441 * 'false' otherwise.
1443 bool pci_check_pme_status(struct pci_dev *dev)
1452 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1453 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1454 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1457 /* Clear PME status. */
1458 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1459 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1460 /* Disable PME to avoid interrupt flood. */
1461 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1465 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1471 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1472 * @dev: Device to handle.
1473 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1475 * Check if @dev has generated PME and queue a resume request for it in that
1478 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1480 if (pme_poll_reset && dev->pme_poll)
1481 dev->pme_poll = false;
1483 if (pci_check_pme_status(dev)) {
1484 pci_wakeup_event(dev);
1485 pm_request_resume(&dev->dev);
1491 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1492 * @bus: Top bus of the subtree to walk.
1494 void pci_pme_wakeup_bus(struct pci_bus *bus)
1497 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1501 * pci_wakeup - Wake up a PCI device
1502 * @pci_dev: Device to handle.
1503 * @ign: ignored parameter
1505 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1507 pci_wakeup_event(pci_dev);
1508 pm_request_resume(&pci_dev->dev);
1513 * pci_wakeup_bus - Walk given bus and wake up devices on it
1514 * @bus: Top bus of the subtree to walk.
1516 void pci_wakeup_bus(struct pci_bus *bus)
1519 pci_walk_bus(bus, pci_wakeup, NULL);
1523 * pci_pme_capable - check the capability of PCI device to generate PME#
1524 * @dev: PCI device to handle.
1525 * @state: PCI state from which device will issue PME#.
1527 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1532 return !!(dev->pme_support & (1 << state));
1535 static void pci_pme_list_scan(struct work_struct *work)
1537 struct pci_pme_device *pme_dev, *n;
1539 mutex_lock(&pci_pme_list_mutex);
1540 if (!list_empty(&pci_pme_list)) {
1541 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1542 if (pme_dev->dev->pme_poll) {
1543 struct pci_dev *bridge;
1545 bridge = pme_dev->dev->bus->self;
1547 * If bridge is in low power state, the
1548 * configuration space of subordinate devices
1549 * may be not accessible
1551 if (bridge && bridge->current_state != PCI_D0)
1553 pci_pme_wakeup(pme_dev->dev, NULL);
1555 list_del(&pme_dev->list);
1559 if (!list_empty(&pci_pme_list))
1560 schedule_delayed_work(&pci_pme_work,
1561 msecs_to_jiffies(PME_TIMEOUT));
1563 mutex_unlock(&pci_pme_list_mutex);
1567 * pci_pme_active - enable or disable PCI device's PME# function
1568 * @dev: PCI device to handle.
1569 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1571 * The caller must verify that the device is capable of generating PME# before
1572 * calling this function with @enable equal to 'true'.
1574 void pci_pme_active(struct pci_dev *dev, bool enable)
1581 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1582 /* Clear PME_Status by writing 1 to it and enable PME# */
1583 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1585 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1587 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1590 * PCI (as opposed to PCIe) PME requires that the device have
1591 * its PME# line hooked up correctly. Not all hardware vendors
1592 * do this, so the PME never gets delivered and the device
1593 * remains asleep. The easiest way around this is to
1594 * periodically walk the list of suspended devices and check
1595 * whether any have their PME flag set. The assumption is that
1596 * we'll wake up often enough anyway that this won't be a huge
1597 * hit, and the power savings from the devices will still be a
1600 * Although PCIe uses in-band PME message instead of PME# line
1601 * to report PME, PME does not work for some PCIe devices in
1602 * reality. For example, there are devices that set their PME
1603 * status bits, but don't really bother to send a PME message;
1604 * there are PCI Express Root Ports that don't bother to
1605 * trigger interrupts when they receive PME messages from the
1606 * devices below. So PME poll is used for PCIe devices too.
1609 if (dev->pme_poll) {
1610 struct pci_pme_device *pme_dev;
1612 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1617 mutex_lock(&pci_pme_list_mutex);
1618 list_add(&pme_dev->list, &pci_pme_list);
1619 if (list_is_singular(&pci_pme_list))
1620 schedule_delayed_work(&pci_pme_work,
1621 msecs_to_jiffies(PME_TIMEOUT));
1622 mutex_unlock(&pci_pme_list_mutex);
1624 mutex_lock(&pci_pme_list_mutex);
1625 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1626 if (pme_dev->dev == dev) {
1627 list_del(&pme_dev->list);
1632 mutex_unlock(&pci_pme_list_mutex);
1637 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1641 * __pci_enable_wake - enable PCI device as wakeup event source
1642 * @dev: PCI device affected
1643 * @state: PCI state from which device will issue wakeup events
1644 * @runtime: True if the events are to be generated at run time
1645 * @enable: True to enable event generation; false to disable
1647 * This enables the device as a wakeup event source, or disables it.
1648 * When such events involves platform-specific hooks, those hooks are
1649 * called automatically by this routine.
1651 * Devices with legacy power management (no standard PCI PM capabilities)
1652 * always require such platform hooks.
1655 * 0 is returned on success
1656 * -EINVAL is returned if device is not supposed to wake up the system
1657 * Error code depending on the platform is returned if both the platform and
1658 * the native mechanism fail to enable the generation of wake-up events
1660 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1661 bool runtime, bool enable)
1665 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1668 /* Don't do the same thing twice in a row for one device. */
1669 if (!!enable == !!dev->wakeup_prepared)
1673 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1674 * Anderson we should be doing PME# wake enable followed by ACPI wake
1675 * enable. To disable wake-up we call the platform first, for symmetry.
1681 if (pci_pme_capable(dev, state))
1682 pci_pme_active(dev, true);
1685 error = runtime ? platform_pci_run_wake(dev, true) :
1686 platform_pci_sleep_wake(dev, true);
1690 dev->wakeup_prepared = true;
1693 platform_pci_run_wake(dev, false);
1695 platform_pci_sleep_wake(dev, false);
1696 pci_pme_active(dev, false);
1697 dev->wakeup_prepared = false;
1702 EXPORT_SYMBOL(__pci_enable_wake);
1705 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1706 * @dev: PCI device to prepare
1707 * @enable: True to enable wake-up event generation; false to disable
1709 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1710 * and this function allows them to set that up cleanly - pci_enable_wake()
1711 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1712 * ordering constraints.
1714 * This function only returns error code if the device is not capable of
1715 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1716 * enable wake-up power for it.
1718 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1720 return pci_pme_capable(dev, PCI_D3cold) ?
1721 pci_enable_wake(dev, PCI_D3cold, enable) :
1722 pci_enable_wake(dev, PCI_D3hot, enable);
1726 * pci_target_state - find an appropriate low power state for a given PCI dev
1729 * Use underlying platform code to find a supported low power state for @dev.
1730 * If the platform can't manage @dev, return the deepest state from which it
1731 * can generate wake events, based on any available PME info.
1733 pci_power_t pci_target_state(struct pci_dev *dev)
1735 pci_power_t target_state = PCI_D3hot;
1737 if (platform_pci_power_manageable(dev)) {
1739 * Call the platform to choose the target state of the device
1740 * and enable wake-up from this state if supported.
1742 pci_power_t state = platform_pci_choose_state(dev);
1745 case PCI_POWER_ERROR:
1750 if (pci_no_d1d2(dev))
1753 target_state = state;
1755 } else if (!dev->pm_cap) {
1756 target_state = PCI_D0;
1757 } else if (device_may_wakeup(&dev->dev)) {
1759 * Find the deepest state from which the device can generate
1760 * wake-up events, make it the target state and enable device
1763 if (dev->pme_support) {
1765 && !(dev->pme_support & (1 << target_state)))
1770 return target_state;
1774 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1775 * @dev: Device to handle.
1777 * Choose the power state appropriate for the device depending on whether
1778 * it can wake up the system and/or is power manageable by the platform
1779 * (PCI_D3hot is the default) and put the device into that state.
1781 int pci_prepare_to_sleep(struct pci_dev *dev)
1783 pci_power_t target_state = pci_target_state(dev);
1786 if (target_state == PCI_POWER_ERROR)
1789 /* D3cold during system suspend/hibernate is not supported */
1790 if (target_state > PCI_D3hot)
1791 target_state = PCI_D3hot;
1793 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1795 error = pci_set_power_state(dev, target_state);
1798 pci_enable_wake(dev, target_state, false);
1804 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1805 * @dev: Device to handle.
1807 * Disable device's system wake-up capability and put it into D0.
1809 int pci_back_from_sleep(struct pci_dev *dev)
1811 pci_enable_wake(dev, PCI_D0, false);
1812 return pci_set_power_state(dev, PCI_D0);
1816 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1817 * @dev: PCI device being suspended.
1819 * Prepare @dev to generate wake-up events at run time and put it into a low
1822 int pci_finish_runtime_suspend(struct pci_dev *dev)
1824 pci_power_t target_state = pci_target_state(dev);
1827 if (target_state == PCI_POWER_ERROR)
1830 dev->runtime_d3cold = target_state == PCI_D3cold;
1832 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1834 error = pci_set_power_state(dev, target_state);
1837 __pci_enable_wake(dev, target_state, true, false);
1838 dev->runtime_d3cold = false;
1845 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1846 * @dev: Device to check.
1848 * Return true if the device itself is cabable of generating wake-up events
1849 * (through the platform or using the native PCIe PME) or if the device supports
1850 * PME and one of its upstream bridges can generate wake-up events.
1852 bool pci_dev_run_wake(struct pci_dev *dev)
1854 struct pci_bus *bus = dev->bus;
1856 if (device_run_wake(&dev->dev))
1859 if (!dev->pme_support)
1862 while (bus->parent) {
1863 struct pci_dev *bridge = bus->self;
1865 if (device_run_wake(&bridge->dev))
1871 /* We have reached the root bus. */
1873 return device_run_wake(bus->bridge);
1877 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1879 void pci_config_pm_runtime_get(struct pci_dev *pdev)
1881 struct device *dev = &pdev->dev;
1882 struct device *parent = dev->parent;
1885 pm_runtime_get_sync(parent);
1886 pm_runtime_get_noresume(dev);
1888 * pdev->current_state is set to PCI_D3cold during suspending,
1889 * so wait until suspending completes
1891 pm_runtime_barrier(dev);
1893 * Only need to resume devices in D3cold, because config
1894 * registers are still accessible for devices suspended but
1897 if (pdev->current_state == PCI_D3cold)
1898 pm_runtime_resume(dev);
1901 void pci_config_pm_runtime_put(struct pci_dev *pdev)
1903 struct device *dev = &pdev->dev;
1904 struct device *parent = dev->parent;
1906 pm_runtime_put(dev);
1908 pm_runtime_put_sync(parent);
1912 * pci_pm_init - Initialize PM functions of given PCI device
1913 * @dev: PCI device to handle.
1915 void pci_pm_init(struct pci_dev *dev)
1920 pm_runtime_forbid(&dev->dev);
1921 pm_runtime_set_active(&dev->dev);
1922 pm_runtime_enable(&dev->dev);
1923 device_enable_async_suspend(&dev->dev);
1924 dev->wakeup_prepared = false;
1928 /* find PCI PM capability in list */
1929 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1932 /* Check device's ability to generate PME# */
1933 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1935 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1936 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1937 pmc & PCI_PM_CAP_VER_MASK);
1942 dev->d3_delay = PCI_PM_D3_WAIT;
1943 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1944 dev->d3cold_allowed = true;
1946 dev->d1_support = false;
1947 dev->d2_support = false;
1948 if (!pci_no_d1d2(dev)) {
1949 if (pmc & PCI_PM_CAP_D1)
1950 dev->d1_support = true;
1951 if (pmc & PCI_PM_CAP_D2)
1952 dev->d2_support = true;
1954 if (dev->d1_support || dev->d2_support)
1955 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1956 dev->d1_support ? " D1" : "",
1957 dev->d2_support ? " D2" : "");
1960 pmc &= PCI_PM_CAP_PME_MASK;
1962 dev_printk(KERN_DEBUG, &dev->dev,
1963 "PME# supported from%s%s%s%s%s\n",
1964 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1965 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1966 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1967 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1968 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1969 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1970 dev->pme_poll = true;
1972 * Make device's PM flags reflect the wake-up capability, but
1973 * let the user space enable it to wake up the system as needed.
1975 device_set_wakeup_capable(&dev->dev, true);
1976 /* Disable the PME# generation functionality */
1977 pci_pme_active(dev, false);
1979 dev->pme_support = 0;
1983 static void pci_add_saved_cap(struct pci_dev *pci_dev,
1984 struct pci_cap_saved_state *new_cap)
1986 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
1990 * pci_add_save_buffer - allocate buffer for saving given capability registers
1991 * @dev: the PCI device
1992 * @cap: the capability to allocate the buffer for
1993 * @size: requested size of the buffer
1995 static int pci_add_cap_save_buffer(
1996 struct pci_dev *dev, char cap, unsigned int size)
1999 struct pci_cap_saved_state *save_state;
2001 pos = pci_find_capability(dev, cap);
2005 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2009 save_state->cap.cap_nr = cap;
2010 save_state->cap.size = size;
2011 pci_add_saved_cap(dev, save_state);
2017 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2018 * @dev: the PCI device
2020 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2024 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2025 PCI_EXP_SAVE_REGS * sizeof(u16));
2028 "unable to preallocate PCI Express save buffer\n");
2030 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2033 "unable to preallocate PCI-X save buffer\n");
2036 void pci_free_cap_save_buffers(struct pci_dev *dev)
2038 struct pci_cap_saved_state *tmp;
2039 struct hlist_node *pos, *n;
2041 hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next)
2046 * pci_enable_ari - enable ARI forwarding if hardware support it
2047 * @dev: the PCI device
2049 void pci_enable_ari(struct pci_dev *dev)
2052 struct pci_dev *bridge;
2054 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2057 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
2060 bridge = dev->bus->self;
2064 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2065 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2068 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
2069 bridge->ari_enabled = 1;
2073 * pci_enable_ido - enable ID-based Ordering on a device
2074 * @dev: the PCI device
2075 * @type: which types of IDO to enable
2077 * Enable ID-based ordering on @dev. @type can contain the bits
2078 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2079 * which types of transactions are allowed to be re-ordered.
2081 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2085 if (type & PCI_EXP_IDO_REQUEST)
2086 ctrl |= PCI_EXP_IDO_REQ_EN;
2087 if (type & PCI_EXP_IDO_COMPLETION)
2088 ctrl |= PCI_EXP_IDO_CMP_EN;
2090 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2092 EXPORT_SYMBOL(pci_enable_ido);
2095 * pci_disable_ido - disable ID-based ordering on a device
2096 * @dev: the PCI device
2097 * @type: which types of IDO to disable
2099 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2103 if (type & PCI_EXP_IDO_REQUEST)
2104 ctrl |= PCI_EXP_IDO_REQ_EN;
2105 if (type & PCI_EXP_IDO_COMPLETION)
2106 ctrl |= PCI_EXP_IDO_CMP_EN;
2108 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2110 EXPORT_SYMBOL(pci_disable_ido);
2113 * pci_enable_obff - enable optimized buffer flush/fill
2115 * @type: type of signaling to use
2117 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2118 * signaling if possible, falling back to message signaling only if
2119 * WAKE# isn't supported. @type should indicate whether the PCIe link
2120 * be brought out of L0s or L1 to send the message. It should be either
2121 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2123 * If your device can benefit from receiving all messages, even at the
2124 * power cost of bringing the link back up from a low power state, use
2125 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2129 * Zero on success, appropriate error number on failure.
2131 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2137 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2138 if (!(cap & PCI_EXP_OBFF_MASK))
2139 return -ENOTSUPP; /* no OBFF support at all */
2141 /* Make sure the topology supports OBFF as well */
2142 if (dev->bus->self) {
2143 ret = pci_enable_obff(dev->bus->self, type);
2148 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2149 if (cap & PCI_EXP_OBFF_WAKE)
2150 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2153 case PCI_EXP_OBFF_SIGNAL_L0:
2154 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2155 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2157 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2158 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2159 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2162 WARN(1, "bad OBFF signal type\n");
2166 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2170 EXPORT_SYMBOL(pci_enable_obff);
2173 * pci_disable_obff - disable optimized buffer flush/fill
2176 * Disable OBFF on @dev.
2178 void pci_disable_obff(struct pci_dev *dev)
2180 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
2182 EXPORT_SYMBOL(pci_disable_obff);
2185 * pci_ltr_supported - check whether a device supports LTR
2189 * True if @dev supports latency tolerance reporting, false otherwise.
2191 static bool pci_ltr_supported(struct pci_dev *dev)
2195 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2197 return cap & PCI_EXP_DEVCAP2_LTR;
2201 * pci_enable_ltr - enable latency tolerance reporting
2204 * Enable LTR on @dev if possible, which means enabling it first on
2208 * Zero on success, errno on failure.
2210 int pci_enable_ltr(struct pci_dev *dev)
2214 /* Only primary function can enable/disable LTR */
2215 if (PCI_FUNC(dev->devfn) != 0)
2218 if (!pci_ltr_supported(dev))
2221 /* Enable upstream ports first */
2222 if (dev->bus->self) {
2223 ret = pci_enable_ltr(dev->bus->self);
2228 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2230 EXPORT_SYMBOL(pci_enable_ltr);
2233 * pci_disable_ltr - disable latency tolerance reporting
2236 void pci_disable_ltr(struct pci_dev *dev)
2238 /* Only primary function can enable/disable LTR */
2239 if (PCI_FUNC(dev->devfn) != 0)
2242 if (!pci_ltr_supported(dev))
2245 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2247 EXPORT_SYMBOL(pci_disable_ltr);
2249 static int __pci_ltr_scale(int *val)
2253 while (*val > 1023) {
2254 *val = (*val + 31) / 32;
2261 * pci_set_ltr - set LTR latency values
2263 * @snoop_lat_ns: snoop latency in nanoseconds
2264 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2266 * Figure out the scale and set the LTR values accordingly.
2268 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2270 int pos, ret, snoop_scale, nosnoop_scale;
2273 if (!pci_ltr_supported(dev))
2276 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2277 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2279 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2280 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2283 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2284 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2287 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2291 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2292 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2296 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2297 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2303 EXPORT_SYMBOL(pci_set_ltr);
2305 static int pci_acs_enable;
2308 * pci_request_acs - ask for ACS to be enabled if supported
2310 void pci_request_acs(void)
2316 * pci_enable_acs - enable ACS if hardware support it
2317 * @dev: the PCI device
2319 void pci_enable_acs(struct pci_dev *dev)
2325 if (!pci_acs_enable)
2328 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2332 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2333 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2335 /* Source Validation */
2336 ctrl |= (cap & PCI_ACS_SV);
2338 /* P2P Request Redirect */
2339 ctrl |= (cap & PCI_ACS_RR);
2341 /* P2P Completion Redirect */
2342 ctrl |= (cap & PCI_ACS_CR);
2344 /* Upstream Forwarding */
2345 ctrl |= (cap & PCI_ACS_UF);
2347 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2351 * pci_acs_enabled - test ACS against required flags for a given device
2352 * @pdev: device to test
2353 * @acs_flags: required PCI ACS flags
2355 * Return true if the device supports the provided flags. Automatically
2356 * filters out flags that are not implemented on multifunction devices.
2358 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2363 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2367 if (!pci_is_pcie(pdev))
2370 /* Filter out flags not applicable to multifunction */
2371 if (pdev->multifunction)
2372 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2373 PCI_ACS_EC | PCI_ACS_DT);
2375 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2376 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
2377 pdev->multifunction) {
2378 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2382 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2383 if ((ctrl & acs_flags) != acs_flags)
2391 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2392 * @start: starting downstream device
2393 * @end: ending upstream device or NULL to search to the root bus
2394 * @acs_flags: required flags
2396 * Walk up a device tree from start to end testing PCI ACS support. If
2397 * any step along the way does not support the required flags, return false.
2399 bool pci_acs_path_enabled(struct pci_dev *start,
2400 struct pci_dev *end, u16 acs_flags)
2402 struct pci_dev *pdev, *parent = start;
2407 if (!pci_acs_enabled(pdev, acs_flags))
2410 if (pci_is_root_bus(pdev->bus))
2411 return (end == NULL);
2413 parent = pdev->bus->self;
2414 } while (pdev != end);
2420 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2421 * @dev: the PCI device
2422 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2424 * Perform INTx swizzling for a device behind one level of bridge. This is
2425 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2426 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2427 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2428 * the PCI Express Base Specification, Revision 2.1)
2430 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2434 if (pci_ari_enabled(dev->bus))
2437 slot = PCI_SLOT(dev->devfn);
2439 return (((pin - 1) + slot) % 4) + 1;
2443 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2451 while (!pci_is_root_bus(dev->bus)) {
2452 pin = pci_swizzle_interrupt_pin(dev, pin);
2453 dev = dev->bus->self;
2460 * pci_common_swizzle - swizzle INTx all the way to root bridge
2461 * @dev: the PCI device
2462 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2464 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2465 * bridges all the way up to a PCI root bus.
2467 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2471 while (!pci_is_root_bus(dev->bus)) {
2472 pin = pci_swizzle_interrupt_pin(dev, pin);
2473 dev = dev->bus->self;
2476 return PCI_SLOT(dev->devfn);
2480 * pci_release_region - Release a PCI bar
2481 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2482 * @bar: BAR to release
2484 * Releases the PCI I/O and memory resources previously reserved by a
2485 * successful call to pci_request_region. Call this function only
2486 * after all use of the PCI regions has ceased.
2488 void pci_release_region(struct pci_dev *pdev, int bar)
2490 struct pci_devres *dr;
2492 if (pci_resource_len(pdev, bar) == 0)
2494 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2495 release_region(pci_resource_start(pdev, bar),
2496 pci_resource_len(pdev, bar));
2497 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2498 release_mem_region(pci_resource_start(pdev, bar),
2499 pci_resource_len(pdev, bar));
2501 dr = find_pci_dr(pdev);
2503 dr->region_mask &= ~(1 << bar);
2507 * __pci_request_region - Reserved PCI I/O and memory resource
2508 * @pdev: PCI device whose resources are to be reserved
2509 * @bar: BAR to be reserved
2510 * @res_name: Name to be associated with resource.
2511 * @exclusive: whether the region access is exclusive or not
2513 * Mark the PCI region associated with PCI device @pdev BR @bar as
2514 * being reserved by owner @res_name. Do not access any
2515 * address inside the PCI regions unless this call returns
2518 * If @exclusive is set, then the region is marked so that userspace
2519 * is explicitly not allowed to map the resource via /dev/mem or
2520 * sysfs MMIO access.
2522 * Returns 0 on success, or %EBUSY on error. A warning
2523 * message is also printed on failure.
2525 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2528 struct pci_devres *dr;
2530 if (pci_resource_len(pdev, bar) == 0)
2533 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2534 if (!request_region(pci_resource_start(pdev, bar),
2535 pci_resource_len(pdev, bar), res_name))
2538 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2539 if (!__request_mem_region(pci_resource_start(pdev, bar),
2540 pci_resource_len(pdev, bar), res_name,
2545 dr = find_pci_dr(pdev);
2547 dr->region_mask |= 1 << bar;
2552 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2553 &pdev->resource[bar]);
2558 * pci_request_region - Reserve PCI I/O and memory resource
2559 * @pdev: PCI device whose resources are to be reserved
2560 * @bar: BAR to be reserved
2561 * @res_name: Name to be associated with resource
2563 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2564 * being reserved by owner @res_name. Do not access any
2565 * address inside the PCI regions unless this call returns
2568 * Returns 0 on success, or %EBUSY on error. A warning
2569 * message is also printed on failure.
2571 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2573 return __pci_request_region(pdev, bar, res_name, 0);
2577 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2578 * @pdev: PCI device whose resources are to be reserved
2579 * @bar: BAR to be reserved
2580 * @res_name: Name to be associated with resource.
2582 * Mark the PCI region associated with PCI device @pdev BR @bar as
2583 * being reserved by owner @res_name. Do not access any
2584 * address inside the PCI regions unless this call returns
2587 * Returns 0 on success, or %EBUSY on error. A warning
2588 * message is also printed on failure.
2590 * The key difference that _exclusive makes it that userspace is
2591 * explicitly not allowed to map the resource via /dev/mem or
2594 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2596 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2599 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2600 * @pdev: PCI device whose resources were previously reserved
2601 * @bars: Bitmask of BARs to be released
2603 * Release selected PCI I/O and memory resources previously reserved.
2604 * Call this function only after all use of the PCI regions has ceased.
2606 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2610 for (i = 0; i < 6; i++)
2611 if (bars & (1 << i))
2612 pci_release_region(pdev, i);
2615 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2616 const char *res_name, int excl)
2620 for (i = 0; i < 6; i++)
2621 if (bars & (1 << i))
2622 if (__pci_request_region(pdev, i, res_name, excl))
2628 if (bars & (1 << i))
2629 pci_release_region(pdev, i);
2636 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2637 * @pdev: PCI device whose resources are to be reserved
2638 * @bars: Bitmask of BARs to be requested
2639 * @res_name: Name to be associated with resource
2641 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2642 const char *res_name)
2644 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2647 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2648 int bars, const char *res_name)
2650 return __pci_request_selected_regions(pdev, bars, res_name,
2651 IORESOURCE_EXCLUSIVE);
2655 * pci_release_regions - Release reserved PCI I/O and memory resources
2656 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2658 * Releases all PCI I/O and memory resources previously reserved by a
2659 * successful call to pci_request_regions. Call this function only
2660 * after all use of the PCI regions has ceased.
2663 void pci_release_regions(struct pci_dev *pdev)
2665 pci_release_selected_regions(pdev, (1 << 6) - 1);
2669 * pci_request_regions - Reserved PCI I/O and memory resources
2670 * @pdev: PCI device whose resources are to be reserved
2671 * @res_name: Name to be associated with resource.
2673 * Mark all PCI regions associated with PCI device @pdev as
2674 * being reserved by owner @res_name. Do not access any
2675 * address inside the PCI regions unless this call returns
2678 * Returns 0 on success, or %EBUSY on error. A warning
2679 * message is also printed on failure.
2681 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2683 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2687 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2688 * @pdev: PCI device whose resources are to be reserved
2689 * @res_name: Name to be associated with resource.
2691 * Mark all PCI regions associated with PCI device @pdev as
2692 * being reserved by owner @res_name. Do not access any
2693 * address inside the PCI regions unless this call returns
2696 * pci_request_regions_exclusive() will mark the region so that
2697 * /dev/mem and the sysfs MMIO access will not be allowed.
2699 * Returns 0 on success, or %EBUSY on error. A warning
2700 * message is also printed on failure.
2702 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2704 return pci_request_selected_regions_exclusive(pdev,
2705 ((1 << 6) - 1), res_name);
2708 static void __pci_set_master(struct pci_dev *dev, bool enable)
2712 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2714 cmd = old_cmd | PCI_COMMAND_MASTER;
2716 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2717 if (cmd != old_cmd) {
2718 dev_dbg(&dev->dev, "%s bus mastering\n",
2719 enable ? "enabling" : "disabling");
2720 pci_write_config_word(dev, PCI_COMMAND, cmd);
2722 dev->is_busmaster = enable;
2726 * pcibios_setup - process "pci=" kernel boot arguments
2727 * @str: string used to pass in "pci=" kernel boot arguments
2729 * Process kernel boot arguments. This is the default implementation.
2730 * Architecture specific implementations can override this as necessary.
2732 char * __weak __init pcibios_setup(char *str)
2738 * pcibios_set_master - enable PCI bus-mastering for device dev
2739 * @dev: the PCI device to enable
2741 * Enables PCI bus-mastering for the device. This is the default
2742 * implementation. Architecture specific implementations can override
2743 * this if necessary.
2745 void __weak pcibios_set_master(struct pci_dev *dev)
2749 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2750 if (pci_is_pcie(dev))
2753 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2755 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2756 else if (lat > pcibios_max_latency)
2757 lat = pcibios_max_latency;
2760 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2761 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2765 * pci_set_master - enables bus-mastering for device dev
2766 * @dev: the PCI device to enable
2768 * Enables bus-mastering on the device and calls pcibios_set_master()
2769 * to do the needed arch specific settings.
2771 void pci_set_master(struct pci_dev *dev)
2773 __pci_set_master(dev, true);
2774 pcibios_set_master(dev);
2778 * pci_clear_master - disables bus-mastering for device dev
2779 * @dev: the PCI device to disable
2781 void pci_clear_master(struct pci_dev *dev)
2783 __pci_set_master(dev, false);
2787 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2788 * @dev: the PCI device for which MWI is to be enabled
2790 * Helper function for pci_set_mwi.
2791 * Originally copied from drivers/net/acenic.c.
2792 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2794 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2796 int pci_set_cacheline_size(struct pci_dev *dev)
2800 if (!pci_cache_line_size)
2803 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2804 equal to or multiple of the right value. */
2805 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2806 if (cacheline_size >= pci_cache_line_size &&
2807 (cacheline_size % pci_cache_line_size) == 0)
2810 /* Write the correct value. */
2811 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2813 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2814 if (cacheline_size == pci_cache_line_size)
2817 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2818 "supported\n", pci_cache_line_size << 2);
2822 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2824 #ifdef PCI_DISABLE_MWI
2825 int pci_set_mwi(struct pci_dev *dev)
2830 int pci_try_set_mwi(struct pci_dev *dev)
2835 void pci_clear_mwi(struct pci_dev *dev)
2842 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2843 * @dev: the PCI device for which MWI is enabled
2845 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2847 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2850 pci_set_mwi(struct pci_dev *dev)
2855 rc = pci_set_cacheline_size(dev);
2859 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2860 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2861 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2862 cmd |= PCI_COMMAND_INVALIDATE;
2863 pci_write_config_word(dev, PCI_COMMAND, cmd);
2870 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2871 * @dev: the PCI device for which MWI is enabled
2873 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2874 * Callers are not required to check the return value.
2876 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2878 int pci_try_set_mwi(struct pci_dev *dev)
2880 int rc = pci_set_mwi(dev);
2885 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2886 * @dev: the PCI device to disable
2888 * Disables PCI Memory-Write-Invalidate transaction on the device
2891 pci_clear_mwi(struct pci_dev *dev)
2895 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2896 if (cmd & PCI_COMMAND_INVALIDATE) {
2897 cmd &= ~PCI_COMMAND_INVALIDATE;
2898 pci_write_config_word(dev, PCI_COMMAND, cmd);
2901 #endif /* ! PCI_DISABLE_MWI */
2904 * pci_intx - enables/disables PCI INTx for device dev
2905 * @pdev: the PCI device to operate on
2906 * @enable: boolean: whether to enable or disable PCI INTx
2908 * Enables/disables PCI INTx for device dev
2911 pci_intx(struct pci_dev *pdev, int enable)
2913 u16 pci_command, new;
2915 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2918 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2920 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2923 if (new != pci_command) {
2924 struct pci_devres *dr;
2926 pci_write_config_word(pdev, PCI_COMMAND, new);
2928 dr = find_pci_dr(pdev);
2929 if (dr && !dr->restore_intx) {
2930 dr->restore_intx = 1;
2931 dr->orig_intx = !enable;
2937 * pci_intx_mask_supported - probe for INTx masking support
2938 * @dev: the PCI device to operate on
2940 * Check if the device dev support INTx masking via the config space
2943 bool pci_intx_mask_supported(struct pci_dev *dev)
2945 bool mask_supported = false;
2948 if (dev->broken_intx_masking)
2951 pci_cfg_access_lock(dev);
2953 pci_read_config_word(dev, PCI_COMMAND, &orig);
2954 pci_write_config_word(dev, PCI_COMMAND,
2955 orig ^ PCI_COMMAND_INTX_DISABLE);
2956 pci_read_config_word(dev, PCI_COMMAND, &new);
2959 * There's no way to protect against hardware bugs or detect them
2960 * reliably, but as long as we know what the value should be, let's
2961 * go ahead and check it.
2963 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2964 dev_err(&dev->dev, "Command register changed from "
2965 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2966 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2967 mask_supported = true;
2968 pci_write_config_word(dev, PCI_COMMAND, orig);
2971 pci_cfg_access_unlock(dev);
2972 return mask_supported;
2974 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2976 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2978 struct pci_bus *bus = dev->bus;
2979 bool mask_updated = true;
2980 u32 cmd_status_dword;
2981 u16 origcmd, newcmd;
2982 unsigned long flags;
2986 * We do a single dword read to retrieve both command and status.
2987 * Document assumptions that make this possible.
2989 BUILD_BUG_ON(PCI_COMMAND % 4);
2990 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2992 raw_spin_lock_irqsave(&pci_lock, flags);
2994 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2996 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2999 * Check interrupt status register to see whether our device
3000 * triggered the interrupt (when masking) or the next IRQ is
3001 * already pending (when unmasking).
3003 if (mask != irq_pending) {
3004 mask_updated = false;
3008 origcmd = cmd_status_dword;
3009 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3011 newcmd |= PCI_COMMAND_INTX_DISABLE;
3012 if (newcmd != origcmd)
3013 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3016 raw_spin_unlock_irqrestore(&pci_lock, flags);
3018 return mask_updated;
3022 * pci_check_and_mask_intx - mask INTx on pending interrupt
3023 * @dev: the PCI device to operate on
3025 * Check if the device dev has its INTx line asserted, mask it and
3026 * return true in that case. False is returned if not interrupt was
3029 bool pci_check_and_mask_intx(struct pci_dev *dev)
3031 return pci_check_and_set_intx_mask(dev, true);
3033 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3036 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
3037 * @dev: the PCI device to operate on
3039 * Check if the device dev has its INTx line asserted, unmask it if not
3040 * and return true. False is returned and the mask remains active if
3041 * there was still an interrupt pending.
3043 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3045 return pci_check_and_set_intx_mask(dev, false);
3047 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3050 * pci_msi_off - disables any msi or msix capabilities
3051 * @dev: the PCI device to operate on
3053 * If you want to use msi see pci_enable_msi and friends.
3054 * This is a lower level primitive that allows us to disable
3055 * msi operation at the device level.
3057 void pci_msi_off(struct pci_dev *dev)
3062 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3064 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3065 control &= ~PCI_MSI_FLAGS_ENABLE;
3066 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3068 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3070 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3071 control &= ~PCI_MSIX_FLAGS_ENABLE;
3072 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3075 EXPORT_SYMBOL_GPL(pci_msi_off);
3077 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3079 return dma_set_max_seg_size(&dev->dev, size);
3081 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3083 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3085 return dma_set_seg_boundary(&dev->dev, mask);
3087 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3089 static int pcie_flr(struct pci_dev *dev, int probe)
3095 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3096 if (!(cap & PCI_EXP_DEVCAP_FLR))
3102 /* Wait for Transaction Pending bit clean */
3103 for (i = 0; i < 4; i++) {
3105 msleep((1 << (i - 1)) * 100);
3107 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3108 if (!(status & PCI_EXP_DEVSTA_TRPND))
3112 dev_err(&dev->dev, "transaction is not cleared; "
3113 "proceeding with reset anyway\n");
3116 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3123 static int pci_af_flr(struct pci_dev *dev, int probe)
3130 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3134 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3135 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3141 /* Wait for Transaction Pending bit clean */
3142 for (i = 0; i < 4; i++) {
3144 msleep((1 << (i - 1)) * 100);
3146 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3147 if (!(status & PCI_AF_STATUS_TP))
3151 dev_err(&dev->dev, "transaction is not cleared; "
3152 "proceeding with reset anyway\n");
3155 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3162 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3163 * @dev: Device to reset.
3164 * @probe: If set, only check if the device can be reset this way.
3166 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3167 * unset, it will be reinitialized internally when going from PCI_D3hot to
3168 * PCI_D0. If that's the case and the device is not in a low-power state
3169 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3171 * NOTE: This causes the caller to sleep for twice the device power transition
3172 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3173 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3174 * Moreover, only devices in D0 can be reset by this function.
3176 static int pci_pm_reset(struct pci_dev *dev, int probe)
3183 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3184 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3190 if (dev->current_state != PCI_D0)
3193 csr &= ~PCI_PM_CTRL_STATE_MASK;
3195 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3196 pci_dev_d3_sleep(dev);
3198 csr &= ~PCI_PM_CTRL_STATE_MASK;
3200 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3201 pci_dev_d3_sleep(dev);
3206 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3209 struct pci_dev *pdev;
3211 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3214 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3221 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3222 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3223 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3226 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3227 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3233 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3239 rc = pci_dev_specific_reset(dev, probe);
3243 rc = pcie_flr(dev, probe);
3247 rc = pci_af_flr(dev, probe);
3251 rc = pci_pm_reset(dev, probe);
3255 rc = pci_parent_bus_reset(dev, probe);
3260 static int pci_dev_reset(struct pci_dev *dev, int probe)
3265 pci_cfg_access_lock(dev);
3266 /* block PM suspend, driver probe, etc. */
3267 device_lock(&dev->dev);
3270 rc = __pci_dev_reset(dev, probe);
3273 device_unlock(&dev->dev);
3274 pci_cfg_access_unlock(dev);
3279 * __pci_reset_function - reset a PCI device function
3280 * @dev: PCI device to reset
3282 * Some devices allow an individual function to be reset without affecting
3283 * other functions in the same device. The PCI device must be responsive
3284 * to PCI config space in order to use this function.
3286 * The device function is presumed to be unused when this function is called.
3287 * Resetting the device will make the contents of PCI configuration space
3288 * random, so any caller of this must be prepared to reinitialise the
3289 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3292 * Returns 0 if the device function was successfully reset or negative if the
3293 * device doesn't support resetting a single function.
3295 int __pci_reset_function(struct pci_dev *dev)
3297 return pci_dev_reset(dev, 0);
3299 EXPORT_SYMBOL_GPL(__pci_reset_function);
3302 * __pci_reset_function_locked - reset a PCI device function while holding
3303 * the @dev mutex lock.
3304 * @dev: PCI device to reset
3306 * Some devices allow an individual function to be reset without affecting
3307 * other functions in the same device. The PCI device must be responsive
3308 * to PCI config space in order to use this function.
3310 * The device function is presumed to be unused and the caller is holding
3311 * the device mutex lock when this function is called.
3312 * Resetting the device will make the contents of PCI configuration space
3313 * random, so any caller of this must be prepared to reinitialise the
3314 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3317 * Returns 0 if the device function was successfully reset or negative if the
3318 * device doesn't support resetting a single function.
3320 int __pci_reset_function_locked(struct pci_dev *dev)
3322 return __pci_dev_reset(dev, 0);
3324 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3327 * pci_probe_reset_function - check whether the device can be safely reset
3328 * @dev: PCI device to reset
3330 * Some devices allow an individual function to be reset without affecting
3331 * other functions in the same device. The PCI device must be responsive
3332 * to PCI config space in order to use this function.
3334 * Returns 0 if the device function can be reset or negative if the
3335 * device doesn't support resetting a single function.
3337 int pci_probe_reset_function(struct pci_dev *dev)
3339 return pci_dev_reset(dev, 1);
3343 * pci_reset_function - quiesce and reset a PCI device function
3344 * @dev: PCI device to reset
3346 * Some devices allow an individual function to be reset without affecting
3347 * other functions in the same device. The PCI device must be responsive
3348 * to PCI config space in order to use this function.
3350 * This function does not just reset the PCI portion of a device, but
3351 * clears all the state associated with the device. This function differs
3352 * from __pci_reset_function in that it saves and restores device state
3355 * Returns 0 if the device function was successfully reset or negative if the
3356 * device doesn't support resetting a single function.
3358 int pci_reset_function(struct pci_dev *dev)
3362 rc = pci_dev_reset(dev, 1);
3366 pci_save_state(dev);
3369 * both INTx and MSI are disabled after the Interrupt Disable bit
3370 * is set and the Bus Master bit is cleared.
3372 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3374 rc = pci_dev_reset(dev, 0);
3376 pci_restore_state(dev);
3380 EXPORT_SYMBOL_GPL(pci_reset_function);
3383 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3384 * @dev: PCI device to query
3386 * Returns mmrbc: maximum designed memory read count in bytes
3387 * or appropriate error value.
3389 int pcix_get_max_mmrbc(struct pci_dev *dev)
3394 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3398 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3401 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3403 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3406 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3407 * @dev: PCI device to query
3409 * Returns mmrbc: maximum memory read count in bytes
3410 * or appropriate error value.
3412 int pcix_get_mmrbc(struct pci_dev *dev)
3417 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3421 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3424 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3426 EXPORT_SYMBOL(pcix_get_mmrbc);
3429 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3430 * @dev: PCI device to query
3431 * @mmrbc: maximum memory read count in bytes
3432 * valid values are 512, 1024, 2048, 4096
3434 * If possible sets maximum memory read byte count, some bridges have erratas
3435 * that prevent this.
3437 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3443 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3446 v = ffs(mmrbc) - 10;
3448 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3452 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3455 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3458 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3461 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3463 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3466 cmd &= ~PCI_X_CMD_MAX_READ;
3468 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3473 EXPORT_SYMBOL(pcix_set_mmrbc);
3476 * pcie_get_readrq - get PCI Express read request size
3477 * @dev: PCI device to query
3479 * Returns maximum memory read request in bytes
3480 * or appropriate error value.
3482 int pcie_get_readrq(struct pci_dev *dev)
3486 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3488 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3490 EXPORT_SYMBOL(pcie_get_readrq);
3493 * pcie_set_readrq - set PCI Express maximum memory read request
3494 * @dev: PCI device to query
3495 * @rq: maximum memory read count in bytes
3496 * valid values are 128, 256, 512, 1024, 2048, 4096
3498 * If possible sets maximum memory read request in bytes
3500 int pcie_set_readrq(struct pci_dev *dev, int rq)
3504 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3508 * If using the "performance" PCIe config, we clamp the
3509 * read rq size to the max packet size to prevent the
3510 * host bridge generating requests larger than we can
3513 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3514 int mps = pcie_get_mps(dev);
3522 v = (ffs(rq) - 8) << 12;
3524 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3525 PCI_EXP_DEVCTL_READRQ, v);
3527 EXPORT_SYMBOL(pcie_set_readrq);
3530 * pcie_get_mps - get PCI Express maximum payload size
3531 * @dev: PCI device to query
3533 * Returns maximum payload size in bytes
3534 * or appropriate error value.
3536 int pcie_get_mps(struct pci_dev *dev)
3540 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3542 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3546 * pcie_set_mps - set PCI Express maximum payload size
3547 * @dev: PCI device to query
3548 * @mps: maximum payload size in bytes
3549 * valid values are 128, 256, 512, 1024, 2048, 4096
3551 * If possible sets maximum payload size
3553 int pcie_set_mps(struct pci_dev *dev, int mps)
3557 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3561 if (v > dev->pcie_mpss)
3565 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3566 PCI_EXP_DEVCTL_PAYLOAD, v);
3570 * pci_select_bars - Make BAR mask from the type of resource
3571 * @dev: the PCI device for which BAR mask is made
3572 * @flags: resource type mask to be selected
3574 * This helper routine makes bar mask from the type of resource.
3576 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3579 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3580 if (pci_resource_flags(dev, i) & flags)
3586 * pci_resource_bar - get position of the BAR associated with a resource
3587 * @dev: the PCI device
3588 * @resno: the resource number
3589 * @type: the BAR type to be filled in
3591 * Returns BAR position in config space, or 0 if the BAR is invalid.
3593 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3597 if (resno < PCI_ROM_RESOURCE) {
3598 *type = pci_bar_unknown;
3599 return PCI_BASE_ADDRESS_0 + 4 * resno;
3600 } else if (resno == PCI_ROM_RESOURCE) {
3601 *type = pci_bar_mem32;
3602 return dev->rom_base_reg;
3603 } else if (resno < PCI_BRIDGE_RESOURCES) {
3604 /* device specific resource */
3605 reg = pci_iov_resource_bar(dev, resno, type);
3610 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3614 /* Some architectures require additional programming to enable VGA */
3615 static arch_set_vga_state_t arch_set_vga_state;
3617 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3619 arch_set_vga_state = func; /* NULL disables */
3622 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3623 unsigned int command_bits, u32 flags)
3625 if (arch_set_vga_state)
3626 return arch_set_vga_state(dev, decode, command_bits,
3632 * pci_set_vga_state - set VGA decode state on device and parents if requested
3633 * @dev: the PCI device
3634 * @decode: true = enable decoding, false = disable decoding
3635 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3636 * @flags: traverse ancestors and change bridges
3637 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3639 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3640 unsigned int command_bits, u32 flags)
3642 struct pci_bus *bus;
3643 struct pci_dev *bridge;
3647 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3649 /* ARCH specific VGA enables */
3650 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3654 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3655 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3657 cmd |= command_bits;
3659 cmd &= ~command_bits;
3660 pci_write_config_word(dev, PCI_COMMAND, cmd);
3663 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3670 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3673 cmd |= PCI_BRIDGE_CTL_VGA;
3675 cmd &= ~PCI_BRIDGE_CTL_VGA;
3676 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3684 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3685 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3686 static DEFINE_SPINLOCK(resource_alignment_lock);
3689 * pci_specified_resource_alignment - get resource alignment specified by user.
3690 * @dev: the PCI device to get
3692 * RETURNS: Resource alignment if it is specified.
3693 * Zero if it is not specified.
3695 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3697 int seg, bus, slot, func, align_order, count;
3698 resource_size_t align = 0;
3701 spin_lock(&resource_alignment_lock);
3702 p = resource_alignment_param;
3705 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3711 if (sscanf(p, "%x:%x:%x.%x%n",
3712 &seg, &bus, &slot, &func, &count) != 4) {
3714 if (sscanf(p, "%x:%x.%x%n",
3715 &bus, &slot, &func, &count) != 3) {
3716 /* Invalid format */
3717 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3723 if (seg == pci_domain_nr(dev->bus) &&
3724 bus == dev->bus->number &&
3725 slot == PCI_SLOT(dev->devfn) &&
3726 func == PCI_FUNC(dev->devfn)) {
3727 if (align_order == -1) {
3730 align = 1 << align_order;
3735 if (*p != ';' && *p != ',') {
3736 /* End of param or invalid format */
3741 spin_unlock(&resource_alignment_lock);
3746 * pci_is_reassigndev - check if specified PCI is target device to reassign
3747 * @dev: the PCI device to check
3749 * RETURNS: non-zero for PCI device is a target device to reassign,
3752 int pci_is_reassigndev(struct pci_dev *dev)
3754 return (pci_specified_resource_alignment(dev) != 0);
3758 * This function disables memory decoding and releases memory resources
3759 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3760 * It also rounds up size to specified alignment.
3761 * Later on, the kernel will assign page-aligned memory resource back
3764 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3768 resource_size_t align, size;
3771 if (!pci_is_reassigndev(dev))
3774 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3775 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3777 "Can't reassign resources to host bridge.\n");
3782 "Disabling memory decoding and releasing memory resources.\n");
3783 pci_read_config_word(dev, PCI_COMMAND, &command);
3784 command &= ~PCI_COMMAND_MEMORY;
3785 pci_write_config_word(dev, PCI_COMMAND, command);
3787 align = pci_specified_resource_alignment(dev);
3788 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3789 r = &dev->resource[i];
3790 if (!(r->flags & IORESOURCE_MEM))
3792 size = resource_size(r);
3796 "Rounding up size of resource #%d to %#llx.\n",
3797 i, (unsigned long long)size);
3802 /* Need to disable bridge's resource window,
3803 * to enable the kernel to reassign new resource
3806 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3807 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3808 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3809 r = &dev->resource[i];
3810 if (!(r->flags & IORESOURCE_MEM))
3812 r->end = resource_size(r) - 1;
3815 pci_disable_bridge_window(dev);
3819 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3821 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3822 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3823 spin_lock(&resource_alignment_lock);
3824 strncpy(resource_alignment_param, buf, count);
3825 resource_alignment_param[count] = '\0';
3826 spin_unlock(&resource_alignment_lock);
3830 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3833 spin_lock(&resource_alignment_lock);
3834 count = snprintf(buf, size, "%s", resource_alignment_param);
3835 spin_unlock(&resource_alignment_lock);
3839 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3841 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3844 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3845 const char *buf, size_t count)
3847 return pci_set_resource_alignment_param(buf, count);
3850 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3851 pci_resource_alignment_store);
3853 static int __init pci_resource_alignment_sysfs_init(void)
3855 return bus_create_file(&pci_bus_type,
3856 &bus_attr_resource_alignment);
3859 late_initcall(pci_resource_alignment_sysfs_init);
3861 static void pci_no_domains(void)
3863 #ifdef CONFIG_PCI_DOMAINS
3864 pci_domains_supported = 0;
3869 * pci_ext_cfg_avail - can we access extended PCI config space?
3871 * Returns 1 if we can access PCI extended config space (offsets
3872 * greater than 0xff). This is the default implementation. Architecture
3873 * implementations can override this.
3875 int __weak pci_ext_cfg_avail(void)
3880 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3883 EXPORT_SYMBOL(pci_fixup_cardbus);
3885 static int __init pci_setup(char *str)
3888 char *k = strchr(str, ',');
3891 if (*str && (str = pcibios_setup(str)) && *str) {
3892 if (!strcmp(str, "nomsi")) {
3894 } else if (!strcmp(str, "noaer")) {
3896 } else if (!strncmp(str, "realloc=", 8)) {
3897 pci_realloc_get_opt(str + 8);
3898 } else if (!strncmp(str, "realloc", 7)) {
3899 pci_realloc_get_opt("on");
3900 } else if (!strcmp(str, "nodomains")) {
3902 } else if (!strncmp(str, "noari", 5)) {
3903 pcie_ari_disabled = true;
3904 } else if (!strncmp(str, "cbiosize=", 9)) {
3905 pci_cardbus_io_size = memparse(str + 9, &str);
3906 } else if (!strncmp(str, "cbmemsize=", 10)) {
3907 pci_cardbus_mem_size = memparse(str + 10, &str);
3908 } else if (!strncmp(str, "resource_alignment=", 19)) {
3909 pci_set_resource_alignment_param(str + 19,
3911 } else if (!strncmp(str, "ecrc=", 5)) {
3912 pcie_ecrc_get_policy(str + 5);
3913 } else if (!strncmp(str, "hpiosize=", 9)) {
3914 pci_hotplug_io_size = memparse(str + 9, &str);
3915 } else if (!strncmp(str, "hpmemsize=", 10)) {
3916 pci_hotplug_mem_size = memparse(str + 10, &str);
3917 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3918 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3919 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3920 pcie_bus_config = PCIE_BUS_SAFE;
3921 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3922 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3923 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3924 pcie_bus_config = PCIE_BUS_PEER2PEER;
3925 } else if (!strncmp(str, "pcie_scan_all", 13)) {
3926 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
3928 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3936 early_param("pci", pci_setup);
3938 EXPORT_SYMBOL(pci_reenable_device);
3939 EXPORT_SYMBOL(pci_enable_device_io);
3940 EXPORT_SYMBOL(pci_enable_device_mem);
3941 EXPORT_SYMBOL(pci_enable_device);
3942 EXPORT_SYMBOL(pcim_enable_device);
3943 EXPORT_SYMBOL(pcim_pin_device);
3944 EXPORT_SYMBOL(pci_disable_device);
3945 EXPORT_SYMBOL(pci_find_capability);
3946 EXPORT_SYMBOL(pci_bus_find_capability);
3947 EXPORT_SYMBOL(pci_release_regions);
3948 EXPORT_SYMBOL(pci_request_regions);
3949 EXPORT_SYMBOL(pci_request_regions_exclusive);
3950 EXPORT_SYMBOL(pci_release_region);
3951 EXPORT_SYMBOL(pci_request_region);
3952 EXPORT_SYMBOL(pci_request_region_exclusive);
3953 EXPORT_SYMBOL(pci_release_selected_regions);
3954 EXPORT_SYMBOL(pci_request_selected_regions);
3955 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3956 EXPORT_SYMBOL(pci_set_master);
3957 EXPORT_SYMBOL(pci_clear_master);
3958 EXPORT_SYMBOL(pci_set_mwi);
3959 EXPORT_SYMBOL(pci_try_set_mwi);
3960 EXPORT_SYMBOL(pci_clear_mwi);
3961 EXPORT_SYMBOL_GPL(pci_intx);
3962 EXPORT_SYMBOL(pci_assign_resource);
3963 EXPORT_SYMBOL(pci_find_parent_resource);
3964 EXPORT_SYMBOL(pci_select_bars);
3966 EXPORT_SYMBOL(pci_set_power_state);
3967 EXPORT_SYMBOL(pci_save_state);
3968 EXPORT_SYMBOL(pci_restore_state);
3969 EXPORT_SYMBOL(pci_pme_capable);
3970 EXPORT_SYMBOL(pci_pme_active);
3971 EXPORT_SYMBOL(pci_wake_from_d3);
3972 EXPORT_SYMBOL(pci_target_state);
3973 EXPORT_SYMBOL(pci_prepare_to_sleep);
3974 EXPORT_SYMBOL(pci_back_from_sleep);
3975 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);