2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm-generic/pci-bridge.h>
26 #include <asm/setup.h>
29 const char *pci_power_names[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
32 EXPORT_SYMBOL_GPL(pci_power_names);
34 int isa_dma_bridge_buggy;
35 EXPORT_SYMBOL(isa_dma_bridge_buggy);
38 EXPORT_SYMBOL(pci_pci_problems);
40 unsigned int pci_pm_d3_delay;
42 static void pci_pme_list_scan(struct work_struct *work);
44 static LIST_HEAD(pci_pme_list);
45 static DEFINE_MUTEX(pci_pme_list_mutex);
46 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
48 struct pci_pme_device {
49 struct list_head list;
53 #define PME_TIMEOUT 1000 /* How long between PME checks */
55 static void pci_dev_d3_sleep(struct pci_dev *dev)
57 unsigned int delay = dev->d3_delay;
59 if (delay < pci_pm_d3_delay)
60 delay = pci_pm_d3_delay;
65 #ifdef CONFIG_PCI_DOMAINS
66 int pci_domains_supported = 1;
69 #define DEFAULT_CARDBUS_IO_SIZE (256)
70 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
72 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
73 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
75 #define DEFAULT_HOTPLUG_IO_SIZE (256)
76 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
78 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
79 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
84 * The default CLS is used if arch didn't set CLS explicitly and not
85 * all pci devices agree on the same value. Arch can override either
86 * the dfl or actual value as it sees fit. Don't forget this is
87 * measured in 32-bit words, not bytes.
89 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
90 u8 pci_cache_line_size;
93 * If we set up a device for bus mastering, we need to check the latency
94 * timer as certain BIOSes forget to set it properly.
96 unsigned int pcibios_max_latency = 255;
98 /* If set, the PCIe ARI capability will not be used. */
99 static bool pcie_ari_disabled;
102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
103 * @bus: pointer to PCI bus structure to search
105 * Given a PCI bus, returns the highest PCI bus number present in the set
106 * including the given PCI bus and its list of child PCI buses.
108 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
110 struct list_head *tmp;
111 unsigned char max, n;
113 max = bus->busn_res.end;
114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp));
121 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
123 #ifdef CONFIG_HAS_IOMEM
124 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
127 * Make sure the BAR is actually a memory resource, not an IO resource
129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
133 return ioremap_nocache(pci_resource_start(pdev, bar),
134 pci_resource_len(pdev, bar));
136 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
139 #define PCI_FIND_CAP_TTL 48
141 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
142 u8 pos, int cap, int *ttl)
147 pci_bus_read_config_byte(bus, devfn, pos, &pos);
151 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
157 pos += PCI_CAP_LIST_NEXT;
162 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
165 int ttl = PCI_FIND_CAP_TTL;
167 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
170 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
172 return __pci_find_next_cap(dev->bus, dev->devfn,
173 pos + PCI_CAP_LIST_NEXT, cap);
175 EXPORT_SYMBOL_GPL(pci_find_next_capability);
177 static int __pci_bus_find_cap_start(struct pci_bus *bus,
178 unsigned int devfn, u8 hdr_type)
182 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
183 if (!(status & PCI_STATUS_CAP_LIST))
187 case PCI_HEADER_TYPE_NORMAL:
188 case PCI_HEADER_TYPE_BRIDGE:
189 return PCI_CAPABILITY_LIST;
190 case PCI_HEADER_TYPE_CARDBUS:
191 return PCI_CB_CAPABILITY_LIST;
200 * pci_find_capability - query for devices' capabilities
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Tell if a device supports a given PCI capability.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
207 * support it. Possible values for @cap:
209 * %PCI_CAP_ID_PM Power Management
210 * %PCI_CAP_ID_AGP Accelerated Graphics Port
211 * %PCI_CAP_ID_VPD Vital Product Data
212 * %PCI_CAP_ID_SLOTID Slot Identification
213 * %PCI_CAP_ID_MSI Message Signalled Interrupts
214 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
215 * %PCI_CAP_ID_PCIX PCI-X
216 * %PCI_CAP_ID_EXP PCI Express
218 int pci_find_capability(struct pci_dev *dev, int cap)
222 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
224 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
230 * pci_bus_find_capability - query for devices' capabilities
231 * @bus: the PCI bus to query
232 * @devfn: PCI device to query
233 * @cap: capability code
235 * Like pci_find_capability() but works for pci devices that do not have a
236 * pci_dev structure set up yet.
238 * Returns the address of the requested capability structure within the
239 * device's PCI configuration space or 0 in case the device does not
242 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
247 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
249 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
251 pos = __pci_find_next_cap(bus, devfn, pos, cap);
257 * pci_find_next_ext_capability - Find an extended capability
258 * @dev: PCI device to query
259 * @start: address at which to start looking (0 to start at beginning of list)
260 * @cap: capability code
262 * Returns the address of the next matching extended capability structure
263 * within the device's PCI configuration space or 0 if the device does
264 * not support it. Some capabilities can occur several times, e.g., the
265 * vendor-specific capability, and this provides a way to find them all.
267 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
271 int pos = PCI_CFG_SPACE_SIZE;
273 /* minimum 8 bytes per capability */
274 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
286 * If we have no capabilities, this is indicated by cap ID,
287 * cap version and next pointer all being 0.
293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
296 pos = PCI_EXT_CAP_NEXT(header);
297 if (pos < PCI_CFG_SPACE_SIZE)
300 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
306 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
309 * pci_find_ext_capability - Find an extended capability
310 * @dev: PCI device to query
311 * @cap: capability code
313 * Returns the address of the requested extended capability structure
314 * within the device's PCI configuration space or 0 if the device does
315 * not support it. Possible values for @cap:
317 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
318 * %PCI_EXT_CAP_ID_VC Virtual Channel
319 * %PCI_EXT_CAP_ID_DSN Device Serial Number
320 * %PCI_EXT_CAP_ID_PWR Power Budgeting
322 int pci_find_ext_capability(struct pci_dev *dev, int cap)
324 return pci_find_next_ext_capability(dev, 0, cap);
326 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
328 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
330 int rc, ttl = PCI_FIND_CAP_TTL;
333 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
334 mask = HT_3BIT_CAP_MASK;
336 mask = HT_5BIT_CAP_MASK;
338 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
339 PCI_CAP_ID_HT, &ttl);
341 rc = pci_read_config_byte(dev, pos + 3, &cap);
342 if (rc != PCIBIOS_SUCCESSFUL)
345 if ((cap & mask) == ht_cap)
348 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
349 pos + PCI_CAP_LIST_NEXT,
350 PCI_CAP_ID_HT, &ttl);
356 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
357 * @dev: PCI device to query
358 * @pos: Position from which to continue searching
359 * @ht_cap: Hypertransport capability code
361 * To be used in conjunction with pci_find_ht_capability() to search for
362 * all capabilities matching @ht_cap. @pos should always be a value returned
363 * from pci_find_ht_capability().
365 * NB. To be 100% safe against broken PCI devices, the caller should take
366 * steps to avoid an infinite loop.
368 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
370 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
372 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
375 * pci_find_ht_capability - query a device's Hypertransport capabilities
376 * @dev: PCI device to query
377 * @ht_cap: Hypertransport capability code
379 * Tell if a device supports a given Hypertransport capability.
380 * Returns an address within the device's PCI configuration space
381 * or 0 in case the device does not support the request capability.
382 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
383 * which has a Hypertransport capability matching @ht_cap.
385 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
389 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
391 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
395 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
398 * pci_find_parent_resource - return resource region of parent bus of given region
399 * @dev: PCI device structure contains resources to be searched
400 * @res: child resource record for which parent is sought
402 * For given resource region of given device, return the resource
403 * region of parent bus the given region is contained in or where
404 * it should be allocated from.
407 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
409 const struct pci_bus *bus = dev->bus;
411 struct resource *best = NULL, *r;
413 pci_bus_for_each_resource(bus, r, i) {
416 if (res->start && !(res->start >= r->start && res->end <= r->end))
417 continue; /* Not contained */
418 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
419 continue; /* Wrong type */
420 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
421 return r; /* Exact match */
422 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
423 if (r->flags & IORESOURCE_PREFETCH)
425 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
433 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
434 * @dev: PCI device to have its BARs restored
436 * Restore the BAR values for a given device, so as to make it
437 * accessible by its driver.
440 pci_restore_bars(struct pci_dev *dev)
444 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
445 pci_update_resource(dev, i);
448 static struct pci_platform_pm_ops *pci_platform_pm;
450 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
452 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
455 pci_platform_pm = ops;
459 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
461 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
464 static inline int platform_pci_set_power_state(struct pci_dev *dev,
467 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
470 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
472 return pci_platform_pm ?
473 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
476 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
478 return pci_platform_pm ?
479 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
482 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
484 return pci_platform_pm ?
485 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
489 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
491 * @dev: PCI device to handle.
492 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
495 * -EINVAL if the requested state is invalid.
496 * -EIO if device does not support PCI PM or its PM capabilities register has a
497 * wrong version, or device doesn't support the requested state.
498 * 0 if device already is in the requested state.
499 * 0 if device's power state has been successfully changed.
501 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
504 bool need_restore = false;
506 /* Check if we're already there */
507 if (dev->current_state == state)
513 if (state < PCI_D0 || state > PCI_D3hot)
516 /* Validate current state:
517 * Can enter D0 from any state, but if we can only go deeper
518 * to sleep if we're already in a low power state
520 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
521 && dev->current_state > state) {
522 dev_err(&dev->dev, "invalid power transition "
523 "(from state %d to %d)\n", dev->current_state, state);
527 /* check if this device supports the desired state */
528 if ((state == PCI_D1 && !dev->d1_support)
529 || (state == PCI_D2 && !dev->d2_support))
532 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
534 /* If we're (effectively) in D3, force entire word to 0.
535 * This doesn't affect PME_Status, disables PME_En, and
536 * sets PowerState to 0.
538 switch (dev->current_state) {
542 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
547 case PCI_UNKNOWN: /* Boot-up */
548 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
549 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
551 /* Fall-through: force to D0 */
557 /* enter specified state */
558 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
560 /* Mandatory power management transition delays */
561 /* see PCI PM 1.1 5.6.1 table 18 */
562 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
563 pci_dev_d3_sleep(dev);
564 else if (state == PCI_D2 || dev->current_state == PCI_D2)
565 udelay(PCI_PM_D2_DELAY);
567 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
568 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
569 if (dev->current_state != state && printk_ratelimit())
570 dev_info(&dev->dev, "Refused to change power state, "
571 "currently in D%d\n", dev->current_state);
574 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
575 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
576 * from D3hot to D0 _may_ perform an internal reset, thereby
577 * going to "D0 Uninitialized" rather than "D0 Initialized".
578 * For example, at least some versions of the 3c905B and the
579 * 3c556B exhibit this behaviour.
581 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
582 * devices in a D3hot state at boot. Consequently, we need to
583 * restore at least the BARs so that the device will be
584 * accessible to its driver.
587 pci_restore_bars(dev);
590 pcie_aspm_pm_state_change(dev->bus->self);
596 * pci_update_current_state - Read PCI power state of given device from its
597 * PCI PM registers and cache it
598 * @dev: PCI device to handle.
599 * @state: State to cache in case the device doesn't have the PM capability
601 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
607 * Configuration space is not accessible for device in
608 * D3cold, so just keep or set D3cold for safety
610 if (dev->current_state == PCI_D3cold)
612 if (state == PCI_D3cold) {
613 dev->current_state = PCI_D3cold;
616 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
617 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
619 dev->current_state = state;
624 * pci_power_up - Put the given device into D0 forcibly
625 * @dev: PCI device to power up
627 void pci_power_up(struct pci_dev *dev)
629 if (platform_pci_power_manageable(dev))
630 platform_pci_set_power_state(dev, PCI_D0);
632 pci_raw_set_power_state(dev, PCI_D0);
633 pci_update_current_state(dev, PCI_D0);
637 * pci_platform_power_transition - Use platform to change device power state
638 * @dev: PCI device to handle.
639 * @state: State to put the device into.
641 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
645 if (platform_pci_power_manageable(dev)) {
646 error = platform_pci_set_power_state(dev, state);
648 pci_update_current_state(dev, state);
652 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
653 dev->current_state = PCI_D0;
659 * __pci_start_power_transition - Start power transition of a PCI device
660 * @dev: PCI device to handle.
661 * @state: State to put the device into.
663 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
665 if (state == PCI_D0) {
666 pci_platform_power_transition(dev, PCI_D0);
668 * Mandatory power management transition delays, see
669 * PCI Express Base Specification Revision 2.0 Section
670 * 6.6.1: Conventional Reset. Do not delay for
671 * devices powered on/off by corresponding bridge,
672 * because have already delayed for the bridge.
674 if (dev->runtime_d3cold) {
675 msleep(dev->d3cold_delay);
677 * When powering on a bridge from D3cold, the
678 * whole hierarchy may be powered on into
679 * D0uninitialized state, resume them to give
680 * them a chance to suspend again
682 pci_wakeup_bus(dev->subordinate);
688 * __pci_dev_set_current_state - Set current state of a PCI device
689 * @dev: Device to handle
690 * @data: pointer to state to be set
692 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
694 pci_power_t state = *(pci_power_t *)data;
696 dev->current_state = state;
701 * __pci_bus_set_current_state - Walk given bus and set current state of devices
702 * @bus: Top bus of the subtree to walk.
703 * @state: state to be set
705 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
708 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
712 * __pci_complete_power_transition - Complete power transition of a PCI device
713 * @dev: PCI device to handle.
714 * @state: State to put the device into.
716 * This function should not be called directly by device drivers.
718 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
724 ret = pci_platform_power_transition(dev, state);
725 /* Power off the bridge may power off the whole hierarchy */
726 if (!ret && state == PCI_D3cold)
727 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
730 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
733 * pci_set_power_state - Set the power state of a PCI device
734 * @dev: PCI device to handle.
735 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
737 * Transition a device to a new power state, using the platform firmware and/or
738 * the device's PCI PM registers.
741 * -EINVAL if the requested state is invalid.
742 * -EIO if device does not support PCI PM or its PM capabilities register has a
743 * wrong version, or device doesn't support the requested state.
744 * 0 if device already is in the requested state.
745 * 0 if device's power state has been successfully changed.
747 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
751 /* bound the state we're entering */
752 if (state > PCI_D3cold)
754 else if (state < PCI_D0)
756 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
758 * If the device or the parent bridge do not support PCI PM,
759 * ignore the request if we're doing anything other than putting
760 * it into D0 (which would only happen on boot).
764 /* Check if we're already there */
765 if (dev->current_state == state)
768 __pci_start_power_transition(dev, state);
770 /* This device is quirked not to be put into D3, so
771 don't put it in D3 */
772 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
776 * To put device in D3cold, we put device into D3hot in native
777 * way, then put device into D3cold with platform ops
779 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
782 if (!__pci_complete_power_transition(dev, state))
785 * When aspm_policy is "powersave" this call ensures
786 * that ASPM is configured.
788 if (!error && dev->bus->self)
789 pcie_aspm_powersave_config_link(dev->bus->self);
795 * pci_choose_state - Choose the power state of a PCI device
796 * @dev: PCI device to be suspended
797 * @state: target sleep state for the whole system. This is the value
798 * that is passed to suspend() function.
800 * Returns PCI power state suitable for given device and given system
804 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
811 ret = platform_pci_choose_state(dev);
812 if (ret != PCI_POWER_ERROR)
815 switch (state.event) {
818 case PM_EVENT_FREEZE:
819 case PM_EVENT_PRETHAW:
820 /* REVISIT both freeze and pre-thaw "should" use D0 */
821 case PM_EVENT_SUSPEND:
822 case PM_EVENT_HIBERNATE:
825 dev_info(&dev->dev, "unrecognized suspend event %d\n",
832 EXPORT_SYMBOL(pci_choose_state);
834 #define PCI_EXP_SAVE_REGS 7
837 static struct pci_cap_saved_state *pci_find_saved_cap(
838 struct pci_dev *pci_dev, char cap)
840 struct pci_cap_saved_state *tmp;
842 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
843 if (tmp->cap.cap_nr == cap)
849 static int pci_save_pcie_state(struct pci_dev *dev)
852 struct pci_cap_saved_state *save_state;
855 if (!pci_is_pcie(dev))
858 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
860 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
864 cap = (u16 *)&save_state->cap.data[0];
865 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
866 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
867 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
868 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
869 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
870 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
876 static void pci_restore_pcie_state(struct pci_dev *dev)
879 struct pci_cap_saved_state *save_state;
882 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
886 cap = (u16 *)&save_state->cap.data[0];
887 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
888 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
889 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
890 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
891 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
892 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
897 static int pci_save_pcix_state(struct pci_dev *dev)
900 struct pci_cap_saved_state *save_state;
902 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
906 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
908 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
912 pci_read_config_word(dev, pos + PCI_X_CMD,
913 (u16 *)save_state->cap.data);
918 static void pci_restore_pcix_state(struct pci_dev *dev)
921 struct pci_cap_saved_state *save_state;
924 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
925 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
926 if (!save_state || pos <= 0)
928 cap = (u16 *)&save_state->cap.data[0];
930 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
935 * pci_save_state - save the PCI configuration space of a device before suspending
936 * @dev: - PCI device that we're dealing with
939 pci_save_state(struct pci_dev *dev)
942 /* XXX: 100% dword access ok here? */
943 for (i = 0; i < 16; i++)
944 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
945 dev->state_saved = true;
946 if ((i = pci_save_pcie_state(dev)) != 0)
948 if ((i = pci_save_pcix_state(dev)) != 0)
953 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
954 u32 saved_val, int retry)
958 pci_read_config_dword(pdev, offset, &val);
959 if (val == saved_val)
963 dev_dbg(&pdev->dev, "restoring config space at offset "
964 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
965 pci_write_config_dword(pdev, offset, saved_val);
969 pci_read_config_dword(pdev, offset, &val);
970 if (val == saved_val)
977 static void pci_restore_config_space_range(struct pci_dev *pdev,
978 int start, int end, int retry)
982 for (index = end; index >= start; index--)
983 pci_restore_config_dword(pdev, 4 * index,
984 pdev->saved_config_space[index],
988 static void pci_restore_config_space(struct pci_dev *pdev)
990 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
991 pci_restore_config_space_range(pdev, 10, 15, 0);
992 /* Restore BARs before the command register. */
993 pci_restore_config_space_range(pdev, 4, 9, 10);
994 pci_restore_config_space_range(pdev, 0, 3, 0);
996 pci_restore_config_space_range(pdev, 0, 15, 0);
1001 * pci_restore_state - Restore the saved state of a PCI device
1002 * @dev: - PCI device that we're dealing with
1004 void pci_restore_state(struct pci_dev *dev)
1006 if (!dev->state_saved)
1009 /* PCI Express register must be restored first */
1010 pci_restore_pcie_state(dev);
1011 pci_restore_ats_state(dev);
1013 pci_restore_config_space(dev);
1015 pci_restore_pcix_state(dev);
1016 pci_restore_msi_state(dev);
1017 pci_restore_iov_state(dev);
1019 dev->state_saved = false;
1022 struct pci_saved_state {
1023 u32 config_space[16];
1024 struct pci_cap_saved_data cap[0];
1028 * pci_store_saved_state - Allocate and return an opaque struct containing
1029 * the device saved state.
1030 * @dev: PCI device that we're dealing with
1032 * Rerturn NULL if no state or error.
1034 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1036 struct pci_saved_state *state;
1037 struct pci_cap_saved_state *tmp;
1038 struct pci_cap_saved_data *cap;
1041 if (!dev->state_saved)
1044 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1046 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1047 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1049 state = kzalloc(size, GFP_KERNEL);
1053 memcpy(state->config_space, dev->saved_config_space,
1054 sizeof(state->config_space));
1057 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1058 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1059 memcpy(cap, &tmp->cap, len);
1060 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1062 /* Empty cap_save terminates list */
1066 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1069 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1070 * @dev: PCI device that we're dealing with
1071 * @state: Saved state returned from pci_store_saved_state()
1073 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1075 struct pci_cap_saved_data *cap;
1077 dev->state_saved = false;
1082 memcpy(dev->saved_config_space, state->config_space,
1083 sizeof(state->config_space));
1087 struct pci_cap_saved_state *tmp;
1089 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1090 if (!tmp || tmp->cap.size != cap->size)
1093 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1094 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1095 sizeof(struct pci_cap_saved_data) + cap->size);
1098 dev->state_saved = true;
1101 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1104 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1105 * and free the memory allocated for it.
1106 * @dev: PCI device that we're dealing with
1107 * @state: Pointer to saved state returned from pci_store_saved_state()
1109 int pci_load_and_free_saved_state(struct pci_dev *dev,
1110 struct pci_saved_state **state)
1112 int ret = pci_load_saved_state(dev, *state);
1117 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1119 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1123 err = pci_set_power_state(dev, PCI_D0);
1124 if (err < 0 && err != -EIO)
1126 err = pcibios_enable_device(dev, bars);
1129 pci_fixup_device(pci_fixup_enable, dev);
1135 * pci_reenable_device - Resume abandoned device
1136 * @dev: PCI device to be resumed
1138 * Note this function is a backend of pci_default_resume and is not supposed
1139 * to be called by normal code, write proper resume handler and use it instead.
1141 int pci_reenable_device(struct pci_dev *dev)
1143 if (pci_is_enabled(dev))
1144 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1148 static void pci_enable_bridge(struct pci_dev *dev)
1155 pci_enable_bridge(dev->bus->self);
1157 if (pci_is_enabled(dev))
1159 retval = pci_enable_device(dev);
1161 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1163 pci_set_master(dev);
1166 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1172 * Power state could be unknown at this point, either due to a fresh
1173 * boot or a device removal call. So get the current power state
1174 * so that things like MSI message writing will behave as expected
1175 * (e.g. if the device really is in D0 at enable time).
1179 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1180 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1183 if (atomic_inc_return(&dev->enable_cnt) > 1)
1184 return 0; /* already enabled */
1186 pci_enable_bridge(dev->bus->self);
1188 /* only skip sriov related */
1189 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1190 if (dev->resource[i].flags & flags)
1192 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1193 if (dev->resource[i].flags & flags)
1196 err = do_pci_enable_device(dev, bars);
1198 atomic_dec(&dev->enable_cnt);
1203 * pci_enable_device_io - Initialize a device for use with IO space
1204 * @dev: PCI device to be initialized
1206 * Initialize device before it's used by a driver. Ask low-level code
1207 * to enable I/O resources. Wake up the device if it was suspended.
1208 * Beware, this function can fail.
1210 int pci_enable_device_io(struct pci_dev *dev)
1212 return pci_enable_device_flags(dev, IORESOURCE_IO);
1216 * pci_enable_device_mem - Initialize a device for use with Memory space
1217 * @dev: PCI device to be initialized
1219 * Initialize device before it's used by a driver. Ask low-level code
1220 * to enable Memory resources. Wake up the device if it was suspended.
1221 * Beware, this function can fail.
1223 int pci_enable_device_mem(struct pci_dev *dev)
1225 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1229 * pci_enable_device - Initialize device before it's used by a driver.
1230 * @dev: PCI device to be initialized
1232 * Initialize device before it's used by a driver. Ask low-level code
1233 * to enable I/O and memory. Wake up the device if it was suspended.
1234 * Beware, this function can fail.
1236 * Note we don't actually enable the device many times if we call
1237 * this function repeatedly (we just increment the count).
1239 int pci_enable_device(struct pci_dev *dev)
1241 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1245 * Managed PCI resources. This manages device on/off, intx/msi/msix
1246 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1247 * there's no need to track it separately. pci_devres is initialized
1248 * when a device is enabled using managed PCI device enable interface.
1251 unsigned int enabled:1;
1252 unsigned int pinned:1;
1253 unsigned int orig_intx:1;
1254 unsigned int restore_intx:1;
1258 static void pcim_release(struct device *gendev, void *res)
1260 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1261 struct pci_devres *this = res;
1264 if (dev->msi_enabled)
1265 pci_disable_msi(dev);
1266 if (dev->msix_enabled)
1267 pci_disable_msix(dev);
1269 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1270 if (this->region_mask & (1 << i))
1271 pci_release_region(dev, i);
1273 if (this->restore_intx)
1274 pci_intx(dev, this->orig_intx);
1276 if (this->enabled && !this->pinned)
1277 pci_disable_device(dev);
1280 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1282 struct pci_devres *dr, *new_dr;
1284 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1288 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1291 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1294 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1296 if (pci_is_managed(pdev))
1297 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1302 * pcim_enable_device - Managed pci_enable_device()
1303 * @pdev: PCI device to be initialized
1305 * Managed pci_enable_device().
1307 int pcim_enable_device(struct pci_dev *pdev)
1309 struct pci_devres *dr;
1312 dr = get_pci_dr(pdev);
1318 rc = pci_enable_device(pdev);
1320 pdev->is_managed = 1;
1327 * pcim_pin_device - Pin managed PCI device
1328 * @pdev: PCI device to pin
1330 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1331 * driver detach. @pdev must have been enabled with
1332 * pcim_enable_device().
1334 void pcim_pin_device(struct pci_dev *pdev)
1336 struct pci_devres *dr;
1338 dr = find_pci_dr(pdev);
1339 WARN_ON(!dr || !dr->enabled);
1345 * pcibios_add_device - provide arch specific hooks when adding device dev
1346 * @dev: the PCI device being added
1348 * Permits the platform to provide architecture specific functionality when
1349 * devices are added. This is the default implementation. Architecture
1350 * implementations can override this.
1352 int __weak pcibios_add_device (struct pci_dev *dev)
1358 * pcibios_release_device - provide arch specific hooks when releasing device dev
1359 * @dev: the PCI device being released
1361 * Permits the platform to provide architecture specific functionality when
1362 * devices are released. This is the default implementation. Architecture
1363 * implementations can override this.
1365 void __weak pcibios_release_device(struct pci_dev *dev) {}
1368 * pcibios_disable_device - disable arch specific PCI resources for device dev
1369 * @dev: the PCI device to disable
1371 * Disables architecture specific PCI resources for the device. This
1372 * is the default implementation. Architecture implementations can
1375 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1377 static void do_pci_disable_device(struct pci_dev *dev)
1381 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1382 if (pci_command & PCI_COMMAND_MASTER) {
1383 pci_command &= ~PCI_COMMAND_MASTER;
1384 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1387 pcibios_disable_device(dev);
1391 * pci_disable_enabled_device - Disable device without updating enable_cnt
1392 * @dev: PCI device to disable
1394 * NOTE: This function is a backend of PCI power management routines and is
1395 * not supposed to be called drivers.
1397 void pci_disable_enabled_device(struct pci_dev *dev)
1399 if (pci_is_enabled(dev))
1400 do_pci_disable_device(dev);
1404 * pci_disable_device - Disable PCI device after use
1405 * @dev: PCI device to be disabled
1407 * Signal to the system that the PCI device is not in use by the system
1408 * anymore. This only involves disabling PCI bus-mastering, if active.
1410 * Note we don't actually disable the device until all callers of
1411 * pci_enable_device() have called pci_disable_device().
1414 pci_disable_device(struct pci_dev *dev)
1416 struct pci_devres *dr;
1418 dr = find_pci_dr(dev);
1422 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1423 "disabling already-disabled device");
1425 if (atomic_dec_return(&dev->enable_cnt) != 0)
1428 do_pci_disable_device(dev);
1430 dev->is_busmaster = 0;
1434 * pcibios_set_pcie_reset_state - set reset state for device dev
1435 * @dev: the PCIe device reset
1436 * @state: Reset state to enter into
1439 * Sets the PCIe reset state for the device. This is the default
1440 * implementation. Architecture implementations can override this.
1442 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1443 enum pcie_reset_state state)
1449 * pci_set_pcie_reset_state - set reset state for device dev
1450 * @dev: the PCIe device reset
1451 * @state: Reset state to enter into
1454 * Sets the PCI reset state for the device.
1456 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1458 return pcibios_set_pcie_reset_state(dev, state);
1462 * pci_check_pme_status - Check if given device has generated PME.
1463 * @dev: Device to check.
1465 * Check the PME status of the device and if set, clear it and clear PME enable
1466 * (if set). Return 'true' if PME status and PME enable were both set or
1467 * 'false' otherwise.
1469 bool pci_check_pme_status(struct pci_dev *dev)
1478 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1479 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1480 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1483 /* Clear PME status. */
1484 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1485 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1486 /* Disable PME to avoid interrupt flood. */
1487 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1491 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1497 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1498 * @dev: Device to handle.
1499 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1501 * Check if @dev has generated PME and queue a resume request for it in that
1504 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1506 if (pme_poll_reset && dev->pme_poll)
1507 dev->pme_poll = false;
1509 if (pci_check_pme_status(dev)) {
1510 pci_wakeup_event(dev);
1511 pm_request_resume(&dev->dev);
1517 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1518 * @bus: Top bus of the subtree to walk.
1520 void pci_pme_wakeup_bus(struct pci_bus *bus)
1523 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1527 * pci_wakeup - Wake up a PCI device
1528 * @pci_dev: Device to handle.
1529 * @ign: ignored parameter
1531 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1533 pci_wakeup_event(pci_dev);
1534 pm_request_resume(&pci_dev->dev);
1539 * pci_wakeup_bus - Walk given bus and wake up devices on it
1540 * @bus: Top bus of the subtree to walk.
1542 void pci_wakeup_bus(struct pci_bus *bus)
1545 pci_walk_bus(bus, pci_wakeup, NULL);
1549 * pci_pme_capable - check the capability of PCI device to generate PME#
1550 * @dev: PCI device to handle.
1551 * @state: PCI state from which device will issue PME#.
1553 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1558 return !!(dev->pme_support & (1 << state));
1561 static void pci_pme_list_scan(struct work_struct *work)
1563 struct pci_pme_device *pme_dev, *n;
1565 mutex_lock(&pci_pme_list_mutex);
1566 if (!list_empty(&pci_pme_list)) {
1567 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1568 if (pme_dev->dev->pme_poll) {
1569 struct pci_dev *bridge;
1571 bridge = pme_dev->dev->bus->self;
1573 * If bridge is in low power state, the
1574 * configuration space of subordinate devices
1575 * may be not accessible
1577 if (bridge && bridge->current_state != PCI_D0)
1579 pci_pme_wakeup(pme_dev->dev, NULL);
1581 list_del(&pme_dev->list);
1585 if (!list_empty(&pci_pme_list))
1586 schedule_delayed_work(&pci_pme_work,
1587 msecs_to_jiffies(PME_TIMEOUT));
1589 mutex_unlock(&pci_pme_list_mutex);
1593 * pci_pme_active - enable or disable PCI device's PME# function
1594 * @dev: PCI device to handle.
1595 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1597 * The caller must verify that the device is capable of generating PME# before
1598 * calling this function with @enable equal to 'true'.
1600 void pci_pme_active(struct pci_dev *dev, bool enable)
1604 if (!dev->pme_support)
1607 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1608 /* Clear PME_Status by writing 1 to it and enable PME# */
1609 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1611 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1613 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1616 * PCI (as opposed to PCIe) PME requires that the device have
1617 * its PME# line hooked up correctly. Not all hardware vendors
1618 * do this, so the PME never gets delivered and the device
1619 * remains asleep. The easiest way around this is to
1620 * periodically walk the list of suspended devices and check
1621 * whether any have their PME flag set. The assumption is that
1622 * we'll wake up often enough anyway that this won't be a huge
1623 * hit, and the power savings from the devices will still be a
1626 * Although PCIe uses in-band PME message instead of PME# line
1627 * to report PME, PME does not work for some PCIe devices in
1628 * reality. For example, there are devices that set their PME
1629 * status bits, but don't really bother to send a PME message;
1630 * there are PCI Express Root Ports that don't bother to
1631 * trigger interrupts when they receive PME messages from the
1632 * devices below. So PME poll is used for PCIe devices too.
1635 if (dev->pme_poll) {
1636 struct pci_pme_device *pme_dev;
1638 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1643 mutex_lock(&pci_pme_list_mutex);
1644 list_add(&pme_dev->list, &pci_pme_list);
1645 if (list_is_singular(&pci_pme_list))
1646 schedule_delayed_work(&pci_pme_work,
1647 msecs_to_jiffies(PME_TIMEOUT));
1648 mutex_unlock(&pci_pme_list_mutex);
1650 mutex_lock(&pci_pme_list_mutex);
1651 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1652 if (pme_dev->dev == dev) {
1653 list_del(&pme_dev->list);
1658 mutex_unlock(&pci_pme_list_mutex);
1663 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1667 * __pci_enable_wake - enable PCI device as wakeup event source
1668 * @dev: PCI device affected
1669 * @state: PCI state from which device will issue wakeup events
1670 * @runtime: True if the events are to be generated at run time
1671 * @enable: True to enable event generation; false to disable
1673 * This enables the device as a wakeup event source, or disables it.
1674 * When such events involves platform-specific hooks, those hooks are
1675 * called automatically by this routine.
1677 * Devices with legacy power management (no standard PCI PM capabilities)
1678 * always require such platform hooks.
1681 * 0 is returned on success
1682 * -EINVAL is returned if device is not supposed to wake up the system
1683 * Error code depending on the platform is returned if both the platform and
1684 * the native mechanism fail to enable the generation of wake-up events
1686 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1687 bool runtime, bool enable)
1691 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1694 /* Don't do the same thing twice in a row for one device. */
1695 if (!!enable == !!dev->wakeup_prepared)
1699 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1700 * Anderson we should be doing PME# wake enable followed by ACPI wake
1701 * enable. To disable wake-up we call the platform first, for symmetry.
1707 if (pci_pme_capable(dev, state))
1708 pci_pme_active(dev, true);
1711 error = runtime ? platform_pci_run_wake(dev, true) :
1712 platform_pci_sleep_wake(dev, true);
1716 dev->wakeup_prepared = true;
1719 platform_pci_run_wake(dev, false);
1721 platform_pci_sleep_wake(dev, false);
1722 pci_pme_active(dev, false);
1723 dev->wakeup_prepared = false;
1728 EXPORT_SYMBOL(__pci_enable_wake);
1731 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1732 * @dev: PCI device to prepare
1733 * @enable: True to enable wake-up event generation; false to disable
1735 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1736 * and this function allows them to set that up cleanly - pci_enable_wake()
1737 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1738 * ordering constraints.
1740 * This function only returns error code if the device is not capable of
1741 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1742 * enable wake-up power for it.
1744 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1746 return pci_pme_capable(dev, PCI_D3cold) ?
1747 pci_enable_wake(dev, PCI_D3cold, enable) :
1748 pci_enable_wake(dev, PCI_D3hot, enable);
1752 * pci_target_state - find an appropriate low power state for a given PCI dev
1755 * Use underlying platform code to find a supported low power state for @dev.
1756 * If the platform can't manage @dev, return the deepest state from which it
1757 * can generate wake events, based on any available PME info.
1759 pci_power_t pci_target_state(struct pci_dev *dev)
1761 pci_power_t target_state = PCI_D3hot;
1763 if (platform_pci_power_manageable(dev)) {
1765 * Call the platform to choose the target state of the device
1766 * and enable wake-up from this state if supported.
1768 pci_power_t state = platform_pci_choose_state(dev);
1771 case PCI_POWER_ERROR:
1776 if (pci_no_d1d2(dev))
1779 target_state = state;
1781 } else if (!dev->pm_cap) {
1782 target_state = PCI_D0;
1783 } else if (device_may_wakeup(&dev->dev)) {
1785 * Find the deepest state from which the device can generate
1786 * wake-up events, make it the target state and enable device
1789 if (dev->pme_support) {
1791 && !(dev->pme_support & (1 << target_state)))
1796 return target_state;
1800 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1801 * @dev: Device to handle.
1803 * Choose the power state appropriate for the device depending on whether
1804 * it can wake up the system and/or is power manageable by the platform
1805 * (PCI_D3hot is the default) and put the device into that state.
1807 int pci_prepare_to_sleep(struct pci_dev *dev)
1809 pci_power_t target_state = pci_target_state(dev);
1812 if (target_state == PCI_POWER_ERROR)
1815 /* D3cold during system suspend/hibernate is not supported */
1816 if (target_state > PCI_D3hot)
1817 target_state = PCI_D3hot;
1819 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1821 error = pci_set_power_state(dev, target_state);
1824 pci_enable_wake(dev, target_state, false);
1830 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1831 * @dev: Device to handle.
1833 * Disable device's system wake-up capability and put it into D0.
1835 int pci_back_from_sleep(struct pci_dev *dev)
1837 pci_enable_wake(dev, PCI_D0, false);
1838 return pci_set_power_state(dev, PCI_D0);
1842 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1843 * @dev: PCI device being suspended.
1845 * Prepare @dev to generate wake-up events at run time and put it into a low
1848 int pci_finish_runtime_suspend(struct pci_dev *dev)
1850 pci_power_t target_state = pci_target_state(dev);
1853 if (target_state == PCI_POWER_ERROR)
1856 dev->runtime_d3cold = target_state == PCI_D3cold;
1858 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1860 error = pci_set_power_state(dev, target_state);
1863 __pci_enable_wake(dev, target_state, true, false);
1864 dev->runtime_d3cold = false;
1871 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1872 * @dev: Device to check.
1874 * Return true if the device itself is cabable of generating wake-up events
1875 * (through the platform or using the native PCIe PME) or if the device supports
1876 * PME and one of its upstream bridges can generate wake-up events.
1878 bool pci_dev_run_wake(struct pci_dev *dev)
1880 struct pci_bus *bus = dev->bus;
1882 if (device_run_wake(&dev->dev))
1885 if (!dev->pme_support)
1888 while (bus->parent) {
1889 struct pci_dev *bridge = bus->self;
1891 if (device_run_wake(&bridge->dev))
1897 /* We have reached the root bus. */
1899 return device_run_wake(bus->bridge);
1903 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1905 void pci_config_pm_runtime_get(struct pci_dev *pdev)
1907 struct device *dev = &pdev->dev;
1908 struct device *parent = dev->parent;
1911 pm_runtime_get_sync(parent);
1912 pm_runtime_get_noresume(dev);
1914 * pdev->current_state is set to PCI_D3cold during suspending,
1915 * so wait until suspending completes
1917 pm_runtime_barrier(dev);
1919 * Only need to resume devices in D3cold, because config
1920 * registers are still accessible for devices suspended but
1923 if (pdev->current_state == PCI_D3cold)
1924 pm_runtime_resume(dev);
1927 void pci_config_pm_runtime_put(struct pci_dev *pdev)
1929 struct device *dev = &pdev->dev;
1930 struct device *parent = dev->parent;
1932 pm_runtime_put(dev);
1934 pm_runtime_put_sync(parent);
1938 * pci_pm_init - Initialize PM functions of given PCI device
1939 * @dev: PCI device to handle.
1941 void pci_pm_init(struct pci_dev *dev)
1946 pm_runtime_forbid(&dev->dev);
1947 pm_runtime_set_active(&dev->dev);
1948 pm_runtime_enable(&dev->dev);
1949 device_enable_async_suspend(&dev->dev);
1950 dev->wakeup_prepared = false;
1953 dev->pme_support = 0;
1955 /* find PCI PM capability in list */
1956 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1959 /* Check device's ability to generate PME# */
1960 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1962 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1963 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1964 pmc & PCI_PM_CAP_VER_MASK);
1969 dev->d3_delay = PCI_PM_D3_WAIT;
1970 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1971 dev->d3cold_allowed = true;
1973 dev->d1_support = false;
1974 dev->d2_support = false;
1975 if (!pci_no_d1d2(dev)) {
1976 if (pmc & PCI_PM_CAP_D1)
1977 dev->d1_support = true;
1978 if (pmc & PCI_PM_CAP_D2)
1979 dev->d2_support = true;
1981 if (dev->d1_support || dev->d2_support)
1982 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1983 dev->d1_support ? " D1" : "",
1984 dev->d2_support ? " D2" : "");
1987 pmc &= PCI_PM_CAP_PME_MASK;
1989 dev_printk(KERN_DEBUG, &dev->dev,
1990 "PME# supported from%s%s%s%s%s\n",
1991 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1992 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1993 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1994 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1995 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1996 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1997 dev->pme_poll = true;
1999 * Make device's PM flags reflect the wake-up capability, but
2000 * let the user space enable it to wake up the system as needed.
2002 device_set_wakeup_capable(&dev->dev, true);
2003 /* Disable the PME# generation functionality */
2004 pci_pme_active(dev, false);
2008 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2009 struct pci_cap_saved_state *new_cap)
2011 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2015 * pci_add_save_buffer - allocate buffer for saving given capability registers
2016 * @dev: the PCI device
2017 * @cap: the capability to allocate the buffer for
2018 * @size: requested size of the buffer
2020 static int pci_add_cap_save_buffer(
2021 struct pci_dev *dev, char cap, unsigned int size)
2024 struct pci_cap_saved_state *save_state;
2026 pos = pci_find_capability(dev, cap);
2030 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2034 save_state->cap.cap_nr = cap;
2035 save_state->cap.size = size;
2036 pci_add_saved_cap(dev, save_state);
2042 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2043 * @dev: the PCI device
2045 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2049 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2050 PCI_EXP_SAVE_REGS * sizeof(u16));
2053 "unable to preallocate PCI Express save buffer\n");
2055 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2058 "unable to preallocate PCI-X save buffer\n");
2061 void pci_free_cap_save_buffers(struct pci_dev *dev)
2063 struct pci_cap_saved_state *tmp;
2064 struct hlist_node *n;
2066 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2071 * pci_configure_ari - enable or disable ARI forwarding
2072 * @dev: the PCI device
2074 * If @dev and its upstream bridge both support ARI, enable ARI in the
2075 * bridge. Otherwise, disable ARI in the bridge.
2077 void pci_configure_ari(struct pci_dev *dev)
2080 struct pci_dev *bridge;
2082 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2085 bridge = dev->bus->self;
2089 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2090 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2093 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2094 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2095 PCI_EXP_DEVCTL2_ARI);
2096 bridge->ari_enabled = 1;
2098 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2099 PCI_EXP_DEVCTL2_ARI);
2100 bridge->ari_enabled = 0;
2105 * pci_enable_ido - enable ID-based Ordering on a device
2106 * @dev: the PCI device
2107 * @type: which types of IDO to enable
2109 * Enable ID-based ordering on @dev. @type can contain the bits
2110 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2111 * which types of transactions are allowed to be re-ordered.
2113 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2117 if (type & PCI_EXP_IDO_REQUEST)
2118 ctrl |= PCI_EXP_IDO_REQ_EN;
2119 if (type & PCI_EXP_IDO_COMPLETION)
2120 ctrl |= PCI_EXP_IDO_CMP_EN;
2122 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2124 EXPORT_SYMBOL(pci_enable_ido);
2127 * pci_disable_ido - disable ID-based ordering on a device
2128 * @dev: the PCI device
2129 * @type: which types of IDO to disable
2131 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2135 if (type & PCI_EXP_IDO_REQUEST)
2136 ctrl |= PCI_EXP_IDO_REQ_EN;
2137 if (type & PCI_EXP_IDO_COMPLETION)
2138 ctrl |= PCI_EXP_IDO_CMP_EN;
2140 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2142 EXPORT_SYMBOL(pci_disable_ido);
2145 * pci_enable_obff - enable optimized buffer flush/fill
2147 * @type: type of signaling to use
2149 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2150 * signaling if possible, falling back to message signaling only if
2151 * WAKE# isn't supported. @type should indicate whether the PCIe link
2152 * be brought out of L0s or L1 to send the message. It should be either
2153 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2155 * If your device can benefit from receiving all messages, even at the
2156 * power cost of bringing the link back up from a low power state, use
2157 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2161 * Zero on success, appropriate error number on failure.
2163 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2169 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2170 if (!(cap & PCI_EXP_OBFF_MASK))
2171 return -ENOTSUPP; /* no OBFF support at all */
2173 /* Make sure the topology supports OBFF as well */
2174 if (dev->bus->self) {
2175 ret = pci_enable_obff(dev->bus->self, type);
2180 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2181 if (cap & PCI_EXP_OBFF_WAKE)
2182 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2185 case PCI_EXP_OBFF_SIGNAL_L0:
2186 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2187 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2189 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2190 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2191 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2194 WARN(1, "bad OBFF signal type\n");
2198 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2202 EXPORT_SYMBOL(pci_enable_obff);
2205 * pci_disable_obff - disable optimized buffer flush/fill
2208 * Disable OBFF on @dev.
2210 void pci_disable_obff(struct pci_dev *dev)
2212 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
2214 EXPORT_SYMBOL(pci_disable_obff);
2217 * pci_ltr_supported - check whether a device supports LTR
2221 * True if @dev supports latency tolerance reporting, false otherwise.
2223 static bool pci_ltr_supported(struct pci_dev *dev)
2227 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2229 return cap & PCI_EXP_DEVCAP2_LTR;
2233 * pci_enable_ltr - enable latency tolerance reporting
2236 * Enable LTR on @dev if possible, which means enabling it first on
2240 * Zero on success, errno on failure.
2242 int pci_enable_ltr(struct pci_dev *dev)
2246 /* Only primary function can enable/disable LTR */
2247 if (PCI_FUNC(dev->devfn) != 0)
2250 if (!pci_ltr_supported(dev))
2253 /* Enable upstream ports first */
2254 if (dev->bus->self) {
2255 ret = pci_enable_ltr(dev->bus->self);
2260 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2262 EXPORT_SYMBOL(pci_enable_ltr);
2265 * pci_disable_ltr - disable latency tolerance reporting
2268 void pci_disable_ltr(struct pci_dev *dev)
2270 /* Only primary function can enable/disable LTR */
2271 if (PCI_FUNC(dev->devfn) != 0)
2274 if (!pci_ltr_supported(dev))
2277 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2279 EXPORT_SYMBOL(pci_disable_ltr);
2281 static int __pci_ltr_scale(int *val)
2285 while (*val > 1023) {
2286 *val = (*val + 31) / 32;
2293 * pci_set_ltr - set LTR latency values
2295 * @snoop_lat_ns: snoop latency in nanoseconds
2296 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2298 * Figure out the scale and set the LTR values accordingly.
2300 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2302 int pos, ret, snoop_scale, nosnoop_scale;
2305 if (!pci_ltr_supported(dev))
2308 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2309 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2311 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2312 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2315 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2316 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2319 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2323 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2324 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2328 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2329 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2335 EXPORT_SYMBOL(pci_set_ltr);
2337 static int pci_acs_enable;
2340 * pci_request_acs - ask for ACS to be enabled if supported
2342 void pci_request_acs(void)
2348 * pci_enable_acs - enable ACS if hardware support it
2349 * @dev: the PCI device
2351 void pci_enable_acs(struct pci_dev *dev)
2357 if (!pci_acs_enable)
2360 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2364 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2365 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2367 /* Source Validation */
2368 ctrl |= (cap & PCI_ACS_SV);
2370 /* P2P Request Redirect */
2371 ctrl |= (cap & PCI_ACS_RR);
2373 /* P2P Completion Redirect */
2374 ctrl |= (cap & PCI_ACS_CR);
2376 /* Upstream Forwarding */
2377 ctrl |= (cap & PCI_ACS_UF);
2379 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2383 * pci_acs_enabled - test ACS against required flags for a given device
2384 * @pdev: device to test
2385 * @acs_flags: required PCI ACS flags
2387 * Return true if the device supports the provided flags. Automatically
2388 * filters out flags that are not implemented on multifunction devices.
2390 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2395 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2399 if (!pci_is_pcie(pdev))
2402 /* Filter out flags not applicable to multifunction */
2403 if (pdev->multifunction)
2404 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2405 PCI_ACS_EC | PCI_ACS_DT);
2407 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2408 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
2409 pdev->multifunction) {
2410 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2414 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2415 if ((ctrl & acs_flags) != acs_flags)
2423 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2424 * @start: starting downstream device
2425 * @end: ending upstream device or NULL to search to the root bus
2426 * @acs_flags: required flags
2428 * Walk up a device tree from start to end testing PCI ACS support. If
2429 * any step along the way does not support the required flags, return false.
2431 bool pci_acs_path_enabled(struct pci_dev *start,
2432 struct pci_dev *end, u16 acs_flags)
2434 struct pci_dev *pdev, *parent = start;
2439 if (!pci_acs_enabled(pdev, acs_flags))
2442 if (pci_is_root_bus(pdev->bus))
2443 return (end == NULL);
2445 parent = pdev->bus->self;
2446 } while (pdev != end);
2452 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2453 * @dev: the PCI device
2454 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2456 * Perform INTx swizzling for a device behind one level of bridge. This is
2457 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2458 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2459 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2460 * the PCI Express Base Specification, Revision 2.1)
2462 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2466 if (pci_ari_enabled(dev->bus))
2469 slot = PCI_SLOT(dev->devfn);
2471 return (((pin - 1) + slot) % 4) + 1;
2475 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2483 while (!pci_is_root_bus(dev->bus)) {
2484 pin = pci_swizzle_interrupt_pin(dev, pin);
2485 dev = dev->bus->self;
2492 * pci_common_swizzle - swizzle INTx all the way to root bridge
2493 * @dev: the PCI device
2494 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2496 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2497 * bridges all the way up to a PCI root bus.
2499 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2503 while (!pci_is_root_bus(dev->bus)) {
2504 pin = pci_swizzle_interrupt_pin(dev, pin);
2505 dev = dev->bus->self;
2508 return PCI_SLOT(dev->devfn);
2512 * pci_release_region - Release a PCI bar
2513 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2514 * @bar: BAR to release
2516 * Releases the PCI I/O and memory resources previously reserved by a
2517 * successful call to pci_request_region. Call this function only
2518 * after all use of the PCI regions has ceased.
2520 void pci_release_region(struct pci_dev *pdev, int bar)
2522 struct pci_devres *dr;
2524 if (pci_resource_len(pdev, bar) == 0)
2526 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2527 release_region(pci_resource_start(pdev, bar),
2528 pci_resource_len(pdev, bar));
2529 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2530 release_mem_region(pci_resource_start(pdev, bar),
2531 pci_resource_len(pdev, bar));
2533 dr = find_pci_dr(pdev);
2535 dr->region_mask &= ~(1 << bar);
2539 * __pci_request_region - Reserved PCI I/O and memory resource
2540 * @pdev: PCI device whose resources are to be reserved
2541 * @bar: BAR to be reserved
2542 * @res_name: Name to be associated with resource.
2543 * @exclusive: whether the region access is exclusive or not
2545 * Mark the PCI region associated with PCI device @pdev BR @bar as
2546 * being reserved by owner @res_name. Do not access any
2547 * address inside the PCI regions unless this call returns
2550 * If @exclusive is set, then the region is marked so that userspace
2551 * is explicitly not allowed to map the resource via /dev/mem or
2552 * sysfs MMIO access.
2554 * Returns 0 on success, or %EBUSY on error. A warning
2555 * message is also printed on failure.
2557 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2560 struct pci_devres *dr;
2562 if (pci_resource_len(pdev, bar) == 0)
2565 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2566 if (!request_region(pci_resource_start(pdev, bar),
2567 pci_resource_len(pdev, bar), res_name))
2570 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2571 if (!__request_mem_region(pci_resource_start(pdev, bar),
2572 pci_resource_len(pdev, bar), res_name,
2577 dr = find_pci_dr(pdev);
2579 dr->region_mask |= 1 << bar;
2584 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2585 &pdev->resource[bar]);
2590 * pci_request_region - Reserve PCI I/O and memory resource
2591 * @pdev: PCI device whose resources are to be reserved
2592 * @bar: BAR to be reserved
2593 * @res_name: Name to be associated with resource
2595 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2596 * being reserved by owner @res_name. Do not access any
2597 * address inside the PCI regions unless this call returns
2600 * Returns 0 on success, or %EBUSY on error. A warning
2601 * message is also printed on failure.
2603 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2605 return __pci_request_region(pdev, bar, res_name, 0);
2609 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2610 * @pdev: PCI device whose resources are to be reserved
2611 * @bar: BAR to be reserved
2612 * @res_name: Name to be associated with resource.
2614 * Mark the PCI region associated with PCI device @pdev BR @bar as
2615 * being reserved by owner @res_name. Do not access any
2616 * address inside the PCI regions unless this call returns
2619 * Returns 0 on success, or %EBUSY on error. A warning
2620 * message is also printed on failure.
2622 * The key difference that _exclusive makes it that userspace is
2623 * explicitly not allowed to map the resource via /dev/mem or
2626 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2628 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2631 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2632 * @pdev: PCI device whose resources were previously reserved
2633 * @bars: Bitmask of BARs to be released
2635 * Release selected PCI I/O and memory resources previously reserved.
2636 * Call this function only after all use of the PCI regions has ceased.
2638 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2642 for (i = 0; i < 6; i++)
2643 if (bars & (1 << i))
2644 pci_release_region(pdev, i);
2647 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2648 const char *res_name, int excl)
2652 for (i = 0; i < 6; i++)
2653 if (bars & (1 << i))
2654 if (__pci_request_region(pdev, i, res_name, excl))
2660 if (bars & (1 << i))
2661 pci_release_region(pdev, i);
2668 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2669 * @pdev: PCI device whose resources are to be reserved
2670 * @bars: Bitmask of BARs to be requested
2671 * @res_name: Name to be associated with resource
2673 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2674 const char *res_name)
2676 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2679 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2680 int bars, const char *res_name)
2682 return __pci_request_selected_regions(pdev, bars, res_name,
2683 IORESOURCE_EXCLUSIVE);
2687 * pci_release_regions - Release reserved PCI I/O and memory resources
2688 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2690 * Releases all PCI I/O and memory resources previously reserved by a
2691 * successful call to pci_request_regions. Call this function only
2692 * after all use of the PCI regions has ceased.
2695 void pci_release_regions(struct pci_dev *pdev)
2697 pci_release_selected_regions(pdev, (1 << 6) - 1);
2701 * pci_request_regions - Reserved PCI I/O and memory resources
2702 * @pdev: PCI device whose resources are to be reserved
2703 * @res_name: Name to be associated with resource.
2705 * Mark all PCI regions associated with PCI device @pdev as
2706 * being reserved by owner @res_name. Do not access any
2707 * address inside the PCI regions unless this call returns
2710 * Returns 0 on success, or %EBUSY on error. A warning
2711 * message is also printed on failure.
2713 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2715 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2719 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2720 * @pdev: PCI device whose resources are to be reserved
2721 * @res_name: Name to be associated with resource.
2723 * Mark all PCI regions associated with PCI device @pdev as
2724 * being reserved by owner @res_name. Do not access any
2725 * address inside the PCI regions unless this call returns
2728 * pci_request_regions_exclusive() will mark the region so that
2729 * /dev/mem and the sysfs MMIO access will not be allowed.
2731 * Returns 0 on success, or %EBUSY on error. A warning
2732 * message is also printed on failure.
2734 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2736 return pci_request_selected_regions_exclusive(pdev,
2737 ((1 << 6) - 1), res_name);
2740 static void __pci_set_master(struct pci_dev *dev, bool enable)
2744 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2746 cmd = old_cmd | PCI_COMMAND_MASTER;
2748 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2749 if (cmd != old_cmd) {
2750 dev_dbg(&dev->dev, "%s bus mastering\n",
2751 enable ? "enabling" : "disabling");
2752 pci_write_config_word(dev, PCI_COMMAND, cmd);
2754 dev->is_busmaster = enable;
2758 * pcibios_setup - process "pci=" kernel boot arguments
2759 * @str: string used to pass in "pci=" kernel boot arguments
2761 * Process kernel boot arguments. This is the default implementation.
2762 * Architecture specific implementations can override this as necessary.
2764 char * __weak __init pcibios_setup(char *str)
2770 * pcibios_set_master - enable PCI bus-mastering for device dev
2771 * @dev: the PCI device to enable
2773 * Enables PCI bus-mastering for the device. This is the default
2774 * implementation. Architecture specific implementations can override
2775 * this if necessary.
2777 void __weak pcibios_set_master(struct pci_dev *dev)
2781 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2782 if (pci_is_pcie(dev))
2785 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2787 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2788 else if (lat > pcibios_max_latency)
2789 lat = pcibios_max_latency;
2792 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2793 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2797 * pci_set_master - enables bus-mastering for device dev
2798 * @dev: the PCI device to enable
2800 * Enables bus-mastering on the device and calls pcibios_set_master()
2801 * to do the needed arch specific settings.
2803 void pci_set_master(struct pci_dev *dev)
2805 __pci_set_master(dev, true);
2806 pcibios_set_master(dev);
2810 * pci_clear_master - disables bus-mastering for device dev
2811 * @dev: the PCI device to disable
2813 void pci_clear_master(struct pci_dev *dev)
2815 __pci_set_master(dev, false);
2819 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2820 * @dev: the PCI device for which MWI is to be enabled
2822 * Helper function for pci_set_mwi.
2823 * Originally copied from drivers/net/acenic.c.
2824 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2826 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2828 int pci_set_cacheline_size(struct pci_dev *dev)
2832 if (!pci_cache_line_size)
2835 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2836 equal to or multiple of the right value. */
2837 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2838 if (cacheline_size >= pci_cache_line_size &&
2839 (cacheline_size % pci_cache_line_size) == 0)
2842 /* Write the correct value. */
2843 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2845 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2846 if (cacheline_size == pci_cache_line_size)
2849 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2850 "supported\n", pci_cache_line_size << 2);
2854 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2856 #ifdef PCI_DISABLE_MWI
2857 int pci_set_mwi(struct pci_dev *dev)
2862 int pci_try_set_mwi(struct pci_dev *dev)
2867 void pci_clear_mwi(struct pci_dev *dev)
2874 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2875 * @dev: the PCI device for which MWI is enabled
2877 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2879 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2882 pci_set_mwi(struct pci_dev *dev)
2887 rc = pci_set_cacheline_size(dev);
2891 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2892 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2893 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2894 cmd |= PCI_COMMAND_INVALIDATE;
2895 pci_write_config_word(dev, PCI_COMMAND, cmd);
2902 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2903 * @dev: the PCI device for which MWI is enabled
2905 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2906 * Callers are not required to check the return value.
2908 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2910 int pci_try_set_mwi(struct pci_dev *dev)
2912 int rc = pci_set_mwi(dev);
2917 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2918 * @dev: the PCI device to disable
2920 * Disables PCI Memory-Write-Invalidate transaction on the device
2923 pci_clear_mwi(struct pci_dev *dev)
2927 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2928 if (cmd & PCI_COMMAND_INVALIDATE) {
2929 cmd &= ~PCI_COMMAND_INVALIDATE;
2930 pci_write_config_word(dev, PCI_COMMAND, cmd);
2933 #endif /* ! PCI_DISABLE_MWI */
2936 * pci_intx - enables/disables PCI INTx for device dev
2937 * @pdev: the PCI device to operate on
2938 * @enable: boolean: whether to enable or disable PCI INTx
2940 * Enables/disables PCI INTx for device dev
2943 pci_intx(struct pci_dev *pdev, int enable)
2945 u16 pci_command, new;
2947 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2950 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2952 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2955 if (new != pci_command) {
2956 struct pci_devres *dr;
2958 pci_write_config_word(pdev, PCI_COMMAND, new);
2960 dr = find_pci_dr(pdev);
2961 if (dr && !dr->restore_intx) {
2962 dr->restore_intx = 1;
2963 dr->orig_intx = !enable;
2969 * pci_intx_mask_supported - probe for INTx masking support
2970 * @dev: the PCI device to operate on
2972 * Check if the device dev support INTx masking via the config space
2975 bool pci_intx_mask_supported(struct pci_dev *dev)
2977 bool mask_supported = false;
2980 if (dev->broken_intx_masking)
2983 pci_cfg_access_lock(dev);
2985 pci_read_config_word(dev, PCI_COMMAND, &orig);
2986 pci_write_config_word(dev, PCI_COMMAND,
2987 orig ^ PCI_COMMAND_INTX_DISABLE);
2988 pci_read_config_word(dev, PCI_COMMAND, &new);
2991 * There's no way to protect against hardware bugs or detect them
2992 * reliably, but as long as we know what the value should be, let's
2993 * go ahead and check it.
2995 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2996 dev_err(&dev->dev, "Command register changed from "
2997 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2998 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2999 mask_supported = true;
3000 pci_write_config_word(dev, PCI_COMMAND, orig);
3003 pci_cfg_access_unlock(dev);
3004 return mask_supported;
3006 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3008 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3010 struct pci_bus *bus = dev->bus;
3011 bool mask_updated = true;
3012 u32 cmd_status_dword;
3013 u16 origcmd, newcmd;
3014 unsigned long flags;
3018 * We do a single dword read to retrieve both command and status.
3019 * Document assumptions that make this possible.
3021 BUILD_BUG_ON(PCI_COMMAND % 4);
3022 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3024 raw_spin_lock_irqsave(&pci_lock, flags);
3026 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3028 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3031 * Check interrupt status register to see whether our device
3032 * triggered the interrupt (when masking) or the next IRQ is
3033 * already pending (when unmasking).
3035 if (mask != irq_pending) {
3036 mask_updated = false;
3040 origcmd = cmd_status_dword;
3041 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3043 newcmd |= PCI_COMMAND_INTX_DISABLE;
3044 if (newcmd != origcmd)
3045 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3048 raw_spin_unlock_irqrestore(&pci_lock, flags);
3050 return mask_updated;
3054 * pci_check_and_mask_intx - mask INTx on pending interrupt
3055 * @dev: the PCI device to operate on
3057 * Check if the device dev has its INTx line asserted, mask it and
3058 * return true in that case. False is returned if not interrupt was
3061 bool pci_check_and_mask_intx(struct pci_dev *dev)
3063 return pci_check_and_set_intx_mask(dev, true);
3065 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3068 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
3069 * @dev: the PCI device to operate on
3071 * Check if the device dev has its INTx line asserted, unmask it if not
3072 * and return true. False is returned and the mask remains active if
3073 * there was still an interrupt pending.
3075 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3077 return pci_check_and_set_intx_mask(dev, false);
3079 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3082 * pci_msi_off - disables any msi or msix capabilities
3083 * @dev: the PCI device to operate on
3085 * If you want to use msi see pci_enable_msi and friends.
3086 * This is a lower level primitive that allows us to disable
3087 * msi operation at the device level.
3089 void pci_msi_off(struct pci_dev *dev)
3094 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3096 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3097 control &= ~PCI_MSI_FLAGS_ENABLE;
3098 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3100 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3102 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3103 control &= ~PCI_MSIX_FLAGS_ENABLE;
3104 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3107 EXPORT_SYMBOL_GPL(pci_msi_off);
3109 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3111 return dma_set_max_seg_size(&dev->dev, size);
3113 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3115 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3117 return dma_set_seg_boundary(&dev->dev, mask);
3119 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3121 static int pcie_flr(struct pci_dev *dev, int probe)
3127 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3128 if (!(cap & PCI_EXP_DEVCAP_FLR))
3134 /* Wait for Transaction Pending bit clean */
3135 for (i = 0; i < 4; i++) {
3137 msleep((1 << (i - 1)) * 100);
3139 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3140 if (!(status & PCI_EXP_DEVSTA_TRPND))
3144 dev_err(&dev->dev, "transaction is not cleared; "
3145 "proceeding with reset anyway\n");
3148 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3155 static int pci_af_flr(struct pci_dev *dev, int probe)
3162 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3166 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3167 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3173 /* Wait for Transaction Pending bit clean */
3174 for (i = 0; i < 4; i++) {
3176 msleep((1 << (i - 1)) * 100);
3178 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3179 if (!(status & PCI_AF_STATUS_TP))
3183 dev_err(&dev->dev, "transaction is not cleared; "
3184 "proceeding with reset anyway\n");
3187 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3194 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3195 * @dev: Device to reset.
3196 * @probe: If set, only check if the device can be reset this way.
3198 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3199 * unset, it will be reinitialized internally when going from PCI_D3hot to
3200 * PCI_D0. If that's the case and the device is not in a low-power state
3201 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3203 * NOTE: This causes the caller to sleep for twice the device power transition
3204 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3205 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3206 * Moreover, only devices in D0 can be reset by this function.
3208 static int pci_pm_reset(struct pci_dev *dev, int probe)
3215 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3216 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3222 if (dev->current_state != PCI_D0)
3225 csr &= ~PCI_PM_CTRL_STATE_MASK;
3227 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3228 pci_dev_d3_sleep(dev);
3230 csr &= ~PCI_PM_CTRL_STATE_MASK;
3232 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3233 pci_dev_d3_sleep(dev);
3238 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3241 struct pci_dev *pdev;
3243 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3246 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3253 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3254 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3255 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3258 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3259 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3265 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3271 rc = pci_dev_specific_reset(dev, probe);
3275 rc = pcie_flr(dev, probe);
3279 rc = pci_af_flr(dev, probe);
3283 rc = pci_pm_reset(dev, probe);
3287 rc = pci_parent_bus_reset(dev, probe);
3292 static int pci_dev_reset(struct pci_dev *dev, int probe)
3297 pci_cfg_access_lock(dev);
3298 /* block PM suspend, driver probe, etc. */
3299 device_lock(&dev->dev);
3302 rc = __pci_dev_reset(dev, probe);
3305 device_unlock(&dev->dev);
3306 pci_cfg_access_unlock(dev);
3311 * __pci_reset_function - reset a PCI device function
3312 * @dev: PCI device to reset
3314 * Some devices allow an individual function to be reset without affecting
3315 * other functions in the same device. The PCI device must be responsive
3316 * to PCI config space in order to use this function.
3318 * The device function is presumed to be unused when this function is called.
3319 * Resetting the device will make the contents of PCI configuration space
3320 * random, so any caller of this must be prepared to reinitialise the
3321 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3324 * Returns 0 if the device function was successfully reset or negative if the
3325 * device doesn't support resetting a single function.
3327 int __pci_reset_function(struct pci_dev *dev)
3329 return pci_dev_reset(dev, 0);
3331 EXPORT_SYMBOL_GPL(__pci_reset_function);
3334 * __pci_reset_function_locked - reset a PCI device function while holding
3335 * the @dev mutex lock.
3336 * @dev: PCI device to reset
3338 * Some devices allow an individual function to be reset without affecting
3339 * other functions in the same device. The PCI device must be responsive
3340 * to PCI config space in order to use this function.
3342 * The device function is presumed to be unused and the caller is holding
3343 * the device mutex lock when this function is called.
3344 * Resetting the device will make the contents of PCI configuration space
3345 * random, so any caller of this must be prepared to reinitialise the
3346 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3349 * Returns 0 if the device function was successfully reset or negative if the
3350 * device doesn't support resetting a single function.
3352 int __pci_reset_function_locked(struct pci_dev *dev)
3354 return __pci_dev_reset(dev, 0);
3356 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3359 * pci_probe_reset_function - check whether the device can be safely reset
3360 * @dev: PCI device to reset
3362 * Some devices allow an individual function to be reset without affecting
3363 * other functions in the same device. The PCI device must be responsive
3364 * to PCI config space in order to use this function.
3366 * Returns 0 if the device function can be reset or negative if the
3367 * device doesn't support resetting a single function.
3369 int pci_probe_reset_function(struct pci_dev *dev)
3371 return pci_dev_reset(dev, 1);
3375 * pci_reset_function - quiesce and reset a PCI device function
3376 * @dev: PCI device to reset
3378 * Some devices allow an individual function to be reset without affecting
3379 * other functions in the same device. The PCI device must be responsive
3380 * to PCI config space in order to use this function.
3382 * This function does not just reset the PCI portion of a device, but
3383 * clears all the state associated with the device. This function differs
3384 * from __pci_reset_function in that it saves and restores device state
3387 * Returns 0 if the device function was successfully reset or negative if the
3388 * device doesn't support resetting a single function.
3390 int pci_reset_function(struct pci_dev *dev)
3394 rc = pci_dev_reset(dev, 1);
3398 pci_save_state(dev);
3401 * both INTx and MSI are disabled after the Interrupt Disable bit
3402 * is set and the Bus Master bit is cleared.
3404 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3406 rc = pci_dev_reset(dev, 0);
3408 pci_restore_state(dev);
3412 EXPORT_SYMBOL_GPL(pci_reset_function);
3415 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3416 * @dev: PCI device to query
3418 * Returns mmrbc: maximum designed memory read count in bytes
3419 * or appropriate error value.
3421 int pcix_get_max_mmrbc(struct pci_dev *dev)
3426 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3430 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3433 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3435 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3438 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3439 * @dev: PCI device to query
3441 * Returns mmrbc: maximum memory read count in bytes
3442 * or appropriate error value.
3444 int pcix_get_mmrbc(struct pci_dev *dev)
3449 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3453 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3456 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3458 EXPORT_SYMBOL(pcix_get_mmrbc);
3461 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3462 * @dev: PCI device to query
3463 * @mmrbc: maximum memory read count in bytes
3464 * valid values are 512, 1024, 2048, 4096
3466 * If possible sets maximum memory read byte count, some bridges have erratas
3467 * that prevent this.
3469 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3475 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3478 v = ffs(mmrbc) - 10;
3480 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3484 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3487 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3490 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3493 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3495 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3498 cmd &= ~PCI_X_CMD_MAX_READ;
3500 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3505 EXPORT_SYMBOL(pcix_set_mmrbc);
3508 * pcie_get_readrq - get PCI Express read request size
3509 * @dev: PCI device to query
3511 * Returns maximum memory read request in bytes
3512 * or appropriate error value.
3514 int pcie_get_readrq(struct pci_dev *dev)
3518 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3520 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3522 EXPORT_SYMBOL(pcie_get_readrq);
3525 * pcie_set_readrq - set PCI Express maximum memory read request
3526 * @dev: PCI device to query
3527 * @rq: maximum memory read count in bytes
3528 * valid values are 128, 256, 512, 1024, 2048, 4096
3530 * If possible sets maximum memory read request in bytes
3532 int pcie_set_readrq(struct pci_dev *dev, int rq)
3536 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3540 * If using the "performance" PCIe config, we clamp the
3541 * read rq size to the max packet size to prevent the
3542 * host bridge generating requests larger than we can
3545 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3546 int mps = pcie_get_mps(dev);
3554 v = (ffs(rq) - 8) << 12;
3556 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3557 PCI_EXP_DEVCTL_READRQ, v);
3559 EXPORT_SYMBOL(pcie_set_readrq);
3562 * pcie_get_mps - get PCI Express maximum payload size
3563 * @dev: PCI device to query
3565 * Returns maximum payload size in bytes
3566 * or appropriate error value.
3568 int pcie_get_mps(struct pci_dev *dev)
3572 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3574 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3578 * pcie_set_mps - set PCI Express maximum payload size
3579 * @dev: PCI device to query
3580 * @mps: maximum payload size in bytes
3581 * valid values are 128, 256, 512, 1024, 2048, 4096
3583 * If possible sets maximum payload size
3585 int pcie_set_mps(struct pci_dev *dev, int mps)
3589 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3593 if (v > dev->pcie_mpss)
3597 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3598 PCI_EXP_DEVCTL_PAYLOAD, v);
3602 * pci_select_bars - Make BAR mask from the type of resource
3603 * @dev: the PCI device for which BAR mask is made
3604 * @flags: resource type mask to be selected
3606 * This helper routine makes bar mask from the type of resource.
3608 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3611 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3612 if (pci_resource_flags(dev, i) & flags)
3618 * pci_resource_bar - get position of the BAR associated with a resource
3619 * @dev: the PCI device
3620 * @resno: the resource number
3621 * @type: the BAR type to be filled in
3623 * Returns BAR position in config space, or 0 if the BAR is invalid.
3625 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3629 if (resno < PCI_ROM_RESOURCE) {
3630 *type = pci_bar_unknown;
3631 return PCI_BASE_ADDRESS_0 + 4 * resno;
3632 } else if (resno == PCI_ROM_RESOURCE) {
3633 *type = pci_bar_mem32;
3634 return dev->rom_base_reg;
3635 } else if (resno < PCI_BRIDGE_RESOURCES) {
3636 /* device specific resource */
3637 reg = pci_iov_resource_bar(dev, resno, type);
3642 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3646 /* Some architectures require additional programming to enable VGA */
3647 static arch_set_vga_state_t arch_set_vga_state;
3649 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3651 arch_set_vga_state = func; /* NULL disables */
3654 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3655 unsigned int command_bits, u32 flags)
3657 if (arch_set_vga_state)
3658 return arch_set_vga_state(dev, decode, command_bits,
3664 * pci_set_vga_state - set VGA decode state on device and parents if requested
3665 * @dev: the PCI device
3666 * @decode: true = enable decoding, false = disable decoding
3667 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3668 * @flags: traverse ancestors and change bridges
3669 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3671 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3672 unsigned int command_bits, u32 flags)
3674 struct pci_bus *bus;
3675 struct pci_dev *bridge;
3679 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3681 /* ARCH specific VGA enables */
3682 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3686 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3687 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3689 cmd |= command_bits;
3691 cmd &= ~command_bits;
3692 pci_write_config_word(dev, PCI_COMMAND, cmd);
3695 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3702 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3705 cmd |= PCI_BRIDGE_CTL_VGA;
3707 cmd &= ~PCI_BRIDGE_CTL_VGA;
3708 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3716 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3717 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3718 static DEFINE_SPINLOCK(resource_alignment_lock);
3721 * pci_specified_resource_alignment - get resource alignment specified by user.
3722 * @dev: the PCI device to get
3724 * RETURNS: Resource alignment if it is specified.
3725 * Zero if it is not specified.
3727 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3729 int seg, bus, slot, func, align_order, count;
3730 resource_size_t align = 0;
3733 spin_lock(&resource_alignment_lock);
3734 p = resource_alignment_param;
3737 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3743 if (sscanf(p, "%x:%x:%x.%x%n",
3744 &seg, &bus, &slot, &func, &count) != 4) {
3746 if (sscanf(p, "%x:%x.%x%n",
3747 &bus, &slot, &func, &count) != 3) {
3748 /* Invalid format */
3749 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3755 if (seg == pci_domain_nr(dev->bus) &&
3756 bus == dev->bus->number &&
3757 slot == PCI_SLOT(dev->devfn) &&
3758 func == PCI_FUNC(dev->devfn)) {
3759 if (align_order == -1) {
3762 align = 1 << align_order;
3767 if (*p != ';' && *p != ',') {
3768 /* End of param or invalid format */
3773 spin_unlock(&resource_alignment_lock);
3778 * This function disables memory decoding and releases memory resources
3779 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3780 * It also rounds up size to specified alignment.
3781 * Later on, the kernel will assign page-aligned memory resource back
3784 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3788 resource_size_t align, size;
3791 /* check if specified PCI is target device to reassign */
3792 align = pci_specified_resource_alignment(dev);
3796 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3797 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3799 "Can't reassign resources to host bridge.\n");
3804 "Disabling memory decoding and releasing memory resources.\n");
3805 pci_read_config_word(dev, PCI_COMMAND, &command);
3806 command &= ~PCI_COMMAND_MEMORY;
3807 pci_write_config_word(dev, PCI_COMMAND, command);
3809 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3810 r = &dev->resource[i];
3811 if (!(r->flags & IORESOURCE_MEM))
3813 size = resource_size(r);
3817 "Rounding up size of resource #%d to %#llx.\n",
3818 i, (unsigned long long)size);
3823 /* Need to disable bridge's resource window,
3824 * to enable the kernel to reassign new resource
3827 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3828 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3829 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3830 r = &dev->resource[i];
3831 if (!(r->flags & IORESOURCE_MEM))
3833 r->end = resource_size(r) - 1;
3836 pci_disable_bridge_window(dev);
3840 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3842 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3843 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3844 spin_lock(&resource_alignment_lock);
3845 strncpy(resource_alignment_param, buf, count);
3846 resource_alignment_param[count] = '\0';
3847 spin_unlock(&resource_alignment_lock);
3851 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3854 spin_lock(&resource_alignment_lock);
3855 count = snprintf(buf, size, "%s", resource_alignment_param);
3856 spin_unlock(&resource_alignment_lock);
3860 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3862 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3865 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3866 const char *buf, size_t count)
3868 return pci_set_resource_alignment_param(buf, count);
3871 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3872 pci_resource_alignment_store);
3874 static int __init pci_resource_alignment_sysfs_init(void)
3876 return bus_create_file(&pci_bus_type,
3877 &bus_attr_resource_alignment);
3880 late_initcall(pci_resource_alignment_sysfs_init);
3882 static void pci_no_domains(void)
3884 #ifdef CONFIG_PCI_DOMAINS
3885 pci_domains_supported = 0;
3890 * pci_ext_cfg_avail - can we access extended PCI config space?
3892 * Returns 1 if we can access PCI extended config space (offsets
3893 * greater than 0xff). This is the default implementation. Architecture
3894 * implementations can override this.
3896 int __weak pci_ext_cfg_avail(void)
3901 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3904 EXPORT_SYMBOL(pci_fixup_cardbus);
3906 static int __init pci_setup(char *str)
3909 char *k = strchr(str, ',');
3912 if (*str && (str = pcibios_setup(str)) && *str) {
3913 if (!strcmp(str, "nomsi")) {
3915 } else if (!strcmp(str, "noaer")) {
3917 } else if (!strncmp(str, "realloc=", 8)) {
3918 pci_realloc_get_opt(str + 8);
3919 } else if (!strncmp(str, "realloc", 7)) {
3920 pci_realloc_get_opt("on");
3921 } else if (!strcmp(str, "nodomains")) {
3923 } else if (!strncmp(str, "noari", 5)) {
3924 pcie_ari_disabled = true;
3925 } else if (!strncmp(str, "cbiosize=", 9)) {
3926 pci_cardbus_io_size = memparse(str + 9, &str);
3927 } else if (!strncmp(str, "cbmemsize=", 10)) {
3928 pci_cardbus_mem_size = memparse(str + 10, &str);
3929 } else if (!strncmp(str, "resource_alignment=", 19)) {
3930 pci_set_resource_alignment_param(str + 19,
3932 } else if (!strncmp(str, "ecrc=", 5)) {
3933 pcie_ecrc_get_policy(str + 5);
3934 } else if (!strncmp(str, "hpiosize=", 9)) {
3935 pci_hotplug_io_size = memparse(str + 9, &str);
3936 } else if (!strncmp(str, "hpmemsize=", 10)) {
3937 pci_hotplug_mem_size = memparse(str + 10, &str);
3938 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3939 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3940 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3941 pcie_bus_config = PCIE_BUS_SAFE;
3942 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3943 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3944 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3945 pcie_bus_config = PCIE_BUS_PEER2PEER;
3946 } else if (!strncmp(str, "pcie_scan_all", 13)) {
3947 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
3949 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3957 early_param("pci", pci_setup);
3959 EXPORT_SYMBOL(pci_reenable_device);
3960 EXPORT_SYMBOL(pci_enable_device_io);
3961 EXPORT_SYMBOL(pci_enable_device_mem);
3962 EXPORT_SYMBOL(pci_enable_device);
3963 EXPORT_SYMBOL(pcim_enable_device);
3964 EXPORT_SYMBOL(pcim_pin_device);
3965 EXPORT_SYMBOL(pci_disable_device);
3966 EXPORT_SYMBOL(pci_find_capability);
3967 EXPORT_SYMBOL(pci_bus_find_capability);
3968 EXPORT_SYMBOL(pci_release_regions);
3969 EXPORT_SYMBOL(pci_request_regions);
3970 EXPORT_SYMBOL(pci_request_regions_exclusive);
3971 EXPORT_SYMBOL(pci_release_region);
3972 EXPORT_SYMBOL(pci_request_region);
3973 EXPORT_SYMBOL(pci_request_region_exclusive);
3974 EXPORT_SYMBOL(pci_release_selected_regions);
3975 EXPORT_SYMBOL(pci_request_selected_regions);
3976 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3977 EXPORT_SYMBOL(pci_set_master);
3978 EXPORT_SYMBOL(pci_clear_master);
3979 EXPORT_SYMBOL(pci_set_mwi);
3980 EXPORT_SYMBOL(pci_try_set_mwi);
3981 EXPORT_SYMBOL(pci_clear_mwi);
3982 EXPORT_SYMBOL_GPL(pci_intx);
3983 EXPORT_SYMBOL(pci_assign_resource);
3984 EXPORT_SYMBOL(pci_find_parent_resource);
3985 EXPORT_SYMBOL(pci_select_bars);
3987 EXPORT_SYMBOL(pci_set_power_state);
3988 EXPORT_SYMBOL(pci_save_state);
3989 EXPORT_SYMBOL(pci_restore_state);
3990 EXPORT_SYMBOL(pci_pme_capable);
3991 EXPORT_SYMBOL(pci_pme_active);
3992 EXPORT_SYMBOL(pci_wake_from_d3);
3993 EXPORT_SYMBOL(pci_target_state);
3994 EXPORT_SYMBOL(pci_prepare_to_sleep);
3995 EXPORT_SYMBOL(pci_back_from_sleep);
3996 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);