2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_pme_list_scan(struct work_struct *work);
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47 struct pci_pme_device {
48 struct list_head list;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev *dev)
56 unsigned int delay = dev->d3_delay;
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81 * The default CLS is used if arch didn't set CLS explicitly and not
82 * all pci devices agree on the same value. Arch can override either
83 * the dfl or actual value as it sees fit. Don't forget this is
84 * measured in 32-bit words, not bytes.
86 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
87 u8 pci_cache_line_size;
90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
91 * @bus: pointer to PCI bus structure to search
93 * Given a PCI bus, returns the highest PCI bus number present in the set
94 * including the given PCI bus and its list of child PCI buses.
96 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
98 struct list_head *tmp;
101 max = bus->subordinate;
102 list_for_each(tmp, &bus->children) {
103 n = pci_bus_max_busnr(pci_bus_b(tmp));
109 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
111 #ifdef CONFIG_HAS_IOMEM
112 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
115 * Make sure the BAR is actually a memory resource, not an IO resource
117 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
121 return ioremap_nocache(pci_resource_start(pdev, bar),
122 pci_resource_len(pdev, bar));
124 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
129 * pci_max_busnr - returns maximum PCI bus number
131 * Returns the highest PCI bus number present in the system global list of
134 unsigned char __devinit
137 struct pci_bus *bus = NULL;
138 unsigned char max, n;
141 while ((bus = pci_find_next_bus(bus)) != NULL) {
142 n = pci_bus_max_busnr(bus);
151 #define PCI_FIND_CAP_TTL 48
153 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
154 u8 pos, int cap, int *ttl)
159 pci_bus_read_config_byte(bus, devfn, pos, &pos);
163 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
169 pos += PCI_CAP_LIST_NEXT;
174 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
177 int ttl = PCI_FIND_CAP_TTL;
179 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
182 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
184 return __pci_find_next_cap(dev->bus, dev->devfn,
185 pos + PCI_CAP_LIST_NEXT, cap);
187 EXPORT_SYMBOL_GPL(pci_find_next_capability);
189 static int __pci_bus_find_cap_start(struct pci_bus *bus,
190 unsigned int devfn, u8 hdr_type)
194 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
195 if (!(status & PCI_STATUS_CAP_LIST))
199 case PCI_HEADER_TYPE_NORMAL:
200 case PCI_HEADER_TYPE_BRIDGE:
201 return PCI_CAPABILITY_LIST;
202 case PCI_HEADER_TYPE_CARDBUS:
203 return PCI_CB_CAPABILITY_LIST;
212 * pci_find_capability - query for devices' capabilities
213 * @dev: PCI device to query
214 * @cap: capability code
216 * Tell if a device supports a given PCI capability.
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it. Possible values for @cap:
221 * %PCI_CAP_ID_PM Power Management
222 * %PCI_CAP_ID_AGP Accelerated Graphics Port
223 * %PCI_CAP_ID_VPD Vital Product Data
224 * %PCI_CAP_ID_SLOTID Slot Identification
225 * %PCI_CAP_ID_MSI Message Signalled Interrupts
226 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
227 * %PCI_CAP_ID_PCIX PCI-X
228 * %PCI_CAP_ID_EXP PCI Express
230 int pci_find_capability(struct pci_dev *dev, int cap)
234 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
236 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
242 * pci_bus_find_capability - query for devices' capabilities
243 * @bus: the PCI bus to query
244 * @devfn: PCI device to query
245 * @cap: capability code
247 * Like pci_find_capability() but works for pci devices that do not have a
248 * pci_dev structure set up yet.
250 * Returns the address of the requested capability structure within the
251 * device's PCI configuration space or 0 in case the device does not
254 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
259 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
261 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
263 pos = __pci_find_next_cap(bus, devfn, pos, cap);
269 * pci_find_ext_capability - Find an extended capability
270 * @dev: PCI device to query
271 * @cap: capability code
273 * Returns the address of the requested extended capability structure
274 * within the device's PCI configuration space or 0 if the device does
275 * not support it. Possible values for @cap:
277 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
278 * %PCI_EXT_CAP_ID_VC Virtual Channel
279 * %PCI_EXT_CAP_ID_DSN Device Serial Number
280 * %PCI_EXT_CAP_ID_PWR Power Budgeting
282 int pci_find_ext_capability(struct pci_dev *dev, int cap)
286 int pos = PCI_CFG_SPACE_SIZE;
288 /* minimum 8 bytes per capability */
289 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
291 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
294 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
298 * If we have no capabilities, this is indicated by cap ID,
299 * cap version and next pointer all being 0.
305 if (PCI_EXT_CAP_ID(header) == cap)
308 pos = PCI_EXT_CAP_NEXT(header);
309 if (pos < PCI_CFG_SPACE_SIZE)
312 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
318 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
321 * pci_bus_find_ext_capability - find an extended capability
322 * @bus: the PCI bus to query
323 * @devfn: PCI device to query
324 * @cap: capability code
326 * Like pci_find_ext_capability() but works for pci devices that do not have a
327 * pci_dev structure set up yet.
329 * Returns the address of the requested capability structure within the
330 * device's PCI configuration space or 0 in case the device does not
333 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
338 int pos = PCI_CFG_SPACE_SIZE;
340 /* minimum 8 bytes per capability */
341 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
345 if (header == 0xffffffff || header == 0)
349 if (PCI_EXT_CAP_ID(header) == cap)
352 pos = PCI_EXT_CAP_NEXT(header);
353 if (pos < PCI_CFG_SPACE_SIZE)
356 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
363 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
365 int rc, ttl = PCI_FIND_CAP_TTL;
368 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
369 mask = HT_3BIT_CAP_MASK;
371 mask = HT_5BIT_CAP_MASK;
373 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
374 PCI_CAP_ID_HT, &ttl);
376 rc = pci_read_config_byte(dev, pos + 3, &cap);
377 if (rc != PCIBIOS_SUCCESSFUL)
380 if ((cap & mask) == ht_cap)
383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
384 pos + PCI_CAP_LIST_NEXT,
385 PCI_CAP_ID_HT, &ttl);
391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
392 * @dev: PCI device to query
393 * @pos: Position from which to continue searching
394 * @ht_cap: Hypertransport capability code
396 * To be used in conjunction with pci_find_ht_capability() to search for
397 * all capabilities matching @ht_cap. @pos should always be a value returned
398 * from pci_find_ht_capability().
400 * NB. To be 100% safe against broken PCI devices, the caller should take
401 * steps to avoid an infinite loop.
403 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
405 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
407 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
410 * pci_find_ht_capability - query a device's Hypertransport capabilities
411 * @dev: PCI device to query
412 * @ht_cap: Hypertransport capability code
414 * Tell if a device supports a given Hypertransport capability.
415 * Returns an address within the device's PCI configuration space
416 * or 0 in case the device does not support the request capability.
417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
418 * which has a Hypertransport capability matching @ht_cap.
420 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
424 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
426 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
430 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
433 * pci_find_parent_resource - return resource region of parent bus of given region
434 * @dev: PCI device structure contains resources to be searched
435 * @res: child resource record for which parent is sought
437 * For given resource region of given device, return the resource
438 * region of parent bus the given region is contained in or where
439 * it should be allocated from.
442 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
444 const struct pci_bus *bus = dev->bus;
446 struct resource *best = NULL, *r;
448 pci_bus_for_each_resource(bus, r, i) {
451 if (res->start && !(res->start >= r->start && res->end <= r->end))
452 continue; /* Not contained */
453 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
454 continue; /* Wrong type */
455 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
456 return r; /* Exact match */
457 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
458 if (r->flags & IORESOURCE_PREFETCH)
460 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
469 * @dev: PCI device to have its BARs restored
471 * Restore the BAR values for a given device, so as to make it
472 * accessible by its driver.
475 pci_restore_bars(struct pci_dev *dev)
479 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
480 pci_update_resource(dev, i);
483 static struct pci_platform_pm_ops *pci_platform_pm;
485 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
487 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
488 || !ops->sleep_wake || !ops->can_wakeup)
490 pci_platform_pm = ops;
494 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
496 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
499 static inline int platform_pci_set_power_state(struct pci_dev *dev,
502 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
505 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
507 return pci_platform_pm ?
508 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
511 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
513 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
516 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
518 return pci_platform_pm ?
519 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
522 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
524 return pci_platform_pm ?
525 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
531 * @dev: PCI device to handle.
532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
535 * -EINVAL if the requested state is invalid.
536 * -EIO if device does not support PCI PM or its PM capabilities register has a
537 * wrong version, or device doesn't support the requested state.
538 * 0 if device already is in the requested state.
539 * 0 if device's power state has been successfully changed.
541 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
544 bool need_restore = false;
546 /* Check if we're already there */
547 if (dev->current_state == state)
553 if (state < PCI_D0 || state > PCI_D3hot)
556 /* Validate current state:
557 * Can enter D0 from any state, but if we can only go deeper
558 * to sleep if we're already in a low power state
560 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
561 && dev->current_state > state) {
562 dev_err(&dev->dev, "invalid power transition "
563 "(from state %d to %d)\n", dev->current_state, state);
567 /* check if this device supports the desired state */
568 if ((state == PCI_D1 && !dev->d1_support)
569 || (state == PCI_D2 && !dev->d2_support))
572 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
574 /* If we're (effectively) in D3, force entire word to 0.
575 * This doesn't affect PME_Status, disables PME_En, and
576 * sets PowerState to 0.
578 switch (dev->current_state) {
582 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
587 case PCI_UNKNOWN: /* Boot-up */
588 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
589 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
591 /* Fall-through: force to D0 */
597 /* enter specified state */
598 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
600 /* Mandatory power management transition delays */
601 /* see PCI PM 1.1 5.6.1 table 18 */
602 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
603 pci_dev_d3_sleep(dev);
604 else if (state == PCI_D2 || dev->current_state == PCI_D2)
605 udelay(PCI_PM_D2_DELAY);
607 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
608 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
609 if (dev->current_state != state && printk_ratelimit())
610 dev_info(&dev->dev, "Refused to change power state, "
611 "currently in D%d\n", dev->current_state);
613 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
614 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
615 * from D3hot to D0 _may_ perform an internal reset, thereby
616 * going to "D0 Uninitialized" rather than "D0 Initialized".
617 * For example, at least some versions of the 3c905B and the
618 * 3c556B exhibit this behaviour.
620 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
621 * devices in a D3hot state at boot. Consequently, we need to
622 * restore at least the BARs so that the device will be
623 * accessible to its driver.
626 pci_restore_bars(dev);
629 pcie_aspm_pm_state_change(dev->bus->self);
635 * pci_update_current_state - Read PCI power state of given device from its
636 * PCI PM registers and cache it
637 * @dev: PCI device to handle.
638 * @state: State to cache in case the device doesn't have the PM capability
640 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
645 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
646 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
648 dev->current_state = state;
653 * pci_platform_power_transition - Use platform to change device power state
654 * @dev: PCI device to handle.
655 * @state: State to put the device into.
657 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
661 if (platform_pci_power_manageable(dev)) {
662 error = platform_pci_set_power_state(dev, state);
664 pci_update_current_state(dev, state);
667 /* Fall back to PCI_D0 if native PM is not supported */
669 dev->current_state = PCI_D0;
676 * __pci_start_power_transition - Start power transition of a PCI device
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
680 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
683 pci_platform_power_transition(dev, PCI_D0);
687 * __pci_complete_power_transition - Complete power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
691 * This function should not be called directly by device drivers.
693 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
695 return state >= PCI_D0 ?
696 pci_platform_power_transition(dev, state) : -EINVAL;
698 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
701 * pci_set_power_state - Set the power state of a PCI device
702 * @dev: PCI device to handle.
703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
705 * Transition a device to a new power state, using the platform firmware and/or
706 * the device's PCI PM registers.
709 * -EINVAL if the requested state is invalid.
710 * -EIO if device does not support PCI PM or its PM capabilities register has a
711 * wrong version, or device doesn't support the requested state.
712 * 0 if device already is in the requested state.
713 * 0 if device's power state has been successfully changed.
715 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
719 /* bound the state we're entering */
720 if (state > PCI_D3hot)
722 else if (state < PCI_D0)
724 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
726 * If the device or the parent bridge do not support PCI PM,
727 * ignore the request if we're doing anything other than putting
728 * it into D0 (which would only happen on boot).
732 __pci_start_power_transition(dev, state);
734 /* This device is quirked not to be put into D3, so
735 don't put it in D3 */
736 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
739 error = pci_raw_set_power_state(dev, state);
741 if (!__pci_complete_power_transition(dev, state))
744 * When aspm_policy is "powersave" this call ensures
745 * that ASPM is configured.
747 if (!error && dev->bus->self)
748 pcie_aspm_powersave_config_link(dev->bus->self);
754 * pci_choose_state - Choose the power state of a PCI device
755 * @dev: PCI device to be suspended
756 * @state: target sleep state for the whole system. This is the value
757 * that is passed to suspend() function.
759 * Returns PCI power state suitable for given device and given system
763 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
767 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
770 ret = platform_pci_choose_state(dev);
771 if (ret != PCI_POWER_ERROR)
774 switch (state.event) {
777 case PM_EVENT_FREEZE:
778 case PM_EVENT_PRETHAW:
779 /* REVISIT both freeze and pre-thaw "should" use D0 */
780 case PM_EVENT_SUSPEND:
781 case PM_EVENT_HIBERNATE:
784 dev_info(&dev->dev, "unrecognized suspend event %d\n",
791 EXPORT_SYMBOL(pci_choose_state);
793 #define PCI_EXP_SAVE_REGS 7
795 #define pcie_cap_has_devctl(type, flags) 1
796 #define pcie_cap_has_lnkctl(type, flags) \
797 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
798 (type == PCI_EXP_TYPE_ROOT_PORT || \
799 type == PCI_EXP_TYPE_ENDPOINT || \
800 type == PCI_EXP_TYPE_LEG_END))
801 #define pcie_cap_has_sltctl(type, flags) \
802 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
803 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
804 (type == PCI_EXP_TYPE_DOWNSTREAM && \
805 (flags & PCI_EXP_FLAGS_SLOT))))
806 #define pcie_cap_has_rtctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 (type == PCI_EXP_TYPE_ROOT_PORT || \
809 type == PCI_EXP_TYPE_RC_EC))
810 #define pcie_cap_has_devctl2(type, flags) \
811 ((flags & PCI_EXP_FLAGS_VERS) > 1)
812 #define pcie_cap_has_lnkctl2(type, flags) \
813 ((flags & PCI_EXP_FLAGS_VERS) > 1)
814 #define pcie_cap_has_sltctl2(type, flags) \
815 ((flags & PCI_EXP_FLAGS_VERS) > 1)
817 static int pci_save_pcie_state(struct pci_dev *dev)
820 struct pci_cap_saved_state *save_state;
824 pos = pci_pcie_cap(dev);
828 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
830 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
833 cap = (u16 *)&save_state->cap.data[0];
835 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
837 if (pcie_cap_has_devctl(dev->pcie_type, flags))
838 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
839 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
840 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
841 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
842 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
843 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
844 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
845 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
846 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
847 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
848 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
849 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
850 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
855 static void pci_restore_pcie_state(struct pci_dev *dev)
858 struct pci_cap_saved_state *save_state;
862 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
863 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
864 if (!save_state || pos <= 0)
866 cap = (u16 *)&save_state->cap.data[0];
868 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
870 if (pcie_cap_has_devctl(dev->pcie_type, flags))
871 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
872 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
873 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
874 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
875 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
876 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
877 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
878 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
879 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
880 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
881 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
882 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
883 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
887 static int pci_save_pcix_state(struct pci_dev *dev)
890 struct pci_cap_saved_state *save_state;
892 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
896 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
898 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
902 pci_read_config_word(dev, pos + PCI_X_CMD,
903 (u16 *)save_state->cap.data);
908 static void pci_restore_pcix_state(struct pci_dev *dev)
911 struct pci_cap_saved_state *save_state;
914 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
915 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
916 if (!save_state || pos <= 0)
918 cap = (u16 *)&save_state->cap.data[0];
920 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
925 * pci_save_state - save the PCI configuration space of a device before suspending
926 * @dev: - PCI device that we're dealing with
929 pci_save_state(struct pci_dev *dev)
932 /* XXX: 100% dword access ok here? */
933 for (i = 0; i < 16; i++)
934 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
935 dev->state_saved = true;
936 if ((i = pci_save_pcie_state(dev)) != 0)
938 if ((i = pci_save_pcix_state(dev)) != 0)
944 * pci_restore_state - Restore the saved state of a PCI device
945 * @dev: - PCI device that we're dealing with
947 void pci_restore_state(struct pci_dev *dev)
952 if (!dev->state_saved)
955 /* PCI Express register must be restored first */
956 pci_restore_pcie_state(dev);
959 * The Base Address register should be programmed before the command
962 for (i = 15; i >= 0; i--) {
963 pci_read_config_dword(dev, i * 4, &val);
964 if (val != dev->saved_config_space[i]) {
965 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
966 "space at offset %#x (was %#x, writing %#x)\n",
967 i, val, (int)dev->saved_config_space[i]);
968 pci_write_config_dword(dev,i * 4,
969 dev->saved_config_space[i]);
972 pci_restore_pcix_state(dev);
973 pci_restore_msi_state(dev);
974 pci_restore_iov_state(dev);
976 dev->state_saved = false;
979 struct pci_saved_state {
980 u32 config_space[16];
981 struct pci_cap_saved_data cap[0];
985 * pci_store_saved_state - Allocate and return an opaque struct containing
986 * the device saved state.
987 * @dev: PCI device that we're dealing with
989 * Rerturn NULL if no state or error.
991 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
993 struct pci_saved_state *state;
994 struct pci_cap_saved_state *tmp;
995 struct pci_cap_saved_data *cap;
996 struct hlist_node *pos;
999 if (!dev->state_saved)
1002 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1004 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1005 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1007 state = kzalloc(size, GFP_KERNEL);
1011 memcpy(state->config_space, dev->saved_config_space,
1012 sizeof(state->config_space));
1015 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1016 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1017 memcpy(cap, &tmp->cap, len);
1018 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1020 /* Empty cap_save terminates list */
1024 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1027 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1028 * @dev: PCI device that we're dealing with
1029 * @state: Saved state returned from pci_store_saved_state()
1031 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1033 struct pci_cap_saved_data *cap;
1035 dev->state_saved = false;
1040 memcpy(dev->saved_config_space, state->config_space,
1041 sizeof(state->config_space));
1045 struct pci_cap_saved_state *tmp;
1047 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1048 if (!tmp || tmp->cap.size != cap->size)
1051 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1052 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1053 sizeof(struct pci_cap_saved_data) + cap->size);
1056 dev->state_saved = true;
1059 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1062 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1063 * and free the memory allocated for it.
1064 * @dev: PCI device that we're dealing with
1065 * @state: Pointer to saved state returned from pci_store_saved_state()
1067 int pci_load_and_free_saved_state(struct pci_dev *dev,
1068 struct pci_saved_state **state)
1070 int ret = pci_load_saved_state(dev, *state);
1075 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1077 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1081 err = pci_set_power_state(dev, PCI_D0);
1082 if (err < 0 && err != -EIO)
1084 err = pcibios_enable_device(dev, bars);
1087 pci_fixup_device(pci_fixup_enable, dev);
1093 * pci_reenable_device - Resume abandoned device
1094 * @dev: PCI device to be resumed
1096 * Note this function is a backend of pci_default_resume and is not supposed
1097 * to be called by normal code, write proper resume handler and use it instead.
1099 int pci_reenable_device(struct pci_dev *dev)
1101 if (pci_is_enabled(dev))
1102 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1106 static int __pci_enable_device_flags(struct pci_dev *dev,
1107 resource_size_t flags)
1113 * Power state could be unknown at this point, either due to a fresh
1114 * boot or a device removal call. So get the current power state
1115 * so that things like MSI message writing will behave as expected
1116 * (e.g. if the device really is in D0 at enable time).
1120 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1121 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1124 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1125 return 0; /* already enabled */
1127 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1128 if (dev->resource[i].flags & flags)
1131 err = do_pci_enable_device(dev, bars);
1133 atomic_dec(&dev->enable_cnt);
1138 * pci_enable_device_io - Initialize a device for use with IO space
1139 * @dev: PCI device to be initialized
1141 * Initialize device before it's used by a driver. Ask low-level code
1142 * to enable I/O resources. Wake up the device if it was suspended.
1143 * Beware, this function can fail.
1145 int pci_enable_device_io(struct pci_dev *dev)
1147 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1151 * pci_enable_device_mem - Initialize a device for use with Memory space
1152 * @dev: PCI device to be initialized
1154 * Initialize device before it's used by a driver. Ask low-level code
1155 * to enable Memory resources. Wake up the device if it was suspended.
1156 * Beware, this function can fail.
1158 int pci_enable_device_mem(struct pci_dev *dev)
1160 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1164 * pci_enable_device - Initialize device before it's used by a driver.
1165 * @dev: PCI device to be initialized
1167 * Initialize device before it's used by a driver. Ask low-level code
1168 * to enable I/O and memory. Wake up the device if it was suspended.
1169 * Beware, this function can fail.
1171 * Note we don't actually enable the device many times if we call
1172 * this function repeatedly (we just increment the count).
1174 int pci_enable_device(struct pci_dev *dev)
1176 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1180 * Managed PCI resources. This manages device on/off, intx/msi/msix
1181 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1182 * there's no need to track it separately. pci_devres is initialized
1183 * when a device is enabled using managed PCI device enable interface.
1186 unsigned int enabled:1;
1187 unsigned int pinned:1;
1188 unsigned int orig_intx:1;
1189 unsigned int restore_intx:1;
1193 static void pcim_release(struct device *gendev, void *res)
1195 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1196 struct pci_devres *this = res;
1199 if (dev->msi_enabled)
1200 pci_disable_msi(dev);
1201 if (dev->msix_enabled)
1202 pci_disable_msix(dev);
1204 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1205 if (this->region_mask & (1 << i))
1206 pci_release_region(dev, i);
1208 if (this->restore_intx)
1209 pci_intx(dev, this->orig_intx);
1211 if (this->enabled && !this->pinned)
1212 pci_disable_device(dev);
1215 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1217 struct pci_devres *dr, *new_dr;
1219 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1223 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1226 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1229 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1231 if (pci_is_managed(pdev))
1232 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1237 * pcim_enable_device - Managed pci_enable_device()
1238 * @pdev: PCI device to be initialized
1240 * Managed pci_enable_device().
1242 int pcim_enable_device(struct pci_dev *pdev)
1244 struct pci_devres *dr;
1247 dr = get_pci_dr(pdev);
1253 rc = pci_enable_device(pdev);
1255 pdev->is_managed = 1;
1262 * pcim_pin_device - Pin managed PCI device
1263 * @pdev: PCI device to pin
1265 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1266 * driver detach. @pdev must have been enabled with
1267 * pcim_enable_device().
1269 void pcim_pin_device(struct pci_dev *pdev)
1271 struct pci_devres *dr;
1273 dr = find_pci_dr(pdev);
1274 WARN_ON(!dr || !dr->enabled);
1280 * pcibios_disable_device - disable arch specific PCI resources for device dev
1281 * @dev: the PCI device to disable
1283 * Disables architecture specific PCI resources for the device. This
1284 * is the default implementation. Architecture implementations can
1287 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1289 static void do_pci_disable_device(struct pci_dev *dev)
1293 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1294 if (pci_command & PCI_COMMAND_MASTER) {
1295 pci_command &= ~PCI_COMMAND_MASTER;
1296 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1299 pcibios_disable_device(dev);
1303 * pci_disable_enabled_device - Disable device without updating enable_cnt
1304 * @dev: PCI device to disable
1306 * NOTE: This function is a backend of PCI power management routines and is
1307 * not supposed to be called drivers.
1309 void pci_disable_enabled_device(struct pci_dev *dev)
1311 if (pci_is_enabled(dev))
1312 do_pci_disable_device(dev);
1316 * pci_disable_device - Disable PCI device after use
1317 * @dev: PCI device to be disabled
1319 * Signal to the system that the PCI device is not in use by the system
1320 * anymore. This only involves disabling PCI bus-mastering, if active.
1322 * Note we don't actually disable the device until all callers of
1323 * pci_enable_device() have called pci_disable_device().
1326 pci_disable_device(struct pci_dev *dev)
1328 struct pci_devres *dr;
1330 dr = find_pci_dr(dev);
1334 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1337 do_pci_disable_device(dev);
1339 dev->is_busmaster = 0;
1343 * pcibios_set_pcie_reset_state - set reset state for device dev
1344 * @dev: the PCIe device reset
1345 * @state: Reset state to enter into
1348 * Sets the PCIe reset state for the device. This is the default
1349 * implementation. Architecture implementations can override this.
1351 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1352 enum pcie_reset_state state)
1358 * pci_set_pcie_reset_state - set reset state for device dev
1359 * @dev: the PCIe device reset
1360 * @state: Reset state to enter into
1363 * Sets the PCI reset state for the device.
1365 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1367 return pcibios_set_pcie_reset_state(dev, state);
1371 * pci_check_pme_status - Check if given device has generated PME.
1372 * @dev: Device to check.
1374 * Check the PME status of the device and if set, clear it and clear PME enable
1375 * (if set). Return 'true' if PME status and PME enable were both set or
1376 * 'false' otherwise.
1378 bool pci_check_pme_status(struct pci_dev *dev)
1387 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1388 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1389 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1392 /* Clear PME status. */
1393 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1394 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1395 /* Disable PME to avoid interrupt flood. */
1396 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1400 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1406 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1407 * @dev: Device to handle.
1410 * Check if @dev has generated PME and queue a resume request for it in that
1413 static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1415 if (pci_check_pme_status(dev)) {
1416 pci_wakeup_event(dev);
1417 pm_request_resume(&dev->dev);
1423 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1424 * @bus: Top bus of the subtree to walk.
1426 void pci_pme_wakeup_bus(struct pci_bus *bus)
1429 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1433 * pci_pme_capable - check the capability of PCI device to generate PME#
1434 * @dev: PCI device to handle.
1435 * @state: PCI state from which device will issue PME#.
1437 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1442 return !!(dev->pme_support & (1 << state));
1445 static void pci_pme_list_scan(struct work_struct *work)
1447 struct pci_pme_device *pme_dev;
1449 mutex_lock(&pci_pme_list_mutex);
1450 if (!list_empty(&pci_pme_list)) {
1451 list_for_each_entry(pme_dev, &pci_pme_list, list)
1452 pci_pme_wakeup(pme_dev->dev, NULL);
1453 schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
1455 mutex_unlock(&pci_pme_list_mutex);
1459 * pci_external_pme - is a device an external PCI PME source?
1460 * @dev: PCI device to check
1464 static bool pci_external_pme(struct pci_dev *dev)
1466 if (pci_is_pcie(dev) || dev->bus->number == 0)
1472 * pci_pme_active - enable or disable PCI device's PME# function
1473 * @dev: PCI device to handle.
1474 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1476 * The caller must verify that the device is capable of generating PME# before
1477 * calling this function with @enable equal to 'true'.
1479 void pci_pme_active(struct pci_dev *dev, bool enable)
1486 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1487 /* Clear PME_Status by writing 1 to it and enable PME# */
1488 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1490 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1492 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1494 /* PCI (as opposed to PCIe) PME requires that the device have
1495 its PME# line hooked up correctly. Not all hardware vendors
1496 do this, so the PME never gets delivered and the device
1497 remains asleep. The easiest way around this is to
1498 periodically walk the list of suspended devices and check
1499 whether any have their PME flag set. The assumption is that
1500 we'll wake up often enough anyway that this won't be a huge
1501 hit, and the power savings from the devices will still be a
1504 if (pci_external_pme(dev)) {
1505 struct pci_pme_device *pme_dev;
1507 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1512 mutex_lock(&pci_pme_list_mutex);
1513 list_add(&pme_dev->list, &pci_pme_list);
1514 if (list_is_singular(&pci_pme_list))
1515 schedule_delayed_work(&pci_pme_work,
1516 msecs_to_jiffies(PME_TIMEOUT));
1517 mutex_unlock(&pci_pme_list_mutex);
1519 mutex_lock(&pci_pme_list_mutex);
1520 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1521 if (pme_dev->dev == dev) {
1522 list_del(&pme_dev->list);
1527 mutex_unlock(&pci_pme_list_mutex);
1532 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1533 enable ? "enabled" : "disabled");
1537 * __pci_enable_wake - enable PCI device as wakeup event source
1538 * @dev: PCI device affected
1539 * @state: PCI state from which device will issue wakeup events
1540 * @runtime: True if the events are to be generated at run time
1541 * @enable: True to enable event generation; false to disable
1543 * This enables the device as a wakeup event source, or disables it.
1544 * When such events involves platform-specific hooks, those hooks are
1545 * called automatically by this routine.
1547 * Devices with legacy power management (no standard PCI PM capabilities)
1548 * always require such platform hooks.
1551 * 0 is returned on success
1552 * -EINVAL is returned if device is not supposed to wake up the system
1553 * Error code depending on the platform is returned if both the platform and
1554 * the native mechanism fail to enable the generation of wake-up events
1556 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1557 bool runtime, bool enable)
1561 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1564 /* Don't do the same thing twice in a row for one device. */
1565 if (!!enable == !!dev->wakeup_prepared)
1569 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1570 * Anderson we should be doing PME# wake enable followed by ACPI wake
1571 * enable. To disable wake-up we call the platform first, for symmetry.
1577 if (pci_pme_capable(dev, state))
1578 pci_pme_active(dev, true);
1581 error = runtime ? platform_pci_run_wake(dev, true) :
1582 platform_pci_sleep_wake(dev, true);
1586 dev->wakeup_prepared = true;
1589 platform_pci_run_wake(dev, false);
1591 platform_pci_sleep_wake(dev, false);
1592 pci_pme_active(dev, false);
1593 dev->wakeup_prepared = false;
1598 EXPORT_SYMBOL(__pci_enable_wake);
1601 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1602 * @dev: PCI device to prepare
1603 * @enable: True to enable wake-up event generation; false to disable
1605 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1606 * and this function allows them to set that up cleanly - pci_enable_wake()
1607 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1608 * ordering constraints.
1610 * This function only returns error code if the device is not capable of
1611 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1612 * enable wake-up power for it.
1614 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1616 return pci_pme_capable(dev, PCI_D3cold) ?
1617 pci_enable_wake(dev, PCI_D3cold, enable) :
1618 pci_enable_wake(dev, PCI_D3hot, enable);
1622 * pci_target_state - find an appropriate low power state for a given PCI dev
1625 * Use underlying platform code to find a supported low power state for @dev.
1626 * If the platform can't manage @dev, return the deepest state from which it
1627 * can generate wake events, based on any available PME info.
1629 pci_power_t pci_target_state(struct pci_dev *dev)
1631 pci_power_t target_state = PCI_D3hot;
1633 if (platform_pci_power_manageable(dev)) {
1635 * Call the platform to choose the target state of the device
1636 * and enable wake-up from this state if supported.
1638 pci_power_t state = platform_pci_choose_state(dev);
1641 case PCI_POWER_ERROR:
1646 if (pci_no_d1d2(dev))
1649 target_state = state;
1651 } else if (!dev->pm_cap) {
1652 target_state = PCI_D0;
1653 } else if (device_may_wakeup(&dev->dev)) {
1655 * Find the deepest state from which the device can generate
1656 * wake-up events, make it the target state and enable device
1659 if (dev->pme_support) {
1661 && !(dev->pme_support & (1 << target_state)))
1666 return target_state;
1670 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1671 * @dev: Device to handle.
1673 * Choose the power state appropriate for the device depending on whether
1674 * it can wake up the system and/or is power manageable by the platform
1675 * (PCI_D3hot is the default) and put the device into that state.
1677 int pci_prepare_to_sleep(struct pci_dev *dev)
1679 pci_power_t target_state = pci_target_state(dev);
1682 if (target_state == PCI_POWER_ERROR)
1685 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1687 error = pci_set_power_state(dev, target_state);
1690 pci_enable_wake(dev, target_state, false);
1696 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1697 * @dev: Device to handle.
1699 * Disable device's system wake-up capability and put it into D0.
1701 int pci_back_from_sleep(struct pci_dev *dev)
1703 pci_enable_wake(dev, PCI_D0, false);
1704 return pci_set_power_state(dev, PCI_D0);
1708 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1709 * @dev: PCI device being suspended.
1711 * Prepare @dev to generate wake-up events at run time and put it into a low
1714 int pci_finish_runtime_suspend(struct pci_dev *dev)
1716 pci_power_t target_state = pci_target_state(dev);
1719 if (target_state == PCI_POWER_ERROR)
1722 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1724 error = pci_set_power_state(dev, target_state);
1727 __pci_enable_wake(dev, target_state, true, false);
1733 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1734 * @dev: Device to check.
1736 * Return true if the device itself is cabable of generating wake-up events
1737 * (through the platform or using the native PCIe PME) or if the device supports
1738 * PME and one of its upstream bridges can generate wake-up events.
1740 bool pci_dev_run_wake(struct pci_dev *dev)
1742 struct pci_bus *bus = dev->bus;
1744 if (device_run_wake(&dev->dev))
1747 if (!dev->pme_support)
1750 while (bus->parent) {
1751 struct pci_dev *bridge = bus->self;
1753 if (device_run_wake(&bridge->dev))
1759 /* We have reached the root bus. */
1761 return device_run_wake(bus->bridge);
1765 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1768 * pci_pm_init - Initialize PM functions of given PCI device
1769 * @dev: PCI device to handle.
1771 void pci_pm_init(struct pci_dev *dev)
1776 pm_runtime_forbid(&dev->dev);
1777 device_enable_async_suspend(&dev->dev);
1778 dev->wakeup_prepared = false;
1782 /* find PCI PM capability in list */
1783 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1786 /* Check device's ability to generate PME# */
1787 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1789 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1790 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1791 pmc & PCI_PM_CAP_VER_MASK);
1796 dev->d3_delay = PCI_PM_D3_WAIT;
1798 dev->d1_support = false;
1799 dev->d2_support = false;
1800 if (!pci_no_d1d2(dev)) {
1801 if (pmc & PCI_PM_CAP_D1)
1802 dev->d1_support = true;
1803 if (pmc & PCI_PM_CAP_D2)
1804 dev->d2_support = true;
1806 if (dev->d1_support || dev->d2_support)
1807 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1808 dev->d1_support ? " D1" : "",
1809 dev->d2_support ? " D2" : "");
1812 pmc &= PCI_PM_CAP_PME_MASK;
1814 dev_printk(KERN_DEBUG, &dev->dev,
1815 "PME# supported from%s%s%s%s%s\n",
1816 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1817 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1818 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1819 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1820 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1821 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1823 * Make device's PM flags reflect the wake-up capability, but
1824 * let the user space enable it to wake up the system as needed.
1826 device_set_wakeup_capable(&dev->dev, true);
1827 /* Disable the PME# generation functionality */
1828 pci_pme_active(dev, false);
1830 dev->pme_support = 0;
1835 * platform_pci_wakeup_init - init platform wakeup if present
1838 * Some devices don't have PCI PM caps but can still generate wakeup
1839 * events through platform methods (like ACPI events). If @dev supports
1840 * platform wakeup events, set the device flag to indicate as much. This
1841 * may be redundant if the device also supports PCI PM caps, but double
1842 * initialization should be safe in that case.
1844 void platform_pci_wakeup_init(struct pci_dev *dev)
1846 if (!platform_pci_can_wakeup(dev))
1849 device_set_wakeup_capable(&dev->dev, true);
1850 platform_pci_sleep_wake(dev, false);
1854 * pci_add_save_buffer - allocate buffer for saving given capability registers
1855 * @dev: the PCI device
1856 * @cap: the capability to allocate the buffer for
1857 * @size: requested size of the buffer
1859 static int pci_add_cap_save_buffer(
1860 struct pci_dev *dev, char cap, unsigned int size)
1863 struct pci_cap_saved_state *save_state;
1865 pos = pci_find_capability(dev, cap);
1869 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1873 save_state->cap.cap_nr = cap;
1874 save_state->cap.size = size;
1875 pci_add_saved_cap(dev, save_state);
1881 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1882 * @dev: the PCI device
1884 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1888 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1889 PCI_EXP_SAVE_REGS * sizeof(u16));
1892 "unable to preallocate PCI Express save buffer\n");
1894 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1897 "unable to preallocate PCI-X save buffer\n");
1901 * pci_enable_ari - enable ARI forwarding if hardware support it
1902 * @dev: the PCI device
1904 void pci_enable_ari(struct pci_dev *dev)
1909 struct pci_dev *bridge;
1911 if (!pci_is_pcie(dev) || dev->devfn)
1914 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1918 bridge = dev->bus->self;
1919 if (!bridge || !pci_is_pcie(bridge))
1922 pos = pci_pcie_cap(bridge);
1926 /* ARI is a PCIe v2 feature */
1927 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1928 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1931 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1932 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1935 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1936 ctrl |= PCI_EXP_DEVCTL2_ARI;
1937 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1939 bridge->ari_enabled = 1;
1943 * pci_enable_ido - enable ID-based ordering on a device
1944 * @dev: the PCI device
1945 * @type: which types of IDO to enable
1947 * Enable ID-based ordering on @dev. @type can contain the bits
1948 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1949 * which types of transactions are allowed to be re-ordered.
1951 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1956 pos = pci_pcie_cap(dev);
1960 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1961 if (type & PCI_EXP_IDO_REQUEST)
1962 ctrl |= PCI_EXP_IDO_REQ_EN;
1963 if (type & PCI_EXP_IDO_COMPLETION)
1964 ctrl |= PCI_EXP_IDO_CMP_EN;
1965 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1967 EXPORT_SYMBOL(pci_enable_ido);
1970 * pci_disable_ido - disable ID-based ordering on a device
1971 * @dev: the PCI device
1972 * @type: which types of IDO to disable
1974 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1979 if (!pci_is_pcie(dev))
1982 pos = pci_pcie_cap(dev);
1986 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1987 if (type & PCI_EXP_IDO_REQUEST)
1988 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1989 if (type & PCI_EXP_IDO_COMPLETION)
1990 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1991 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1993 EXPORT_SYMBOL(pci_disable_ido);
1996 * pci_enable_obff - enable optimized buffer flush/fill
1998 * @type: type of signaling to use
2000 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2001 * signaling if possible, falling back to message signaling only if
2002 * WAKE# isn't supported. @type should indicate whether the PCIe link
2003 * be brought out of L0s or L1 to send the message. It should be either
2004 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2006 * If your device can benefit from receiving all messages, even at the
2007 * power cost of bringing the link back up from a low power state, use
2008 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2012 * Zero on success, appropriate error number on failure.
2014 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2021 if (!pci_is_pcie(dev))
2024 pos = pci_pcie_cap(dev);
2028 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2029 if (!(cap & PCI_EXP_OBFF_MASK))
2030 return -ENOTSUPP; /* no OBFF support at all */
2032 /* Make sure the topology supports OBFF as well */
2034 ret = pci_enable_obff(dev->bus->self, type);
2039 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2040 if (cap & PCI_EXP_OBFF_WAKE)
2041 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2044 case PCI_EXP_OBFF_SIGNAL_L0:
2045 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2046 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2048 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2049 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2050 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2053 WARN(1, "bad OBFF signal type\n");
2057 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2061 EXPORT_SYMBOL(pci_enable_obff);
2064 * pci_disable_obff - disable optimized buffer flush/fill
2067 * Disable OBFF on @dev.
2069 void pci_disable_obff(struct pci_dev *dev)
2074 if (!pci_is_pcie(dev))
2077 pos = pci_pcie_cap(dev);
2081 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2082 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2083 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2085 EXPORT_SYMBOL(pci_disable_obff);
2088 * pci_ltr_supported - check whether a device supports LTR
2092 * True if @dev supports latency tolerance reporting, false otherwise.
2094 bool pci_ltr_supported(struct pci_dev *dev)
2099 if (!pci_is_pcie(dev))
2102 pos = pci_pcie_cap(dev);
2106 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2108 return cap & PCI_EXP_DEVCAP2_LTR;
2110 EXPORT_SYMBOL(pci_ltr_supported);
2113 * pci_enable_ltr - enable latency tolerance reporting
2116 * Enable LTR on @dev if possible, which means enabling it first on
2120 * Zero on success, errno on failure.
2122 int pci_enable_ltr(struct pci_dev *dev)
2128 if (!pci_ltr_supported(dev))
2131 pos = pci_pcie_cap(dev);
2135 /* Only primary function can enable/disable LTR */
2136 if (PCI_FUNC(dev->devfn) != 0)
2139 /* Enable upstream ports first */
2141 ret = pci_enable_ltr(dev->bus->self);
2146 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2147 ctrl |= PCI_EXP_LTR_EN;
2148 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2152 EXPORT_SYMBOL(pci_enable_ltr);
2155 * pci_disable_ltr - disable latency tolerance reporting
2158 void pci_disable_ltr(struct pci_dev *dev)
2163 if (!pci_ltr_supported(dev))
2166 pos = pci_pcie_cap(dev);
2170 /* Only primary function can enable/disable LTR */
2171 if (PCI_FUNC(dev->devfn) != 0)
2174 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2175 ctrl &= ~PCI_EXP_LTR_EN;
2176 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2178 EXPORT_SYMBOL(pci_disable_ltr);
2180 static int __pci_ltr_scale(int *val)
2184 while (*val > 1023) {
2185 *val = (*val + 31) / 32;
2192 * pci_set_ltr - set LTR latency values
2194 * @snoop_lat_ns: snoop latency in nanoseconds
2195 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2197 * Figure out the scale and set the LTR values accordingly.
2199 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2201 int pos, ret, snoop_scale, nosnoop_scale;
2204 if (!pci_ltr_supported(dev))
2207 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2208 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2210 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2211 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2214 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2215 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2218 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2222 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2223 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2227 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2228 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2234 EXPORT_SYMBOL(pci_set_ltr);
2236 static int pci_acs_enable;
2239 * pci_request_acs - ask for ACS to be enabled if supported
2241 void pci_request_acs(void)
2247 * pci_enable_acs - enable ACS if hardware support it
2248 * @dev: the PCI device
2250 void pci_enable_acs(struct pci_dev *dev)
2256 if (!pci_acs_enable)
2259 if (!pci_is_pcie(dev))
2262 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2266 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2267 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2269 /* Source Validation */
2270 ctrl |= (cap & PCI_ACS_SV);
2272 /* P2P Request Redirect */
2273 ctrl |= (cap & PCI_ACS_RR);
2275 /* P2P Completion Redirect */
2276 ctrl |= (cap & PCI_ACS_CR);
2278 /* Upstream Forwarding */
2279 ctrl |= (cap & PCI_ACS_UF);
2281 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2285 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2286 * @dev: the PCI device
2287 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2289 * Perform INTx swizzling for a device behind one level of bridge. This is
2290 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2291 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2292 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2293 * the PCI Express Base Specification, Revision 2.1)
2295 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2299 if (pci_ari_enabled(dev->bus))
2302 slot = PCI_SLOT(dev->devfn);
2304 return (((pin - 1) + slot) % 4) + 1;
2308 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2316 while (!pci_is_root_bus(dev->bus)) {
2317 pin = pci_swizzle_interrupt_pin(dev, pin);
2318 dev = dev->bus->self;
2325 * pci_common_swizzle - swizzle INTx all the way to root bridge
2326 * @dev: the PCI device
2327 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2329 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2330 * bridges all the way up to a PCI root bus.
2332 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2336 while (!pci_is_root_bus(dev->bus)) {
2337 pin = pci_swizzle_interrupt_pin(dev, pin);
2338 dev = dev->bus->self;
2341 return PCI_SLOT(dev->devfn);
2345 * pci_release_region - Release a PCI bar
2346 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2347 * @bar: BAR to release
2349 * Releases the PCI I/O and memory resources previously reserved by a
2350 * successful call to pci_request_region. Call this function only
2351 * after all use of the PCI regions has ceased.
2353 void pci_release_region(struct pci_dev *pdev, int bar)
2355 struct pci_devres *dr;
2357 if (pci_resource_len(pdev, bar) == 0)
2359 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2360 release_region(pci_resource_start(pdev, bar),
2361 pci_resource_len(pdev, bar));
2362 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2363 release_mem_region(pci_resource_start(pdev, bar),
2364 pci_resource_len(pdev, bar));
2366 dr = find_pci_dr(pdev);
2368 dr->region_mask &= ~(1 << bar);
2372 * __pci_request_region - Reserved PCI I/O and memory resource
2373 * @pdev: PCI device whose resources are to be reserved
2374 * @bar: BAR to be reserved
2375 * @res_name: Name to be associated with resource.
2376 * @exclusive: whether the region access is exclusive or not
2378 * Mark the PCI region associated with PCI device @pdev BR @bar as
2379 * being reserved by owner @res_name. Do not access any
2380 * address inside the PCI regions unless this call returns
2383 * If @exclusive is set, then the region is marked so that userspace
2384 * is explicitly not allowed to map the resource via /dev/mem or
2385 * sysfs MMIO access.
2387 * Returns 0 on success, or %EBUSY on error. A warning
2388 * message is also printed on failure.
2390 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2393 struct pci_devres *dr;
2395 if (pci_resource_len(pdev, bar) == 0)
2398 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2399 if (!request_region(pci_resource_start(pdev, bar),
2400 pci_resource_len(pdev, bar), res_name))
2403 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2404 if (!__request_mem_region(pci_resource_start(pdev, bar),
2405 pci_resource_len(pdev, bar), res_name,
2410 dr = find_pci_dr(pdev);
2412 dr->region_mask |= 1 << bar;
2417 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2418 &pdev->resource[bar]);
2423 * pci_request_region - Reserve PCI I/O and memory resource
2424 * @pdev: PCI device whose resources are to be reserved
2425 * @bar: BAR to be reserved
2426 * @res_name: Name to be associated with resource
2428 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2429 * being reserved by owner @res_name. Do not access any
2430 * address inside the PCI regions unless this call returns
2433 * Returns 0 on success, or %EBUSY on error. A warning
2434 * message is also printed on failure.
2436 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2438 return __pci_request_region(pdev, bar, res_name, 0);
2442 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2443 * @pdev: PCI device whose resources are to be reserved
2444 * @bar: BAR to be reserved
2445 * @res_name: Name to be associated with resource.
2447 * Mark the PCI region associated with PCI device @pdev BR @bar as
2448 * being reserved by owner @res_name. Do not access any
2449 * address inside the PCI regions unless this call returns
2452 * Returns 0 on success, or %EBUSY on error. A warning
2453 * message is also printed on failure.
2455 * The key difference that _exclusive makes it that userspace is
2456 * explicitly not allowed to map the resource via /dev/mem or
2459 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2461 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2464 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2465 * @pdev: PCI device whose resources were previously reserved
2466 * @bars: Bitmask of BARs to be released
2468 * Release selected PCI I/O and memory resources previously reserved.
2469 * Call this function only after all use of the PCI regions has ceased.
2471 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2475 for (i = 0; i < 6; i++)
2476 if (bars & (1 << i))
2477 pci_release_region(pdev, i);
2480 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2481 const char *res_name, int excl)
2485 for (i = 0; i < 6; i++)
2486 if (bars & (1 << i))
2487 if (__pci_request_region(pdev, i, res_name, excl))
2493 if (bars & (1 << i))
2494 pci_release_region(pdev, i);
2501 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2502 * @pdev: PCI device whose resources are to be reserved
2503 * @bars: Bitmask of BARs to be requested
2504 * @res_name: Name to be associated with resource
2506 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2507 const char *res_name)
2509 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2512 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2513 int bars, const char *res_name)
2515 return __pci_request_selected_regions(pdev, bars, res_name,
2516 IORESOURCE_EXCLUSIVE);
2520 * pci_release_regions - Release reserved PCI I/O and memory resources
2521 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2523 * Releases all PCI I/O and memory resources previously reserved by a
2524 * successful call to pci_request_regions. Call this function only
2525 * after all use of the PCI regions has ceased.
2528 void pci_release_regions(struct pci_dev *pdev)
2530 pci_release_selected_regions(pdev, (1 << 6) - 1);
2534 * pci_request_regions - Reserved PCI I/O and memory resources
2535 * @pdev: PCI device whose resources are to be reserved
2536 * @res_name: Name to be associated with resource.
2538 * Mark all PCI regions associated with PCI device @pdev as
2539 * being reserved by owner @res_name. Do not access any
2540 * address inside the PCI regions unless this call returns
2543 * Returns 0 on success, or %EBUSY on error. A warning
2544 * message is also printed on failure.
2546 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2548 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2552 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2553 * @pdev: PCI device whose resources are to be reserved
2554 * @res_name: Name to be associated with resource.
2556 * Mark all PCI regions associated with PCI device @pdev as
2557 * being reserved by owner @res_name. Do not access any
2558 * address inside the PCI regions unless this call returns
2561 * pci_request_regions_exclusive() will mark the region so that
2562 * /dev/mem and the sysfs MMIO access will not be allowed.
2564 * Returns 0 on success, or %EBUSY on error. A warning
2565 * message is also printed on failure.
2567 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2569 return pci_request_selected_regions_exclusive(pdev,
2570 ((1 << 6) - 1), res_name);
2573 static void __pci_set_master(struct pci_dev *dev, bool enable)
2577 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2579 cmd = old_cmd | PCI_COMMAND_MASTER;
2581 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2582 if (cmd != old_cmd) {
2583 dev_dbg(&dev->dev, "%s bus mastering\n",
2584 enable ? "enabling" : "disabling");
2585 pci_write_config_word(dev, PCI_COMMAND, cmd);
2587 dev->is_busmaster = enable;
2591 * pci_set_master - enables bus-mastering for device dev
2592 * @dev: the PCI device to enable
2594 * Enables bus-mastering on the device and calls pcibios_set_master()
2595 * to do the needed arch specific settings.
2597 void pci_set_master(struct pci_dev *dev)
2599 __pci_set_master(dev, true);
2600 pcibios_set_master(dev);
2604 * pci_clear_master - disables bus-mastering for device dev
2605 * @dev: the PCI device to disable
2607 void pci_clear_master(struct pci_dev *dev)
2609 __pci_set_master(dev, false);
2613 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2614 * @dev: the PCI device for which MWI is to be enabled
2616 * Helper function for pci_set_mwi.
2617 * Originally copied from drivers/net/acenic.c.
2618 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2620 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2622 int pci_set_cacheline_size(struct pci_dev *dev)
2626 if (!pci_cache_line_size)
2629 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2630 equal to or multiple of the right value. */
2631 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2632 if (cacheline_size >= pci_cache_line_size &&
2633 (cacheline_size % pci_cache_line_size) == 0)
2636 /* Write the correct value. */
2637 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2639 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2640 if (cacheline_size == pci_cache_line_size)
2643 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2644 "supported\n", pci_cache_line_size << 2);
2648 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2650 #ifdef PCI_DISABLE_MWI
2651 int pci_set_mwi(struct pci_dev *dev)
2656 int pci_try_set_mwi(struct pci_dev *dev)
2661 void pci_clear_mwi(struct pci_dev *dev)
2668 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2669 * @dev: the PCI device for which MWI is enabled
2671 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2673 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2676 pci_set_mwi(struct pci_dev *dev)
2681 rc = pci_set_cacheline_size(dev);
2685 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2686 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2687 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2688 cmd |= PCI_COMMAND_INVALIDATE;
2689 pci_write_config_word(dev, PCI_COMMAND, cmd);
2696 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2697 * @dev: the PCI device for which MWI is enabled
2699 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2700 * Callers are not required to check the return value.
2702 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2704 int pci_try_set_mwi(struct pci_dev *dev)
2706 int rc = pci_set_mwi(dev);
2711 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2712 * @dev: the PCI device to disable
2714 * Disables PCI Memory-Write-Invalidate transaction on the device
2717 pci_clear_mwi(struct pci_dev *dev)
2721 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2722 if (cmd & PCI_COMMAND_INVALIDATE) {
2723 cmd &= ~PCI_COMMAND_INVALIDATE;
2724 pci_write_config_word(dev, PCI_COMMAND, cmd);
2727 #endif /* ! PCI_DISABLE_MWI */
2730 * pci_intx - enables/disables PCI INTx for device dev
2731 * @pdev: the PCI device to operate on
2732 * @enable: boolean: whether to enable or disable PCI INTx
2734 * Enables/disables PCI INTx for device dev
2737 pci_intx(struct pci_dev *pdev, int enable)
2739 u16 pci_command, new;
2741 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2744 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2746 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2749 if (new != pci_command) {
2750 struct pci_devres *dr;
2752 pci_write_config_word(pdev, PCI_COMMAND, new);
2754 dr = find_pci_dr(pdev);
2755 if (dr && !dr->restore_intx) {
2756 dr->restore_intx = 1;
2757 dr->orig_intx = !enable;
2763 * pci_msi_off - disables any msi or msix capabilities
2764 * @dev: the PCI device to operate on
2766 * If you want to use msi see pci_enable_msi and friends.
2767 * This is a lower level primitive that allows us to disable
2768 * msi operation at the device level.
2770 void pci_msi_off(struct pci_dev *dev)
2775 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2777 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2778 control &= ~PCI_MSI_FLAGS_ENABLE;
2779 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2781 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2783 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2784 control &= ~PCI_MSIX_FLAGS_ENABLE;
2785 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2788 EXPORT_SYMBOL_GPL(pci_msi_off);
2790 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2792 return dma_set_max_seg_size(&dev->dev, size);
2794 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2796 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2798 return dma_set_seg_boundary(&dev->dev, mask);
2800 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2802 static int pcie_flr(struct pci_dev *dev, int probe)
2807 u16 status, control;
2809 pos = pci_pcie_cap(dev);
2813 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2814 if (!(cap & PCI_EXP_DEVCAP_FLR))
2820 /* Wait for Transaction Pending bit clean */
2821 for (i = 0; i < 4; i++) {
2823 msleep((1 << (i - 1)) * 100);
2825 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2826 if (!(status & PCI_EXP_DEVSTA_TRPND))
2830 dev_err(&dev->dev, "transaction is not cleared; "
2831 "proceeding with reset anyway\n");
2834 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2835 control |= PCI_EXP_DEVCTL_BCR_FLR;
2836 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2843 static int pci_af_flr(struct pci_dev *dev, int probe)
2850 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2854 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2855 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2861 /* Wait for Transaction Pending bit clean */
2862 for (i = 0; i < 4; i++) {
2864 msleep((1 << (i - 1)) * 100);
2866 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2867 if (!(status & PCI_AF_STATUS_TP))
2871 dev_err(&dev->dev, "transaction is not cleared; "
2872 "proceeding with reset anyway\n");
2875 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2882 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2883 * @dev: Device to reset.
2884 * @probe: If set, only check if the device can be reset this way.
2886 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2887 * unset, it will be reinitialized internally when going from PCI_D3hot to
2888 * PCI_D0. If that's the case and the device is not in a low-power state
2889 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2891 * NOTE: This causes the caller to sleep for twice the device power transition
2892 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2893 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2894 * Moreover, only devices in D0 can be reset by this function.
2896 static int pci_pm_reset(struct pci_dev *dev, int probe)
2903 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2904 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2910 if (dev->current_state != PCI_D0)
2913 csr &= ~PCI_PM_CTRL_STATE_MASK;
2915 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2916 pci_dev_d3_sleep(dev);
2918 csr &= ~PCI_PM_CTRL_STATE_MASK;
2920 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2921 pci_dev_d3_sleep(dev);
2926 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2929 struct pci_dev *pdev;
2931 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2934 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2941 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2942 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2943 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2946 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2947 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2953 static int pci_dev_reset(struct pci_dev *dev, int probe)
2960 pci_block_user_cfg_access(dev);
2961 /* block PM suspend, driver probe, etc. */
2962 device_lock(&dev->dev);
2965 rc = pci_dev_specific_reset(dev, probe);
2969 rc = pcie_flr(dev, probe);
2973 rc = pci_af_flr(dev, probe);
2977 rc = pci_pm_reset(dev, probe);
2981 rc = pci_parent_bus_reset(dev, probe);
2984 device_unlock(&dev->dev);
2985 pci_unblock_user_cfg_access(dev);
2992 * __pci_reset_function - reset a PCI device function
2993 * @dev: PCI device to reset
2995 * Some devices allow an individual function to be reset without affecting
2996 * other functions in the same device. The PCI device must be responsive
2997 * to PCI config space in order to use this function.
2999 * The device function is presumed to be unused when this function is called.
3000 * Resetting the device will make the contents of PCI configuration space
3001 * random, so any caller of this must be prepared to reinitialise the
3002 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3005 * Returns 0 if the device function was successfully reset or negative if the
3006 * device doesn't support resetting a single function.
3008 int __pci_reset_function(struct pci_dev *dev)
3010 return pci_dev_reset(dev, 0);
3012 EXPORT_SYMBOL_GPL(__pci_reset_function);
3015 * pci_probe_reset_function - check whether the device can be safely reset
3016 * @dev: PCI device to reset
3018 * Some devices allow an individual function to be reset without affecting
3019 * other functions in the same device. The PCI device must be responsive
3020 * to PCI config space in order to use this function.
3022 * Returns 0 if the device function can be reset or negative if the
3023 * device doesn't support resetting a single function.
3025 int pci_probe_reset_function(struct pci_dev *dev)
3027 return pci_dev_reset(dev, 1);
3031 * pci_reset_function - quiesce and reset a PCI device function
3032 * @dev: PCI device to reset
3034 * Some devices allow an individual function to be reset without affecting
3035 * other functions in the same device. The PCI device must be responsive
3036 * to PCI config space in order to use this function.
3038 * This function does not just reset the PCI portion of a device, but
3039 * clears all the state associated with the device. This function differs
3040 * from __pci_reset_function in that it saves and restores device state
3043 * Returns 0 if the device function was successfully reset or negative if the
3044 * device doesn't support resetting a single function.
3046 int pci_reset_function(struct pci_dev *dev)
3050 rc = pci_dev_reset(dev, 1);
3054 pci_save_state(dev);
3057 * both INTx and MSI are disabled after the Interrupt Disable bit
3058 * is set and the Bus Master bit is cleared.
3060 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3062 rc = pci_dev_reset(dev, 0);
3064 pci_restore_state(dev);
3068 EXPORT_SYMBOL_GPL(pci_reset_function);
3071 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3072 * @dev: PCI device to query
3074 * Returns mmrbc: maximum designed memory read count in bytes
3075 * or appropriate error value.
3077 int pcix_get_max_mmrbc(struct pci_dev *dev)
3082 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3086 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3089 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3091 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3094 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3095 * @dev: PCI device to query
3097 * Returns mmrbc: maximum memory read count in bytes
3098 * or appropriate error value.
3100 int pcix_get_mmrbc(struct pci_dev *dev)
3105 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3109 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3112 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3114 EXPORT_SYMBOL(pcix_get_mmrbc);
3117 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3118 * @dev: PCI device to query
3119 * @mmrbc: maximum memory read count in bytes
3120 * valid values are 512, 1024, 2048, 4096
3122 * If possible sets maximum memory read byte count, some bridges have erratas
3123 * that prevent this.
3125 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3131 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3134 v = ffs(mmrbc) - 10;
3136 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3140 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3143 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3146 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3149 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3151 if (v > o && dev->bus &&
3152 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3155 cmd &= ~PCI_X_CMD_MAX_READ;
3157 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3162 EXPORT_SYMBOL(pcix_set_mmrbc);
3165 * pcie_get_readrq - get PCI Express read request size
3166 * @dev: PCI device to query
3168 * Returns maximum memory read request in bytes
3169 * or appropriate error value.
3171 int pcie_get_readrq(struct pci_dev *dev)
3176 cap = pci_pcie_cap(dev);
3180 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3182 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3186 EXPORT_SYMBOL(pcie_get_readrq);
3189 * pcie_set_readrq - set PCI Express maximum memory read request
3190 * @dev: PCI device to query
3191 * @rq: maximum memory read count in bytes
3192 * valid values are 128, 256, 512, 1024, 2048, 4096
3194 * If possible sets maximum read byte count
3196 int pcie_set_readrq(struct pci_dev *dev, int rq)
3198 int cap, err = -EINVAL;
3201 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3204 v = (ffs(rq) - 8) << 12;
3206 cap = pci_pcie_cap(dev);
3210 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3214 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3215 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3217 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
3223 EXPORT_SYMBOL(pcie_set_readrq);
3226 * pci_select_bars - Make BAR mask from the type of resource
3227 * @dev: the PCI device for which BAR mask is made
3228 * @flags: resource type mask to be selected
3230 * This helper routine makes bar mask from the type of resource.
3232 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3235 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3236 if (pci_resource_flags(dev, i) & flags)
3242 * pci_resource_bar - get position of the BAR associated with a resource
3243 * @dev: the PCI device
3244 * @resno: the resource number
3245 * @type: the BAR type to be filled in
3247 * Returns BAR position in config space, or 0 if the BAR is invalid.
3249 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3253 if (resno < PCI_ROM_RESOURCE) {
3254 *type = pci_bar_unknown;
3255 return PCI_BASE_ADDRESS_0 + 4 * resno;
3256 } else if (resno == PCI_ROM_RESOURCE) {
3257 *type = pci_bar_mem32;
3258 return dev->rom_base_reg;
3259 } else if (resno < PCI_BRIDGE_RESOURCES) {
3260 /* device specific resource */
3261 reg = pci_iov_resource_bar(dev, resno, type);
3266 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3270 /* Some architectures require additional programming to enable VGA */
3271 static arch_set_vga_state_t arch_set_vga_state;
3273 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3275 arch_set_vga_state = func; /* NULL disables */
3278 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3279 unsigned int command_bits, u32 flags)
3281 if (arch_set_vga_state)
3282 return arch_set_vga_state(dev, decode, command_bits,
3288 * pci_set_vga_state - set VGA decode state on device and parents if requested
3289 * @dev: the PCI device
3290 * @decode: true = enable decoding, false = disable decoding
3291 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3292 * @flags: traverse ancestors and change bridges
3293 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3295 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3296 unsigned int command_bits, u32 flags)
3298 struct pci_bus *bus;
3299 struct pci_dev *bridge;
3303 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3305 /* ARCH specific VGA enables */
3306 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3310 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3311 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3313 cmd |= command_bits;
3315 cmd &= ~command_bits;
3316 pci_write_config_word(dev, PCI_COMMAND, cmd);
3319 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3326 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3329 cmd |= PCI_BRIDGE_CTL_VGA;
3331 cmd &= ~PCI_BRIDGE_CTL_VGA;
3332 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3340 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3341 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3342 static DEFINE_SPINLOCK(resource_alignment_lock);
3345 * pci_specified_resource_alignment - get resource alignment specified by user.
3346 * @dev: the PCI device to get
3348 * RETURNS: Resource alignment if it is specified.
3349 * Zero if it is not specified.
3351 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3353 int seg, bus, slot, func, align_order, count;
3354 resource_size_t align = 0;
3357 spin_lock(&resource_alignment_lock);
3358 p = resource_alignment_param;
3361 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3367 if (sscanf(p, "%x:%x:%x.%x%n",
3368 &seg, &bus, &slot, &func, &count) != 4) {
3370 if (sscanf(p, "%x:%x.%x%n",
3371 &bus, &slot, &func, &count) != 3) {
3372 /* Invalid format */
3373 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3379 if (seg == pci_domain_nr(dev->bus) &&
3380 bus == dev->bus->number &&
3381 slot == PCI_SLOT(dev->devfn) &&
3382 func == PCI_FUNC(dev->devfn)) {
3383 if (align_order == -1) {
3386 align = 1 << align_order;
3391 if (*p != ';' && *p != ',') {
3392 /* End of param or invalid format */
3397 spin_unlock(&resource_alignment_lock);
3402 * pci_is_reassigndev - check if specified PCI is target device to reassign
3403 * @dev: the PCI device to check
3405 * RETURNS: non-zero for PCI device is a target device to reassign,
3408 int pci_is_reassigndev(struct pci_dev *dev)
3410 return (pci_specified_resource_alignment(dev) != 0);
3413 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3415 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3416 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3417 spin_lock(&resource_alignment_lock);
3418 strncpy(resource_alignment_param, buf, count);
3419 resource_alignment_param[count] = '\0';
3420 spin_unlock(&resource_alignment_lock);
3424 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3427 spin_lock(&resource_alignment_lock);
3428 count = snprintf(buf, size, "%s", resource_alignment_param);
3429 spin_unlock(&resource_alignment_lock);
3433 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3435 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3438 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3439 const char *buf, size_t count)
3441 return pci_set_resource_alignment_param(buf, count);
3444 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3445 pci_resource_alignment_store);
3447 static int __init pci_resource_alignment_sysfs_init(void)
3449 return bus_create_file(&pci_bus_type,
3450 &bus_attr_resource_alignment);
3453 late_initcall(pci_resource_alignment_sysfs_init);
3455 static void __devinit pci_no_domains(void)
3457 #ifdef CONFIG_PCI_DOMAINS
3458 pci_domains_supported = 0;
3463 * pci_ext_cfg_enabled - can we access extended PCI config space?
3464 * @dev: The PCI device of the root bridge.
3466 * Returns 1 if we can access PCI extended config space (offsets
3467 * greater than 0xff). This is the default implementation. Architecture
3468 * implementations can override this.
3470 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3475 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3478 EXPORT_SYMBOL(pci_fixup_cardbus);
3480 static int __init pci_setup(char *str)
3483 char *k = strchr(str, ',');
3486 if (*str && (str = pcibios_setup(str)) && *str) {
3487 if (!strcmp(str, "nomsi")) {
3489 } else if (!strcmp(str, "noaer")) {
3491 } else if (!strncmp(str, "realloc", 7)) {
3493 } else if (!strcmp(str, "nodomains")) {
3495 } else if (!strncmp(str, "cbiosize=", 9)) {
3496 pci_cardbus_io_size = memparse(str + 9, &str);
3497 } else if (!strncmp(str, "cbmemsize=", 10)) {
3498 pci_cardbus_mem_size = memparse(str + 10, &str);
3499 } else if (!strncmp(str, "resource_alignment=", 19)) {
3500 pci_set_resource_alignment_param(str + 19,
3502 } else if (!strncmp(str, "ecrc=", 5)) {
3503 pcie_ecrc_get_policy(str + 5);
3504 } else if (!strncmp(str, "hpiosize=", 9)) {
3505 pci_hotplug_io_size = memparse(str + 9, &str);
3506 } else if (!strncmp(str, "hpmemsize=", 10)) {
3507 pci_hotplug_mem_size = memparse(str + 10, &str);
3509 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3517 early_param("pci", pci_setup);
3519 EXPORT_SYMBOL(pci_reenable_device);
3520 EXPORT_SYMBOL(pci_enable_device_io);
3521 EXPORT_SYMBOL(pci_enable_device_mem);
3522 EXPORT_SYMBOL(pci_enable_device);
3523 EXPORT_SYMBOL(pcim_enable_device);
3524 EXPORT_SYMBOL(pcim_pin_device);
3525 EXPORT_SYMBOL(pci_disable_device);
3526 EXPORT_SYMBOL(pci_find_capability);
3527 EXPORT_SYMBOL(pci_bus_find_capability);
3528 EXPORT_SYMBOL(pci_release_regions);
3529 EXPORT_SYMBOL(pci_request_regions);
3530 EXPORT_SYMBOL(pci_request_regions_exclusive);
3531 EXPORT_SYMBOL(pci_release_region);
3532 EXPORT_SYMBOL(pci_request_region);
3533 EXPORT_SYMBOL(pci_request_region_exclusive);
3534 EXPORT_SYMBOL(pci_release_selected_regions);
3535 EXPORT_SYMBOL(pci_request_selected_regions);
3536 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3537 EXPORT_SYMBOL(pci_set_master);
3538 EXPORT_SYMBOL(pci_clear_master);
3539 EXPORT_SYMBOL(pci_set_mwi);
3540 EXPORT_SYMBOL(pci_try_set_mwi);
3541 EXPORT_SYMBOL(pci_clear_mwi);
3542 EXPORT_SYMBOL_GPL(pci_intx);
3543 EXPORT_SYMBOL(pci_assign_resource);
3544 EXPORT_SYMBOL(pci_find_parent_resource);
3545 EXPORT_SYMBOL(pci_select_bars);
3547 EXPORT_SYMBOL(pci_set_power_state);
3548 EXPORT_SYMBOL(pci_save_state);
3549 EXPORT_SYMBOL(pci_restore_state);
3550 EXPORT_SYMBOL(pci_pme_capable);
3551 EXPORT_SYMBOL(pci_pme_active);
3552 EXPORT_SYMBOL(pci_wake_from_d3);
3553 EXPORT_SYMBOL(pci_target_state);
3554 EXPORT_SYMBOL(pci_prepare_to_sleep);
3555 EXPORT_SYMBOL(pci_back_from_sleep);
3556 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);