2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names);
35 int isa_dma_bridge_buggy;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy);
39 EXPORT_SYMBOL(pci_pci_problems);
41 unsigned int pci_pm_d3_delay;
43 static void pci_pme_list_scan(struct work_struct *work);
45 static LIST_HEAD(pci_pme_list);
46 static DEFINE_MUTEX(pci_pme_list_mutex);
47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
49 struct pci_pme_device {
50 struct list_head list;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev *dev)
58 unsigned int delay = dev->d3_delay;
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported = 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 u8 pci_cache_line_size;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency = 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
111 struct list_head *tmp;
112 unsigned char max, n;
114 max = bus->busn_res.end;
115 list_for_each(tmp, &bus->children) {
116 n = pci_bus_max_busnr(pci_bus_b(tmp));
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
158 pos += PCI_CAP_LIST_NEXT;
163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
166 int ttl = PCI_FIND_CAP_TTL;
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability);
178 static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev *dev, int cap)
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
231 * pci_bus_find_capability - query for devices' capabilities
232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
236 * Like pci_find_capability() but works for pci devices that do not have a
237 * pci_dev structure set up yet.
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
243 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
258 * pci_find_next_ext_capability - Find an extended capability
259 * @dev: PCI device to query
260 * @start: address at which to start looking (0 to start at beginning of list)
261 * @cap: capability code
263 * Returns the address of the next matching extended capability structure
264 * within the device's PCI configuration space or 0 if the device does
265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
268 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
272 int pos = PCI_CFG_SPACE_SIZE;
274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
297 pos = PCI_EXT_CAP_NEXT(header);
298 if (pos < PCI_CFG_SPACE_SIZE)
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
323 int pci_find_ext_capability(struct pci_dev *dev, int cap)
325 return pci_find_next_ext_capability(dev, 0, cap);
327 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
329 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
331 int rc, ttl = PCI_FIND_CAP_TTL;
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
337 mask = HT_5BIT_CAP_MASK;
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
346 if ((cap & mask) == ht_cap)
349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
351 PCI_CAP_ID_HT, &ttl);
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
369 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
386 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
396 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
403 * For given resource region of given device, return the resource
404 * region of parent bus the given region is contained in or where
405 * it should be allocated from.
408 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
410 const struct pci_bus *bus = dev->bus;
412 struct resource *best = NULL, *r;
414 pci_bus_for_each_resource(bus, r, i) {
417 if (res->start && !(res->start >= r->start && res->end <= r->end))
418 continue; /* Not contained */
419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
420 continue; /* Wrong type */
421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
422 return r; /* Exact match */
423 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
424 if (r->flags & IORESOURCE_PREFETCH)
426 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
434 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
435 * @dev: PCI device to have its BARs restored
437 * Restore the BAR values for a given device, so as to make it
438 * accessible by its driver.
441 pci_restore_bars(struct pci_dev *dev)
445 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
446 pci_update_resource(dev, i);
449 static struct pci_platform_pm_ops *pci_platform_pm;
451 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
453 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
456 pci_platform_pm = ops;
460 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
462 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
465 static inline int platform_pci_set_power_state(struct pci_dev *dev,
468 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
471 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
473 return pci_platform_pm ?
474 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
477 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
479 return pci_platform_pm ?
480 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
483 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
485 return pci_platform_pm ?
486 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
490 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
492 * @dev: PCI device to handle.
493 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
496 * -EINVAL if the requested state is invalid.
497 * -EIO if device does not support PCI PM or its PM capabilities register has a
498 * wrong version, or device doesn't support the requested state.
499 * 0 if device already is in the requested state.
500 * 0 if device's power state has been successfully changed.
502 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
505 bool need_restore = false;
507 /* Check if we're already there */
508 if (dev->current_state == state)
514 if (state < PCI_D0 || state > PCI_D3hot)
517 /* Validate current state:
518 * Can enter D0 from any state, but if we can only go deeper
519 * to sleep if we're already in a low power state
521 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
522 && dev->current_state > state) {
523 dev_err(&dev->dev, "invalid power transition "
524 "(from state %d to %d)\n", dev->current_state, state);
528 /* check if this device supports the desired state */
529 if ((state == PCI_D1 && !dev->d1_support)
530 || (state == PCI_D2 && !dev->d2_support))
533 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
535 /* If we're (effectively) in D3, force entire word to 0.
536 * This doesn't affect PME_Status, disables PME_En, and
537 * sets PowerState to 0.
539 switch (dev->current_state) {
543 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
548 case PCI_UNKNOWN: /* Boot-up */
549 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
550 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
552 /* Fall-through: force to D0 */
558 /* enter specified state */
559 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
561 /* Mandatory power management transition delays */
562 /* see PCI PM 1.1 5.6.1 table 18 */
563 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
564 pci_dev_d3_sleep(dev);
565 else if (state == PCI_D2 || dev->current_state == PCI_D2)
566 udelay(PCI_PM_D2_DELAY);
568 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
569 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
570 if (dev->current_state != state && printk_ratelimit())
571 dev_info(&dev->dev, "Refused to change power state, "
572 "currently in D%d\n", dev->current_state);
575 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
576 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
577 * from D3hot to D0 _may_ perform an internal reset, thereby
578 * going to "D0 Uninitialized" rather than "D0 Initialized".
579 * For example, at least some versions of the 3c905B and the
580 * 3c556B exhibit this behaviour.
582 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
583 * devices in a D3hot state at boot. Consequently, we need to
584 * restore at least the BARs so that the device will be
585 * accessible to its driver.
588 pci_restore_bars(dev);
591 pcie_aspm_pm_state_change(dev->bus->self);
597 * pci_update_current_state - Read PCI power state of given device from its
598 * PCI PM registers and cache it
599 * @dev: PCI device to handle.
600 * @state: State to cache in case the device doesn't have the PM capability
602 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
608 * Configuration space is not accessible for device in
609 * D3cold, so just keep or set D3cold for safety
611 if (dev->current_state == PCI_D3cold)
613 if (state == PCI_D3cold) {
614 dev->current_state = PCI_D3cold;
617 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
618 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
620 dev->current_state = state;
625 * pci_power_up - Put the given device into D0 forcibly
626 * @dev: PCI device to power up
628 void pci_power_up(struct pci_dev *dev)
630 if (platform_pci_power_manageable(dev))
631 platform_pci_set_power_state(dev, PCI_D0);
633 pci_raw_set_power_state(dev, PCI_D0);
634 pci_update_current_state(dev, PCI_D0);
638 * pci_platform_power_transition - Use platform to change device power state
639 * @dev: PCI device to handle.
640 * @state: State to put the device into.
642 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
646 if (platform_pci_power_manageable(dev)) {
647 error = platform_pci_set_power_state(dev, state);
649 pci_update_current_state(dev, state);
653 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
654 dev->current_state = PCI_D0;
660 * __pci_start_power_transition - Start power transition of a PCI device
661 * @dev: PCI device to handle.
662 * @state: State to put the device into.
664 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
666 if (state == PCI_D0) {
667 pci_platform_power_transition(dev, PCI_D0);
669 * Mandatory power management transition delays, see
670 * PCI Express Base Specification Revision 2.0 Section
671 * 6.6.1: Conventional Reset. Do not delay for
672 * devices powered on/off by corresponding bridge,
673 * because have already delayed for the bridge.
675 if (dev->runtime_d3cold) {
676 msleep(dev->d3cold_delay);
678 * When powering on a bridge from D3cold, the
679 * whole hierarchy may be powered on into
680 * D0uninitialized state, resume them to give
681 * them a chance to suspend again
683 pci_wakeup_bus(dev->subordinate);
689 * __pci_dev_set_current_state - Set current state of a PCI device
690 * @dev: Device to handle
691 * @data: pointer to state to be set
693 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
695 pci_power_t state = *(pci_power_t *)data;
697 dev->current_state = state;
702 * __pci_bus_set_current_state - Walk given bus and set current state of devices
703 * @bus: Top bus of the subtree to walk.
704 * @state: state to be set
706 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
709 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
713 * __pci_complete_power_transition - Complete power transition of a PCI device
714 * @dev: PCI device to handle.
715 * @state: State to put the device into.
717 * This function should not be called directly by device drivers.
719 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
725 ret = pci_platform_power_transition(dev, state);
726 /* Power off the bridge may power off the whole hierarchy */
727 if (!ret && state == PCI_D3cold)
728 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
731 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
734 * pci_set_power_state - Set the power state of a PCI device
735 * @dev: PCI device to handle.
736 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
738 * Transition a device to a new power state, using the platform firmware and/or
739 * the device's PCI PM registers.
742 * -EINVAL if the requested state is invalid.
743 * -EIO if device does not support PCI PM or its PM capabilities register has a
744 * wrong version, or device doesn't support the requested state.
745 * 0 if device already is in the requested state.
746 * 0 if device's power state has been successfully changed.
748 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
752 /* bound the state we're entering */
753 if (state > PCI_D3cold)
755 else if (state < PCI_D0)
757 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
759 * If the device or the parent bridge do not support PCI PM,
760 * ignore the request if we're doing anything other than putting
761 * it into D0 (which would only happen on boot).
765 /* Check if we're already there */
766 if (dev->current_state == state)
769 __pci_start_power_transition(dev, state);
771 /* This device is quirked not to be put into D3, so
772 don't put it in D3 */
773 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
777 * To put device in D3cold, we put device into D3hot in native
778 * way, then put device into D3cold with platform ops
780 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
783 if (!__pci_complete_power_transition(dev, state))
786 * When aspm_policy is "powersave" this call ensures
787 * that ASPM is configured.
789 if (!error && dev->bus->self)
790 pcie_aspm_powersave_config_link(dev->bus->self);
796 * pci_choose_state - Choose the power state of a PCI device
797 * @dev: PCI device to be suspended
798 * @state: target sleep state for the whole system. This is the value
799 * that is passed to suspend() function.
801 * Returns PCI power state suitable for given device and given system
805 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
812 ret = platform_pci_choose_state(dev);
813 if (ret != PCI_POWER_ERROR)
816 switch (state.event) {
819 case PM_EVENT_FREEZE:
820 case PM_EVENT_PRETHAW:
821 /* REVISIT both freeze and pre-thaw "should" use D0 */
822 case PM_EVENT_SUSPEND:
823 case PM_EVENT_HIBERNATE:
826 dev_info(&dev->dev, "unrecognized suspend event %d\n",
833 EXPORT_SYMBOL(pci_choose_state);
835 #define PCI_EXP_SAVE_REGS 7
838 static struct pci_cap_saved_state *pci_find_saved_cap(
839 struct pci_dev *pci_dev, char cap)
841 struct pci_cap_saved_state *tmp;
843 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
844 if (tmp->cap.cap_nr == cap)
850 static int pci_save_pcie_state(struct pci_dev *dev)
853 struct pci_cap_saved_state *save_state;
856 if (!pci_is_pcie(dev))
859 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
861 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
865 cap = (u16 *)&save_state->cap.data[0];
866 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
867 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
868 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
869 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
870 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
872 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
877 static void pci_restore_pcie_state(struct pci_dev *dev)
880 struct pci_cap_saved_state *save_state;
883 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
887 cap = (u16 *)&save_state->cap.data[0];
888 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
889 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
890 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
891 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
892 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
894 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
898 static int pci_save_pcix_state(struct pci_dev *dev)
901 struct pci_cap_saved_state *save_state;
903 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
907 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
909 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
913 pci_read_config_word(dev, pos + PCI_X_CMD,
914 (u16 *)save_state->cap.data);
919 static void pci_restore_pcix_state(struct pci_dev *dev)
922 struct pci_cap_saved_state *save_state;
925 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
926 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
927 if (!save_state || pos <= 0)
929 cap = (u16 *)&save_state->cap.data[0];
931 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
936 * pci_save_state - save the PCI configuration space of a device before suspending
937 * @dev: - PCI device that we're dealing with
940 pci_save_state(struct pci_dev *dev)
943 /* XXX: 100% dword access ok here? */
944 for (i = 0; i < 16; i++)
945 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
946 dev->state_saved = true;
947 if ((i = pci_save_pcie_state(dev)) != 0)
949 if ((i = pci_save_pcix_state(dev)) != 0)
954 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
955 u32 saved_val, int retry)
959 pci_read_config_dword(pdev, offset, &val);
960 if (val == saved_val)
964 dev_dbg(&pdev->dev, "restoring config space at offset "
965 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
966 pci_write_config_dword(pdev, offset, saved_val);
970 pci_read_config_dword(pdev, offset, &val);
971 if (val == saved_val)
978 static void pci_restore_config_space_range(struct pci_dev *pdev,
979 int start, int end, int retry)
983 for (index = end; index >= start; index--)
984 pci_restore_config_dword(pdev, 4 * index,
985 pdev->saved_config_space[index],
989 static void pci_restore_config_space(struct pci_dev *pdev)
991 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
992 pci_restore_config_space_range(pdev, 10, 15, 0);
993 /* Restore BARs before the command register. */
994 pci_restore_config_space_range(pdev, 4, 9, 10);
995 pci_restore_config_space_range(pdev, 0, 3, 0);
997 pci_restore_config_space_range(pdev, 0, 15, 0);
1002 * pci_restore_state - Restore the saved state of a PCI device
1003 * @dev: - PCI device that we're dealing with
1005 void pci_restore_state(struct pci_dev *dev)
1007 if (!dev->state_saved)
1010 /* PCI Express register must be restored first */
1011 pci_restore_pcie_state(dev);
1012 pci_restore_ats_state(dev);
1014 pci_restore_config_space(dev);
1016 pci_restore_pcix_state(dev);
1017 pci_restore_msi_state(dev);
1018 pci_restore_iov_state(dev);
1020 dev->state_saved = false;
1023 struct pci_saved_state {
1024 u32 config_space[16];
1025 struct pci_cap_saved_data cap[0];
1029 * pci_store_saved_state - Allocate and return an opaque struct containing
1030 * the device saved state.
1031 * @dev: PCI device that we're dealing with
1033 * Rerturn NULL if no state or error.
1035 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1037 struct pci_saved_state *state;
1038 struct pci_cap_saved_state *tmp;
1039 struct pci_cap_saved_data *cap;
1042 if (!dev->state_saved)
1045 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1047 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1048 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1050 state = kzalloc(size, GFP_KERNEL);
1054 memcpy(state->config_space, dev->saved_config_space,
1055 sizeof(state->config_space));
1058 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1059 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1060 memcpy(cap, &tmp->cap, len);
1061 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1063 /* Empty cap_save terminates list */
1067 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1070 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1071 * @dev: PCI device that we're dealing with
1072 * @state: Saved state returned from pci_store_saved_state()
1074 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1076 struct pci_cap_saved_data *cap;
1078 dev->state_saved = false;
1083 memcpy(dev->saved_config_space, state->config_space,
1084 sizeof(state->config_space));
1088 struct pci_cap_saved_state *tmp;
1090 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1091 if (!tmp || tmp->cap.size != cap->size)
1094 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1095 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1096 sizeof(struct pci_cap_saved_data) + cap->size);
1099 dev->state_saved = true;
1102 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1105 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1106 * and free the memory allocated for it.
1107 * @dev: PCI device that we're dealing with
1108 * @state: Pointer to saved state returned from pci_store_saved_state()
1110 int pci_load_and_free_saved_state(struct pci_dev *dev,
1111 struct pci_saved_state **state)
1113 int ret = pci_load_saved_state(dev, *state);
1118 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1120 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1124 err = pci_set_power_state(dev, PCI_D0);
1125 if (err < 0 && err != -EIO)
1127 err = pcibios_enable_device(dev, bars);
1130 pci_fixup_device(pci_fixup_enable, dev);
1136 * pci_reenable_device - Resume abandoned device
1137 * @dev: PCI device to be resumed
1139 * Note this function is a backend of pci_default_resume and is not supposed
1140 * to be called by normal code, write proper resume handler and use it instead.
1142 int pci_reenable_device(struct pci_dev *dev)
1144 if (pci_is_enabled(dev))
1145 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1149 static void pci_enable_bridge(struct pci_dev *dev)
1156 pci_enable_bridge(dev->bus->self);
1158 if (pci_is_enabled(dev))
1160 retval = pci_enable_device(dev);
1162 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1164 pci_set_master(dev);
1167 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1173 * Power state could be unknown at this point, either due to a fresh
1174 * boot or a device removal call. So get the current power state
1175 * so that things like MSI message writing will behave as expected
1176 * (e.g. if the device really is in D0 at enable time).
1180 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1181 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1184 if (atomic_inc_return(&dev->enable_cnt) > 1)
1185 return 0; /* already enabled */
1187 pci_enable_bridge(dev->bus->self);
1189 /* only skip sriov related */
1190 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1191 if (dev->resource[i].flags & flags)
1193 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1194 if (dev->resource[i].flags & flags)
1197 err = do_pci_enable_device(dev, bars);
1199 atomic_dec(&dev->enable_cnt);
1204 * pci_enable_device_io - Initialize a device for use with IO space
1205 * @dev: PCI device to be initialized
1207 * Initialize device before it's used by a driver. Ask low-level code
1208 * to enable I/O resources. Wake up the device if it was suspended.
1209 * Beware, this function can fail.
1211 int pci_enable_device_io(struct pci_dev *dev)
1213 return pci_enable_device_flags(dev, IORESOURCE_IO);
1217 * pci_enable_device_mem - Initialize a device for use with Memory space
1218 * @dev: PCI device to be initialized
1220 * Initialize device before it's used by a driver. Ask low-level code
1221 * to enable Memory resources. Wake up the device if it was suspended.
1222 * Beware, this function can fail.
1224 int pci_enable_device_mem(struct pci_dev *dev)
1226 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1230 * pci_enable_device - Initialize device before it's used by a driver.
1231 * @dev: PCI device to be initialized
1233 * Initialize device before it's used by a driver. Ask low-level code
1234 * to enable I/O and memory. Wake up the device if it was suspended.
1235 * Beware, this function can fail.
1237 * Note we don't actually enable the device many times if we call
1238 * this function repeatedly (we just increment the count).
1240 int pci_enable_device(struct pci_dev *dev)
1242 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1246 * Managed PCI resources. This manages device on/off, intx/msi/msix
1247 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1248 * there's no need to track it separately. pci_devres is initialized
1249 * when a device is enabled using managed PCI device enable interface.
1252 unsigned int enabled:1;
1253 unsigned int pinned:1;
1254 unsigned int orig_intx:1;
1255 unsigned int restore_intx:1;
1259 static void pcim_release(struct device *gendev, void *res)
1261 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1262 struct pci_devres *this = res;
1265 if (dev->msi_enabled)
1266 pci_disable_msi(dev);
1267 if (dev->msix_enabled)
1268 pci_disable_msix(dev);
1270 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1271 if (this->region_mask & (1 << i))
1272 pci_release_region(dev, i);
1274 if (this->restore_intx)
1275 pci_intx(dev, this->orig_intx);
1277 if (this->enabled && !this->pinned)
1278 pci_disable_device(dev);
1281 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1283 struct pci_devres *dr, *new_dr;
1285 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1289 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1292 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1295 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1297 if (pci_is_managed(pdev))
1298 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1303 * pcim_enable_device - Managed pci_enable_device()
1304 * @pdev: PCI device to be initialized
1306 * Managed pci_enable_device().
1308 int pcim_enable_device(struct pci_dev *pdev)
1310 struct pci_devres *dr;
1313 dr = get_pci_dr(pdev);
1319 rc = pci_enable_device(pdev);
1321 pdev->is_managed = 1;
1328 * pcim_pin_device - Pin managed PCI device
1329 * @pdev: PCI device to pin
1331 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1332 * driver detach. @pdev must have been enabled with
1333 * pcim_enable_device().
1335 void pcim_pin_device(struct pci_dev *pdev)
1337 struct pci_devres *dr;
1339 dr = find_pci_dr(pdev);
1340 WARN_ON(!dr || !dr->enabled);
1346 * pcibios_add_device - provide arch specific hooks when adding device dev
1347 * @dev: the PCI device being added
1349 * Permits the platform to provide architecture specific functionality when
1350 * devices are added. This is the default implementation. Architecture
1351 * implementations can override this.
1353 int __weak pcibios_add_device (struct pci_dev *dev)
1359 * pcibios_release_device - provide arch specific hooks when releasing device dev
1360 * @dev: the PCI device being released
1362 * Permits the platform to provide architecture specific functionality when
1363 * devices are released. This is the default implementation. Architecture
1364 * implementations can override this.
1366 void __weak pcibios_release_device(struct pci_dev *dev) {}
1369 * pcibios_disable_device - disable arch specific PCI resources for device dev
1370 * @dev: the PCI device to disable
1372 * Disables architecture specific PCI resources for the device. This
1373 * is the default implementation. Architecture implementations can
1376 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1378 static void do_pci_disable_device(struct pci_dev *dev)
1382 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1383 if (pci_command & PCI_COMMAND_MASTER) {
1384 pci_command &= ~PCI_COMMAND_MASTER;
1385 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1388 pcibios_disable_device(dev);
1392 * pci_disable_enabled_device - Disable device without updating enable_cnt
1393 * @dev: PCI device to disable
1395 * NOTE: This function is a backend of PCI power management routines and is
1396 * not supposed to be called drivers.
1398 void pci_disable_enabled_device(struct pci_dev *dev)
1400 if (pci_is_enabled(dev))
1401 do_pci_disable_device(dev);
1405 * pci_disable_device - Disable PCI device after use
1406 * @dev: PCI device to be disabled
1408 * Signal to the system that the PCI device is not in use by the system
1409 * anymore. This only involves disabling PCI bus-mastering, if active.
1411 * Note we don't actually disable the device until all callers of
1412 * pci_enable_device() have called pci_disable_device().
1415 pci_disable_device(struct pci_dev *dev)
1417 struct pci_devres *dr;
1419 dr = find_pci_dr(dev);
1423 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1424 "disabling already-disabled device");
1426 if (atomic_dec_return(&dev->enable_cnt) != 0)
1429 do_pci_disable_device(dev);
1431 dev->is_busmaster = 0;
1435 * pcibios_set_pcie_reset_state - set reset state for device dev
1436 * @dev: the PCIe device reset
1437 * @state: Reset state to enter into
1440 * Sets the PCIe reset state for the device. This is the default
1441 * implementation. Architecture implementations can override this.
1443 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1444 enum pcie_reset_state state)
1450 * pci_set_pcie_reset_state - set reset state for device dev
1451 * @dev: the PCIe device reset
1452 * @state: Reset state to enter into
1455 * Sets the PCI reset state for the device.
1457 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1459 return pcibios_set_pcie_reset_state(dev, state);
1463 * pci_check_pme_status - Check if given device has generated PME.
1464 * @dev: Device to check.
1466 * Check the PME status of the device and if set, clear it and clear PME enable
1467 * (if set). Return 'true' if PME status and PME enable were both set or
1468 * 'false' otherwise.
1470 bool pci_check_pme_status(struct pci_dev *dev)
1479 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1480 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1481 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1484 /* Clear PME status. */
1485 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1486 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1487 /* Disable PME to avoid interrupt flood. */
1488 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1492 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1498 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1499 * @dev: Device to handle.
1500 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1502 * Check if @dev has generated PME and queue a resume request for it in that
1505 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1507 if (pme_poll_reset && dev->pme_poll)
1508 dev->pme_poll = false;
1510 if (pci_check_pme_status(dev)) {
1511 pci_wakeup_event(dev);
1512 pm_request_resume(&dev->dev);
1518 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1519 * @bus: Top bus of the subtree to walk.
1521 void pci_pme_wakeup_bus(struct pci_bus *bus)
1524 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1528 * pci_wakeup - Wake up a PCI device
1529 * @pci_dev: Device to handle.
1530 * @ign: ignored parameter
1532 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1534 pci_wakeup_event(pci_dev);
1535 pm_request_resume(&pci_dev->dev);
1540 * pci_wakeup_bus - Walk given bus and wake up devices on it
1541 * @bus: Top bus of the subtree to walk.
1543 void pci_wakeup_bus(struct pci_bus *bus)
1546 pci_walk_bus(bus, pci_wakeup, NULL);
1550 * pci_pme_capable - check the capability of PCI device to generate PME#
1551 * @dev: PCI device to handle.
1552 * @state: PCI state from which device will issue PME#.
1554 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1559 return !!(dev->pme_support & (1 << state));
1562 static void pci_pme_list_scan(struct work_struct *work)
1564 struct pci_pme_device *pme_dev, *n;
1566 mutex_lock(&pci_pme_list_mutex);
1567 if (!list_empty(&pci_pme_list)) {
1568 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1569 if (pme_dev->dev->pme_poll) {
1570 struct pci_dev *bridge;
1572 bridge = pme_dev->dev->bus->self;
1574 * If bridge is in low power state, the
1575 * configuration space of subordinate devices
1576 * may be not accessible
1578 if (bridge && bridge->current_state != PCI_D0)
1580 pci_pme_wakeup(pme_dev->dev, NULL);
1582 list_del(&pme_dev->list);
1586 if (!list_empty(&pci_pme_list))
1587 schedule_delayed_work(&pci_pme_work,
1588 msecs_to_jiffies(PME_TIMEOUT));
1590 mutex_unlock(&pci_pme_list_mutex);
1594 * pci_pme_active - enable or disable PCI device's PME# function
1595 * @dev: PCI device to handle.
1596 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1598 * The caller must verify that the device is capable of generating PME# before
1599 * calling this function with @enable equal to 'true'.
1601 void pci_pme_active(struct pci_dev *dev, bool enable)
1605 if (!dev->pme_support)
1608 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1609 /* Clear PME_Status by writing 1 to it and enable PME# */
1610 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1612 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1614 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1617 * PCI (as opposed to PCIe) PME requires that the device have
1618 * its PME# line hooked up correctly. Not all hardware vendors
1619 * do this, so the PME never gets delivered and the device
1620 * remains asleep. The easiest way around this is to
1621 * periodically walk the list of suspended devices and check
1622 * whether any have their PME flag set. The assumption is that
1623 * we'll wake up often enough anyway that this won't be a huge
1624 * hit, and the power savings from the devices will still be a
1627 * Although PCIe uses in-band PME message instead of PME# line
1628 * to report PME, PME does not work for some PCIe devices in
1629 * reality. For example, there are devices that set their PME
1630 * status bits, but don't really bother to send a PME message;
1631 * there are PCI Express Root Ports that don't bother to
1632 * trigger interrupts when they receive PME messages from the
1633 * devices below. So PME poll is used for PCIe devices too.
1636 if (dev->pme_poll) {
1637 struct pci_pme_device *pme_dev;
1639 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1644 mutex_lock(&pci_pme_list_mutex);
1645 list_add(&pme_dev->list, &pci_pme_list);
1646 if (list_is_singular(&pci_pme_list))
1647 schedule_delayed_work(&pci_pme_work,
1648 msecs_to_jiffies(PME_TIMEOUT));
1649 mutex_unlock(&pci_pme_list_mutex);
1651 mutex_lock(&pci_pme_list_mutex);
1652 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1653 if (pme_dev->dev == dev) {
1654 list_del(&pme_dev->list);
1659 mutex_unlock(&pci_pme_list_mutex);
1664 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1668 * __pci_enable_wake - enable PCI device as wakeup event source
1669 * @dev: PCI device affected
1670 * @state: PCI state from which device will issue wakeup events
1671 * @runtime: True if the events are to be generated at run time
1672 * @enable: True to enable event generation; false to disable
1674 * This enables the device as a wakeup event source, or disables it.
1675 * When such events involves platform-specific hooks, those hooks are
1676 * called automatically by this routine.
1678 * Devices with legacy power management (no standard PCI PM capabilities)
1679 * always require such platform hooks.
1682 * 0 is returned on success
1683 * -EINVAL is returned if device is not supposed to wake up the system
1684 * Error code depending on the platform is returned if both the platform and
1685 * the native mechanism fail to enable the generation of wake-up events
1687 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1688 bool runtime, bool enable)
1692 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1695 /* Don't do the same thing twice in a row for one device. */
1696 if (!!enable == !!dev->wakeup_prepared)
1700 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1701 * Anderson we should be doing PME# wake enable followed by ACPI wake
1702 * enable. To disable wake-up we call the platform first, for symmetry.
1708 if (pci_pme_capable(dev, state))
1709 pci_pme_active(dev, true);
1712 error = runtime ? platform_pci_run_wake(dev, true) :
1713 platform_pci_sleep_wake(dev, true);
1717 dev->wakeup_prepared = true;
1720 platform_pci_run_wake(dev, false);
1722 platform_pci_sleep_wake(dev, false);
1723 pci_pme_active(dev, false);
1724 dev->wakeup_prepared = false;
1729 EXPORT_SYMBOL(__pci_enable_wake);
1732 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1733 * @dev: PCI device to prepare
1734 * @enable: True to enable wake-up event generation; false to disable
1736 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1737 * and this function allows them to set that up cleanly - pci_enable_wake()
1738 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1739 * ordering constraints.
1741 * This function only returns error code if the device is not capable of
1742 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1743 * enable wake-up power for it.
1745 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1747 return pci_pme_capable(dev, PCI_D3cold) ?
1748 pci_enable_wake(dev, PCI_D3cold, enable) :
1749 pci_enable_wake(dev, PCI_D3hot, enable);
1753 * pci_target_state - find an appropriate low power state for a given PCI dev
1756 * Use underlying platform code to find a supported low power state for @dev.
1757 * If the platform can't manage @dev, return the deepest state from which it
1758 * can generate wake events, based on any available PME info.
1760 pci_power_t pci_target_state(struct pci_dev *dev)
1762 pci_power_t target_state = PCI_D3hot;
1764 if (platform_pci_power_manageable(dev)) {
1766 * Call the platform to choose the target state of the device
1767 * and enable wake-up from this state if supported.
1769 pci_power_t state = platform_pci_choose_state(dev);
1772 case PCI_POWER_ERROR:
1777 if (pci_no_d1d2(dev))
1780 target_state = state;
1782 } else if (!dev->pm_cap) {
1783 target_state = PCI_D0;
1784 } else if (device_may_wakeup(&dev->dev)) {
1786 * Find the deepest state from which the device can generate
1787 * wake-up events, make it the target state and enable device
1790 if (dev->pme_support) {
1792 && !(dev->pme_support & (1 << target_state)))
1797 return target_state;
1801 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1802 * @dev: Device to handle.
1804 * Choose the power state appropriate for the device depending on whether
1805 * it can wake up the system and/or is power manageable by the platform
1806 * (PCI_D3hot is the default) and put the device into that state.
1808 int pci_prepare_to_sleep(struct pci_dev *dev)
1810 pci_power_t target_state = pci_target_state(dev);
1813 if (target_state == PCI_POWER_ERROR)
1816 /* D3cold during system suspend/hibernate is not supported */
1817 if (target_state > PCI_D3hot)
1818 target_state = PCI_D3hot;
1820 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1822 error = pci_set_power_state(dev, target_state);
1825 pci_enable_wake(dev, target_state, false);
1831 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1832 * @dev: Device to handle.
1834 * Disable device's system wake-up capability and put it into D0.
1836 int pci_back_from_sleep(struct pci_dev *dev)
1838 pci_enable_wake(dev, PCI_D0, false);
1839 return pci_set_power_state(dev, PCI_D0);
1843 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1844 * @dev: PCI device being suspended.
1846 * Prepare @dev to generate wake-up events at run time and put it into a low
1849 int pci_finish_runtime_suspend(struct pci_dev *dev)
1851 pci_power_t target_state = pci_target_state(dev);
1854 if (target_state == PCI_POWER_ERROR)
1857 dev->runtime_d3cold = target_state == PCI_D3cold;
1859 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1861 error = pci_set_power_state(dev, target_state);
1864 __pci_enable_wake(dev, target_state, true, false);
1865 dev->runtime_d3cold = false;
1872 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1873 * @dev: Device to check.
1875 * Return true if the device itself is cabable of generating wake-up events
1876 * (through the platform or using the native PCIe PME) or if the device supports
1877 * PME and one of its upstream bridges can generate wake-up events.
1879 bool pci_dev_run_wake(struct pci_dev *dev)
1881 struct pci_bus *bus = dev->bus;
1883 if (device_run_wake(&dev->dev))
1886 if (!dev->pme_support)
1889 while (bus->parent) {
1890 struct pci_dev *bridge = bus->self;
1892 if (device_run_wake(&bridge->dev))
1898 /* We have reached the root bus. */
1900 return device_run_wake(bus->bridge);
1904 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1906 void pci_config_pm_runtime_get(struct pci_dev *pdev)
1908 struct device *dev = &pdev->dev;
1909 struct device *parent = dev->parent;
1912 pm_runtime_get_sync(parent);
1913 pm_runtime_get_noresume(dev);
1915 * pdev->current_state is set to PCI_D3cold during suspending,
1916 * so wait until suspending completes
1918 pm_runtime_barrier(dev);
1920 * Only need to resume devices in D3cold, because config
1921 * registers are still accessible for devices suspended but
1924 if (pdev->current_state == PCI_D3cold)
1925 pm_runtime_resume(dev);
1928 void pci_config_pm_runtime_put(struct pci_dev *pdev)
1930 struct device *dev = &pdev->dev;
1931 struct device *parent = dev->parent;
1933 pm_runtime_put(dev);
1935 pm_runtime_put_sync(parent);
1939 * pci_pm_init - Initialize PM functions of given PCI device
1940 * @dev: PCI device to handle.
1942 void pci_pm_init(struct pci_dev *dev)
1947 pm_runtime_forbid(&dev->dev);
1948 pm_runtime_set_active(&dev->dev);
1949 pm_runtime_enable(&dev->dev);
1950 device_enable_async_suspend(&dev->dev);
1951 dev->wakeup_prepared = false;
1954 dev->pme_support = 0;
1956 /* find PCI PM capability in list */
1957 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1960 /* Check device's ability to generate PME# */
1961 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1963 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1964 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1965 pmc & PCI_PM_CAP_VER_MASK);
1970 dev->d3_delay = PCI_PM_D3_WAIT;
1971 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1972 dev->d3cold_allowed = true;
1974 dev->d1_support = false;
1975 dev->d2_support = false;
1976 if (!pci_no_d1d2(dev)) {
1977 if (pmc & PCI_PM_CAP_D1)
1978 dev->d1_support = true;
1979 if (pmc & PCI_PM_CAP_D2)
1980 dev->d2_support = true;
1982 if (dev->d1_support || dev->d2_support)
1983 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1984 dev->d1_support ? " D1" : "",
1985 dev->d2_support ? " D2" : "");
1988 pmc &= PCI_PM_CAP_PME_MASK;
1990 dev_printk(KERN_DEBUG, &dev->dev,
1991 "PME# supported from%s%s%s%s%s\n",
1992 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1993 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1994 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1995 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1996 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1997 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1998 dev->pme_poll = true;
2000 * Make device's PM flags reflect the wake-up capability, but
2001 * let the user space enable it to wake up the system as needed.
2003 device_set_wakeup_capable(&dev->dev, true);
2004 /* Disable the PME# generation functionality */
2005 pci_pme_active(dev, false);
2009 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2010 struct pci_cap_saved_state *new_cap)
2012 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2016 * pci_add_cap_save_buffer - allocate buffer for saving given capability registers
2017 * @dev: the PCI device
2018 * @cap: the capability to allocate the buffer for
2019 * @size: requested size of the buffer
2021 static int pci_add_cap_save_buffer(
2022 struct pci_dev *dev, char cap, unsigned int size)
2025 struct pci_cap_saved_state *save_state;
2027 pos = pci_find_capability(dev, cap);
2031 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2035 save_state->cap.cap_nr = cap;
2036 save_state->cap.size = size;
2037 pci_add_saved_cap(dev, save_state);
2043 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2044 * @dev: the PCI device
2046 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2050 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2051 PCI_EXP_SAVE_REGS * sizeof(u16));
2054 "unable to preallocate PCI Express save buffer\n");
2056 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2059 "unable to preallocate PCI-X save buffer\n");
2062 void pci_free_cap_save_buffers(struct pci_dev *dev)
2064 struct pci_cap_saved_state *tmp;
2065 struct hlist_node *n;
2067 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2072 * pci_configure_ari - enable or disable ARI forwarding
2073 * @dev: the PCI device
2075 * If @dev and its upstream bridge both support ARI, enable ARI in the
2076 * bridge. Otherwise, disable ARI in the bridge.
2078 void pci_configure_ari(struct pci_dev *dev)
2081 struct pci_dev *bridge;
2083 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2086 bridge = dev->bus->self;
2090 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2091 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2094 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2095 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2096 PCI_EXP_DEVCTL2_ARI);
2097 bridge->ari_enabled = 1;
2099 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2100 PCI_EXP_DEVCTL2_ARI);
2101 bridge->ari_enabled = 0;
2106 * pci_enable_ido - enable ID-based Ordering on a device
2107 * @dev: the PCI device
2108 * @type: which types of IDO to enable
2110 * Enable ID-based ordering on @dev. @type can contain the bits
2111 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2112 * which types of transactions are allowed to be re-ordered.
2114 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2118 if (type & PCI_EXP_IDO_REQUEST)
2119 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
2120 if (type & PCI_EXP_IDO_COMPLETION)
2121 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
2123 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2125 EXPORT_SYMBOL(pci_enable_ido);
2128 * pci_disable_ido - disable ID-based ordering on a device
2129 * @dev: the PCI device
2130 * @type: which types of IDO to disable
2132 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2136 if (type & PCI_EXP_IDO_REQUEST)
2137 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
2138 if (type & PCI_EXP_IDO_COMPLETION)
2139 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
2141 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2143 EXPORT_SYMBOL(pci_disable_ido);
2146 * pci_enable_obff - enable optimized buffer flush/fill
2148 * @type: type of signaling to use
2150 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2151 * signaling if possible, falling back to message signaling only if
2152 * WAKE# isn't supported. @type should indicate whether the PCIe link
2153 * be brought out of L0s or L1 to send the message. It should be either
2154 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2156 * If your device can benefit from receiving all messages, even at the
2157 * power cost of bringing the link back up from a low power state, use
2158 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2162 * Zero on success, appropriate error number on failure.
2164 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2170 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2171 if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))
2172 return -ENOTSUPP; /* no OBFF support at all */
2174 /* Make sure the topology supports OBFF as well */
2175 if (dev->bus->self) {
2176 ret = pci_enable_obff(dev->bus->self, type);
2181 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2182 if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)
2183 ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
2186 case PCI_EXP_OBFF_SIGNAL_L0:
2187 if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))
2188 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;
2190 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2191 ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
2192 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;
2195 WARN(1, "bad OBFF signal type\n");
2199 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2203 EXPORT_SYMBOL(pci_enable_obff);
2206 * pci_disable_obff - disable optimized buffer flush/fill
2209 * Disable OBFF on @dev.
2211 void pci_disable_obff(struct pci_dev *dev)
2213 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2214 PCI_EXP_DEVCTL2_OBFF_WAKE_EN);
2216 EXPORT_SYMBOL(pci_disable_obff);
2219 * pci_ltr_supported - check whether a device supports LTR
2223 * True if @dev supports latency tolerance reporting, false otherwise.
2225 static bool pci_ltr_supported(struct pci_dev *dev)
2229 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2231 return cap & PCI_EXP_DEVCAP2_LTR;
2235 * pci_enable_ltr - enable latency tolerance reporting
2238 * Enable LTR on @dev if possible, which means enabling it first on
2242 * Zero on success, errno on failure.
2244 int pci_enable_ltr(struct pci_dev *dev)
2248 /* Only primary function can enable/disable LTR */
2249 if (PCI_FUNC(dev->devfn) != 0)
2252 if (!pci_ltr_supported(dev))
2255 /* Enable upstream ports first */
2256 if (dev->bus->self) {
2257 ret = pci_enable_ltr(dev->bus->self);
2262 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2263 PCI_EXP_DEVCTL2_LTR_EN);
2265 EXPORT_SYMBOL(pci_enable_ltr);
2268 * pci_disable_ltr - disable latency tolerance reporting
2271 void pci_disable_ltr(struct pci_dev *dev)
2273 /* Only primary function can enable/disable LTR */
2274 if (PCI_FUNC(dev->devfn) != 0)
2277 if (!pci_ltr_supported(dev))
2280 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2281 PCI_EXP_DEVCTL2_LTR_EN);
2283 EXPORT_SYMBOL(pci_disable_ltr);
2285 static int __pci_ltr_scale(int *val)
2289 while (*val > 1023) {
2290 *val = (*val + 31) / 32;
2297 * pci_set_ltr - set LTR latency values
2299 * @snoop_lat_ns: snoop latency in nanoseconds
2300 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2302 * Figure out the scale and set the LTR values accordingly.
2304 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2306 int pos, ret, snoop_scale, nosnoop_scale;
2309 if (!pci_ltr_supported(dev))
2312 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2313 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2315 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2316 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2319 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2320 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2323 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2327 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2328 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2332 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2333 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2339 EXPORT_SYMBOL(pci_set_ltr);
2341 static int pci_acs_enable;
2344 * pci_request_acs - ask for ACS to be enabled if supported
2346 void pci_request_acs(void)
2352 * pci_enable_acs - enable ACS if hardware support it
2353 * @dev: the PCI device
2355 void pci_enable_acs(struct pci_dev *dev)
2361 if (!pci_acs_enable)
2364 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2368 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2369 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2371 /* Source Validation */
2372 ctrl |= (cap & PCI_ACS_SV);
2374 /* P2P Request Redirect */
2375 ctrl |= (cap & PCI_ACS_RR);
2377 /* P2P Completion Redirect */
2378 ctrl |= (cap & PCI_ACS_CR);
2380 /* Upstream Forwarding */
2381 ctrl |= (cap & PCI_ACS_UF);
2383 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2386 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2391 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2396 * Except for egress control, capabilities are either required
2397 * or only required if controllable. Features missing from the
2398 * capability field can therefore be assumed as hard-wired enabled.
2400 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2401 acs_flags &= (cap | PCI_ACS_EC);
2403 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2404 return (ctrl & acs_flags) == acs_flags;
2408 * pci_acs_enabled - test ACS against required flags for a given device
2409 * @pdev: device to test
2410 * @acs_flags: required PCI ACS flags
2412 * Return true if the device supports the provided flags. Automatically
2413 * filters out flags that are not implemented on multifunction devices.
2415 * Note that this interface checks the effective ACS capabilities of the
2416 * device rather than the actual capabilities. For instance, most single
2417 * function endpoints are not required to support ACS because they have no
2418 * opportunity for peer-to-peer access. We therefore return 'true'
2419 * regardless of whether the device exposes an ACS capability. This makes
2420 * it much easier for callers of this function to ignore the actual type
2421 * or topology of the device when testing ACS support.
2423 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2427 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2432 * Conventional PCI and PCI-X devices never support ACS, either
2433 * effectively or actually. The shared bus topology implies that
2434 * any device on the bus can receive or snoop DMA.
2436 if (!pci_is_pcie(pdev))
2439 switch (pci_pcie_type(pdev)) {
2441 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2442 * but since their primary inteface is PCI/X, we conservatively
2443 * handle them as we would a non-PCIe device.
2445 case PCI_EXP_TYPE_PCIE_BRIDGE:
2447 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2448 * applicable... must never implement an ACS Extended Capability...".
2449 * This seems arbitrary, but we take a conservative interpretation
2450 * of this statement.
2452 case PCI_EXP_TYPE_PCI_BRIDGE:
2453 case PCI_EXP_TYPE_RC_EC:
2456 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2457 * implement ACS in order to indicate their peer-to-peer capabilities,
2458 * regardless of whether they are single- or multi-function devices.
2460 case PCI_EXP_TYPE_DOWNSTREAM:
2461 case PCI_EXP_TYPE_ROOT_PORT:
2462 return pci_acs_flags_enabled(pdev, acs_flags);
2464 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2465 * implemented by the remaining PCIe types to indicate peer-to-peer
2466 * capabilities, but only when they are part of a multifunciton
2467 * device. The footnote for section 6.12 indicates the specific
2468 * PCIe types included here.
2470 case PCI_EXP_TYPE_ENDPOINT:
2471 case PCI_EXP_TYPE_UPSTREAM:
2472 case PCI_EXP_TYPE_LEG_END:
2473 case PCI_EXP_TYPE_RC_END:
2474 if (!pdev->multifunction)
2477 return pci_acs_flags_enabled(pdev, acs_flags);
2481 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable
2482 * to single function devices with the exception of downstream ports.
2488 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2489 * @start: starting downstream device
2490 * @end: ending upstream device or NULL to search to the root bus
2491 * @acs_flags: required flags
2493 * Walk up a device tree from start to end testing PCI ACS support. If
2494 * any step along the way does not support the required flags, return false.
2496 bool pci_acs_path_enabled(struct pci_dev *start,
2497 struct pci_dev *end, u16 acs_flags)
2499 struct pci_dev *pdev, *parent = start;
2504 if (!pci_acs_enabled(pdev, acs_flags))
2507 if (pci_is_root_bus(pdev->bus))
2508 return (end == NULL);
2510 parent = pdev->bus->self;
2511 } while (pdev != end);
2517 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2518 * @dev: the PCI device
2519 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2521 * Perform INTx swizzling for a device behind one level of bridge. This is
2522 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2523 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2524 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2525 * the PCI Express Base Specification, Revision 2.1)
2527 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2531 if (pci_ari_enabled(dev->bus))
2534 slot = PCI_SLOT(dev->devfn);
2536 return (((pin - 1) + slot) % 4) + 1;
2540 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2548 while (!pci_is_root_bus(dev->bus)) {
2549 pin = pci_swizzle_interrupt_pin(dev, pin);
2550 dev = dev->bus->self;
2557 * pci_common_swizzle - swizzle INTx all the way to root bridge
2558 * @dev: the PCI device
2559 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2561 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2562 * bridges all the way up to a PCI root bus.
2564 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2568 while (!pci_is_root_bus(dev->bus)) {
2569 pin = pci_swizzle_interrupt_pin(dev, pin);
2570 dev = dev->bus->self;
2573 return PCI_SLOT(dev->devfn);
2577 * pci_release_region - Release a PCI bar
2578 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2579 * @bar: BAR to release
2581 * Releases the PCI I/O and memory resources previously reserved by a
2582 * successful call to pci_request_region. Call this function only
2583 * after all use of the PCI regions has ceased.
2585 void pci_release_region(struct pci_dev *pdev, int bar)
2587 struct pci_devres *dr;
2589 if (pci_resource_len(pdev, bar) == 0)
2591 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2592 release_region(pci_resource_start(pdev, bar),
2593 pci_resource_len(pdev, bar));
2594 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2595 release_mem_region(pci_resource_start(pdev, bar),
2596 pci_resource_len(pdev, bar));
2598 dr = find_pci_dr(pdev);
2600 dr->region_mask &= ~(1 << bar);
2604 * __pci_request_region - Reserved PCI I/O and memory resource
2605 * @pdev: PCI device whose resources are to be reserved
2606 * @bar: BAR to be reserved
2607 * @res_name: Name to be associated with resource.
2608 * @exclusive: whether the region access is exclusive or not
2610 * Mark the PCI region associated with PCI device @pdev BR @bar as
2611 * being reserved by owner @res_name. Do not access any
2612 * address inside the PCI regions unless this call returns
2615 * If @exclusive is set, then the region is marked so that userspace
2616 * is explicitly not allowed to map the resource via /dev/mem or
2617 * sysfs MMIO access.
2619 * Returns 0 on success, or %EBUSY on error. A warning
2620 * message is also printed on failure.
2622 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2625 struct pci_devres *dr;
2627 if (pci_resource_len(pdev, bar) == 0)
2630 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2631 if (!request_region(pci_resource_start(pdev, bar),
2632 pci_resource_len(pdev, bar), res_name))
2635 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2636 if (!__request_mem_region(pci_resource_start(pdev, bar),
2637 pci_resource_len(pdev, bar), res_name,
2642 dr = find_pci_dr(pdev);
2644 dr->region_mask |= 1 << bar;
2649 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2650 &pdev->resource[bar]);
2655 * pci_request_region - Reserve PCI I/O and memory resource
2656 * @pdev: PCI device whose resources are to be reserved
2657 * @bar: BAR to be reserved
2658 * @res_name: Name to be associated with resource
2660 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2661 * being reserved by owner @res_name. Do not access any
2662 * address inside the PCI regions unless this call returns
2665 * Returns 0 on success, or %EBUSY on error. A warning
2666 * message is also printed on failure.
2668 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2670 return __pci_request_region(pdev, bar, res_name, 0);
2674 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2675 * @pdev: PCI device whose resources are to be reserved
2676 * @bar: BAR to be reserved
2677 * @res_name: Name to be associated with resource.
2679 * Mark the PCI region associated with PCI device @pdev BR @bar as
2680 * being reserved by owner @res_name. Do not access any
2681 * address inside the PCI regions unless this call returns
2684 * Returns 0 on success, or %EBUSY on error. A warning
2685 * message is also printed on failure.
2687 * The key difference that _exclusive makes it that userspace is
2688 * explicitly not allowed to map the resource via /dev/mem or
2691 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2693 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2696 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2697 * @pdev: PCI device whose resources were previously reserved
2698 * @bars: Bitmask of BARs to be released
2700 * Release selected PCI I/O and memory resources previously reserved.
2701 * Call this function only after all use of the PCI regions has ceased.
2703 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2707 for (i = 0; i < 6; i++)
2708 if (bars & (1 << i))
2709 pci_release_region(pdev, i);
2712 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2713 const char *res_name, int excl)
2717 for (i = 0; i < 6; i++)
2718 if (bars & (1 << i))
2719 if (__pci_request_region(pdev, i, res_name, excl))
2725 if (bars & (1 << i))
2726 pci_release_region(pdev, i);
2733 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2734 * @pdev: PCI device whose resources are to be reserved
2735 * @bars: Bitmask of BARs to be requested
2736 * @res_name: Name to be associated with resource
2738 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2739 const char *res_name)
2741 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2744 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2745 int bars, const char *res_name)
2747 return __pci_request_selected_regions(pdev, bars, res_name,
2748 IORESOURCE_EXCLUSIVE);
2752 * pci_release_regions - Release reserved PCI I/O and memory resources
2753 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2755 * Releases all PCI I/O and memory resources previously reserved by a
2756 * successful call to pci_request_regions. Call this function only
2757 * after all use of the PCI regions has ceased.
2760 void pci_release_regions(struct pci_dev *pdev)
2762 pci_release_selected_regions(pdev, (1 << 6) - 1);
2766 * pci_request_regions - Reserved PCI I/O and memory resources
2767 * @pdev: PCI device whose resources are to be reserved
2768 * @res_name: Name to be associated with resource.
2770 * Mark all PCI regions associated with PCI device @pdev as
2771 * being reserved by owner @res_name. Do not access any
2772 * address inside the PCI regions unless this call returns
2775 * Returns 0 on success, or %EBUSY on error. A warning
2776 * message is also printed on failure.
2778 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2780 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2784 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2785 * @pdev: PCI device whose resources are to be reserved
2786 * @res_name: Name to be associated with resource.
2788 * Mark all PCI regions associated with PCI device @pdev as
2789 * being reserved by owner @res_name. Do not access any
2790 * address inside the PCI regions unless this call returns
2793 * pci_request_regions_exclusive() will mark the region so that
2794 * /dev/mem and the sysfs MMIO access will not be allowed.
2796 * Returns 0 on success, or %EBUSY on error. A warning
2797 * message is also printed on failure.
2799 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2801 return pci_request_selected_regions_exclusive(pdev,
2802 ((1 << 6) - 1), res_name);
2805 static void __pci_set_master(struct pci_dev *dev, bool enable)
2809 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2811 cmd = old_cmd | PCI_COMMAND_MASTER;
2813 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2814 if (cmd != old_cmd) {
2815 dev_dbg(&dev->dev, "%s bus mastering\n",
2816 enable ? "enabling" : "disabling");
2817 pci_write_config_word(dev, PCI_COMMAND, cmd);
2819 dev->is_busmaster = enable;
2823 * pcibios_setup - process "pci=" kernel boot arguments
2824 * @str: string used to pass in "pci=" kernel boot arguments
2826 * Process kernel boot arguments. This is the default implementation.
2827 * Architecture specific implementations can override this as necessary.
2829 char * __weak __init pcibios_setup(char *str)
2835 * pcibios_set_master - enable PCI bus-mastering for device dev
2836 * @dev: the PCI device to enable
2838 * Enables PCI bus-mastering for the device. This is the default
2839 * implementation. Architecture specific implementations can override
2840 * this if necessary.
2842 void __weak pcibios_set_master(struct pci_dev *dev)
2846 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2847 if (pci_is_pcie(dev))
2850 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2852 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2853 else if (lat > pcibios_max_latency)
2854 lat = pcibios_max_latency;
2857 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2858 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2862 * pci_set_master - enables bus-mastering for device dev
2863 * @dev: the PCI device to enable
2865 * Enables bus-mastering on the device and calls pcibios_set_master()
2866 * to do the needed arch specific settings.
2868 void pci_set_master(struct pci_dev *dev)
2870 __pci_set_master(dev, true);
2871 pcibios_set_master(dev);
2875 * pci_clear_master - disables bus-mastering for device dev
2876 * @dev: the PCI device to disable
2878 void pci_clear_master(struct pci_dev *dev)
2880 __pci_set_master(dev, false);
2884 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2885 * @dev: the PCI device for which MWI is to be enabled
2887 * Helper function for pci_set_mwi.
2888 * Originally copied from drivers/net/acenic.c.
2889 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2891 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2893 int pci_set_cacheline_size(struct pci_dev *dev)
2897 if (!pci_cache_line_size)
2900 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2901 equal to or multiple of the right value. */
2902 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2903 if (cacheline_size >= pci_cache_line_size &&
2904 (cacheline_size % pci_cache_line_size) == 0)
2907 /* Write the correct value. */
2908 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2910 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2911 if (cacheline_size == pci_cache_line_size)
2914 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2915 "supported\n", pci_cache_line_size << 2);
2919 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2921 #ifdef PCI_DISABLE_MWI
2922 int pci_set_mwi(struct pci_dev *dev)
2927 int pci_try_set_mwi(struct pci_dev *dev)
2932 void pci_clear_mwi(struct pci_dev *dev)
2939 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2940 * @dev: the PCI device for which MWI is enabled
2942 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2944 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2947 pci_set_mwi(struct pci_dev *dev)
2952 rc = pci_set_cacheline_size(dev);
2956 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2957 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2958 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2959 cmd |= PCI_COMMAND_INVALIDATE;
2960 pci_write_config_word(dev, PCI_COMMAND, cmd);
2967 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2968 * @dev: the PCI device for which MWI is enabled
2970 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2971 * Callers are not required to check the return value.
2973 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2975 int pci_try_set_mwi(struct pci_dev *dev)
2977 int rc = pci_set_mwi(dev);
2982 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2983 * @dev: the PCI device to disable
2985 * Disables PCI Memory-Write-Invalidate transaction on the device
2988 pci_clear_mwi(struct pci_dev *dev)
2992 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2993 if (cmd & PCI_COMMAND_INVALIDATE) {
2994 cmd &= ~PCI_COMMAND_INVALIDATE;
2995 pci_write_config_word(dev, PCI_COMMAND, cmd);
2998 #endif /* ! PCI_DISABLE_MWI */
3001 * pci_intx - enables/disables PCI INTx for device dev
3002 * @pdev: the PCI device to operate on
3003 * @enable: boolean: whether to enable or disable PCI INTx
3005 * Enables/disables PCI INTx for device dev
3008 pci_intx(struct pci_dev *pdev, int enable)
3010 u16 pci_command, new;
3012 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3015 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3017 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3020 if (new != pci_command) {
3021 struct pci_devres *dr;
3023 pci_write_config_word(pdev, PCI_COMMAND, new);
3025 dr = find_pci_dr(pdev);
3026 if (dr && !dr->restore_intx) {
3027 dr->restore_intx = 1;
3028 dr->orig_intx = !enable;
3034 * pci_intx_mask_supported - probe for INTx masking support
3035 * @dev: the PCI device to operate on
3037 * Check if the device dev support INTx masking via the config space
3040 bool pci_intx_mask_supported(struct pci_dev *dev)
3042 bool mask_supported = false;
3045 if (dev->broken_intx_masking)
3048 pci_cfg_access_lock(dev);
3050 pci_read_config_word(dev, PCI_COMMAND, &orig);
3051 pci_write_config_word(dev, PCI_COMMAND,
3052 orig ^ PCI_COMMAND_INTX_DISABLE);
3053 pci_read_config_word(dev, PCI_COMMAND, &new);
3056 * There's no way to protect against hardware bugs or detect them
3057 * reliably, but as long as we know what the value should be, let's
3058 * go ahead and check it.
3060 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3061 dev_err(&dev->dev, "Command register changed from "
3062 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
3063 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3064 mask_supported = true;
3065 pci_write_config_word(dev, PCI_COMMAND, orig);
3068 pci_cfg_access_unlock(dev);
3069 return mask_supported;
3071 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3073 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3075 struct pci_bus *bus = dev->bus;
3076 bool mask_updated = true;
3077 u32 cmd_status_dword;
3078 u16 origcmd, newcmd;
3079 unsigned long flags;
3083 * We do a single dword read to retrieve both command and status.
3084 * Document assumptions that make this possible.
3086 BUILD_BUG_ON(PCI_COMMAND % 4);
3087 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3089 raw_spin_lock_irqsave(&pci_lock, flags);
3091 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3093 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3096 * Check interrupt status register to see whether our device
3097 * triggered the interrupt (when masking) or the next IRQ is
3098 * already pending (when unmasking).
3100 if (mask != irq_pending) {
3101 mask_updated = false;
3105 origcmd = cmd_status_dword;
3106 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3108 newcmd |= PCI_COMMAND_INTX_DISABLE;
3109 if (newcmd != origcmd)
3110 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3113 raw_spin_unlock_irqrestore(&pci_lock, flags);
3115 return mask_updated;
3119 * pci_check_and_mask_intx - mask INTx on pending interrupt
3120 * @dev: the PCI device to operate on
3122 * Check if the device dev has its INTx line asserted, mask it and
3123 * return true in that case. False is returned if not interrupt was
3126 bool pci_check_and_mask_intx(struct pci_dev *dev)
3128 return pci_check_and_set_intx_mask(dev, true);
3130 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3133 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
3134 * @dev: the PCI device to operate on
3136 * Check if the device dev has its INTx line asserted, unmask it if not
3137 * and return true. False is returned and the mask remains active if
3138 * there was still an interrupt pending.
3140 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3142 return pci_check_and_set_intx_mask(dev, false);
3144 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3147 * pci_msi_off - disables any MSI or MSI-X capabilities
3148 * @dev: the PCI device to operate on
3150 * If you want to use MSI, see pci_enable_msi() and friends.
3151 * This is a lower-level primitive that allows us to disable
3152 * MSI operation at the device level.
3154 void pci_msi_off(struct pci_dev *dev)
3160 * This looks like it could go in msi.c, but we need it even when
3161 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3162 * dev->msi_cap or dev->msix_cap here.
3164 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3166 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3167 control &= ~PCI_MSI_FLAGS_ENABLE;
3168 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3170 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3172 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3173 control &= ~PCI_MSIX_FLAGS_ENABLE;
3174 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3177 EXPORT_SYMBOL_GPL(pci_msi_off);
3179 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3181 return dma_set_max_seg_size(&dev->dev, size);
3183 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3185 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3187 return dma_set_seg_boundary(&dev->dev, mask);
3189 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3192 * pci_wait_for_pending_transaction - waits for pending transaction
3193 * @dev: the PCI device to operate on
3195 * Return 0 if transaction is pending 1 otherwise.
3197 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3202 /* Wait for Transaction Pending bit clean */
3203 for (i = 0; i < 4; i++) {
3205 msleep((1 << (i - 1)) * 100);
3207 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3208 if (!(status & PCI_EXP_DEVSTA_TRPND))
3214 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3216 static int pcie_flr(struct pci_dev *dev, int probe)
3220 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3221 if (!(cap & PCI_EXP_DEVCAP_FLR))
3227 if (!pci_wait_for_pending_transaction(dev))
3228 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3230 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3237 static int pci_af_flr(struct pci_dev *dev, int probe)
3244 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3248 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3249 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3255 /* Wait for Transaction Pending bit clean */
3256 for (i = 0; i < 4; i++) {
3258 msleep((1 << (i - 1)) * 100);
3260 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3261 if (!(status & PCI_AF_STATUS_TP))
3265 dev_err(&dev->dev, "transaction is not cleared; "
3266 "proceeding with reset anyway\n");
3269 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3276 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3277 * @dev: Device to reset.
3278 * @probe: If set, only check if the device can be reset this way.
3280 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3281 * unset, it will be reinitialized internally when going from PCI_D3hot to
3282 * PCI_D0. If that's the case and the device is not in a low-power state
3283 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3285 * NOTE: This causes the caller to sleep for twice the device power transition
3286 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3287 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3288 * Moreover, only devices in D0 can be reset by this function.
3290 static int pci_pm_reset(struct pci_dev *dev, int probe)
3297 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3298 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3304 if (dev->current_state != PCI_D0)
3307 csr &= ~PCI_PM_CTRL_STATE_MASK;
3309 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3310 pci_dev_d3_sleep(dev);
3312 csr &= ~PCI_PM_CTRL_STATE_MASK;
3314 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3315 pci_dev_d3_sleep(dev);
3321 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3322 * @dev: Bridge device
3324 * Use the bridge control register to assert reset on the secondary bus.
3325 * Devices on the secondary bus are left in power-on state.
3327 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3331 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3332 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3333 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3335 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3336 * this to 2ms to ensure that we meet the minium requirement.
3340 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3341 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3344 * Trhfa for conventional PCI is 2^25 clock cycles.
3345 * Assuming a minimum 33MHz clock this results in a 1s
3346 * delay before we can consider subordinate devices to
3347 * be re-initialized. PCIe has some ways to shorten this,
3348 * but we don't make use of them yet.
3352 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3354 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3356 struct pci_dev *pdev;
3358 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3361 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3368 pci_reset_bridge_secondary_bus(dev->bus->self);
3373 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3377 if (!hotplug || !try_module_get(hotplug->ops->owner))
3380 if (hotplug->ops->reset_slot)
3381 rc = hotplug->ops->reset_slot(hotplug, probe);
3383 module_put(hotplug->ops->owner);
3388 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3390 struct pci_dev *pdev;
3392 if (dev->subordinate || !dev->slot)
3395 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3396 if (pdev != dev && pdev->slot == dev->slot)
3399 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3402 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3408 rc = pci_dev_specific_reset(dev, probe);
3412 rc = pcie_flr(dev, probe);
3416 rc = pci_af_flr(dev, probe);
3420 rc = pci_pm_reset(dev, probe);
3424 rc = pci_dev_reset_slot_function(dev, probe);
3428 rc = pci_parent_bus_reset(dev, probe);
3433 static void pci_dev_lock(struct pci_dev *dev)
3435 pci_cfg_access_lock(dev);
3436 /* block PM suspend, driver probe, etc. */
3437 device_lock(&dev->dev);
3440 static void pci_dev_unlock(struct pci_dev *dev)
3442 device_unlock(&dev->dev);
3443 pci_cfg_access_unlock(dev);
3446 static void pci_dev_save_and_disable(struct pci_dev *dev)
3449 * Wake-up device prior to save. PM registers default to D0 after
3450 * reset and a simple register restore doesn't reliably return
3451 * to a non-D0 state anyway.
3453 pci_set_power_state(dev, PCI_D0);
3455 pci_save_state(dev);
3457 * Disable the device by clearing the Command register, except for
3458 * INTx-disable which is set. This not only disables MMIO and I/O port
3459 * BARs, but also prevents the device from being Bus Master, preventing
3460 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3461 * compliant devices, INTx-disable prevents legacy interrupts.
3463 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3466 static void pci_dev_restore(struct pci_dev *dev)
3468 pci_restore_state(dev);
3471 static int pci_dev_reset(struct pci_dev *dev, int probe)
3478 rc = __pci_dev_reset(dev, probe);
3481 pci_dev_unlock(dev);
3486 * __pci_reset_function - reset a PCI device function
3487 * @dev: PCI device to reset
3489 * Some devices allow an individual function to be reset without affecting
3490 * other functions in the same device. The PCI device must be responsive
3491 * to PCI config space in order to use this function.
3493 * The device function is presumed to be unused when this function is called.
3494 * Resetting the device will make the contents of PCI configuration space
3495 * random, so any caller of this must be prepared to reinitialise the
3496 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3499 * Returns 0 if the device function was successfully reset or negative if the
3500 * device doesn't support resetting a single function.
3502 int __pci_reset_function(struct pci_dev *dev)
3504 return pci_dev_reset(dev, 0);
3506 EXPORT_SYMBOL_GPL(__pci_reset_function);
3509 * __pci_reset_function_locked - reset a PCI device function while holding
3510 * the @dev mutex lock.
3511 * @dev: PCI device to reset
3513 * Some devices allow an individual function to be reset without affecting
3514 * other functions in the same device. The PCI device must be responsive
3515 * to PCI config space in order to use this function.
3517 * The device function is presumed to be unused and the caller is holding
3518 * the device mutex lock when this function is called.
3519 * Resetting the device will make the contents of PCI configuration space
3520 * random, so any caller of this must be prepared to reinitialise the
3521 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3524 * Returns 0 if the device function was successfully reset or negative if the
3525 * device doesn't support resetting a single function.
3527 int __pci_reset_function_locked(struct pci_dev *dev)
3529 return __pci_dev_reset(dev, 0);
3531 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3534 * pci_probe_reset_function - check whether the device can be safely reset
3535 * @dev: PCI device to reset
3537 * Some devices allow an individual function to be reset without affecting
3538 * other functions in the same device. The PCI device must be responsive
3539 * to PCI config space in order to use this function.
3541 * Returns 0 if the device function can be reset or negative if the
3542 * device doesn't support resetting a single function.
3544 int pci_probe_reset_function(struct pci_dev *dev)
3546 return pci_dev_reset(dev, 1);
3550 * pci_reset_function - quiesce and reset a PCI device function
3551 * @dev: PCI device to reset
3553 * Some devices allow an individual function to be reset without affecting
3554 * other functions in the same device. The PCI device must be responsive
3555 * to PCI config space in order to use this function.
3557 * This function does not just reset the PCI portion of a device, but
3558 * clears all the state associated with the device. This function differs
3559 * from __pci_reset_function in that it saves and restores device state
3562 * Returns 0 if the device function was successfully reset or negative if the
3563 * device doesn't support resetting a single function.
3565 int pci_reset_function(struct pci_dev *dev)
3569 rc = pci_dev_reset(dev, 1);
3573 pci_dev_save_and_disable(dev);
3575 rc = pci_dev_reset(dev, 0);
3577 pci_dev_restore(dev);
3581 EXPORT_SYMBOL_GPL(pci_reset_function);
3583 /* Lock devices from the top of the tree down */
3584 static void pci_bus_lock(struct pci_bus *bus)
3586 struct pci_dev *dev;
3588 list_for_each_entry(dev, &bus->devices, bus_list) {
3590 if (dev->subordinate)
3591 pci_bus_lock(dev->subordinate);
3595 /* Unlock devices from the bottom of the tree up */
3596 static void pci_bus_unlock(struct pci_bus *bus)
3598 struct pci_dev *dev;
3600 list_for_each_entry(dev, &bus->devices, bus_list) {
3601 if (dev->subordinate)
3602 pci_bus_unlock(dev->subordinate);
3603 pci_dev_unlock(dev);
3607 /* Lock devices from the top of the tree down */
3608 static void pci_slot_lock(struct pci_slot *slot)
3610 struct pci_dev *dev;
3612 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3613 if (!dev->slot || dev->slot != slot)
3616 if (dev->subordinate)
3617 pci_bus_lock(dev->subordinate);
3621 /* Unlock devices from the bottom of the tree up */
3622 static void pci_slot_unlock(struct pci_slot *slot)
3624 struct pci_dev *dev;
3626 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3627 if (!dev->slot || dev->slot != slot)
3629 if (dev->subordinate)
3630 pci_bus_unlock(dev->subordinate);
3631 pci_dev_unlock(dev);
3635 /* Save and disable devices from the top of the tree down */
3636 static void pci_bus_save_and_disable(struct pci_bus *bus)
3638 struct pci_dev *dev;
3640 list_for_each_entry(dev, &bus->devices, bus_list) {
3641 pci_dev_save_and_disable(dev);
3642 if (dev->subordinate)
3643 pci_bus_save_and_disable(dev->subordinate);
3648 * Restore devices from top of the tree down - parent bridges need to be
3649 * restored before we can get to subordinate devices.
3651 static void pci_bus_restore(struct pci_bus *bus)
3653 struct pci_dev *dev;
3655 list_for_each_entry(dev, &bus->devices, bus_list) {
3656 pci_dev_restore(dev);
3657 if (dev->subordinate)
3658 pci_bus_restore(dev->subordinate);
3662 /* Save and disable devices from the top of the tree down */
3663 static void pci_slot_save_and_disable(struct pci_slot *slot)
3665 struct pci_dev *dev;
3667 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3668 if (!dev->slot || dev->slot != slot)
3670 pci_dev_save_and_disable(dev);
3671 if (dev->subordinate)
3672 pci_bus_save_and_disable(dev->subordinate);
3677 * Restore devices from top of the tree down - parent bridges need to be
3678 * restored before we can get to subordinate devices.
3680 static void pci_slot_restore(struct pci_slot *slot)
3682 struct pci_dev *dev;
3684 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3685 if (!dev->slot || dev->slot != slot)
3687 pci_dev_restore(dev);
3688 if (dev->subordinate)
3689 pci_bus_restore(dev->subordinate);
3693 static int pci_slot_reset(struct pci_slot *slot, int probe)
3701 pci_slot_lock(slot);
3705 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3708 pci_slot_unlock(slot);
3714 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3715 * @slot: PCI slot to probe
3717 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3719 int pci_probe_reset_slot(struct pci_slot *slot)
3721 return pci_slot_reset(slot, 1);
3723 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3726 * pci_reset_slot - reset a PCI slot
3727 * @slot: PCI slot to reset
3729 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3730 * independent of other slots. For instance, some slots may support slot power
3731 * control. In the case of a 1:1 bus to slot architecture, this function may
3732 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3733 * Generally a slot reset should be attempted before a bus reset. All of the
3734 * function of the slot and any subordinate buses behind the slot are reset
3735 * through this function. PCI config space of all devices in the slot and
3736 * behind the slot is saved before and restored after reset.
3738 * Return 0 on success, non-zero on error.
3740 int pci_reset_slot(struct pci_slot *slot)
3744 rc = pci_slot_reset(slot, 1);
3748 pci_slot_save_and_disable(slot);
3750 rc = pci_slot_reset(slot, 0);
3752 pci_slot_restore(slot);
3756 EXPORT_SYMBOL_GPL(pci_reset_slot);
3758 static int pci_bus_reset(struct pci_bus *bus, int probe)
3770 pci_reset_bridge_secondary_bus(bus->self);
3772 pci_bus_unlock(bus);
3778 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3779 * @bus: PCI bus to probe
3781 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3783 int pci_probe_reset_bus(struct pci_bus *bus)
3785 return pci_bus_reset(bus, 1);
3787 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3790 * pci_reset_bus - reset a PCI bus
3791 * @bus: top level PCI bus to reset
3793 * Do a bus reset on the given bus and any subordinate buses, saving
3794 * and restoring state of all devices.
3796 * Return 0 on success, non-zero on error.
3798 int pci_reset_bus(struct pci_bus *bus)
3802 rc = pci_bus_reset(bus, 1);
3806 pci_bus_save_and_disable(bus);
3808 rc = pci_bus_reset(bus, 0);
3810 pci_bus_restore(bus);
3814 EXPORT_SYMBOL_GPL(pci_reset_bus);
3817 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3818 * @dev: PCI device to query
3820 * Returns mmrbc: maximum designed memory read count in bytes
3821 * or appropriate error value.
3823 int pcix_get_max_mmrbc(struct pci_dev *dev)
3828 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3832 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3835 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3837 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3840 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3841 * @dev: PCI device to query
3843 * Returns mmrbc: maximum memory read count in bytes
3844 * or appropriate error value.
3846 int pcix_get_mmrbc(struct pci_dev *dev)
3851 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3855 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3858 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3860 EXPORT_SYMBOL(pcix_get_mmrbc);
3863 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3864 * @dev: PCI device to query
3865 * @mmrbc: maximum memory read count in bytes
3866 * valid values are 512, 1024, 2048, 4096
3868 * If possible sets maximum memory read byte count, some bridges have erratas
3869 * that prevent this.
3871 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3877 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3880 v = ffs(mmrbc) - 10;
3882 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3886 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3889 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3892 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3895 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3897 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3900 cmd &= ~PCI_X_CMD_MAX_READ;
3902 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3907 EXPORT_SYMBOL(pcix_set_mmrbc);
3910 * pcie_get_readrq - get PCI Express read request size
3911 * @dev: PCI device to query
3913 * Returns maximum memory read request in bytes
3914 * or appropriate error value.
3916 int pcie_get_readrq(struct pci_dev *dev)
3920 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3922 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3924 EXPORT_SYMBOL(pcie_get_readrq);
3927 * pcie_set_readrq - set PCI Express maximum memory read request
3928 * @dev: PCI device to query
3929 * @rq: maximum memory read count in bytes
3930 * valid values are 128, 256, 512, 1024, 2048, 4096
3932 * If possible sets maximum memory read request in bytes
3934 int pcie_set_readrq(struct pci_dev *dev, int rq)
3938 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3942 * If using the "performance" PCIe config, we clamp the
3943 * read rq size to the max packet size to prevent the
3944 * host bridge generating requests larger than we can
3947 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3948 int mps = pcie_get_mps(dev);
3954 v = (ffs(rq) - 8) << 12;
3956 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3957 PCI_EXP_DEVCTL_READRQ, v);
3959 EXPORT_SYMBOL(pcie_set_readrq);
3962 * pcie_get_mps - get PCI Express maximum payload size
3963 * @dev: PCI device to query
3965 * Returns maximum payload size in bytes
3967 int pcie_get_mps(struct pci_dev *dev)
3971 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3973 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3977 * pcie_set_mps - set PCI Express maximum payload size
3978 * @dev: PCI device to query
3979 * @mps: maximum payload size in bytes
3980 * valid values are 128, 256, 512, 1024, 2048, 4096
3982 * If possible sets maximum payload size
3984 int pcie_set_mps(struct pci_dev *dev, int mps)
3988 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3992 if (v > dev->pcie_mpss)
3996 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3997 PCI_EXP_DEVCTL_PAYLOAD, v);
4001 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4002 * @dev: PCI device to query
4003 * @speed: storage for minimum speed
4004 * @width: storage for minimum width
4006 * This function will walk up the PCI device chain and determine the minimum
4007 * link width and speed of the device.
4009 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4010 enum pcie_link_width *width)
4014 *speed = PCI_SPEED_UNKNOWN;
4015 *width = PCIE_LNK_WIDTH_UNKNOWN;
4019 enum pci_bus_speed next_speed;
4020 enum pcie_link_width next_width;
4022 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4026 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4027 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4028 PCI_EXP_LNKSTA_NLW_SHIFT;
4030 if (next_speed < *speed)
4031 *speed = next_speed;
4033 if (next_width < *width)
4034 *width = next_width;
4036 dev = dev->bus->self;
4041 EXPORT_SYMBOL(pcie_get_minimum_link);
4044 * pci_select_bars - Make BAR mask from the type of resource
4045 * @dev: the PCI device for which BAR mask is made
4046 * @flags: resource type mask to be selected
4048 * This helper routine makes bar mask from the type of resource.
4050 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4053 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4054 if (pci_resource_flags(dev, i) & flags)
4060 * pci_resource_bar - get position of the BAR associated with a resource
4061 * @dev: the PCI device
4062 * @resno: the resource number
4063 * @type: the BAR type to be filled in
4065 * Returns BAR position in config space, or 0 if the BAR is invalid.
4067 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4071 if (resno < PCI_ROM_RESOURCE) {
4072 *type = pci_bar_unknown;
4073 return PCI_BASE_ADDRESS_0 + 4 * resno;
4074 } else if (resno == PCI_ROM_RESOURCE) {
4075 *type = pci_bar_mem32;
4076 return dev->rom_base_reg;
4077 } else if (resno < PCI_BRIDGE_RESOURCES) {
4078 /* device specific resource */
4079 reg = pci_iov_resource_bar(dev, resno, type);
4084 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4088 /* Some architectures require additional programming to enable VGA */
4089 static arch_set_vga_state_t arch_set_vga_state;
4091 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4093 arch_set_vga_state = func; /* NULL disables */
4096 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4097 unsigned int command_bits, u32 flags)
4099 if (arch_set_vga_state)
4100 return arch_set_vga_state(dev, decode, command_bits,
4106 * pci_set_vga_state - set VGA decode state on device and parents if requested
4107 * @dev: the PCI device
4108 * @decode: true = enable decoding, false = disable decoding
4109 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4110 * @flags: traverse ancestors and change bridges
4111 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4113 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4114 unsigned int command_bits, u32 flags)
4116 struct pci_bus *bus;
4117 struct pci_dev *bridge;
4121 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4123 /* ARCH specific VGA enables */
4124 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4128 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4129 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4131 cmd |= command_bits;
4133 cmd &= ~command_bits;
4134 pci_write_config_word(dev, PCI_COMMAND, cmd);
4137 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4144 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4147 cmd |= PCI_BRIDGE_CTL_VGA;
4149 cmd &= ~PCI_BRIDGE_CTL_VGA;
4150 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4158 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4159 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4160 static DEFINE_SPINLOCK(resource_alignment_lock);
4163 * pci_specified_resource_alignment - get resource alignment specified by user.
4164 * @dev: the PCI device to get
4166 * RETURNS: Resource alignment if it is specified.
4167 * Zero if it is not specified.
4169 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4171 int seg, bus, slot, func, align_order, count;
4172 resource_size_t align = 0;
4175 spin_lock(&resource_alignment_lock);
4176 p = resource_alignment_param;
4179 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4185 if (sscanf(p, "%x:%x:%x.%x%n",
4186 &seg, &bus, &slot, &func, &count) != 4) {
4188 if (sscanf(p, "%x:%x.%x%n",
4189 &bus, &slot, &func, &count) != 3) {
4190 /* Invalid format */
4191 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4197 if (seg == pci_domain_nr(dev->bus) &&
4198 bus == dev->bus->number &&
4199 slot == PCI_SLOT(dev->devfn) &&
4200 func == PCI_FUNC(dev->devfn)) {
4201 if (align_order == -1) {
4204 align = 1 << align_order;
4209 if (*p != ';' && *p != ',') {
4210 /* End of param or invalid format */
4215 spin_unlock(&resource_alignment_lock);
4220 * This function disables memory decoding and releases memory resources
4221 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4222 * It also rounds up size to specified alignment.
4223 * Later on, the kernel will assign page-aligned memory resource back
4226 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4230 resource_size_t align, size;
4233 /* check if specified PCI is target device to reassign */
4234 align = pci_specified_resource_alignment(dev);
4238 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4239 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4241 "Can't reassign resources to host bridge.\n");
4246 "Disabling memory decoding and releasing memory resources.\n");
4247 pci_read_config_word(dev, PCI_COMMAND, &command);
4248 command &= ~PCI_COMMAND_MEMORY;
4249 pci_write_config_word(dev, PCI_COMMAND, command);
4251 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4252 r = &dev->resource[i];
4253 if (!(r->flags & IORESOURCE_MEM))
4255 size = resource_size(r);
4259 "Rounding up size of resource #%d to %#llx.\n",
4260 i, (unsigned long long)size);
4265 /* Need to disable bridge's resource window,
4266 * to enable the kernel to reassign new resource
4269 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4270 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4271 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4272 r = &dev->resource[i];
4273 if (!(r->flags & IORESOURCE_MEM))
4275 r->end = resource_size(r) - 1;
4278 pci_disable_bridge_window(dev);
4282 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4284 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4285 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4286 spin_lock(&resource_alignment_lock);
4287 strncpy(resource_alignment_param, buf, count);
4288 resource_alignment_param[count] = '\0';
4289 spin_unlock(&resource_alignment_lock);
4293 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4296 spin_lock(&resource_alignment_lock);
4297 count = snprintf(buf, size, "%s", resource_alignment_param);
4298 spin_unlock(&resource_alignment_lock);
4302 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4304 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4307 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4308 const char *buf, size_t count)
4310 return pci_set_resource_alignment_param(buf, count);
4313 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4314 pci_resource_alignment_store);
4316 static int __init pci_resource_alignment_sysfs_init(void)
4318 return bus_create_file(&pci_bus_type,
4319 &bus_attr_resource_alignment);
4322 late_initcall(pci_resource_alignment_sysfs_init);
4324 static void pci_no_domains(void)
4326 #ifdef CONFIG_PCI_DOMAINS
4327 pci_domains_supported = 0;
4332 * pci_ext_cfg_avail - can we access extended PCI config space?
4334 * Returns 1 if we can access PCI extended config space (offsets
4335 * greater than 0xff). This is the default implementation. Architecture
4336 * implementations can override this.
4338 int __weak pci_ext_cfg_avail(void)
4343 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4346 EXPORT_SYMBOL(pci_fixup_cardbus);
4348 static int __init pci_setup(char *str)
4351 char *k = strchr(str, ',');
4354 if (*str && (str = pcibios_setup(str)) && *str) {
4355 if (!strcmp(str, "nomsi")) {
4357 } else if (!strcmp(str, "noaer")) {
4359 } else if (!strncmp(str, "realloc=", 8)) {
4360 pci_realloc_get_opt(str + 8);
4361 } else if (!strncmp(str, "realloc", 7)) {
4362 pci_realloc_get_opt("on");
4363 } else if (!strcmp(str, "nodomains")) {
4365 } else if (!strncmp(str, "noari", 5)) {
4366 pcie_ari_disabled = true;
4367 } else if (!strncmp(str, "cbiosize=", 9)) {
4368 pci_cardbus_io_size = memparse(str + 9, &str);
4369 } else if (!strncmp(str, "cbmemsize=", 10)) {
4370 pci_cardbus_mem_size = memparse(str + 10, &str);
4371 } else if (!strncmp(str, "resource_alignment=", 19)) {
4372 pci_set_resource_alignment_param(str + 19,
4374 } else if (!strncmp(str, "ecrc=", 5)) {
4375 pcie_ecrc_get_policy(str + 5);
4376 } else if (!strncmp(str, "hpiosize=", 9)) {
4377 pci_hotplug_io_size = memparse(str + 9, &str);
4378 } else if (!strncmp(str, "hpmemsize=", 10)) {
4379 pci_hotplug_mem_size = memparse(str + 10, &str);
4380 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4381 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4382 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4383 pcie_bus_config = PCIE_BUS_SAFE;
4384 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4385 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4386 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4387 pcie_bus_config = PCIE_BUS_PEER2PEER;
4388 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4389 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4391 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4399 early_param("pci", pci_setup);
4401 EXPORT_SYMBOL(pci_reenable_device);
4402 EXPORT_SYMBOL(pci_enable_device_io);
4403 EXPORT_SYMBOL(pci_enable_device_mem);
4404 EXPORT_SYMBOL(pci_enable_device);
4405 EXPORT_SYMBOL(pcim_enable_device);
4406 EXPORT_SYMBOL(pcim_pin_device);
4407 EXPORT_SYMBOL(pci_disable_device);
4408 EXPORT_SYMBOL(pci_find_capability);
4409 EXPORT_SYMBOL(pci_bus_find_capability);
4410 EXPORT_SYMBOL(pci_release_regions);
4411 EXPORT_SYMBOL(pci_request_regions);
4412 EXPORT_SYMBOL(pci_request_regions_exclusive);
4413 EXPORT_SYMBOL(pci_release_region);
4414 EXPORT_SYMBOL(pci_request_region);
4415 EXPORT_SYMBOL(pci_request_region_exclusive);
4416 EXPORT_SYMBOL(pci_release_selected_regions);
4417 EXPORT_SYMBOL(pci_request_selected_regions);
4418 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4419 EXPORT_SYMBOL(pci_set_master);
4420 EXPORT_SYMBOL(pci_clear_master);
4421 EXPORT_SYMBOL(pci_set_mwi);
4422 EXPORT_SYMBOL(pci_try_set_mwi);
4423 EXPORT_SYMBOL(pci_clear_mwi);
4424 EXPORT_SYMBOL_GPL(pci_intx);
4425 EXPORT_SYMBOL(pci_assign_resource);
4426 EXPORT_SYMBOL(pci_find_parent_resource);
4427 EXPORT_SYMBOL(pci_select_bars);
4429 EXPORT_SYMBOL(pci_set_power_state);
4430 EXPORT_SYMBOL(pci_save_state);
4431 EXPORT_SYMBOL(pci_restore_state);
4432 EXPORT_SYMBOL(pci_pme_capable);
4433 EXPORT_SYMBOL(pci_pme_active);
4434 EXPORT_SYMBOL(pci_wake_from_d3);
4435 EXPORT_SYMBOL(pci_target_state);
4436 EXPORT_SYMBOL(pci_prepare_to_sleep);
4437 EXPORT_SYMBOL(pci_back_from_sleep);
4438 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);