2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names);
35 int isa_dma_bridge_buggy;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy);
39 EXPORT_SYMBOL(pci_pci_problems);
41 unsigned int pci_pm_d3_delay;
43 static void pci_pme_list_scan(struct work_struct *work);
45 static LIST_HEAD(pci_pme_list);
46 static DEFINE_MUTEX(pci_pme_list_mutex);
47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
49 struct pci_pme_device {
50 struct list_head list;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev *dev)
58 unsigned int delay = dev->d3_delay;
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported = 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 u8 pci_cache_line_size;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency = 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
111 struct list_head *tmp;
112 unsigned char max, n;
114 max = bus->busn_res.end;
115 list_for_each(tmp, &bus->children) {
116 n = pci_bus_max_busnr(pci_bus_b(tmp));
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
158 pos += PCI_CAP_LIST_NEXT;
163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
166 int ttl = PCI_FIND_CAP_TTL;
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability);
178 static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev *dev, int cap)
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
231 * pci_bus_find_capability - query for devices' capabilities
232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
236 * Like pci_find_capability() but works for pci devices that do not have a
237 * pci_dev structure set up yet.
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
243 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
258 * pci_find_next_ext_capability - Find an extended capability
259 * @dev: PCI device to query
260 * @start: address at which to start looking (0 to start at beginning of list)
261 * @cap: capability code
263 * Returns the address of the next matching extended capability structure
264 * within the device's PCI configuration space or 0 if the device does
265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
268 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
272 int pos = PCI_CFG_SPACE_SIZE;
274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
297 pos = PCI_EXT_CAP_NEXT(header);
298 if (pos < PCI_CFG_SPACE_SIZE)
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
323 int pci_find_ext_capability(struct pci_dev *dev, int cap)
325 return pci_find_next_ext_capability(dev, 0, cap);
327 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
329 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
331 int rc, ttl = PCI_FIND_CAP_TTL;
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
337 mask = HT_5BIT_CAP_MASK;
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
346 if ((cap & mask) == ht_cap)
349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
351 PCI_CAP_ID_HT, &ttl);
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
369 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
386 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
396 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
403 * For given resource region of given device, return the resource
404 * region of parent bus the given region is contained in or where
405 * it should be allocated from.
408 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
410 const struct pci_bus *bus = dev->bus;
412 struct resource *best = NULL, *r;
414 pci_bus_for_each_resource(bus, r, i) {
417 if (res->start && !(res->start >= r->start && res->end <= r->end))
418 continue; /* Not contained */
419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
420 continue; /* Wrong type */
421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
422 return r; /* Exact match */
423 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
424 if (r->flags & IORESOURCE_PREFETCH)
426 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
434 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
435 * @dev: the PCI device to operate on
436 * @pos: config space offset of status word
437 * @mask: mask of bit(s) to care about in status word
439 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
441 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
445 /* Wait for Transaction Pending bit clean */
446 for (i = 0; i < 4; i++) {
449 msleep((1 << (i - 1)) * 100);
451 pci_read_config_word(dev, pos, &status);
452 if (!(status & mask))
460 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
461 * @dev: PCI device to have its BARs restored
463 * Restore the BAR values for a given device, so as to make it
464 * accessible by its driver.
467 pci_restore_bars(struct pci_dev *dev)
471 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
472 pci_update_resource(dev, i);
475 static struct pci_platform_pm_ops *pci_platform_pm;
477 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
479 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
482 pci_platform_pm = ops;
486 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
488 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
491 static inline int platform_pci_set_power_state(struct pci_dev *dev,
494 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
497 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
499 return pci_platform_pm ?
500 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
503 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
505 return pci_platform_pm ?
506 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
509 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
511 return pci_platform_pm ?
512 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
516 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
518 * @dev: PCI device to handle.
519 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
522 * -EINVAL if the requested state is invalid.
523 * -EIO if device does not support PCI PM or its PM capabilities register has a
524 * wrong version, or device doesn't support the requested state.
525 * 0 if device already is in the requested state.
526 * 0 if device's power state has been successfully changed.
528 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
531 bool need_restore = false;
533 /* Check if we're already there */
534 if (dev->current_state == state)
540 if (state < PCI_D0 || state > PCI_D3hot)
543 /* Validate current state:
544 * Can enter D0 from any state, but if we can only go deeper
545 * to sleep if we're already in a low power state
547 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
548 && dev->current_state > state) {
549 dev_err(&dev->dev, "invalid power transition "
550 "(from state %d to %d)\n", dev->current_state, state);
554 /* check if this device supports the desired state */
555 if ((state == PCI_D1 && !dev->d1_support)
556 || (state == PCI_D2 && !dev->d2_support))
559 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
561 /* If we're (effectively) in D3, force entire word to 0.
562 * This doesn't affect PME_Status, disables PME_En, and
563 * sets PowerState to 0.
565 switch (dev->current_state) {
569 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
574 case PCI_UNKNOWN: /* Boot-up */
575 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
576 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
578 /* Fall-through: force to D0 */
584 /* enter specified state */
585 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
587 /* Mandatory power management transition delays */
588 /* see PCI PM 1.1 5.6.1 table 18 */
589 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
590 pci_dev_d3_sleep(dev);
591 else if (state == PCI_D2 || dev->current_state == PCI_D2)
592 udelay(PCI_PM_D2_DELAY);
594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
595 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
596 if (dev->current_state != state && printk_ratelimit())
597 dev_info(&dev->dev, "Refused to change power state, "
598 "currently in D%d\n", dev->current_state);
601 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
602 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
603 * from D3hot to D0 _may_ perform an internal reset, thereby
604 * going to "D0 Uninitialized" rather than "D0 Initialized".
605 * For example, at least some versions of the 3c905B and the
606 * 3c556B exhibit this behaviour.
608 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
609 * devices in a D3hot state at boot. Consequently, we need to
610 * restore at least the BARs so that the device will be
611 * accessible to its driver.
614 pci_restore_bars(dev);
617 pcie_aspm_pm_state_change(dev->bus->self);
623 * pci_update_current_state - Read PCI power state of given device from its
624 * PCI PM registers and cache it
625 * @dev: PCI device to handle.
626 * @state: State to cache in case the device doesn't have the PM capability
628 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
634 * Configuration space is not accessible for device in
635 * D3cold, so just keep or set D3cold for safety
637 if (dev->current_state == PCI_D3cold)
639 if (state == PCI_D3cold) {
640 dev->current_state = PCI_D3cold;
643 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
644 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
646 dev->current_state = state;
651 * pci_power_up - Put the given device into D0 forcibly
652 * @dev: PCI device to power up
654 void pci_power_up(struct pci_dev *dev)
656 if (platform_pci_power_manageable(dev))
657 platform_pci_set_power_state(dev, PCI_D0);
659 pci_raw_set_power_state(dev, PCI_D0);
660 pci_update_current_state(dev, PCI_D0);
664 * pci_platform_power_transition - Use platform to change device power state
665 * @dev: PCI device to handle.
666 * @state: State to put the device into.
668 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
672 if (platform_pci_power_manageable(dev)) {
673 error = platform_pci_set_power_state(dev, state);
675 pci_update_current_state(dev, state);
679 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
680 dev->current_state = PCI_D0;
686 * pci_wakeup - Wake up a PCI device
687 * @pci_dev: Device to handle.
688 * @ign: ignored parameter
690 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
692 pci_wakeup_event(pci_dev);
693 pm_request_resume(&pci_dev->dev);
698 * pci_wakeup_bus - Walk given bus and wake up devices on it
699 * @bus: Top bus of the subtree to walk.
701 static void pci_wakeup_bus(struct pci_bus *bus)
704 pci_walk_bus(bus, pci_wakeup, NULL);
708 * __pci_start_power_transition - Start power transition of a PCI device
709 * @dev: PCI device to handle.
710 * @state: State to put the device into.
712 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
714 if (state == PCI_D0) {
715 pci_platform_power_transition(dev, PCI_D0);
717 * Mandatory power management transition delays, see
718 * PCI Express Base Specification Revision 2.0 Section
719 * 6.6.1: Conventional Reset. Do not delay for
720 * devices powered on/off by corresponding bridge,
721 * because have already delayed for the bridge.
723 if (dev->runtime_d3cold) {
724 msleep(dev->d3cold_delay);
726 * When powering on a bridge from D3cold, the
727 * whole hierarchy may be powered on into
728 * D0uninitialized state, resume them to give
729 * them a chance to suspend again
731 pci_wakeup_bus(dev->subordinate);
737 * __pci_dev_set_current_state - Set current state of a PCI device
738 * @dev: Device to handle
739 * @data: pointer to state to be set
741 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
743 pci_power_t state = *(pci_power_t *)data;
745 dev->current_state = state;
750 * __pci_bus_set_current_state - Walk given bus and set current state of devices
751 * @bus: Top bus of the subtree to walk.
752 * @state: state to be set
754 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
757 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
761 * __pci_complete_power_transition - Complete power transition of a PCI device
762 * @dev: PCI device to handle.
763 * @state: State to put the device into.
765 * This function should not be called directly by device drivers.
767 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
773 ret = pci_platform_power_transition(dev, state);
774 /* Power off the bridge may power off the whole hierarchy */
775 if (!ret && state == PCI_D3cold)
776 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
779 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
782 * pci_set_power_state - Set the power state of a PCI device
783 * @dev: PCI device to handle.
784 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
786 * Transition a device to a new power state, using the platform firmware and/or
787 * the device's PCI PM registers.
790 * -EINVAL if the requested state is invalid.
791 * -EIO if device does not support PCI PM or its PM capabilities register has a
792 * wrong version, or device doesn't support the requested state.
793 * 0 if device already is in the requested state.
794 * 0 if device's power state has been successfully changed.
796 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
800 /* bound the state we're entering */
801 if (state > PCI_D3cold)
803 else if (state < PCI_D0)
805 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
807 * If the device or the parent bridge do not support PCI PM,
808 * ignore the request if we're doing anything other than putting
809 * it into D0 (which would only happen on boot).
813 /* Check if we're already there */
814 if (dev->current_state == state)
817 __pci_start_power_transition(dev, state);
819 /* This device is quirked not to be put into D3, so
820 don't put it in D3 */
821 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
825 * To put device in D3cold, we put device into D3hot in native
826 * way, then put device into D3cold with platform ops
828 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
831 if (!__pci_complete_power_transition(dev, state))
834 * When aspm_policy is "powersave" this call ensures
835 * that ASPM is configured.
837 if (!error && dev->bus->self)
838 pcie_aspm_powersave_config_link(dev->bus->self);
844 * pci_choose_state - Choose the power state of a PCI device
845 * @dev: PCI device to be suspended
846 * @state: target sleep state for the whole system. This is the value
847 * that is passed to suspend() function.
849 * Returns PCI power state suitable for given device and given system
853 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
860 ret = platform_pci_choose_state(dev);
861 if (ret != PCI_POWER_ERROR)
864 switch (state.event) {
867 case PM_EVENT_FREEZE:
868 case PM_EVENT_PRETHAW:
869 /* REVISIT both freeze and pre-thaw "should" use D0 */
870 case PM_EVENT_SUSPEND:
871 case PM_EVENT_HIBERNATE:
874 dev_info(&dev->dev, "unrecognized suspend event %d\n",
881 EXPORT_SYMBOL(pci_choose_state);
883 #define PCI_EXP_SAVE_REGS 7
886 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
887 u16 cap, bool extended)
889 struct pci_cap_saved_state *tmp;
891 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
892 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
898 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
900 return _pci_find_saved_cap(dev, cap, false);
903 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
905 return _pci_find_saved_cap(dev, cap, true);
908 static int pci_save_pcie_state(struct pci_dev *dev)
911 struct pci_cap_saved_state *save_state;
914 if (!pci_is_pcie(dev))
917 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
919 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
923 cap = (u16 *)&save_state->cap.data[0];
924 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
925 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
926 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
927 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
928 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
929 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
930 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
935 static void pci_restore_pcie_state(struct pci_dev *dev)
938 struct pci_cap_saved_state *save_state;
941 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
945 cap = (u16 *)&save_state->cap.data[0];
946 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
947 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
948 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
949 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
950 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
951 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
952 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
956 static int pci_save_pcix_state(struct pci_dev *dev)
959 struct pci_cap_saved_state *save_state;
961 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
965 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
967 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
971 pci_read_config_word(dev, pos + PCI_X_CMD,
972 (u16 *)save_state->cap.data);
977 static void pci_restore_pcix_state(struct pci_dev *dev)
980 struct pci_cap_saved_state *save_state;
983 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
984 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
985 if (!save_state || pos <= 0)
987 cap = (u16 *)&save_state->cap.data[0];
989 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
994 * pci_save_state - save the PCI configuration space of a device before suspending
995 * @dev: - PCI device that we're dealing with
998 pci_save_state(struct pci_dev *dev)
1001 /* XXX: 100% dword access ok here? */
1002 for (i = 0; i < 16; i++)
1003 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1004 dev->state_saved = true;
1005 if ((i = pci_save_pcie_state(dev)) != 0)
1007 if ((i = pci_save_pcix_state(dev)) != 0)
1009 if ((i = pci_save_vc_state(dev)) != 0)
1014 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1015 u32 saved_val, int retry)
1019 pci_read_config_dword(pdev, offset, &val);
1020 if (val == saved_val)
1024 dev_dbg(&pdev->dev, "restoring config space at offset "
1025 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
1026 pci_write_config_dword(pdev, offset, saved_val);
1030 pci_read_config_dword(pdev, offset, &val);
1031 if (val == saved_val)
1038 static void pci_restore_config_space_range(struct pci_dev *pdev,
1039 int start, int end, int retry)
1043 for (index = end; index >= start; index--)
1044 pci_restore_config_dword(pdev, 4 * index,
1045 pdev->saved_config_space[index],
1049 static void pci_restore_config_space(struct pci_dev *pdev)
1051 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1052 pci_restore_config_space_range(pdev, 10, 15, 0);
1053 /* Restore BARs before the command register. */
1054 pci_restore_config_space_range(pdev, 4, 9, 10);
1055 pci_restore_config_space_range(pdev, 0, 3, 0);
1057 pci_restore_config_space_range(pdev, 0, 15, 0);
1062 * pci_restore_state - Restore the saved state of a PCI device
1063 * @dev: - PCI device that we're dealing with
1065 void pci_restore_state(struct pci_dev *dev)
1067 if (!dev->state_saved)
1070 /* PCI Express register must be restored first */
1071 pci_restore_pcie_state(dev);
1072 pci_restore_ats_state(dev);
1073 pci_restore_vc_state(dev);
1075 pci_restore_config_space(dev);
1077 pci_restore_pcix_state(dev);
1078 pci_restore_msi_state(dev);
1079 pci_restore_iov_state(dev);
1081 dev->state_saved = false;
1084 struct pci_saved_state {
1085 u32 config_space[16];
1086 struct pci_cap_saved_data cap[0];
1090 * pci_store_saved_state - Allocate and return an opaque struct containing
1091 * the device saved state.
1092 * @dev: PCI device that we're dealing with
1094 * Return NULL if no state or error.
1096 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1098 struct pci_saved_state *state;
1099 struct pci_cap_saved_state *tmp;
1100 struct pci_cap_saved_data *cap;
1103 if (!dev->state_saved)
1106 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1108 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1109 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1111 state = kzalloc(size, GFP_KERNEL);
1115 memcpy(state->config_space, dev->saved_config_space,
1116 sizeof(state->config_space));
1119 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1120 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1121 memcpy(cap, &tmp->cap, len);
1122 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1124 /* Empty cap_save terminates list */
1128 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1131 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1132 * @dev: PCI device that we're dealing with
1133 * @state: Saved state returned from pci_store_saved_state()
1135 static int pci_load_saved_state(struct pci_dev *dev,
1136 struct pci_saved_state *state)
1138 struct pci_cap_saved_data *cap;
1140 dev->state_saved = false;
1145 memcpy(dev->saved_config_space, state->config_space,
1146 sizeof(state->config_space));
1150 struct pci_cap_saved_state *tmp;
1152 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1153 if (!tmp || tmp->cap.size != cap->size)
1156 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1157 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1158 sizeof(struct pci_cap_saved_data) + cap->size);
1161 dev->state_saved = true;
1166 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1167 * and free the memory allocated for it.
1168 * @dev: PCI device that we're dealing with
1169 * @state: Pointer to saved state returned from pci_store_saved_state()
1171 int pci_load_and_free_saved_state(struct pci_dev *dev,
1172 struct pci_saved_state **state)
1174 int ret = pci_load_saved_state(dev, *state);
1179 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1181 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1187 err = pci_set_power_state(dev, PCI_D0);
1188 if (err < 0 && err != -EIO)
1190 err = pcibios_enable_device(dev, bars);
1193 pci_fixup_device(pci_fixup_enable, dev);
1195 if (dev->msi_enabled || dev->msix_enabled)
1198 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1200 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1201 if (cmd & PCI_COMMAND_INTX_DISABLE)
1202 pci_write_config_word(dev, PCI_COMMAND,
1203 cmd & ~PCI_COMMAND_INTX_DISABLE);
1210 * pci_reenable_device - Resume abandoned device
1211 * @dev: PCI device to be resumed
1213 * Note this function is a backend of pci_default_resume and is not supposed
1214 * to be called by normal code, write proper resume handler and use it instead.
1216 int pci_reenable_device(struct pci_dev *dev)
1218 if (pci_is_enabled(dev))
1219 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1223 static void pci_enable_bridge(struct pci_dev *dev)
1225 struct pci_dev *bridge;
1228 bridge = pci_upstream_bridge(dev);
1230 pci_enable_bridge(bridge);
1232 if (pci_is_enabled(dev)) {
1233 if (!dev->is_busmaster)
1234 pci_set_master(dev);
1238 retval = pci_enable_device(dev);
1240 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1242 pci_set_master(dev);
1245 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1247 struct pci_dev *bridge;
1252 * Power state could be unknown at this point, either due to a fresh
1253 * boot or a device removal call. So get the current power state
1254 * so that things like MSI message writing will behave as expected
1255 * (e.g. if the device really is in D0 at enable time).
1259 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1260 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1263 if (atomic_inc_return(&dev->enable_cnt) > 1)
1264 return 0; /* already enabled */
1266 bridge = pci_upstream_bridge(dev);
1268 pci_enable_bridge(bridge);
1270 /* only skip sriov related */
1271 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1272 if (dev->resource[i].flags & flags)
1274 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1275 if (dev->resource[i].flags & flags)
1278 err = do_pci_enable_device(dev, bars);
1280 atomic_dec(&dev->enable_cnt);
1285 * pci_enable_device_io - Initialize a device for use with IO space
1286 * @dev: PCI device to be initialized
1288 * Initialize device before it's used by a driver. Ask low-level code
1289 * to enable I/O resources. Wake up the device if it was suspended.
1290 * Beware, this function can fail.
1292 int pci_enable_device_io(struct pci_dev *dev)
1294 return pci_enable_device_flags(dev, IORESOURCE_IO);
1298 * pci_enable_device_mem - Initialize a device for use with Memory space
1299 * @dev: PCI device to be initialized
1301 * Initialize device before it's used by a driver. Ask low-level code
1302 * to enable Memory resources. Wake up the device if it was suspended.
1303 * Beware, this function can fail.
1305 int pci_enable_device_mem(struct pci_dev *dev)
1307 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1311 * pci_enable_device - Initialize device before it's used by a driver.
1312 * @dev: PCI device to be initialized
1314 * Initialize device before it's used by a driver. Ask low-level code
1315 * to enable I/O and memory. Wake up the device if it was suspended.
1316 * Beware, this function can fail.
1318 * Note we don't actually enable the device many times if we call
1319 * this function repeatedly (we just increment the count).
1321 int pci_enable_device(struct pci_dev *dev)
1323 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1327 * Managed PCI resources. This manages device on/off, intx/msi/msix
1328 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1329 * there's no need to track it separately. pci_devres is initialized
1330 * when a device is enabled using managed PCI device enable interface.
1333 unsigned int enabled:1;
1334 unsigned int pinned:1;
1335 unsigned int orig_intx:1;
1336 unsigned int restore_intx:1;
1340 static void pcim_release(struct device *gendev, void *res)
1342 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1343 struct pci_devres *this = res;
1346 if (dev->msi_enabled)
1347 pci_disable_msi(dev);
1348 if (dev->msix_enabled)
1349 pci_disable_msix(dev);
1351 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1352 if (this->region_mask & (1 << i))
1353 pci_release_region(dev, i);
1355 if (this->restore_intx)
1356 pci_intx(dev, this->orig_intx);
1358 if (this->enabled && !this->pinned)
1359 pci_disable_device(dev);
1362 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1364 struct pci_devres *dr, *new_dr;
1366 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1370 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1373 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1376 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1378 if (pci_is_managed(pdev))
1379 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1384 * pcim_enable_device - Managed pci_enable_device()
1385 * @pdev: PCI device to be initialized
1387 * Managed pci_enable_device().
1389 int pcim_enable_device(struct pci_dev *pdev)
1391 struct pci_devres *dr;
1394 dr = get_pci_dr(pdev);
1400 rc = pci_enable_device(pdev);
1402 pdev->is_managed = 1;
1409 * pcim_pin_device - Pin managed PCI device
1410 * @pdev: PCI device to pin
1412 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1413 * driver detach. @pdev must have been enabled with
1414 * pcim_enable_device().
1416 void pcim_pin_device(struct pci_dev *pdev)
1418 struct pci_devres *dr;
1420 dr = find_pci_dr(pdev);
1421 WARN_ON(!dr || !dr->enabled);
1427 * pcibios_add_device - provide arch specific hooks when adding device dev
1428 * @dev: the PCI device being added
1430 * Permits the platform to provide architecture specific functionality when
1431 * devices are added. This is the default implementation. Architecture
1432 * implementations can override this.
1434 int __weak pcibios_add_device (struct pci_dev *dev)
1440 * pcibios_release_device - provide arch specific hooks when releasing device dev
1441 * @dev: the PCI device being released
1443 * Permits the platform to provide architecture specific functionality when
1444 * devices are released. This is the default implementation. Architecture
1445 * implementations can override this.
1447 void __weak pcibios_release_device(struct pci_dev *dev) {}
1450 * pcibios_disable_device - disable arch specific PCI resources for device dev
1451 * @dev: the PCI device to disable
1453 * Disables architecture specific PCI resources for the device. This
1454 * is the default implementation. Architecture implementations can
1457 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1459 static void do_pci_disable_device(struct pci_dev *dev)
1463 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1464 if (pci_command & PCI_COMMAND_MASTER) {
1465 pci_command &= ~PCI_COMMAND_MASTER;
1466 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1469 pcibios_disable_device(dev);
1473 * pci_disable_enabled_device - Disable device without updating enable_cnt
1474 * @dev: PCI device to disable
1476 * NOTE: This function is a backend of PCI power management routines and is
1477 * not supposed to be called drivers.
1479 void pci_disable_enabled_device(struct pci_dev *dev)
1481 if (pci_is_enabled(dev))
1482 do_pci_disable_device(dev);
1486 * pci_disable_device - Disable PCI device after use
1487 * @dev: PCI device to be disabled
1489 * Signal to the system that the PCI device is not in use by the system
1490 * anymore. This only involves disabling PCI bus-mastering, if active.
1492 * Note we don't actually disable the device until all callers of
1493 * pci_enable_device() have called pci_disable_device().
1496 pci_disable_device(struct pci_dev *dev)
1498 struct pci_devres *dr;
1500 dr = find_pci_dr(dev);
1504 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1505 "disabling already-disabled device");
1507 if (atomic_dec_return(&dev->enable_cnt) != 0)
1510 do_pci_disable_device(dev);
1512 dev->is_busmaster = 0;
1516 * pcibios_set_pcie_reset_state - set reset state for device dev
1517 * @dev: the PCIe device reset
1518 * @state: Reset state to enter into
1521 * Sets the PCIe reset state for the device. This is the default
1522 * implementation. Architecture implementations can override this.
1524 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1525 enum pcie_reset_state state)
1531 * pci_set_pcie_reset_state - set reset state for device dev
1532 * @dev: the PCIe device reset
1533 * @state: Reset state to enter into
1536 * Sets the PCI reset state for the device.
1538 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1540 return pcibios_set_pcie_reset_state(dev, state);
1544 * pci_check_pme_status - Check if given device has generated PME.
1545 * @dev: Device to check.
1547 * Check the PME status of the device and if set, clear it and clear PME enable
1548 * (if set). Return 'true' if PME status and PME enable were both set or
1549 * 'false' otherwise.
1551 bool pci_check_pme_status(struct pci_dev *dev)
1560 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1561 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1562 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1565 /* Clear PME status. */
1566 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1567 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1568 /* Disable PME to avoid interrupt flood. */
1569 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1573 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1579 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1580 * @dev: Device to handle.
1581 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1583 * Check if @dev has generated PME and queue a resume request for it in that
1586 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1588 if (pme_poll_reset && dev->pme_poll)
1589 dev->pme_poll = false;
1591 if (pci_check_pme_status(dev)) {
1592 pci_wakeup_event(dev);
1593 pm_request_resume(&dev->dev);
1599 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1600 * @bus: Top bus of the subtree to walk.
1602 void pci_pme_wakeup_bus(struct pci_bus *bus)
1605 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1610 * pci_pme_capable - check the capability of PCI device to generate PME#
1611 * @dev: PCI device to handle.
1612 * @state: PCI state from which device will issue PME#.
1614 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1619 return !!(dev->pme_support & (1 << state));
1622 static void pci_pme_list_scan(struct work_struct *work)
1624 struct pci_pme_device *pme_dev, *n;
1626 mutex_lock(&pci_pme_list_mutex);
1627 if (!list_empty(&pci_pme_list)) {
1628 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1629 if (pme_dev->dev->pme_poll) {
1630 struct pci_dev *bridge;
1632 bridge = pme_dev->dev->bus->self;
1634 * If bridge is in low power state, the
1635 * configuration space of subordinate devices
1636 * may be not accessible
1638 if (bridge && bridge->current_state != PCI_D0)
1640 pci_pme_wakeup(pme_dev->dev, NULL);
1642 list_del(&pme_dev->list);
1646 if (!list_empty(&pci_pme_list))
1647 schedule_delayed_work(&pci_pme_work,
1648 msecs_to_jiffies(PME_TIMEOUT));
1650 mutex_unlock(&pci_pme_list_mutex);
1654 * pci_pme_active - enable or disable PCI device's PME# function
1655 * @dev: PCI device to handle.
1656 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1658 * The caller must verify that the device is capable of generating PME# before
1659 * calling this function with @enable equal to 'true'.
1661 void pci_pme_active(struct pci_dev *dev, bool enable)
1665 if (!dev->pme_support)
1668 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1669 /* Clear PME_Status by writing 1 to it and enable PME# */
1670 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1672 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1674 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1677 * PCI (as opposed to PCIe) PME requires that the device have
1678 * its PME# line hooked up correctly. Not all hardware vendors
1679 * do this, so the PME never gets delivered and the device
1680 * remains asleep. The easiest way around this is to
1681 * periodically walk the list of suspended devices and check
1682 * whether any have their PME flag set. The assumption is that
1683 * we'll wake up often enough anyway that this won't be a huge
1684 * hit, and the power savings from the devices will still be a
1687 * Although PCIe uses in-band PME message instead of PME# line
1688 * to report PME, PME does not work for some PCIe devices in
1689 * reality. For example, there are devices that set their PME
1690 * status bits, but don't really bother to send a PME message;
1691 * there are PCI Express Root Ports that don't bother to
1692 * trigger interrupts when they receive PME messages from the
1693 * devices below. So PME poll is used for PCIe devices too.
1696 if (dev->pme_poll) {
1697 struct pci_pme_device *pme_dev;
1699 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1702 dev_warn(&dev->dev, "can't enable PME#\n");
1706 mutex_lock(&pci_pme_list_mutex);
1707 list_add(&pme_dev->list, &pci_pme_list);
1708 if (list_is_singular(&pci_pme_list))
1709 schedule_delayed_work(&pci_pme_work,
1710 msecs_to_jiffies(PME_TIMEOUT));
1711 mutex_unlock(&pci_pme_list_mutex);
1713 mutex_lock(&pci_pme_list_mutex);
1714 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1715 if (pme_dev->dev == dev) {
1716 list_del(&pme_dev->list);
1721 mutex_unlock(&pci_pme_list_mutex);
1725 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1729 * __pci_enable_wake - enable PCI device as wakeup event source
1730 * @dev: PCI device affected
1731 * @state: PCI state from which device will issue wakeup events
1732 * @runtime: True if the events are to be generated at run time
1733 * @enable: True to enable event generation; false to disable
1735 * This enables the device as a wakeup event source, or disables it.
1736 * When such events involves platform-specific hooks, those hooks are
1737 * called automatically by this routine.
1739 * Devices with legacy power management (no standard PCI PM capabilities)
1740 * always require such platform hooks.
1743 * 0 is returned on success
1744 * -EINVAL is returned if device is not supposed to wake up the system
1745 * Error code depending on the platform is returned if both the platform and
1746 * the native mechanism fail to enable the generation of wake-up events
1748 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1749 bool runtime, bool enable)
1753 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1756 /* Don't do the same thing twice in a row for one device. */
1757 if (!!enable == !!dev->wakeup_prepared)
1761 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1762 * Anderson we should be doing PME# wake enable followed by ACPI wake
1763 * enable. To disable wake-up we call the platform first, for symmetry.
1769 if (pci_pme_capable(dev, state))
1770 pci_pme_active(dev, true);
1773 error = runtime ? platform_pci_run_wake(dev, true) :
1774 platform_pci_sleep_wake(dev, true);
1778 dev->wakeup_prepared = true;
1781 platform_pci_run_wake(dev, false);
1783 platform_pci_sleep_wake(dev, false);
1784 pci_pme_active(dev, false);
1785 dev->wakeup_prepared = false;
1790 EXPORT_SYMBOL(__pci_enable_wake);
1793 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1794 * @dev: PCI device to prepare
1795 * @enable: True to enable wake-up event generation; false to disable
1797 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1798 * and this function allows them to set that up cleanly - pci_enable_wake()
1799 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1800 * ordering constraints.
1802 * This function only returns error code if the device is not capable of
1803 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1804 * enable wake-up power for it.
1806 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1808 return pci_pme_capable(dev, PCI_D3cold) ?
1809 pci_enable_wake(dev, PCI_D3cold, enable) :
1810 pci_enable_wake(dev, PCI_D3hot, enable);
1814 * pci_target_state - find an appropriate low power state for a given PCI dev
1817 * Use underlying platform code to find a supported low power state for @dev.
1818 * If the platform can't manage @dev, return the deepest state from which it
1819 * can generate wake events, based on any available PME info.
1821 static pci_power_t pci_target_state(struct pci_dev *dev)
1823 pci_power_t target_state = PCI_D3hot;
1825 if (platform_pci_power_manageable(dev)) {
1827 * Call the platform to choose the target state of the device
1828 * and enable wake-up from this state if supported.
1830 pci_power_t state = platform_pci_choose_state(dev);
1833 case PCI_POWER_ERROR:
1838 if (pci_no_d1d2(dev))
1841 target_state = state;
1843 } else if (!dev->pm_cap) {
1844 target_state = PCI_D0;
1845 } else if (device_may_wakeup(&dev->dev)) {
1847 * Find the deepest state from which the device can generate
1848 * wake-up events, make it the target state and enable device
1851 if (dev->pme_support) {
1853 && !(dev->pme_support & (1 << target_state)))
1858 return target_state;
1862 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1863 * @dev: Device to handle.
1865 * Choose the power state appropriate for the device depending on whether
1866 * it can wake up the system and/or is power manageable by the platform
1867 * (PCI_D3hot is the default) and put the device into that state.
1869 int pci_prepare_to_sleep(struct pci_dev *dev)
1871 pci_power_t target_state = pci_target_state(dev);
1874 if (target_state == PCI_POWER_ERROR)
1877 /* D3cold during system suspend/hibernate is not supported */
1878 if (target_state > PCI_D3hot)
1879 target_state = PCI_D3hot;
1881 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1883 error = pci_set_power_state(dev, target_state);
1886 pci_enable_wake(dev, target_state, false);
1892 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1893 * @dev: Device to handle.
1895 * Disable device's system wake-up capability and put it into D0.
1897 int pci_back_from_sleep(struct pci_dev *dev)
1899 pci_enable_wake(dev, PCI_D0, false);
1900 return pci_set_power_state(dev, PCI_D0);
1904 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1905 * @dev: PCI device being suspended.
1907 * Prepare @dev to generate wake-up events at run time and put it into a low
1910 int pci_finish_runtime_suspend(struct pci_dev *dev)
1912 pci_power_t target_state = pci_target_state(dev);
1915 if (target_state == PCI_POWER_ERROR)
1918 dev->runtime_d3cold = target_state == PCI_D3cold;
1920 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1922 error = pci_set_power_state(dev, target_state);
1925 __pci_enable_wake(dev, target_state, true, false);
1926 dev->runtime_d3cold = false;
1933 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1934 * @dev: Device to check.
1936 * Return true if the device itself is capable of generating wake-up events
1937 * (through the platform or using the native PCIe PME) or if the device supports
1938 * PME and one of its upstream bridges can generate wake-up events.
1940 bool pci_dev_run_wake(struct pci_dev *dev)
1942 struct pci_bus *bus = dev->bus;
1944 if (device_run_wake(&dev->dev))
1947 if (!dev->pme_support)
1950 while (bus->parent) {
1951 struct pci_dev *bridge = bus->self;
1953 if (device_run_wake(&bridge->dev))
1959 /* We have reached the root bus. */
1961 return device_run_wake(bus->bridge);
1965 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1967 void pci_config_pm_runtime_get(struct pci_dev *pdev)
1969 struct device *dev = &pdev->dev;
1970 struct device *parent = dev->parent;
1973 pm_runtime_get_sync(parent);
1974 pm_runtime_get_noresume(dev);
1976 * pdev->current_state is set to PCI_D3cold during suspending,
1977 * so wait until suspending completes
1979 pm_runtime_barrier(dev);
1981 * Only need to resume devices in D3cold, because config
1982 * registers are still accessible for devices suspended but
1985 if (pdev->current_state == PCI_D3cold)
1986 pm_runtime_resume(dev);
1989 void pci_config_pm_runtime_put(struct pci_dev *pdev)
1991 struct device *dev = &pdev->dev;
1992 struct device *parent = dev->parent;
1994 pm_runtime_put(dev);
1996 pm_runtime_put_sync(parent);
2000 * pci_pm_init - Initialize PM functions of given PCI device
2001 * @dev: PCI device to handle.
2003 void pci_pm_init(struct pci_dev *dev)
2008 pm_runtime_forbid(&dev->dev);
2009 pm_runtime_set_active(&dev->dev);
2010 pm_runtime_enable(&dev->dev);
2011 device_enable_async_suspend(&dev->dev);
2012 dev->wakeup_prepared = false;
2015 dev->pme_support = 0;
2017 /* find PCI PM capability in list */
2018 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2021 /* Check device's ability to generate PME# */
2022 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2024 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2025 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2026 pmc & PCI_PM_CAP_VER_MASK);
2031 dev->d3_delay = PCI_PM_D3_WAIT;
2032 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2033 dev->d3cold_allowed = true;
2035 dev->d1_support = false;
2036 dev->d2_support = false;
2037 if (!pci_no_d1d2(dev)) {
2038 if (pmc & PCI_PM_CAP_D1)
2039 dev->d1_support = true;
2040 if (pmc & PCI_PM_CAP_D2)
2041 dev->d2_support = true;
2043 if (dev->d1_support || dev->d2_support)
2044 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2045 dev->d1_support ? " D1" : "",
2046 dev->d2_support ? " D2" : "");
2049 pmc &= PCI_PM_CAP_PME_MASK;
2051 dev_printk(KERN_DEBUG, &dev->dev,
2052 "PME# supported from%s%s%s%s%s\n",
2053 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2054 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2055 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2056 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2057 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2058 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2059 dev->pme_poll = true;
2061 * Make device's PM flags reflect the wake-up capability, but
2062 * let the user space enable it to wake up the system as needed.
2064 device_set_wakeup_capable(&dev->dev, true);
2065 /* Disable the PME# generation functionality */
2066 pci_pme_active(dev, false);
2070 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2071 struct pci_cap_saved_state *new_cap)
2073 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2077 * _pci_add_cap_save_buffer - allocate buffer for saving given
2078 * capability registers
2079 * @dev: the PCI device
2080 * @cap: the capability to allocate the buffer for
2081 * @extended: Standard or Extended capability ID
2082 * @size: requested size of the buffer
2084 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2085 bool extended, unsigned int size)
2088 struct pci_cap_saved_state *save_state;
2091 pos = pci_find_ext_capability(dev, cap);
2093 pos = pci_find_capability(dev, cap);
2098 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2102 save_state->cap.cap_nr = cap;
2103 save_state->cap.cap_extended = extended;
2104 save_state->cap.size = size;
2105 pci_add_saved_cap(dev, save_state);
2110 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2112 return _pci_add_cap_save_buffer(dev, cap, false, size);
2115 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2117 return _pci_add_cap_save_buffer(dev, cap, true, size);
2121 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2122 * @dev: the PCI device
2124 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2128 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2129 PCI_EXP_SAVE_REGS * sizeof(u16));
2132 "unable to preallocate PCI Express save buffer\n");
2134 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2137 "unable to preallocate PCI-X save buffer\n");
2139 pci_allocate_vc_save_buffers(dev);
2142 void pci_free_cap_save_buffers(struct pci_dev *dev)
2144 struct pci_cap_saved_state *tmp;
2145 struct hlist_node *n;
2147 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2152 * pci_configure_ari - enable or disable ARI forwarding
2153 * @dev: the PCI device
2155 * If @dev and its upstream bridge both support ARI, enable ARI in the
2156 * bridge. Otherwise, disable ARI in the bridge.
2158 void pci_configure_ari(struct pci_dev *dev)
2161 struct pci_dev *bridge;
2163 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2166 bridge = dev->bus->self;
2170 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2171 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2174 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2175 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2176 PCI_EXP_DEVCTL2_ARI);
2177 bridge->ari_enabled = 1;
2179 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2180 PCI_EXP_DEVCTL2_ARI);
2181 bridge->ari_enabled = 0;
2185 static int pci_acs_enable;
2188 * pci_request_acs - ask for ACS to be enabled if supported
2190 void pci_request_acs(void)
2196 * pci_enable_acs - enable ACS if hardware support it
2197 * @dev: the PCI device
2199 void pci_enable_acs(struct pci_dev *dev)
2205 if (!pci_acs_enable)
2208 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2212 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2213 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2215 /* Source Validation */
2216 ctrl |= (cap & PCI_ACS_SV);
2218 /* P2P Request Redirect */
2219 ctrl |= (cap & PCI_ACS_RR);
2221 /* P2P Completion Redirect */
2222 ctrl |= (cap & PCI_ACS_CR);
2224 /* Upstream Forwarding */
2225 ctrl |= (cap & PCI_ACS_UF);
2227 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2230 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2235 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2240 * Except for egress control, capabilities are either required
2241 * or only required if controllable. Features missing from the
2242 * capability field can therefore be assumed as hard-wired enabled.
2244 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2245 acs_flags &= (cap | PCI_ACS_EC);
2247 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2248 return (ctrl & acs_flags) == acs_flags;
2252 * pci_acs_enabled - test ACS against required flags for a given device
2253 * @pdev: device to test
2254 * @acs_flags: required PCI ACS flags
2256 * Return true if the device supports the provided flags. Automatically
2257 * filters out flags that are not implemented on multifunction devices.
2259 * Note that this interface checks the effective ACS capabilities of the
2260 * device rather than the actual capabilities. For instance, most single
2261 * function endpoints are not required to support ACS because they have no
2262 * opportunity for peer-to-peer access. We therefore return 'true'
2263 * regardless of whether the device exposes an ACS capability. This makes
2264 * it much easier for callers of this function to ignore the actual type
2265 * or topology of the device when testing ACS support.
2267 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2271 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2276 * Conventional PCI and PCI-X devices never support ACS, either
2277 * effectively or actually. The shared bus topology implies that
2278 * any device on the bus can receive or snoop DMA.
2280 if (!pci_is_pcie(pdev))
2283 switch (pci_pcie_type(pdev)) {
2285 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2286 * but since their primary interface is PCI/X, we conservatively
2287 * handle them as we would a non-PCIe device.
2289 case PCI_EXP_TYPE_PCIE_BRIDGE:
2291 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2292 * applicable... must never implement an ACS Extended Capability...".
2293 * This seems arbitrary, but we take a conservative interpretation
2294 * of this statement.
2296 case PCI_EXP_TYPE_PCI_BRIDGE:
2297 case PCI_EXP_TYPE_RC_EC:
2300 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2301 * implement ACS in order to indicate their peer-to-peer capabilities,
2302 * regardless of whether they are single- or multi-function devices.
2304 case PCI_EXP_TYPE_DOWNSTREAM:
2305 case PCI_EXP_TYPE_ROOT_PORT:
2306 return pci_acs_flags_enabled(pdev, acs_flags);
2308 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2309 * implemented by the remaining PCIe types to indicate peer-to-peer
2310 * capabilities, but only when they are part of a multifunction
2311 * device. The footnote for section 6.12 indicates the specific
2312 * PCIe types included here.
2314 case PCI_EXP_TYPE_ENDPOINT:
2315 case PCI_EXP_TYPE_UPSTREAM:
2316 case PCI_EXP_TYPE_LEG_END:
2317 case PCI_EXP_TYPE_RC_END:
2318 if (!pdev->multifunction)
2321 return pci_acs_flags_enabled(pdev, acs_flags);
2325 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2326 * to single function devices with the exception of downstream ports.
2332 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2333 * @start: starting downstream device
2334 * @end: ending upstream device or NULL to search to the root bus
2335 * @acs_flags: required flags
2337 * Walk up a device tree from start to end testing PCI ACS support. If
2338 * any step along the way does not support the required flags, return false.
2340 bool pci_acs_path_enabled(struct pci_dev *start,
2341 struct pci_dev *end, u16 acs_flags)
2343 struct pci_dev *pdev, *parent = start;
2348 if (!pci_acs_enabled(pdev, acs_flags))
2351 if (pci_is_root_bus(pdev->bus))
2352 return (end == NULL);
2354 parent = pdev->bus->self;
2355 } while (pdev != end);
2361 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2362 * @dev: the PCI device
2363 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2365 * Perform INTx swizzling for a device behind one level of bridge. This is
2366 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2367 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2368 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2369 * the PCI Express Base Specification, Revision 2.1)
2371 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2375 if (pci_ari_enabled(dev->bus))
2378 slot = PCI_SLOT(dev->devfn);
2380 return (((pin - 1) + slot) % 4) + 1;
2384 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2392 while (!pci_is_root_bus(dev->bus)) {
2393 pin = pci_swizzle_interrupt_pin(dev, pin);
2394 dev = dev->bus->self;
2401 * pci_common_swizzle - swizzle INTx all the way to root bridge
2402 * @dev: the PCI device
2403 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2405 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2406 * bridges all the way up to a PCI root bus.
2408 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2412 while (!pci_is_root_bus(dev->bus)) {
2413 pin = pci_swizzle_interrupt_pin(dev, pin);
2414 dev = dev->bus->self;
2417 return PCI_SLOT(dev->devfn);
2421 * pci_release_region - Release a PCI bar
2422 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2423 * @bar: BAR to release
2425 * Releases the PCI I/O and memory resources previously reserved by a
2426 * successful call to pci_request_region. Call this function only
2427 * after all use of the PCI regions has ceased.
2429 void pci_release_region(struct pci_dev *pdev, int bar)
2431 struct pci_devres *dr;
2433 if (pci_resource_len(pdev, bar) == 0)
2435 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2436 release_region(pci_resource_start(pdev, bar),
2437 pci_resource_len(pdev, bar));
2438 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2439 release_mem_region(pci_resource_start(pdev, bar),
2440 pci_resource_len(pdev, bar));
2442 dr = find_pci_dr(pdev);
2444 dr->region_mask &= ~(1 << bar);
2448 * __pci_request_region - Reserved PCI I/O and memory resource
2449 * @pdev: PCI device whose resources are to be reserved
2450 * @bar: BAR to be reserved
2451 * @res_name: Name to be associated with resource.
2452 * @exclusive: whether the region access is exclusive or not
2454 * Mark the PCI region associated with PCI device @pdev BR @bar as
2455 * being reserved by owner @res_name. Do not access any
2456 * address inside the PCI regions unless this call returns
2459 * If @exclusive is set, then the region is marked so that userspace
2460 * is explicitly not allowed to map the resource via /dev/mem or
2461 * sysfs MMIO access.
2463 * Returns 0 on success, or %EBUSY on error. A warning
2464 * message is also printed on failure.
2466 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2469 struct pci_devres *dr;
2471 if (pci_resource_len(pdev, bar) == 0)
2474 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2475 if (!request_region(pci_resource_start(pdev, bar),
2476 pci_resource_len(pdev, bar), res_name))
2479 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2480 if (!__request_mem_region(pci_resource_start(pdev, bar),
2481 pci_resource_len(pdev, bar), res_name,
2486 dr = find_pci_dr(pdev);
2488 dr->region_mask |= 1 << bar;
2493 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2494 &pdev->resource[bar]);
2499 * pci_request_region - Reserve PCI I/O and memory resource
2500 * @pdev: PCI device whose resources are to be reserved
2501 * @bar: BAR to be reserved
2502 * @res_name: Name to be associated with resource
2504 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2505 * being reserved by owner @res_name. Do not access any
2506 * address inside the PCI regions unless this call returns
2509 * Returns 0 on success, or %EBUSY on error. A warning
2510 * message is also printed on failure.
2512 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2514 return __pci_request_region(pdev, bar, res_name, 0);
2518 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2519 * @pdev: PCI device whose resources are to be reserved
2520 * @bar: BAR to be reserved
2521 * @res_name: Name to be associated with resource.
2523 * Mark the PCI region associated with PCI device @pdev BR @bar as
2524 * being reserved by owner @res_name. Do not access any
2525 * address inside the PCI regions unless this call returns
2528 * Returns 0 on success, or %EBUSY on error. A warning
2529 * message is also printed on failure.
2531 * The key difference that _exclusive makes it that userspace is
2532 * explicitly not allowed to map the resource via /dev/mem or
2535 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2537 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2540 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2541 * @pdev: PCI device whose resources were previously reserved
2542 * @bars: Bitmask of BARs to be released
2544 * Release selected PCI I/O and memory resources previously reserved.
2545 * Call this function only after all use of the PCI regions has ceased.
2547 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2551 for (i = 0; i < 6; i++)
2552 if (bars & (1 << i))
2553 pci_release_region(pdev, i);
2556 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2557 const char *res_name, int excl)
2561 for (i = 0; i < 6; i++)
2562 if (bars & (1 << i))
2563 if (__pci_request_region(pdev, i, res_name, excl))
2569 if (bars & (1 << i))
2570 pci_release_region(pdev, i);
2577 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2578 * @pdev: PCI device whose resources are to be reserved
2579 * @bars: Bitmask of BARs to be requested
2580 * @res_name: Name to be associated with resource
2582 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2583 const char *res_name)
2585 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2588 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2589 int bars, const char *res_name)
2591 return __pci_request_selected_regions(pdev, bars, res_name,
2592 IORESOURCE_EXCLUSIVE);
2596 * pci_release_regions - Release reserved PCI I/O and memory resources
2597 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2599 * Releases all PCI I/O and memory resources previously reserved by a
2600 * successful call to pci_request_regions. Call this function only
2601 * after all use of the PCI regions has ceased.
2604 void pci_release_regions(struct pci_dev *pdev)
2606 pci_release_selected_regions(pdev, (1 << 6) - 1);
2610 * pci_request_regions - Reserved PCI I/O and memory resources
2611 * @pdev: PCI device whose resources are to be reserved
2612 * @res_name: Name to be associated with resource.
2614 * Mark all PCI regions associated with PCI device @pdev as
2615 * being reserved by owner @res_name. Do not access any
2616 * address inside the PCI regions unless this call returns
2619 * Returns 0 on success, or %EBUSY on error. A warning
2620 * message is also printed on failure.
2622 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2624 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2628 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2629 * @pdev: PCI device whose resources are to be reserved
2630 * @res_name: Name to be associated with resource.
2632 * Mark all PCI regions associated with PCI device @pdev as
2633 * being reserved by owner @res_name. Do not access any
2634 * address inside the PCI regions unless this call returns
2637 * pci_request_regions_exclusive() will mark the region so that
2638 * /dev/mem and the sysfs MMIO access will not be allowed.
2640 * Returns 0 on success, or %EBUSY on error. A warning
2641 * message is also printed on failure.
2643 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2645 return pci_request_selected_regions_exclusive(pdev,
2646 ((1 << 6) - 1), res_name);
2649 static void __pci_set_master(struct pci_dev *dev, bool enable)
2653 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2655 cmd = old_cmd | PCI_COMMAND_MASTER;
2657 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2658 if (cmd != old_cmd) {
2659 dev_dbg(&dev->dev, "%s bus mastering\n",
2660 enable ? "enabling" : "disabling");
2661 pci_write_config_word(dev, PCI_COMMAND, cmd);
2663 dev->is_busmaster = enable;
2667 * pcibios_setup - process "pci=" kernel boot arguments
2668 * @str: string used to pass in "pci=" kernel boot arguments
2670 * Process kernel boot arguments. This is the default implementation.
2671 * Architecture specific implementations can override this as necessary.
2673 char * __weak __init pcibios_setup(char *str)
2679 * pcibios_set_master - enable PCI bus-mastering for device dev
2680 * @dev: the PCI device to enable
2682 * Enables PCI bus-mastering for the device. This is the default
2683 * implementation. Architecture specific implementations can override
2684 * this if necessary.
2686 void __weak pcibios_set_master(struct pci_dev *dev)
2690 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2691 if (pci_is_pcie(dev))
2694 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2696 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2697 else if (lat > pcibios_max_latency)
2698 lat = pcibios_max_latency;
2702 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2706 * pci_set_master - enables bus-mastering for device dev
2707 * @dev: the PCI device to enable
2709 * Enables bus-mastering on the device and calls pcibios_set_master()
2710 * to do the needed arch specific settings.
2712 void pci_set_master(struct pci_dev *dev)
2714 __pci_set_master(dev, true);
2715 pcibios_set_master(dev);
2719 * pci_clear_master - disables bus-mastering for device dev
2720 * @dev: the PCI device to disable
2722 void pci_clear_master(struct pci_dev *dev)
2724 __pci_set_master(dev, false);
2728 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2729 * @dev: the PCI device for which MWI is to be enabled
2731 * Helper function for pci_set_mwi.
2732 * Originally copied from drivers/net/acenic.c.
2733 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2735 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2737 int pci_set_cacheline_size(struct pci_dev *dev)
2741 if (!pci_cache_line_size)
2744 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2745 equal to or multiple of the right value. */
2746 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2747 if (cacheline_size >= pci_cache_line_size &&
2748 (cacheline_size % pci_cache_line_size) == 0)
2751 /* Write the correct value. */
2752 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2754 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2755 if (cacheline_size == pci_cache_line_size)
2758 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2759 "supported\n", pci_cache_line_size << 2);
2763 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2765 #ifdef PCI_DISABLE_MWI
2766 int pci_set_mwi(struct pci_dev *dev)
2771 int pci_try_set_mwi(struct pci_dev *dev)
2776 void pci_clear_mwi(struct pci_dev *dev)
2783 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2784 * @dev: the PCI device for which MWI is enabled
2786 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2788 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2791 pci_set_mwi(struct pci_dev *dev)
2796 rc = pci_set_cacheline_size(dev);
2800 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2801 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2802 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2803 cmd |= PCI_COMMAND_INVALIDATE;
2804 pci_write_config_word(dev, PCI_COMMAND, cmd);
2811 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2812 * @dev: the PCI device for which MWI is enabled
2814 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2815 * Callers are not required to check the return value.
2817 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2819 int pci_try_set_mwi(struct pci_dev *dev)
2821 int rc = pci_set_mwi(dev);
2826 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2827 * @dev: the PCI device to disable
2829 * Disables PCI Memory-Write-Invalidate transaction on the device
2832 pci_clear_mwi(struct pci_dev *dev)
2836 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2837 if (cmd & PCI_COMMAND_INVALIDATE) {
2838 cmd &= ~PCI_COMMAND_INVALIDATE;
2839 pci_write_config_word(dev, PCI_COMMAND, cmd);
2842 #endif /* ! PCI_DISABLE_MWI */
2845 * pci_intx - enables/disables PCI INTx for device dev
2846 * @pdev: the PCI device to operate on
2847 * @enable: boolean: whether to enable or disable PCI INTx
2849 * Enables/disables PCI INTx for device dev
2852 pci_intx(struct pci_dev *pdev, int enable)
2854 u16 pci_command, new;
2856 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2859 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2861 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2864 if (new != pci_command) {
2865 struct pci_devres *dr;
2867 pci_write_config_word(pdev, PCI_COMMAND, new);
2869 dr = find_pci_dr(pdev);
2870 if (dr && !dr->restore_intx) {
2871 dr->restore_intx = 1;
2872 dr->orig_intx = !enable;
2878 * pci_intx_mask_supported - probe for INTx masking support
2879 * @dev: the PCI device to operate on
2881 * Check if the device dev support INTx masking via the config space
2884 bool pci_intx_mask_supported(struct pci_dev *dev)
2886 bool mask_supported = false;
2889 if (dev->broken_intx_masking)
2892 pci_cfg_access_lock(dev);
2894 pci_read_config_word(dev, PCI_COMMAND, &orig);
2895 pci_write_config_word(dev, PCI_COMMAND,
2896 orig ^ PCI_COMMAND_INTX_DISABLE);
2897 pci_read_config_word(dev, PCI_COMMAND, &new);
2900 * There's no way to protect against hardware bugs or detect them
2901 * reliably, but as long as we know what the value should be, let's
2902 * go ahead and check it.
2904 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2905 dev_err(&dev->dev, "Command register changed from "
2906 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2907 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2908 mask_supported = true;
2909 pci_write_config_word(dev, PCI_COMMAND, orig);
2912 pci_cfg_access_unlock(dev);
2913 return mask_supported;
2915 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2917 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2919 struct pci_bus *bus = dev->bus;
2920 bool mask_updated = true;
2921 u32 cmd_status_dword;
2922 u16 origcmd, newcmd;
2923 unsigned long flags;
2927 * We do a single dword read to retrieve both command and status.
2928 * Document assumptions that make this possible.
2930 BUILD_BUG_ON(PCI_COMMAND % 4);
2931 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2933 raw_spin_lock_irqsave(&pci_lock, flags);
2935 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2937 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2940 * Check interrupt status register to see whether our device
2941 * triggered the interrupt (when masking) or the next IRQ is
2942 * already pending (when unmasking).
2944 if (mask != irq_pending) {
2945 mask_updated = false;
2949 origcmd = cmd_status_dword;
2950 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2952 newcmd |= PCI_COMMAND_INTX_DISABLE;
2953 if (newcmd != origcmd)
2954 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2957 raw_spin_unlock_irqrestore(&pci_lock, flags);
2959 return mask_updated;
2963 * pci_check_and_mask_intx - mask INTx on pending interrupt
2964 * @dev: the PCI device to operate on
2966 * Check if the device dev has its INTx line asserted, mask it and
2967 * return true in that case. False is returned if not interrupt was
2970 bool pci_check_and_mask_intx(struct pci_dev *dev)
2972 return pci_check_and_set_intx_mask(dev, true);
2974 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
2977 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
2978 * @dev: the PCI device to operate on
2980 * Check if the device dev has its INTx line asserted, unmask it if not
2981 * and return true. False is returned and the mask remains active if
2982 * there was still an interrupt pending.
2984 bool pci_check_and_unmask_intx(struct pci_dev *dev)
2986 return pci_check_and_set_intx_mask(dev, false);
2988 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
2991 * pci_msi_off - disables any MSI or MSI-X capabilities
2992 * @dev: the PCI device to operate on
2994 * If you want to use MSI, see pci_enable_msi() and friends.
2995 * This is a lower-level primitive that allows us to disable
2996 * MSI operation at the device level.
2998 void pci_msi_off(struct pci_dev *dev)
3004 * This looks like it could go in msi.c, but we need it even when
3005 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3006 * dev->msi_cap or dev->msix_cap here.
3008 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3010 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3011 control &= ~PCI_MSI_FLAGS_ENABLE;
3012 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3014 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3016 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3017 control &= ~PCI_MSIX_FLAGS_ENABLE;
3018 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3021 EXPORT_SYMBOL_GPL(pci_msi_off);
3023 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3025 return dma_set_max_seg_size(&dev->dev, size);
3027 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3029 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3031 return dma_set_seg_boundary(&dev->dev, mask);
3033 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3036 * pci_wait_for_pending_transaction - waits for pending transaction
3037 * @dev: the PCI device to operate on
3039 * Return 0 if transaction is pending 1 otherwise.
3041 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3043 if (!pci_is_pcie(dev))
3046 return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND);
3048 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3050 static int pcie_flr(struct pci_dev *dev, int probe)
3054 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3055 if (!(cap & PCI_EXP_DEVCAP_FLR))
3061 if (!pci_wait_for_pending_transaction(dev))
3062 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3064 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3071 static int pci_af_flr(struct pci_dev *dev, int probe)
3076 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3080 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3081 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3087 /* Wait for Transaction Pending bit clean */
3088 if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP))
3091 dev_err(&dev->dev, "transaction is not cleared; "
3092 "proceeding with reset anyway\n");
3095 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3102 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3103 * @dev: Device to reset.
3104 * @probe: If set, only check if the device can be reset this way.
3106 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3107 * unset, it will be reinitialized internally when going from PCI_D3hot to
3108 * PCI_D0. If that's the case and the device is not in a low-power state
3109 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3111 * NOTE: This causes the caller to sleep for twice the device power transition
3112 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3113 * by default (i.e. unless the @dev's d3_delay field has a different value).
3114 * Moreover, only devices in D0 can be reset by this function.
3116 static int pci_pm_reset(struct pci_dev *dev, int probe)
3123 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3124 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3130 if (dev->current_state != PCI_D0)
3133 csr &= ~PCI_PM_CTRL_STATE_MASK;
3135 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3136 pci_dev_d3_sleep(dev);
3138 csr &= ~PCI_PM_CTRL_STATE_MASK;
3140 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3141 pci_dev_d3_sleep(dev);
3147 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3148 * @dev: Bridge device
3150 * Use the bridge control register to assert reset on the secondary bus.
3151 * Devices on the secondary bus are left in power-on state.
3153 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3157 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3158 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3159 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3161 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3162 * this to 2ms to ensure that we meet the minimum requirement.
3166 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3167 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3170 * Trhfa for conventional PCI is 2^25 clock cycles.
3171 * Assuming a minimum 33MHz clock this results in a 1s
3172 * delay before we can consider subordinate devices to
3173 * be re-initialized. PCIe has some ways to shorten this,
3174 * but we don't make use of them yet.
3178 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3180 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3182 struct pci_dev *pdev;
3184 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3187 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3194 pci_reset_bridge_secondary_bus(dev->bus->self);
3199 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3203 if (!hotplug || !try_module_get(hotplug->ops->owner))
3206 if (hotplug->ops->reset_slot)
3207 rc = hotplug->ops->reset_slot(hotplug, probe);
3209 module_put(hotplug->ops->owner);
3214 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3216 struct pci_dev *pdev;
3218 if (dev->subordinate || !dev->slot)
3221 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3222 if (pdev != dev && pdev->slot == dev->slot)
3225 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3228 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3234 rc = pci_dev_specific_reset(dev, probe);
3238 rc = pcie_flr(dev, probe);
3242 rc = pci_af_flr(dev, probe);
3246 rc = pci_pm_reset(dev, probe);
3250 rc = pci_dev_reset_slot_function(dev, probe);
3254 rc = pci_parent_bus_reset(dev, probe);
3259 static void pci_dev_lock(struct pci_dev *dev)
3261 pci_cfg_access_lock(dev);
3262 /* block PM suspend, driver probe, etc. */
3263 device_lock(&dev->dev);
3266 /* Return 1 on successful lock, 0 on contention */
3267 static int pci_dev_trylock(struct pci_dev *dev)
3269 if (pci_cfg_access_trylock(dev)) {
3270 if (device_trylock(&dev->dev))
3272 pci_cfg_access_unlock(dev);
3278 static void pci_dev_unlock(struct pci_dev *dev)
3280 device_unlock(&dev->dev);
3281 pci_cfg_access_unlock(dev);
3284 static void pci_dev_save_and_disable(struct pci_dev *dev)
3287 * Wake-up device prior to save. PM registers default to D0 after
3288 * reset and a simple register restore doesn't reliably return
3289 * to a non-D0 state anyway.
3291 pci_set_power_state(dev, PCI_D0);
3293 pci_save_state(dev);
3295 * Disable the device by clearing the Command register, except for
3296 * INTx-disable which is set. This not only disables MMIO and I/O port
3297 * BARs, but also prevents the device from being Bus Master, preventing
3298 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3299 * compliant devices, INTx-disable prevents legacy interrupts.
3301 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3304 static void pci_dev_restore(struct pci_dev *dev)
3306 pci_restore_state(dev);
3309 static int pci_dev_reset(struct pci_dev *dev, int probe)
3316 rc = __pci_dev_reset(dev, probe);
3319 pci_dev_unlock(dev);
3324 * __pci_reset_function - reset a PCI device function
3325 * @dev: PCI device to reset
3327 * Some devices allow an individual function to be reset without affecting
3328 * other functions in the same device. The PCI device must be responsive
3329 * to PCI config space in order to use this function.
3331 * The device function is presumed to be unused when this function is called.
3332 * Resetting the device will make the contents of PCI configuration space
3333 * random, so any caller of this must be prepared to reinitialise the
3334 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3337 * Returns 0 if the device function was successfully reset or negative if the
3338 * device doesn't support resetting a single function.
3340 int __pci_reset_function(struct pci_dev *dev)
3342 return pci_dev_reset(dev, 0);
3344 EXPORT_SYMBOL_GPL(__pci_reset_function);
3347 * __pci_reset_function_locked - reset a PCI device function while holding
3348 * the @dev mutex lock.
3349 * @dev: PCI device to reset
3351 * Some devices allow an individual function to be reset without affecting
3352 * other functions in the same device. The PCI device must be responsive
3353 * to PCI config space in order to use this function.
3355 * The device function is presumed to be unused and the caller is holding
3356 * the device mutex lock when this function is called.
3357 * Resetting the device will make the contents of PCI configuration space
3358 * random, so any caller of this must be prepared to reinitialise the
3359 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3362 * Returns 0 if the device function was successfully reset or negative if the
3363 * device doesn't support resetting a single function.
3365 int __pci_reset_function_locked(struct pci_dev *dev)
3367 return __pci_dev_reset(dev, 0);
3369 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3372 * pci_probe_reset_function - check whether the device can be safely reset
3373 * @dev: PCI device to reset
3375 * Some devices allow an individual function to be reset without affecting
3376 * other functions in the same device. The PCI device must be responsive
3377 * to PCI config space in order to use this function.
3379 * Returns 0 if the device function can be reset or negative if the
3380 * device doesn't support resetting a single function.
3382 int pci_probe_reset_function(struct pci_dev *dev)
3384 return pci_dev_reset(dev, 1);
3388 * pci_reset_function - quiesce and reset a PCI device function
3389 * @dev: PCI device to reset
3391 * Some devices allow an individual function to be reset without affecting
3392 * other functions in the same device. The PCI device must be responsive
3393 * to PCI config space in order to use this function.
3395 * This function does not just reset the PCI portion of a device, but
3396 * clears all the state associated with the device. This function differs
3397 * from __pci_reset_function in that it saves and restores device state
3400 * Returns 0 if the device function was successfully reset or negative if the
3401 * device doesn't support resetting a single function.
3403 int pci_reset_function(struct pci_dev *dev)
3407 rc = pci_dev_reset(dev, 1);
3411 pci_dev_save_and_disable(dev);
3413 rc = pci_dev_reset(dev, 0);
3415 pci_dev_restore(dev);
3419 EXPORT_SYMBOL_GPL(pci_reset_function);
3422 * pci_try_reset_function - quiesce and reset a PCI device function
3423 * @dev: PCI device to reset
3425 * Same as above, except return -EAGAIN if unable to lock device.
3427 int pci_try_reset_function(struct pci_dev *dev)
3431 rc = pci_dev_reset(dev, 1);
3435 pci_dev_save_and_disable(dev);
3437 if (pci_dev_trylock(dev)) {
3438 rc = __pci_dev_reset(dev, 0);
3439 pci_dev_unlock(dev);
3443 pci_dev_restore(dev);
3447 EXPORT_SYMBOL_GPL(pci_try_reset_function);
3449 /* Lock devices from the top of the tree down */
3450 static void pci_bus_lock(struct pci_bus *bus)
3452 struct pci_dev *dev;
3454 list_for_each_entry(dev, &bus->devices, bus_list) {
3456 if (dev->subordinate)
3457 pci_bus_lock(dev->subordinate);
3461 /* Unlock devices from the bottom of the tree up */
3462 static void pci_bus_unlock(struct pci_bus *bus)
3464 struct pci_dev *dev;
3466 list_for_each_entry(dev, &bus->devices, bus_list) {
3467 if (dev->subordinate)
3468 pci_bus_unlock(dev->subordinate);
3469 pci_dev_unlock(dev);
3473 /* Return 1 on successful lock, 0 on contention */
3474 static int pci_bus_trylock(struct pci_bus *bus)
3476 struct pci_dev *dev;
3478 list_for_each_entry(dev, &bus->devices, bus_list) {
3479 if (!pci_dev_trylock(dev))
3481 if (dev->subordinate) {
3482 if (!pci_bus_trylock(dev->subordinate)) {
3483 pci_dev_unlock(dev);
3491 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3492 if (dev->subordinate)
3493 pci_bus_unlock(dev->subordinate);
3494 pci_dev_unlock(dev);
3499 /* Lock devices from the top of the tree down */
3500 static void pci_slot_lock(struct pci_slot *slot)
3502 struct pci_dev *dev;
3504 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3505 if (!dev->slot || dev->slot != slot)
3508 if (dev->subordinate)
3509 pci_bus_lock(dev->subordinate);
3513 /* Unlock devices from the bottom of the tree up */
3514 static void pci_slot_unlock(struct pci_slot *slot)
3516 struct pci_dev *dev;
3518 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3519 if (!dev->slot || dev->slot != slot)
3521 if (dev->subordinate)
3522 pci_bus_unlock(dev->subordinate);
3523 pci_dev_unlock(dev);
3527 /* Return 1 on successful lock, 0 on contention */
3528 static int pci_slot_trylock(struct pci_slot *slot)
3530 struct pci_dev *dev;
3532 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3533 if (!dev->slot || dev->slot != slot)
3535 if (!pci_dev_trylock(dev))
3537 if (dev->subordinate) {
3538 if (!pci_bus_trylock(dev->subordinate)) {
3539 pci_dev_unlock(dev);
3547 list_for_each_entry_continue_reverse(dev,
3548 &slot->bus->devices, bus_list) {
3549 if (!dev->slot || dev->slot != slot)
3551 if (dev->subordinate)
3552 pci_bus_unlock(dev->subordinate);
3553 pci_dev_unlock(dev);
3558 /* Save and disable devices from the top of the tree down */
3559 static void pci_bus_save_and_disable(struct pci_bus *bus)
3561 struct pci_dev *dev;
3563 list_for_each_entry(dev, &bus->devices, bus_list) {
3564 pci_dev_save_and_disable(dev);
3565 if (dev->subordinate)
3566 pci_bus_save_and_disable(dev->subordinate);
3571 * Restore devices from top of the tree down - parent bridges need to be
3572 * restored before we can get to subordinate devices.
3574 static void pci_bus_restore(struct pci_bus *bus)
3576 struct pci_dev *dev;
3578 list_for_each_entry(dev, &bus->devices, bus_list) {
3579 pci_dev_restore(dev);
3580 if (dev->subordinate)
3581 pci_bus_restore(dev->subordinate);
3585 /* Save and disable devices from the top of the tree down */
3586 static void pci_slot_save_and_disable(struct pci_slot *slot)
3588 struct pci_dev *dev;
3590 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3591 if (!dev->slot || dev->slot != slot)
3593 pci_dev_save_and_disable(dev);
3594 if (dev->subordinate)
3595 pci_bus_save_and_disable(dev->subordinate);
3600 * Restore devices from top of the tree down - parent bridges need to be
3601 * restored before we can get to subordinate devices.
3603 static void pci_slot_restore(struct pci_slot *slot)
3605 struct pci_dev *dev;
3607 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3608 if (!dev->slot || dev->slot != slot)
3610 pci_dev_restore(dev);
3611 if (dev->subordinate)
3612 pci_bus_restore(dev->subordinate);
3616 static int pci_slot_reset(struct pci_slot *slot, int probe)
3624 pci_slot_lock(slot);
3628 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3631 pci_slot_unlock(slot);
3637 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3638 * @slot: PCI slot to probe
3640 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3642 int pci_probe_reset_slot(struct pci_slot *slot)
3644 return pci_slot_reset(slot, 1);
3646 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3649 * pci_reset_slot - reset a PCI slot
3650 * @slot: PCI slot to reset
3652 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3653 * independent of other slots. For instance, some slots may support slot power
3654 * control. In the case of a 1:1 bus to slot architecture, this function may
3655 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3656 * Generally a slot reset should be attempted before a bus reset. All of the
3657 * function of the slot and any subordinate buses behind the slot are reset
3658 * through this function. PCI config space of all devices in the slot and
3659 * behind the slot is saved before and restored after reset.
3661 * Return 0 on success, non-zero on error.
3663 int pci_reset_slot(struct pci_slot *slot)
3667 rc = pci_slot_reset(slot, 1);
3671 pci_slot_save_and_disable(slot);
3673 rc = pci_slot_reset(slot, 0);
3675 pci_slot_restore(slot);
3679 EXPORT_SYMBOL_GPL(pci_reset_slot);
3682 * pci_try_reset_slot - Try to reset a PCI slot
3683 * @slot: PCI slot to reset
3685 * Same as above except return -EAGAIN if the slot cannot be locked
3687 int pci_try_reset_slot(struct pci_slot *slot)
3691 rc = pci_slot_reset(slot, 1);
3695 pci_slot_save_and_disable(slot);
3697 if (pci_slot_trylock(slot)) {
3699 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3700 pci_slot_unlock(slot);
3704 pci_slot_restore(slot);
3708 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3710 static int pci_bus_reset(struct pci_bus *bus, int probe)
3722 pci_reset_bridge_secondary_bus(bus->self);
3724 pci_bus_unlock(bus);
3730 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3731 * @bus: PCI bus to probe
3733 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3735 int pci_probe_reset_bus(struct pci_bus *bus)
3737 return pci_bus_reset(bus, 1);
3739 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3742 * pci_reset_bus - reset a PCI bus
3743 * @bus: top level PCI bus to reset
3745 * Do a bus reset on the given bus and any subordinate buses, saving
3746 * and restoring state of all devices.
3748 * Return 0 on success, non-zero on error.
3750 int pci_reset_bus(struct pci_bus *bus)
3754 rc = pci_bus_reset(bus, 1);
3758 pci_bus_save_and_disable(bus);
3760 rc = pci_bus_reset(bus, 0);
3762 pci_bus_restore(bus);
3766 EXPORT_SYMBOL_GPL(pci_reset_bus);
3769 * pci_try_reset_bus - Try to reset a PCI bus
3770 * @bus: top level PCI bus to reset
3772 * Same as above except return -EAGAIN if the bus cannot be locked
3774 int pci_try_reset_bus(struct pci_bus *bus)
3778 rc = pci_bus_reset(bus, 1);
3782 pci_bus_save_and_disable(bus);
3784 if (pci_bus_trylock(bus)) {
3786 pci_reset_bridge_secondary_bus(bus->self);
3787 pci_bus_unlock(bus);
3791 pci_bus_restore(bus);
3795 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3798 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3799 * @dev: PCI device to query
3801 * Returns mmrbc: maximum designed memory read count in bytes
3802 * or appropriate error value.
3804 int pcix_get_max_mmrbc(struct pci_dev *dev)
3809 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3813 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3816 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3818 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3821 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3822 * @dev: PCI device to query
3824 * Returns mmrbc: maximum memory read count in bytes
3825 * or appropriate error value.
3827 int pcix_get_mmrbc(struct pci_dev *dev)
3832 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3836 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3839 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3841 EXPORT_SYMBOL(pcix_get_mmrbc);
3844 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3845 * @dev: PCI device to query
3846 * @mmrbc: maximum memory read count in bytes
3847 * valid values are 512, 1024, 2048, 4096
3849 * If possible sets maximum memory read byte count, some bridges have erratas
3850 * that prevent this.
3852 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3858 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3861 v = ffs(mmrbc) - 10;
3863 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3867 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3870 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3873 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3876 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3878 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3881 cmd &= ~PCI_X_CMD_MAX_READ;
3883 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3888 EXPORT_SYMBOL(pcix_set_mmrbc);
3891 * pcie_get_readrq - get PCI Express read request size
3892 * @dev: PCI device to query
3894 * Returns maximum memory read request in bytes
3895 * or appropriate error value.
3897 int pcie_get_readrq(struct pci_dev *dev)
3901 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3903 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3905 EXPORT_SYMBOL(pcie_get_readrq);
3908 * pcie_set_readrq - set PCI Express maximum memory read request
3909 * @dev: PCI device to query
3910 * @rq: maximum memory read count in bytes
3911 * valid values are 128, 256, 512, 1024, 2048, 4096
3913 * If possible sets maximum memory read request in bytes
3915 int pcie_set_readrq(struct pci_dev *dev, int rq)
3919 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3923 * If using the "performance" PCIe config, we clamp the
3924 * read rq size to the max packet size to prevent the
3925 * host bridge generating requests larger than we can
3928 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3929 int mps = pcie_get_mps(dev);
3935 v = (ffs(rq) - 8) << 12;
3937 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3938 PCI_EXP_DEVCTL_READRQ, v);
3940 EXPORT_SYMBOL(pcie_set_readrq);
3943 * pcie_get_mps - get PCI Express maximum payload size
3944 * @dev: PCI device to query
3946 * Returns maximum payload size in bytes
3948 int pcie_get_mps(struct pci_dev *dev)
3952 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3954 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3956 EXPORT_SYMBOL(pcie_get_mps);
3959 * pcie_set_mps - set PCI Express maximum payload size
3960 * @dev: PCI device to query
3961 * @mps: maximum payload size in bytes
3962 * valid values are 128, 256, 512, 1024, 2048, 4096
3964 * If possible sets maximum payload size
3966 int pcie_set_mps(struct pci_dev *dev, int mps)
3970 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3974 if (v > dev->pcie_mpss)
3978 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3979 PCI_EXP_DEVCTL_PAYLOAD, v);
3981 EXPORT_SYMBOL(pcie_set_mps);
3984 * pcie_get_minimum_link - determine minimum link settings of a PCI device
3985 * @dev: PCI device to query
3986 * @speed: storage for minimum speed
3987 * @width: storage for minimum width
3989 * This function will walk up the PCI device chain and determine the minimum
3990 * link width and speed of the device.
3992 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
3993 enum pcie_link_width *width)
3997 *speed = PCI_SPEED_UNKNOWN;
3998 *width = PCIE_LNK_WIDTH_UNKNOWN;
4002 enum pci_bus_speed next_speed;
4003 enum pcie_link_width next_width;
4005 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4009 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4010 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4011 PCI_EXP_LNKSTA_NLW_SHIFT;
4013 if (next_speed < *speed)
4014 *speed = next_speed;
4016 if (next_width < *width)
4017 *width = next_width;
4019 dev = dev->bus->self;
4024 EXPORT_SYMBOL(pcie_get_minimum_link);
4027 * pci_select_bars - Make BAR mask from the type of resource
4028 * @dev: the PCI device for which BAR mask is made
4029 * @flags: resource type mask to be selected
4031 * This helper routine makes bar mask from the type of resource.
4033 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4036 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4037 if (pci_resource_flags(dev, i) & flags)
4043 * pci_resource_bar - get position of the BAR associated with a resource
4044 * @dev: the PCI device
4045 * @resno: the resource number
4046 * @type: the BAR type to be filled in
4048 * Returns BAR position in config space, or 0 if the BAR is invalid.
4050 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4054 if (resno < PCI_ROM_RESOURCE) {
4055 *type = pci_bar_unknown;
4056 return PCI_BASE_ADDRESS_0 + 4 * resno;
4057 } else if (resno == PCI_ROM_RESOURCE) {
4058 *type = pci_bar_mem32;
4059 return dev->rom_base_reg;
4060 } else if (resno < PCI_BRIDGE_RESOURCES) {
4061 /* device specific resource */
4062 reg = pci_iov_resource_bar(dev, resno, type);
4067 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4071 /* Some architectures require additional programming to enable VGA */
4072 static arch_set_vga_state_t arch_set_vga_state;
4074 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4076 arch_set_vga_state = func; /* NULL disables */
4079 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4080 unsigned int command_bits, u32 flags)
4082 if (arch_set_vga_state)
4083 return arch_set_vga_state(dev, decode, command_bits,
4089 * pci_set_vga_state - set VGA decode state on device and parents if requested
4090 * @dev: the PCI device
4091 * @decode: true = enable decoding, false = disable decoding
4092 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4093 * @flags: traverse ancestors and change bridges
4094 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4096 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4097 unsigned int command_bits, u32 flags)
4099 struct pci_bus *bus;
4100 struct pci_dev *bridge;
4104 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4106 /* ARCH specific VGA enables */
4107 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4111 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4112 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4114 cmd |= command_bits;
4116 cmd &= ~command_bits;
4117 pci_write_config_word(dev, PCI_COMMAND, cmd);
4120 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4127 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4130 cmd |= PCI_BRIDGE_CTL_VGA;
4132 cmd &= ~PCI_BRIDGE_CTL_VGA;
4133 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4141 bool pci_device_is_present(struct pci_dev *pdev)
4145 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4147 EXPORT_SYMBOL_GPL(pci_device_is_present);
4149 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4150 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4151 static DEFINE_SPINLOCK(resource_alignment_lock);
4154 * pci_specified_resource_alignment - get resource alignment specified by user.
4155 * @dev: the PCI device to get
4157 * RETURNS: Resource alignment if it is specified.
4158 * Zero if it is not specified.
4160 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4162 int seg, bus, slot, func, align_order, count;
4163 resource_size_t align = 0;
4166 spin_lock(&resource_alignment_lock);
4167 p = resource_alignment_param;
4170 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4176 if (sscanf(p, "%x:%x:%x.%x%n",
4177 &seg, &bus, &slot, &func, &count) != 4) {
4179 if (sscanf(p, "%x:%x.%x%n",
4180 &bus, &slot, &func, &count) != 3) {
4181 /* Invalid format */
4182 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4188 if (seg == pci_domain_nr(dev->bus) &&
4189 bus == dev->bus->number &&
4190 slot == PCI_SLOT(dev->devfn) &&
4191 func == PCI_FUNC(dev->devfn)) {
4192 if (align_order == -1) {
4195 align = 1 << align_order;
4200 if (*p != ';' && *p != ',') {
4201 /* End of param or invalid format */
4206 spin_unlock(&resource_alignment_lock);
4211 * This function disables memory decoding and releases memory resources
4212 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4213 * It also rounds up size to specified alignment.
4214 * Later on, the kernel will assign page-aligned memory resource back
4217 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4221 resource_size_t align, size;
4224 /* check if specified PCI is target device to reassign */
4225 align = pci_specified_resource_alignment(dev);
4229 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4230 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4232 "Can't reassign resources to host bridge.\n");
4237 "Disabling memory decoding and releasing memory resources.\n");
4238 pci_read_config_word(dev, PCI_COMMAND, &command);
4239 command &= ~PCI_COMMAND_MEMORY;
4240 pci_write_config_word(dev, PCI_COMMAND, command);
4242 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4243 r = &dev->resource[i];
4244 if (!(r->flags & IORESOURCE_MEM))
4246 size = resource_size(r);
4250 "Rounding up size of resource #%d to %#llx.\n",
4251 i, (unsigned long long)size);
4256 /* Need to disable bridge's resource window,
4257 * to enable the kernel to reassign new resource
4260 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4261 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4262 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4263 r = &dev->resource[i];
4264 if (!(r->flags & IORESOURCE_MEM))
4266 r->end = resource_size(r) - 1;
4269 pci_disable_bridge_window(dev);
4273 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4275 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4276 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4277 spin_lock(&resource_alignment_lock);
4278 strncpy(resource_alignment_param, buf, count);
4279 resource_alignment_param[count] = '\0';
4280 spin_unlock(&resource_alignment_lock);
4284 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4287 spin_lock(&resource_alignment_lock);
4288 count = snprintf(buf, size, "%s", resource_alignment_param);
4289 spin_unlock(&resource_alignment_lock);
4293 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4295 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4298 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4299 const char *buf, size_t count)
4301 return pci_set_resource_alignment_param(buf, count);
4304 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4305 pci_resource_alignment_store);
4307 static int __init pci_resource_alignment_sysfs_init(void)
4309 return bus_create_file(&pci_bus_type,
4310 &bus_attr_resource_alignment);
4313 late_initcall(pci_resource_alignment_sysfs_init);
4315 static void pci_no_domains(void)
4317 #ifdef CONFIG_PCI_DOMAINS
4318 pci_domains_supported = 0;
4323 * pci_ext_cfg_avail - can we access extended PCI config space?
4325 * Returns 1 if we can access PCI extended config space (offsets
4326 * greater than 0xff). This is the default implementation. Architecture
4327 * implementations can override this.
4329 int __weak pci_ext_cfg_avail(void)
4334 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4337 EXPORT_SYMBOL(pci_fixup_cardbus);
4339 static int __init pci_setup(char *str)
4342 char *k = strchr(str, ',');
4345 if (*str && (str = pcibios_setup(str)) && *str) {
4346 if (!strcmp(str, "nomsi")) {
4348 } else if (!strcmp(str, "noaer")) {
4350 } else if (!strncmp(str, "realloc=", 8)) {
4351 pci_realloc_get_opt(str + 8);
4352 } else if (!strncmp(str, "realloc", 7)) {
4353 pci_realloc_get_opt("on");
4354 } else if (!strcmp(str, "nodomains")) {
4356 } else if (!strncmp(str, "noari", 5)) {
4357 pcie_ari_disabled = true;
4358 } else if (!strncmp(str, "cbiosize=", 9)) {
4359 pci_cardbus_io_size = memparse(str + 9, &str);
4360 } else if (!strncmp(str, "cbmemsize=", 10)) {
4361 pci_cardbus_mem_size = memparse(str + 10, &str);
4362 } else if (!strncmp(str, "resource_alignment=", 19)) {
4363 pci_set_resource_alignment_param(str + 19,
4365 } else if (!strncmp(str, "ecrc=", 5)) {
4366 pcie_ecrc_get_policy(str + 5);
4367 } else if (!strncmp(str, "hpiosize=", 9)) {
4368 pci_hotplug_io_size = memparse(str + 9, &str);
4369 } else if (!strncmp(str, "hpmemsize=", 10)) {
4370 pci_hotplug_mem_size = memparse(str + 10, &str);
4371 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4372 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4373 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4374 pcie_bus_config = PCIE_BUS_SAFE;
4375 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4376 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4377 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4378 pcie_bus_config = PCIE_BUS_PEER2PEER;
4379 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4380 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4382 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4390 early_param("pci", pci_setup);
4392 EXPORT_SYMBOL(pci_reenable_device);
4393 EXPORT_SYMBOL(pci_enable_device_io);
4394 EXPORT_SYMBOL(pci_enable_device_mem);
4395 EXPORT_SYMBOL(pci_enable_device);
4396 EXPORT_SYMBOL(pcim_enable_device);
4397 EXPORT_SYMBOL(pcim_pin_device);
4398 EXPORT_SYMBOL(pci_disable_device);
4399 EXPORT_SYMBOL(pci_find_capability);
4400 EXPORT_SYMBOL(pci_bus_find_capability);
4401 EXPORT_SYMBOL(pci_release_regions);
4402 EXPORT_SYMBOL(pci_request_regions);
4403 EXPORT_SYMBOL(pci_request_regions_exclusive);
4404 EXPORT_SYMBOL(pci_release_region);
4405 EXPORT_SYMBOL(pci_request_region);
4406 EXPORT_SYMBOL(pci_request_region_exclusive);
4407 EXPORT_SYMBOL(pci_release_selected_regions);
4408 EXPORT_SYMBOL(pci_request_selected_regions);
4409 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4410 EXPORT_SYMBOL(pci_set_master);
4411 EXPORT_SYMBOL(pci_clear_master);
4412 EXPORT_SYMBOL(pci_set_mwi);
4413 EXPORT_SYMBOL(pci_try_set_mwi);
4414 EXPORT_SYMBOL(pci_clear_mwi);
4415 EXPORT_SYMBOL_GPL(pci_intx);
4416 EXPORT_SYMBOL(pci_assign_resource);
4417 EXPORT_SYMBOL(pci_find_parent_resource);
4418 EXPORT_SYMBOL(pci_select_bars);
4420 EXPORT_SYMBOL(pci_set_power_state);
4421 EXPORT_SYMBOL(pci_save_state);
4422 EXPORT_SYMBOL(pci_restore_state);
4423 EXPORT_SYMBOL(pci_pme_capable);
4424 EXPORT_SYMBOL(pci_pme_active);
4425 EXPORT_SYMBOL(pci_wake_from_d3);
4426 EXPORT_SYMBOL(pci_prepare_to_sleep);
4427 EXPORT_SYMBOL(pci_back_from_sleep);
4428 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);