2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names);
35 int isa_dma_bridge_buggy;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy);
39 EXPORT_SYMBOL(pci_pci_problems);
41 unsigned int pci_pm_d3_delay;
43 static void pci_pme_list_scan(struct work_struct *work);
45 static LIST_HEAD(pci_pme_list);
46 static DEFINE_MUTEX(pci_pme_list_mutex);
47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
49 struct pci_pme_device {
50 struct list_head list;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev *dev)
58 unsigned int delay = dev->d3_delay;
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported = 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 u8 pci_cache_line_size;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency = 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
112 unsigned char max, n;
114 max = bus->busn_res.end;
115 list_for_each_entry(tmp, &bus->children, node) {
116 n = pci_bus_max_busnr(tmp);
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
158 pos += PCI_CAP_LIST_NEXT;
163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
166 int ttl = PCI_FIND_CAP_TTL;
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability);
178 static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev *dev, int cap)
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
229 EXPORT_SYMBOL(pci_find_capability);
232 * pci_bus_find_capability - query for devices' capabilities
233 * @bus: the PCI bus to query
234 * @devfn: PCI device to query
235 * @cap: capability code
237 * Like pci_find_capability() but works for pci devices that do not have a
238 * pci_dev structure set up yet.
240 * Returns the address of the requested capability structure within the
241 * device's PCI configuration space or 0 in case the device does not
244 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
249 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
251 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
253 pos = __pci_find_next_cap(bus, devfn, pos, cap);
257 EXPORT_SYMBOL(pci_bus_find_capability);
260 * pci_find_next_ext_capability - Find an extended capability
261 * @dev: PCI device to query
262 * @start: address at which to start looking (0 to start at beginning of list)
263 * @cap: capability code
265 * Returns the address of the next matching extended capability structure
266 * within the device's PCI configuration space or 0 if the device does
267 * not support it. Some capabilities can occur several times, e.g., the
268 * vendor-specific capability, and this provides a way to find them all.
270 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
274 int pos = PCI_CFG_SPACE_SIZE;
276 /* minimum 8 bytes per capability */
277 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
279 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
285 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
289 * If we have no capabilities, this is indicated by cap ID,
290 * cap version and next pointer all being 0.
296 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
299 pos = PCI_EXT_CAP_NEXT(header);
300 if (pos < PCI_CFG_SPACE_SIZE)
303 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
309 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
312 * pci_find_ext_capability - Find an extended capability
313 * @dev: PCI device to query
314 * @cap: capability code
316 * Returns the address of the requested extended capability structure
317 * within the device's PCI configuration space or 0 if the device does
318 * not support it. Possible values for @cap:
320 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
321 * %PCI_EXT_CAP_ID_VC Virtual Channel
322 * %PCI_EXT_CAP_ID_DSN Device Serial Number
323 * %PCI_EXT_CAP_ID_PWR Power Budgeting
325 int pci_find_ext_capability(struct pci_dev *dev, int cap)
327 return pci_find_next_ext_capability(dev, 0, cap);
329 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
331 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
333 int rc, ttl = PCI_FIND_CAP_TTL;
336 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
337 mask = HT_3BIT_CAP_MASK;
339 mask = HT_5BIT_CAP_MASK;
341 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
342 PCI_CAP_ID_HT, &ttl);
344 rc = pci_read_config_byte(dev, pos + 3, &cap);
345 if (rc != PCIBIOS_SUCCESSFUL)
348 if ((cap & mask) == ht_cap)
351 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
352 pos + PCI_CAP_LIST_NEXT,
353 PCI_CAP_ID_HT, &ttl);
359 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
360 * @dev: PCI device to query
361 * @pos: Position from which to continue searching
362 * @ht_cap: Hypertransport capability code
364 * To be used in conjunction with pci_find_ht_capability() to search for
365 * all capabilities matching @ht_cap. @pos should always be a value returned
366 * from pci_find_ht_capability().
368 * NB. To be 100% safe against broken PCI devices, the caller should take
369 * steps to avoid an infinite loop.
371 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
373 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
375 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
378 * pci_find_ht_capability - query a device's Hypertransport capabilities
379 * @dev: PCI device to query
380 * @ht_cap: Hypertransport capability code
382 * Tell if a device supports a given Hypertransport capability.
383 * Returns an address within the device's PCI configuration space
384 * or 0 in case the device does not support the request capability.
385 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
386 * which has a Hypertransport capability matching @ht_cap.
388 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
392 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
394 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
398 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
401 * pci_find_parent_resource - return resource region of parent bus of given region
402 * @dev: PCI device structure contains resources to be searched
403 * @res: child resource record for which parent is sought
405 * For given resource region of given device, return the resource
406 * region of parent bus the given region is contained in.
408 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
409 struct resource *res)
411 const struct pci_bus *bus = dev->bus;
415 pci_bus_for_each_resource(bus, r, i) {
418 if (res->start && resource_contains(r, res)) {
421 * If the window is prefetchable but the BAR is
422 * not, the allocator made a mistake.
424 if (r->flags & IORESOURCE_PREFETCH &&
425 !(res->flags & IORESOURCE_PREFETCH))
429 * If we're below a transparent bridge, there may
430 * be both a positively-decoded aperture and a
431 * subtractively-decoded region that contain the BAR.
432 * We want the positively-decoded one, so this depends
433 * on pci_bus_for_each_resource() giving us those
441 EXPORT_SYMBOL(pci_find_parent_resource);
444 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
445 * @dev: the PCI device to operate on
446 * @pos: config space offset of status word
447 * @mask: mask of bit(s) to care about in status word
449 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
451 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
455 /* Wait for Transaction Pending bit clean */
456 for (i = 0; i < 4; i++) {
459 msleep((1 << (i - 1)) * 100);
461 pci_read_config_word(dev, pos, &status);
462 if (!(status & mask))
470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
471 * @dev: PCI device to have its BARs restored
473 * Restore the BAR values for a given device, so as to make it
474 * accessible by its driver.
476 static void pci_restore_bars(struct pci_dev *dev)
480 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
481 pci_update_resource(dev, i);
484 static struct pci_platform_pm_ops *pci_platform_pm;
486 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
488 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
491 pci_platform_pm = ops;
495 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
497 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
500 static inline int platform_pci_set_power_state(struct pci_dev *dev,
503 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
506 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
508 return pci_platform_pm ?
509 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
512 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
514 return pci_platform_pm ?
515 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
518 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
520 return pci_platform_pm ?
521 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
525 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
527 * @dev: PCI device to handle.
528 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
531 * -EINVAL if the requested state is invalid.
532 * -EIO if device does not support PCI PM or its PM capabilities register has a
533 * wrong version, or device doesn't support the requested state.
534 * 0 if device already is in the requested state.
535 * 0 if device's power state has been successfully changed.
537 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
540 bool need_restore = false;
542 /* Check if we're already there */
543 if (dev->current_state == state)
549 if (state < PCI_D0 || state > PCI_D3hot)
552 /* Validate current state:
553 * Can enter D0 from any state, but if we can only go deeper
554 * to sleep if we're already in a low power state
556 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
557 && dev->current_state > state) {
558 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
559 dev->current_state, state);
563 /* check if this device supports the desired state */
564 if ((state == PCI_D1 && !dev->d1_support)
565 || (state == PCI_D2 && !dev->d2_support))
568 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
570 /* If we're (effectively) in D3, force entire word to 0.
571 * This doesn't affect PME_Status, disables PME_En, and
572 * sets PowerState to 0.
574 switch (dev->current_state) {
578 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
583 case PCI_UNKNOWN: /* Boot-up */
584 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
585 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
587 /* Fall-through: force to D0 */
593 /* enter specified state */
594 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
596 /* Mandatory power management transition delays */
597 /* see PCI PM 1.1 5.6.1 table 18 */
598 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
599 pci_dev_d3_sleep(dev);
600 else if (state == PCI_D2 || dev->current_state == PCI_D2)
601 udelay(PCI_PM_D2_DELAY);
603 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
604 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
605 if (dev->current_state != state && printk_ratelimit())
606 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
610 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
611 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
612 * from D3hot to D0 _may_ perform an internal reset, thereby
613 * going to "D0 Uninitialized" rather than "D0 Initialized".
614 * For example, at least some versions of the 3c905B and the
615 * 3c556B exhibit this behaviour.
617 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
618 * devices in a D3hot state at boot. Consequently, we need to
619 * restore at least the BARs so that the device will be
620 * accessible to its driver.
623 pci_restore_bars(dev);
626 pcie_aspm_pm_state_change(dev->bus->self);
632 * pci_update_current_state - Read PCI power state of given device from its
633 * PCI PM registers and cache it
634 * @dev: PCI device to handle.
635 * @state: State to cache in case the device doesn't have the PM capability
637 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
643 * Configuration space is not accessible for device in
644 * D3cold, so just keep or set D3cold for safety
646 if (dev->current_state == PCI_D3cold)
648 if (state == PCI_D3cold) {
649 dev->current_state = PCI_D3cold;
652 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
653 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
655 dev->current_state = state;
660 * pci_power_up - Put the given device into D0 forcibly
661 * @dev: PCI device to power up
663 void pci_power_up(struct pci_dev *dev)
665 if (platform_pci_power_manageable(dev))
666 platform_pci_set_power_state(dev, PCI_D0);
668 pci_raw_set_power_state(dev, PCI_D0);
669 pci_update_current_state(dev, PCI_D0);
673 * pci_platform_power_transition - Use platform to change device power state
674 * @dev: PCI device to handle.
675 * @state: State to put the device into.
677 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
681 if (platform_pci_power_manageable(dev)) {
682 error = platform_pci_set_power_state(dev, state);
684 pci_update_current_state(dev, state);
688 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
689 dev->current_state = PCI_D0;
695 * pci_wakeup - Wake up a PCI device
696 * @pci_dev: Device to handle.
697 * @ign: ignored parameter
699 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
701 pci_wakeup_event(pci_dev);
702 pm_request_resume(&pci_dev->dev);
707 * pci_wakeup_bus - Walk given bus and wake up devices on it
708 * @bus: Top bus of the subtree to walk.
710 static void pci_wakeup_bus(struct pci_bus *bus)
713 pci_walk_bus(bus, pci_wakeup, NULL);
717 * __pci_start_power_transition - Start power transition of a PCI device
718 * @dev: PCI device to handle.
719 * @state: State to put the device into.
721 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
723 if (state == PCI_D0) {
724 pci_platform_power_transition(dev, PCI_D0);
726 * Mandatory power management transition delays, see
727 * PCI Express Base Specification Revision 2.0 Section
728 * 6.6.1: Conventional Reset. Do not delay for
729 * devices powered on/off by corresponding bridge,
730 * because have already delayed for the bridge.
732 if (dev->runtime_d3cold) {
733 msleep(dev->d3cold_delay);
735 * When powering on a bridge from D3cold, the
736 * whole hierarchy may be powered on into
737 * D0uninitialized state, resume them to give
738 * them a chance to suspend again
740 pci_wakeup_bus(dev->subordinate);
746 * __pci_dev_set_current_state - Set current state of a PCI device
747 * @dev: Device to handle
748 * @data: pointer to state to be set
750 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
752 pci_power_t state = *(pci_power_t *)data;
754 dev->current_state = state;
759 * __pci_bus_set_current_state - Walk given bus and set current state of devices
760 * @bus: Top bus of the subtree to walk.
761 * @state: state to be set
763 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
766 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
770 * __pci_complete_power_transition - Complete power transition of a PCI device
771 * @dev: PCI device to handle.
772 * @state: State to put the device into.
774 * This function should not be called directly by device drivers.
776 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
782 ret = pci_platform_power_transition(dev, state);
783 /* Power off the bridge may power off the whole hierarchy */
784 if (!ret && state == PCI_D3cold)
785 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
788 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
791 * pci_set_power_state - Set the power state of a PCI device
792 * @dev: PCI device to handle.
793 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
795 * Transition a device to a new power state, using the platform firmware and/or
796 * the device's PCI PM registers.
799 * -EINVAL if the requested state is invalid.
800 * -EIO if device does not support PCI PM or its PM capabilities register has a
801 * wrong version, or device doesn't support the requested state.
802 * 0 if device already is in the requested state.
803 * 0 if device's power state has been successfully changed.
805 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
809 /* bound the state we're entering */
810 if (state > PCI_D3cold)
812 else if (state < PCI_D0)
814 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
816 * If the device or the parent bridge do not support PCI PM,
817 * ignore the request if we're doing anything other than putting
818 * it into D0 (which would only happen on boot).
822 /* Check if we're already there */
823 if (dev->current_state == state)
826 __pci_start_power_transition(dev, state);
828 /* This device is quirked not to be put into D3, so
829 don't put it in D3 */
830 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
834 * To put device in D3cold, we put device into D3hot in native
835 * way, then put device into D3cold with platform ops
837 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
840 if (!__pci_complete_power_transition(dev, state))
845 EXPORT_SYMBOL(pci_set_power_state);
848 * pci_choose_state - Choose the power state of a PCI device
849 * @dev: PCI device to be suspended
850 * @state: target sleep state for the whole system. This is the value
851 * that is passed to suspend() function.
853 * Returns PCI power state suitable for given device and given system
857 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
864 ret = platform_pci_choose_state(dev);
865 if (ret != PCI_POWER_ERROR)
868 switch (state.event) {
871 case PM_EVENT_FREEZE:
872 case PM_EVENT_PRETHAW:
873 /* REVISIT both freeze and pre-thaw "should" use D0 */
874 case PM_EVENT_SUSPEND:
875 case PM_EVENT_HIBERNATE:
878 dev_info(&dev->dev, "unrecognized suspend event %d\n",
884 EXPORT_SYMBOL(pci_choose_state);
886 #define PCI_EXP_SAVE_REGS 7
888 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
889 u16 cap, bool extended)
891 struct pci_cap_saved_state *tmp;
893 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
894 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
900 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
902 return _pci_find_saved_cap(dev, cap, false);
905 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
907 return _pci_find_saved_cap(dev, cap, true);
910 static int pci_save_pcie_state(struct pci_dev *dev)
913 struct pci_cap_saved_state *save_state;
916 if (!pci_is_pcie(dev))
919 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
921 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
925 cap = (u16 *)&save_state->cap.data[0];
926 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
927 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
928 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
929 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
930 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
931 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
932 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
937 static void pci_restore_pcie_state(struct pci_dev *dev)
940 struct pci_cap_saved_state *save_state;
943 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
947 cap = (u16 *)&save_state->cap.data[0];
948 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
949 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
950 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
951 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
952 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
953 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
954 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
958 static int pci_save_pcix_state(struct pci_dev *dev)
961 struct pci_cap_saved_state *save_state;
963 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
967 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
969 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
973 pci_read_config_word(dev, pos + PCI_X_CMD,
974 (u16 *)save_state->cap.data);
979 static void pci_restore_pcix_state(struct pci_dev *dev)
982 struct pci_cap_saved_state *save_state;
985 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
986 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
987 if (!save_state || pos <= 0)
989 cap = (u16 *)&save_state->cap.data[0];
991 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
996 * pci_save_state - save the PCI configuration space of a device before suspending
997 * @dev: - PCI device that we're dealing with
999 int pci_save_state(struct pci_dev *dev)
1002 /* XXX: 100% dword access ok here? */
1003 for (i = 0; i < 16; i++)
1004 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1005 dev->state_saved = true;
1007 i = pci_save_pcie_state(dev);
1011 i = pci_save_pcix_state(dev);
1015 return pci_save_vc_state(dev);
1017 EXPORT_SYMBOL(pci_save_state);
1019 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1020 u32 saved_val, int retry)
1024 pci_read_config_dword(pdev, offset, &val);
1025 if (val == saved_val)
1029 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1030 offset, val, saved_val);
1031 pci_write_config_dword(pdev, offset, saved_val);
1035 pci_read_config_dword(pdev, offset, &val);
1036 if (val == saved_val)
1043 static void pci_restore_config_space_range(struct pci_dev *pdev,
1044 int start, int end, int retry)
1048 for (index = end; index >= start; index--)
1049 pci_restore_config_dword(pdev, 4 * index,
1050 pdev->saved_config_space[index],
1054 static void pci_restore_config_space(struct pci_dev *pdev)
1056 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1057 pci_restore_config_space_range(pdev, 10, 15, 0);
1058 /* Restore BARs before the command register. */
1059 pci_restore_config_space_range(pdev, 4, 9, 10);
1060 pci_restore_config_space_range(pdev, 0, 3, 0);
1062 pci_restore_config_space_range(pdev, 0, 15, 0);
1067 * pci_restore_state - Restore the saved state of a PCI device
1068 * @dev: - PCI device that we're dealing with
1070 void pci_restore_state(struct pci_dev *dev)
1072 if (!dev->state_saved)
1075 /* PCI Express register must be restored first */
1076 pci_restore_pcie_state(dev);
1077 pci_restore_ats_state(dev);
1078 pci_restore_vc_state(dev);
1080 pci_restore_config_space(dev);
1082 pci_restore_pcix_state(dev);
1083 pci_restore_msi_state(dev);
1084 pci_restore_iov_state(dev);
1086 dev->state_saved = false;
1088 EXPORT_SYMBOL(pci_restore_state);
1090 struct pci_saved_state {
1091 u32 config_space[16];
1092 struct pci_cap_saved_data cap[0];
1096 * pci_store_saved_state - Allocate and return an opaque struct containing
1097 * the device saved state.
1098 * @dev: PCI device that we're dealing with
1100 * Return NULL if no state or error.
1102 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1104 struct pci_saved_state *state;
1105 struct pci_cap_saved_state *tmp;
1106 struct pci_cap_saved_data *cap;
1109 if (!dev->state_saved)
1112 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1114 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1115 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1117 state = kzalloc(size, GFP_KERNEL);
1121 memcpy(state->config_space, dev->saved_config_space,
1122 sizeof(state->config_space));
1125 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1126 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1127 memcpy(cap, &tmp->cap, len);
1128 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1130 /* Empty cap_save terminates list */
1134 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1137 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1138 * @dev: PCI device that we're dealing with
1139 * @state: Saved state returned from pci_store_saved_state()
1141 static int pci_load_saved_state(struct pci_dev *dev,
1142 struct pci_saved_state *state)
1144 struct pci_cap_saved_data *cap;
1146 dev->state_saved = false;
1151 memcpy(dev->saved_config_space, state->config_space,
1152 sizeof(state->config_space));
1156 struct pci_cap_saved_state *tmp;
1158 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1159 if (!tmp || tmp->cap.size != cap->size)
1162 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1163 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1164 sizeof(struct pci_cap_saved_data) + cap->size);
1167 dev->state_saved = true;
1172 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1173 * and free the memory allocated for it.
1174 * @dev: PCI device that we're dealing with
1175 * @state: Pointer to saved state returned from pci_store_saved_state()
1177 int pci_load_and_free_saved_state(struct pci_dev *dev,
1178 struct pci_saved_state **state)
1180 int ret = pci_load_saved_state(dev, *state);
1185 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1187 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1189 return pci_enable_resources(dev, bars);
1192 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1195 struct pci_dev *bridge;
1199 err = pci_set_power_state(dev, PCI_D0);
1200 if (err < 0 && err != -EIO)
1203 bridge = pci_upstream_bridge(dev);
1205 pcie_aspm_powersave_config_link(bridge);
1207 err = pcibios_enable_device(dev, bars);
1210 pci_fixup_device(pci_fixup_enable, dev);
1212 if (dev->msi_enabled || dev->msix_enabled)
1215 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1217 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1218 if (cmd & PCI_COMMAND_INTX_DISABLE)
1219 pci_write_config_word(dev, PCI_COMMAND,
1220 cmd & ~PCI_COMMAND_INTX_DISABLE);
1227 * pci_reenable_device - Resume abandoned device
1228 * @dev: PCI device to be resumed
1230 * Note this function is a backend of pci_default_resume and is not supposed
1231 * to be called by normal code, write proper resume handler and use it instead.
1233 int pci_reenable_device(struct pci_dev *dev)
1235 if (pci_is_enabled(dev))
1236 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1239 EXPORT_SYMBOL(pci_reenable_device);
1241 static void pci_enable_bridge(struct pci_dev *dev)
1243 struct pci_dev *bridge;
1246 bridge = pci_upstream_bridge(dev);
1248 pci_enable_bridge(bridge);
1250 if (pci_is_enabled(dev)) {
1251 if (!dev->is_busmaster)
1252 pci_set_master(dev);
1256 retval = pci_enable_device(dev);
1258 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1260 pci_set_master(dev);
1263 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1265 struct pci_dev *bridge;
1270 * Power state could be unknown at this point, either due to a fresh
1271 * boot or a device removal call. So get the current power state
1272 * so that things like MSI message writing will behave as expected
1273 * (e.g. if the device really is in D0 at enable time).
1277 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1278 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1281 if (atomic_inc_return(&dev->enable_cnt) > 1)
1282 return 0; /* already enabled */
1284 bridge = pci_upstream_bridge(dev);
1286 pci_enable_bridge(bridge);
1288 /* only skip sriov related */
1289 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1290 if (dev->resource[i].flags & flags)
1292 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1293 if (dev->resource[i].flags & flags)
1296 err = do_pci_enable_device(dev, bars);
1298 atomic_dec(&dev->enable_cnt);
1303 * pci_enable_device_io - Initialize a device for use with IO space
1304 * @dev: PCI device to be initialized
1306 * Initialize device before it's used by a driver. Ask low-level code
1307 * to enable I/O resources. Wake up the device if it was suspended.
1308 * Beware, this function can fail.
1310 int pci_enable_device_io(struct pci_dev *dev)
1312 return pci_enable_device_flags(dev, IORESOURCE_IO);
1314 EXPORT_SYMBOL(pci_enable_device_io);
1317 * pci_enable_device_mem - Initialize a device for use with Memory space
1318 * @dev: PCI device to be initialized
1320 * Initialize device before it's used by a driver. Ask low-level code
1321 * to enable Memory resources. Wake up the device if it was suspended.
1322 * Beware, this function can fail.
1324 int pci_enable_device_mem(struct pci_dev *dev)
1326 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1328 EXPORT_SYMBOL(pci_enable_device_mem);
1331 * pci_enable_device - Initialize device before it's used by a driver.
1332 * @dev: PCI device to be initialized
1334 * Initialize device before it's used by a driver. Ask low-level code
1335 * to enable I/O and memory. Wake up the device if it was suspended.
1336 * Beware, this function can fail.
1338 * Note we don't actually enable the device many times if we call
1339 * this function repeatedly (we just increment the count).
1341 int pci_enable_device(struct pci_dev *dev)
1343 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1345 EXPORT_SYMBOL(pci_enable_device);
1348 * Managed PCI resources. This manages device on/off, intx/msi/msix
1349 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1350 * there's no need to track it separately. pci_devres is initialized
1351 * when a device is enabled using managed PCI device enable interface.
1354 unsigned int enabled:1;
1355 unsigned int pinned:1;
1356 unsigned int orig_intx:1;
1357 unsigned int restore_intx:1;
1361 static void pcim_release(struct device *gendev, void *res)
1363 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1364 struct pci_devres *this = res;
1367 if (dev->msi_enabled)
1368 pci_disable_msi(dev);
1369 if (dev->msix_enabled)
1370 pci_disable_msix(dev);
1372 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1373 if (this->region_mask & (1 << i))
1374 pci_release_region(dev, i);
1376 if (this->restore_intx)
1377 pci_intx(dev, this->orig_intx);
1379 if (this->enabled && !this->pinned)
1380 pci_disable_device(dev);
1383 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1385 struct pci_devres *dr, *new_dr;
1387 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1391 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1394 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1397 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1399 if (pci_is_managed(pdev))
1400 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1405 * pcim_enable_device - Managed pci_enable_device()
1406 * @pdev: PCI device to be initialized
1408 * Managed pci_enable_device().
1410 int pcim_enable_device(struct pci_dev *pdev)
1412 struct pci_devres *dr;
1415 dr = get_pci_dr(pdev);
1421 rc = pci_enable_device(pdev);
1423 pdev->is_managed = 1;
1428 EXPORT_SYMBOL(pcim_enable_device);
1431 * pcim_pin_device - Pin managed PCI device
1432 * @pdev: PCI device to pin
1434 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1435 * driver detach. @pdev must have been enabled with
1436 * pcim_enable_device().
1438 void pcim_pin_device(struct pci_dev *pdev)
1440 struct pci_devres *dr;
1442 dr = find_pci_dr(pdev);
1443 WARN_ON(!dr || !dr->enabled);
1447 EXPORT_SYMBOL(pcim_pin_device);
1450 * pcibios_add_device - provide arch specific hooks when adding device dev
1451 * @dev: the PCI device being added
1453 * Permits the platform to provide architecture specific functionality when
1454 * devices are added. This is the default implementation. Architecture
1455 * implementations can override this.
1457 int __weak pcibios_add_device(struct pci_dev *dev)
1463 * pcibios_release_device - provide arch specific hooks when releasing device dev
1464 * @dev: the PCI device being released
1466 * Permits the platform to provide architecture specific functionality when
1467 * devices are released. This is the default implementation. Architecture
1468 * implementations can override this.
1470 void __weak pcibios_release_device(struct pci_dev *dev) {}
1473 * pcibios_disable_device - disable arch specific PCI resources for device dev
1474 * @dev: the PCI device to disable
1476 * Disables architecture specific PCI resources for the device. This
1477 * is the default implementation. Architecture implementations can
1480 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1483 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1484 * @irq: ISA IRQ to penalize
1485 * @active: IRQ active or not
1487 * Permits the platform to provide architecture-specific functionality when
1488 * penalizing ISA IRQs. This is the default implementation. Architecture
1489 * implementations can override this.
1491 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1493 static void do_pci_disable_device(struct pci_dev *dev)
1497 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1498 if (pci_command & PCI_COMMAND_MASTER) {
1499 pci_command &= ~PCI_COMMAND_MASTER;
1500 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1503 pcibios_disable_device(dev);
1507 * pci_disable_enabled_device - Disable device without updating enable_cnt
1508 * @dev: PCI device to disable
1510 * NOTE: This function is a backend of PCI power management routines and is
1511 * not supposed to be called drivers.
1513 void pci_disable_enabled_device(struct pci_dev *dev)
1515 if (pci_is_enabled(dev))
1516 do_pci_disable_device(dev);
1520 * pci_disable_device - Disable PCI device after use
1521 * @dev: PCI device to be disabled
1523 * Signal to the system that the PCI device is not in use by the system
1524 * anymore. This only involves disabling PCI bus-mastering, if active.
1526 * Note we don't actually disable the device until all callers of
1527 * pci_enable_device() have called pci_disable_device().
1529 void pci_disable_device(struct pci_dev *dev)
1531 struct pci_devres *dr;
1533 dr = find_pci_dr(dev);
1537 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1538 "disabling already-disabled device");
1540 if (atomic_dec_return(&dev->enable_cnt) != 0)
1543 do_pci_disable_device(dev);
1545 dev->is_busmaster = 0;
1547 EXPORT_SYMBOL(pci_disable_device);
1550 * pcibios_set_pcie_reset_state - set reset state for device dev
1551 * @dev: the PCIe device reset
1552 * @state: Reset state to enter into
1555 * Sets the PCIe reset state for the device. This is the default
1556 * implementation. Architecture implementations can override this.
1558 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1559 enum pcie_reset_state state)
1565 * pci_set_pcie_reset_state - set reset state for device dev
1566 * @dev: the PCIe device reset
1567 * @state: Reset state to enter into
1570 * Sets the PCI reset state for the device.
1572 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1574 return pcibios_set_pcie_reset_state(dev, state);
1576 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1579 * pci_check_pme_status - Check if given device has generated PME.
1580 * @dev: Device to check.
1582 * Check the PME status of the device and if set, clear it and clear PME enable
1583 * (if set). Return 'true' if PME status and PME enable were both set or
1584 * 'false' otherwise.
1586 bool pci_check_pme_status(struct pci_dev *dev)
1595 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1596 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1597 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1600 /* Clear PME status. */
1601 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1602 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1603 /* Disable PME to avoid interrupt flood. */
1604 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1608 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1614 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1615 * @dev: Device to handle.
1616 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1618 * Check if @dev has generated PME and queue a resume request for it in that
1621 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1623 if (pme_poll_reset && dev->pme_poll)
1624 dev->pme_poll = false;
1626 if (pci_check_pme_status(dev)) {
1627 pci_wakeup_event(dev);
1628 pm_request_resume(&dev->dev);
1634 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1635 * @bus: Top bus of the subtree to walk.
1637 void pci_pme_wakeup_bus(struct pci_bus *bus)
1640 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1645 * pci_pme_capable - check the capability of PCI device to generate PME#
1646 * @dev: PCI device to handle.
1647 * @state: PCI state from which device will issue PME#.
1649 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1654 return !!(dev->pme_support & (1 << state));
1656 EXPORT_SYMBOL(pci_pme_capable);
1658 static void pci_pme_list_scan(struct work_struct *work)
1660 struct pci_pme_device *pme_dev, *n;
1662 mutex_lock(&pci_pme_list_mutex);
1663 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1664 if (pme_dev->dev->pme_poll) {
1665 struct pci_dev *bridge;
1667 bridge = pme_dev->dev->bus->self;
1669 * If bridge is in low power state, the
1670 * configuration space of subordinate devices
1671 * may be not accessible
1673 if (bridge && bridge->current_state != PCI_D0)
1675 pci_pme_wakeup(pme_dev->dev, NULL);
1677 list_del(&pme_dev->list);
1681 if (!list_empty(&pci_pme_list))
1682 schedule_delayed_work(&pci_pme_work,
1683 msecs_to_jiffies(PME_TIMEOUT));
1684 mutex_unlock(&pci_pme_list_mutex);
1688 * pci_pme_active - enable or disable PCI device's PME# function
1689 * @dev: PCI device to handle.
1690 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1692 * The caller must verify that the device is capable of generating PME# before
1693 * calling this function with @enable equal to 'true'.
1695 void pci_pme_active(struct pci_dev *dev, bool enable)
1699 if (!dev->pme_support)
1702 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1703 /* Clear PME_Status by writing 1 to it and enable PME# */
1704 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1706 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1708 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1711 * PCI (as opposed to PCIe) PME requires that the device have
1712 * its PME# line hooked up correctly. Not all hardware vendors
1713 * do this, so the PME never gets delivered and the device
1714 * remains asleep. The easiest way around this is to
1715 * periodically walk the list of suspended devices and check
1716 * whether any have their PME flag set. The assumption is that
1717 * we'll wake up often enough anyway that this won't be a huge
1718 * hit, and the power savings from the devices will still be a
1721 * Although PCIe uses in-band PME message instead of PME# line
1722 * to report PME, PME does not work for some PCIe devices in
1723 * reality. For example, there are devices that set their PME
1724 * status bits, but don't really bother to send a PME message;
1725 * there are PCI Express Root Ports that don't bother to
1726 * trigger interrupts when they receive PME messages from the
1727 * devices below. So PME poll is used for PCIe devices too.
1730 if (dev->pme_poll) {
1731 struct pci_pme_device *pme_dev;
1733 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1736 dev_warn(&dev->dev, "can't enable PME#\n");
1740 mutex_lock(&pci_pme_list_mutex);
1741 list_add(&pme_dev->list, &pci_pme_list);
1742 if (list_is_singular(&pci_pme_list))
1743 schedule_delayed_work(&pci_pme_work,
1744 msecs_to_jiffies(PME_TIMEOUT));
1745 mutex_unlock(&pci_pme_list_mutex);
1747 mutex_lock(&pci_pme_list_mutex);
1748 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1749 if (pme_dev->dev == dev) {
1750 list_del(&pme_dev->list);
1755 mutex_unlock(&pci_pme_list_mutex);
1759 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1761 EXPORT_SYMBOL(pci_pme_active);
1764 * __pci_enable_wake - enable PCI device as wakeup event source
1765 * @dev: PCI device affected
1766 * @state: PCI state from which device will issue wakeup events
1767 * @runtime: True if the events are to be generated at run time
1768 * @enable: True to enable event generation; false to disable
1770 * This enables the device as a wakeup event source, or disables it.
1771 * When such events involves platform-specific hooks, those hooks are
1772 * called automatically by this routine.
1774 * Devices with legacy power management (no standard PCI PM capabilities)
1775 * always require such platform hooks.
1778 * 0 is returned on success
1779 * -EINVAL is returned if device is not supposed to wake up the system
1780 * Error code depending on the platform is returned if both the platform and
1781 * the native mechanism fail to enable the generation of wake-up events
1783 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1784 bool runtime, bool enable)
1788 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1791 /* Don't do the same thing twice in a row for one device. */
1792 if (!!enable == !!dev->wakeup_prepared)
1796 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1797 * Anderson we should be doing PME# wake enable followed by ACPI wake
1798 * enable. To disable wake-up we call the platform first, for symmetry.
1804 if (pci_pme_capable(dev, state))
1805 pci_pme_active(dev, true);
1808 error = runtime ? platform_pci_run_wake(dev, true) :
1809 platform_pci_sleep_wake(dev, true);
1813 dev->wakeup_prepared = true;
1816 platform_pci_run_wake(dev, false);
1818 platform_pci_sleep_wake(dev, false);
1819 pci_pme_active(dev, false);
1820 dev->wakeup_prepared = false;
1825 EXPORT_SYMBOL(__pci_enable_wake);
1828 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1829 * @dev: PCI device to prepare
1830 * @enable: True to enable wake-up event generation; false to disable
1832 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1833 * and this function allows them to set that up cleanly - pci_enable_wake()
1834 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1835 * ordering constraints.
1837 * This function only returns error code if the device is not capable of
1838 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1839 * enable wake-up power for it.
1841 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1843 return pci_pme_capable(dev, PCI_D3cold) ?
1844 pci_enable_wake(dev, PCI_D3cold, enable) :
1845 pci_enable_wake(dev, PCI_D3hot, enable);
1847 EXPORT_SYMBOL(pci_wake_from_d3);
1850 * pci_target_state - find an appropriate low power state for a given PCI dev
1853 * Use underlying platform code to find a supported low power state for @dev.
1854 * If the platform can't manage @dev, return the deepest state from which it
1855 * can generate wake events, based on any available PME info.
1857 static pci_power_t pci_target_state(struct pci_dev *dev)
1859 pci_power_t target_state = PCI_D3hot;
1861 if (platform_pci_power_manageable(dev)) {
1863 * Call the platform to choose the target state of the device
1864 * and enable wake-up from this state if supported.
1866 pci_power_t state = platform_pci_choose_state(dev);
1869 case PCI_POWER_ERROR:
1874 if (pci_no_d1d2(dev))
1877 target_state = state;
1879 } else if (!dev->pm_cap) {
1880 target_state = PCI_D0;
1881 } else if (device_may_wakeup(&dev->dev)) {
1883 * Find the deepest state from which the device can generate
1884 * wake-up events, make it the target state and enable device
1887 if (dev->pme_support) {
1889 && !(dev->pme_support & (1 << target_state)))
1894 return target_state;
1898 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1899 * @dev: Device to handle.
1901 * Choose the power state appropriate for the device depending on whether
1902 * it can wake up the system and/or is power manageable by the platform
1903 * (PCI_D3hot is the default) and put the device into that state.
1905 int pci_prepare_to_sleep(struct pci_dev *dev)
1907 pci_power_t target_state = pci_target_state(dev);
1910 if (target_state == PCI_POWER_ERROR)
1913 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1915 error = pci_set_power_state(dev, target_state);
1918 pci_enable_wake(dev, target_state, false);
1922 EXPORT_SYMBOL(pci_prepare_to_sleep);
1925 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1926 * @dev: Device to handle.
1928 * Disable device's system wake-up capability and put it into D0.
1930 int pci_back_from_sleep(struct pci_dev *dev)
1932 pci_enable_wake(dev, PCI_D0, false);
1933 return pci_set_power_state(dev, PCI_D0);
1935 EXPORT_SYMBOL(pci_back_from_sleep);
1938 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1939 * @dev: PCI device being suspended.
1941 * Prepare @dev to generate wake-up events at run time and put it into a low
1944 int pci_finish_runtime_suspend(struct pci_dev *dev)
1946 pci_power_t target_state = pci_target_state(dev);
1949 if (target_state == PCI_POWER_ERROR)
1952 dev->runtime_d3cold = target_state == PCI_D3cold;
1954 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1956 error = pci_set_power_state(dev, target_state);
1959 __pci_enable_wake(dev, target_state, true, false);
1960 dev->runtime_d3cold = false;
1967 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1968 * @dev: Device to check.
1970 * Return true if the device itself is capable of generating wake-up events
1971 * (through the platform or using the native PCIe PME) or if the device supports
1972 * PME and one of its upstream bridges can generate wake-up events.
1974 bool pci_dev_run_wake(struct pci_dev *dev)
1976 struct pci_bus *bus = dev->bus;
1978 if (device_run_wake(&dev->dev))
1981 if (!dev->pme_support)
1984 while (bus->parent) {
1985 struct pci_dev *bridge = bus->self;
1987 if (device_run_wake(&bridge->dev))
1993 /* We have reached the root bus. */
1995 return device_run_wake(bus->bridge);
1999 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2001 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2003 struct device *dev = &pdev->dev;
2004 struct device *parent = dev->parent;
2007 pm_runtime_get_sync(parent);
2008 pm_runtime_get_noresume(dev);
2010 * pdev->current_state is set to PCI_D3cold during suspending,
2011 * so wait until suspending completes
2013 pm_runtime_barrier(dev);
2015 * Only need to resume devices in D3cold, because config
2016 * registers are still accessible for devices suspended but
2019 if (pdev->current_state == PCI_D3cold)
2020 pm_runtime_resume(dev);
2023 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2025 struct device *dev = &pdev->dev;
2026 struct device *parent = dev->parent;
2028 pm_runtime_put(dev);
2030 pm_runtime_put_sync(parent);
2034 * pci_pm_init - Initialize PM functions of given PCI device
2035 * @dev: PCI device to handle.
2037 void pci_pm_init(struct pci_dev *dev)
2042 pm_runtime_forbid(&dev->dev);
2043 pm_runtime_set_active(&dev->dev);
2044 pm_runtime_enable(&dev->dev);
2045 device_enable_async_suspend(&dev->dev);
2046 dev->wakeup_prepared = false;
2049 dev->pme_support = 0;
2051 /* find PCI PM capability in list */
2052 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2055 /* Check device's ability to generate PME# */
2056 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2058 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2059 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2060 pmc & PCI_PM_CAP_VER_MASK);
2065 dev->d3_delay = PCI_PM_D3_WAIT;
2066 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2067 dev->d3cold_allowed = true;
2069 dev->d1_support = false;
2070 dev->d2_support = false;
2071 if (!pci_no_d1d2(dev)) {
2072 if (pmc & PCI_PM_CAP_D1)
2073 dev->d1_support = true;
2074 if (pmc & PCI_PM_CAP_D2)
2075 dev->d2_support = true;
2077 if (dev->d1_support || dev->d2_support)
2078 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2079 dev->d1_support ? " D1" : "",
2080 dev->d2_support ? " D2" : "");
2083 pmc &= PCI_PM_CAP_PME_MASK;
2085 dev_printk(KERN_DEBUG, &dev->dev,
2086 "PME# supported from%s%s%s%s%s\n",
2087 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2088 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2089 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2090 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2091 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2092 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2093 dev->pme_poll = true;
2095 * Make device's PM flags reflect the wake-up capability, but
2096 * let the user space enable it to wake up the system as needed.
2098 device_set_wakeup_capable(&dev->dev, true);
2099 /* Disable the PME# generation functionality */
2100 pci_pme_active(dev, false);
2104 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2105 struct pci_cap_saved_state *new_cap)
2107 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2111 * _pci_add_cap_save_buffer - allocate buffer for saving given
2112 * capability registers
2113 * @dev: the PCI device
2114 * @cap: the capability to allocate the buffer for
2115 * @extended: Standard or Extended capability ID
2116 * @size: requested size of the buffer
2118 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2119 bool extended, unsigned int size)
2122 struct pci_cap_saved_state *save_state;
2125 pos = pci_find_ext_capability(dev, cap);
2127 pos = pci_find_capability(dev, cap);
2132 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2136 save_state->cap.cap_nr = cap;
2137 save_state->cap.cap_extended = extended;
2138 save_state->cap.size = size;
2139 pci_add_saved_cap(dev, save_state);
2144 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2146 return _pci_add_cap_save_buffer(dev, cap, false, size);
2149 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2151 return _pci_add_cap_save_buffer(dev, cap, true, size);
2155 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2156 * @dev: the PCI device
2158 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2162 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2163 PCI_EXP_SAVE_REGS * sizeof(u16));
2166 "unable to preallocate PCI Express save buffer\n");
2168 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2171 "unable to preallocate PCI-X save buffer\n");
2173 pci_allocate_vc_save_buffers(dev);
2176 void pci_free_cap_save_buffers(struct pci_dev *dev)
2178 struct pci_cap_saved_state *tmp;
2179 struct hlist_node *n;
2181 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2186 * pci_configure_ari - enable or disable ARI forwarding
2187 * @dev: the PCI device
2189 * If @dev and its upstream bridge both support ARI, enable ARI in the
2190 * bridge. Otherwise, disable ARI in the bridge.
2192 void pci_configure_ari(struct pci_dev *dev)
2195 struct pci_dev *bridge;
2197 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2200 bridge = dev->bus->self;
2204 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2205 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2208 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2209 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2210 PCI_EXP_DEVCTL2_ARI);
2211 bridge->ari_enabled = 1;
2213 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2214 PCI_EXP_DEVCTL2_ARI);
2215 bridge->ari_enabled = 0;
2219 static int pci_acs_enable;
2222 * pci_request_acs - ask for ACS to be enabled if supported
2224 void pci_request_acs(void)
2230 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2231 * @dev: the PCI device
2233 static int pci_std_enable_acs(struct pci_dev *dev)
2239 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2243 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2244 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2246 /* Source Validation */
2247 ctrl |= (cap & PCI_ACS_SV);
2249 /* P2P Request Redirect */
2250 ctrl |= (cap & PCI_ACS_RR);
2252 /* P2P Completion Redirect */
2253 ctrl |= (cap & PCI_ACS_CR);
2255 /* Upstream Forwarding */
2256 ctrl |= (cap & PCI_ACS_UF);
2258 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2264 * pci_enable_acs - enable ACS if hardware support it
2265 * @dev: the PCI device
2267 void pci_enable_acs(struct pci_dev *dev)
2269 if (!pci_acs_enable)
2272 if (!pci_std_enable_acs(dev))
2275 pci_dev_specific_enable_acs(dev);
2278 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2283 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2288 * Except for egress control, capabilities are either required
2289 * or only required if controllable. Features missing from the
2290 * capability field can therefore be assumed as hard-wired enabled.
2292 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2293 acs_flags &= (cap | PCI_ACS_EC);
2295 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2296 return (ctrl & acs_flags) == acs_flags;
2300 * pci_acs_enabled - test ACS against required flags for a given device
2301 * @pdev: device to test
2302 * @acs_flags: required PCI ACS flags
2304 * Return true if the device supports the provided flags. Automatically
2305 * filters out flags that are not implemented on multifunction devices.
2307 * Note that this interface checks the effective ACS capabilities of the
2308 * device rather than the actual capabilities. For instance, most single
2309 * function endpoints are not required to support ACS because they have no
2310 * opportunity for peer-to-peer access. We therefore return 'true'
2311 * regardless of whether the device exposes an ACS capability. This makes
2312 * it much easier for callers of this function to ignore the actual type
2313 * or topology of the device when testing ACS support.
2315 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2319 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2324 * Conventional PCI and PCI-X devices never support ACS, either
2325 * effectively or actually. The shared bus topology implies that
2326 * any device on the bus can receive or snoop DMA.
2328 if (!pci_is_pcie(pdev))
2331 switch (pci_pcie_type(pdev)) {
2333 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2334 * but since their primary interface is PCI/X, we conservatively
2335 * handle them as we would a non-PCIe device.
2337 case PCI_EXP_TYPE_PCIE_BRIDGE:
2339 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2340 * applicable... must never implement an ACS Extended Capability...".
2341 * This seems arbitrary, but we take a conservative interpretation
2342 * of this statement.
2344 case PCI_EXP_TYPE_PCI_BRIDGE:
2345 case PCI_EXP_TYPE_RC_EC:
2348 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2349 * implement ACS in order to indicate their peer-to-peer capabilities,
2350 * regardless of whether they are single- or multi-function devices.
2352 case PCI_EXP_TYPE_DOWNSTREAM:
2353 case PCI_EXP_TYPE_ROOT_PORT:
2354 return pci_acs_flags_enabled(pdev, acs_flags);
2356 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2357 * implemented by the remaining PCIe types to indicate peer-to-peer
2358 * capabilities, but only when they are part of a multifunction
2359 * device. The footnote for section 6.12 indicates the specific
2360 * PCIe types included here.
2362 case PCI_EXP_TYPE_ENDPOINT:
2363 case PCI_EXP_TYPE_UPSTREAM:
2364 case PCI_EXP_TYPE_LEG_END:
2365 case PCI_EXP_TYPE_RC_END:
2366 if (!pdev->multifunction)
2369 return pci_acs_flags_enabled(pdev, acs_flags);
2373 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2374 * to single function devices with the exception of downstream ports.
2380 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2381 * @start: starting downstream device
2382 * @end: ending upstream device or NULL to search to the root bus
2383 * @acs_flags: required flags
2385 * Walk up a device tree from start to end testing PCI ACS support. If
2386 * any step along the way does not support the required flags, return false.
2388 bool pci_acs_path_enabled(struct pci_dev *start,
2389 struct pci_dev *end, u16 acs_flags)
2391 struct pci_dev *pdev, *parent = start;
2396 if (!pci_acs_enabled(pdev, acs_flags))
2399 if (pci_is_root_bus(pdev->bus))
2400 return (end == NULL);
2402 parent = pdev->bus->self;
2403 } while (pdev != end);
2409 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2410 * @dev: the PCI device
2411 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2413 * Perform INTx swizzling for a device behind one level of bridge. This is
2414 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2415 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2416 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2417 * the PCI Express Base Specification, Revision 2.1)
2419 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2423 if (pci_ari_enabled(dev->bus))
2426 slot = PCI_SLOT(dev->devfn);
2428 return (((pin - 1) + slot) % 4) + 1;
2431 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2439 while (!pci_is_root_bus(dev->bus)) {
2440 pin = pci_swizzle_interrupt_pin(dev, pin);
2441 dev = dev->bus->self;
2448 * pci_common_swizzle - swizzle INTx all the way to root bridge
2449 * @dev: the PCI device
2450 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2452 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2453 * bridges all the way up to a PCI root bus.
2455 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2459 while (!pci_is_root_bus(dev->bus)) {
2460 pin = pci_swizzle_interrupt_pin(dev, pin);
2461 dev = dev->bus->self;
2464 return PCI_SLOT(dev->devfn);
2468 * pci_release_region - Release a PCI bar
2469 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2470 * @bar: BAR to release
2472 * Releases the PCI I/O and memory resources previously reserved by a
2473 * successful call to pci_request_region. Call this function only
2474 * after all use of the PCI regions has ceased.
2476 void pci_release_region(struct pci_dev *pdev, int bar)
2478 struct pci_devres *dr;
2480 if (pci_resource_len(pdev, bar) == 0)
2482 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2483 release_region(pci_resource_start(pdev, bar),
2484 pci_resource_len(pdev, bar));
2485 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2486 release_mem_region(pci_resource_start(pdev, bar),
2487 pci_resource_len(pdev, bar));
2489 dr = find_pci_dr(pdev);
2491 dr->region_mask &= ~(1 << bar);
2493 EXPORT_SYMBOL(pci_release_region);
2496 * __pci_request_region - Reserved PCI I/O and memory resource
2497 * @pdev: PCI device whose resources are to be reserved
2498 * @bar: BAR to be reserved
2499 * @res_name: Name to be associated with resource.
2500 * @exclusive: whether the region access is exclusive or not
2502 * Mark the PCI region associated with PCI device @pdev BR @bar as
2503 * being reserved by owner @res_name. Do not access any
2504 * address inside the PCI regions unless this call returns
2507 * If @exclusive is set, then the region is marked so that userspace
2508 * is explicitly not allowed to map the resource via /dev/mem or
2509 * sysfs MMIO access.
2511 * Returns 0 on success, or %EBUSY on error. A warning
2512 * message is also printed on failure.
2514 static int __pci_request_region(struct pci_dev *pdev, int bar,
2515 const char *res_name, int exclusive)
2517 struct pci_devres *dr;
2519 if (pci_resource_len(pdev, bar) == 0)
2522 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2523 if (!request_region(pci_resource_start(pdev, bar),
2524 pci_resource_len(pdev, bar), res_name))
2526 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2527 if (!__request_mem_region(pci_resource_start(pdev, bar),
2528 pci_resource_len(pdev, bar), res_name,
2533 dr = find_pci_dr(pdev);
2535 dr->region_mask |= 1 << bar;
2540 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2541 &pdev->resource[bar]);
2546 * pci_request_region - Reserve PCI I/O and memory resource
2547 * @pdev: PCI device whose resources are to be reserved
2548 * @bar: BAR to be reserved
2549 * @res_name: Name to be associated with resource
2551 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2552 * being reserved by owner @res_name. Do not access any
2553 * address inside the PCI regions unless this call returns
2556 * Returns 0 on success, or %EBUSY on error. A warning
2557 * message is also printed on failure.
2559 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2561 return __pci_request_region(pdev, bar, res_name, 0);
2563 EXPORT_SYMBOL(pci_request_region);
2566 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2567 * @pdev: PCI device whose resources are to be reserved
2568 * @bar: BAR to be reserved
2569 * @res_name: Name to be associated with resource.
2571 * Mark the PCI region associated with PCI device @pdev BR @bar as
2572 * being reserved by owner @res_name. Do not access any
2573 * address inside the PCI regions unless this call returns
2576 * Returns 0 on success, or %EBUSY on error. A warning
2577 * message is also printed on failure.
2579 * The key difference that _exclusive makes it that userspace is
2580 * explicitly not allowed to map the resource via /dev/mem or
2583 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
2584 const char *res_name)
2586 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2588 EXPORT_SYMBOL(pci_request_region_exclusive);
2591 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2592 * @pdev: PCI device whose resources were previously reserved
2593 * @bars: Bitmask of BARs to be released
2595 * Release selected PCI I/O and memory resources previously reserved.
2596 * Call this function only after all use of the PCI regions has ceased.
2598 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2602 for (i = 0; i < 6; i++)
2603 if (bars & (1 << i))
2604 pci_release_region(pdev, i);
2606 EXPORT_SYMBOL(pci_release_selected_regions);
2608 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2609 const char *res_name, int excl)
2613 for (i = 0; i < 6; i++)
2614 if (bars & (1 << i))
2615 if (__pci_request_region(pdev, i, res_name, excl))
2621 if (bars & (1 << i))
2622 pci_release_region(pdev, i);
2629 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2630 * @pdev: PCI device whose resources are to be reserved
2631 * @bars: Bitmask of BARs to be requested
2632 * @res_name: Name to be associated with resource
2634 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2635 const char *res_name)
2637 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2639 EXPORT_SYMBOL(pci_request_selected_regions);
2641 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
2642 const char *res_name)
2644 return __pci_request_selected_regions(pdev, bars, res_name,
2645 IORESOURCE_EXCLUSIVE);
2647 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2650 * pci_release_regions - Release reserved PCI I/O and memory resources
2651 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2653 * Releases all PCI I/O and memory resources previously reserved by a
2654 * successful call to pci_request_regions. Call this function only
2655 * after all use of the PCI regions has ceased.
2658 void pci_release_regions(struct pci_dev *pdev)
2660 pci_release_selected_regions(pdev, (1 << 6) - 1);
2662 EXPORT_SYMBOL(pci_release_regions);
2665 * pci_request_regions - Reserved PCI I/O and memory resources
2666 * @pdev: PCI device whose resources are to be reserved
2667 * @res_name: Name to be associated with resource.
2669 * Mark all PCI regions associated with PCI device @pdev as
2670 * being reserved by owner @res_name. Do not access any
2671 * address inside the PCI regions unless this call returns
2674 * Returns 0 on success, or %EBUSY on error. A warning
2675 * message is also printed on failure.
2677 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2679 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2681 EXPORT_SYMBOL(pci_request_regions);
2684 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2685 * @pdev: PCI device whose resources are to be reserved
2686 * @res_name: Name to be associated with resource.
2688 * Mark all PCI regions associated with PCI device @pdev as
2689 * being reserved by owner @res_name. Do not access any
2690 * address inside the PCI regions unless this call returns
2693 * pci_request_regions_exclusive() will mark the region so that
2694 * /dev/mem and the sysfs MMIO access will not be allowed.
2696 * Returns 0 on success, or %EBUSY on error. A warning
2697 * message is also printed on failure.
2699 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2701 return pci_request_selected_regions_exclusive(pdev,
2702 ((1 << 6) - 1), res_name);
2704 EXPORT_SYMBOL(pci_request_regions_exclusive);
2707 * pci_remap_iospace - Remap the memory mapped I/O space
2708 * @res: Resource describing the I/O space
2709 * @phys_addr: physical address of range to be mapped
2711 * Remap the memory mapped I/O space described by the @res
2712 * and the CPU physical address @phys_addr into virtual address space.
2713 * Only architectures that have memory mapped IO functions defined
2714 * (and the PCI_IOBASE value defined) should call this function.
2716 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
2718 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
2719 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
2721 if (!(res->flags & IORESOURCE_IO))
2724 if (res->end > IO_SPACE_LIMIT)
2727 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
2728 pgprot_device(PAGE_KERNEL));
2730 /* this architecture does not have memory mapped I/O space,
2731 so this function should never be called */
2732 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
2737 static void __pci_set_master(struct pci_dev *dev, bool enable)
2741 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2743 cmd = old_cmd | PCI_COMMAND_MASTER;
2745 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2746 if (cmd != old_cmd) {
2747 dev_dbg(&dev->dev, "%s bus mastering\n",
2748 enable ? "enabling" : "disabling");
2749 pci_write_config_word(dev, PCI_COMMAND, cmd);
2751 dev->is_busmaster = enable;
2755 * pcibios_setup - process "pci=" kernel boot arguments
2756 * @str: string used to pass in "pci=" kernel boot arguments
2758 * Process kernel boot arguments. This is the default implementation.
2759 * Architecture specific implementations can override this as necessary.
2761 char * __weak __init pcibios_setup(char *str)
2767 * pcibios_set_master - enable PCI bus-mastering for device dev
2768 * @dev: the PCI device to enable
2770 * Enables PCI bus-mastering for the device. This is the default
2771 * implementation. Architecture specific implementations can override
2772 * this if necessary.
2774 void __weak pcibios_set_master(struct pci_dev *dev)
2778 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2779 if (pci_is_pcie(dev))
2782 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2784 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2785 else if (lat > pcibios_max_latency)
2786 lat = pcibios_max_latency;
2790 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2794 * pci_set_master - enables bus-mastering for device dev
2795 * @dev: the PCI device to enable
2797 * Enables bus-mastering on the device and calls pcibios_set_master()
2798 * to do the needed arch specific settings.
2800 void pci_set_master(struct pci_dev *dev)
2802 __pci_set_master(dev, true);
2803 pcibios_set_master(dev);
2805 EXPORT_SYMBOL(pci_set_master);
2808 * pci_clear_master - disables bus-mastering for device dev
2809 * @dev: the PCI device to disable
2811 void pci_clear_master(struct pci_dev *dev)
2813 __pci_set_master(dev, false);
2815 EXPORT_SYMBOL(pci_clear_master);
2818 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2819 * @dev: the PCI device for which MWI is to be enabled
2821 * Helper function for pci_set_mwi.
2822 * Originally copied from drivers/net/acenic.c.
2823 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2825 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2827 int pci_set_cacheline_size(struct pci_dev *dev)
2831 if (!pci_cache_line_size)
2834 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2835 equal to or multiple of the right value. */
2836 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2837 if (cacheline_size >= pci_cache_line_size &&
2838 (cacheline_size % pci_cache_line_size) == 0)
2841 /* Write the correct value. */
2842 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2844 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2845 if (cacheline_size == pci_cache_line_size)
2848 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
2849 pci_cache_line_size << 2);
2853 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2856 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2857 * @dev: the PCI device for which MWI is enabled
2859 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2861 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2863 int pci_set_mwi(struct pci_dev *dev)
2865 #ifdef PCI_DISABLE_MWI
2871 rc = pci_set_cacheline_size(dev);
2875 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2876 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
2877 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2878 cmd |= PCI_COMMAND_INVALIDATE;
2879 pci_write_config_word(dev, PCI_COMMAND, cmd);
2884 EXPORT_SYMBOL(pci_set_mwi);
2887 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2888 * @dev: the PCI device for which MWI is enabled
2890 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2891 * Callers are not required to check the return value.
2893 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2895 int pci_try_set_mwi(struct pci_dev *dev)
2897 #ifdef PCI_DISABLE_MWI
2900 return pci_set_mwi(dev);
2903 EXPORT_SYMBOL(pci_try_set_mwi);
2906 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2907 * @dev: the PCI device to disable
2909 * Disables PCI Memory-Write-Invalidate transaction on the device
2911 void pci_clear_mwi(struct pci_dev *dev)
2913 #ifndef PCI_DISABLE_MWI
2916 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2917 if (cmd & PCI_COMMAND_INVALIDATE) {
2918 cmd &= ~PCI_COMMAND_INVALIDATE;
2919 pci_write_config_word(dev, PCI_COMMAND, cmd);
2923 EXPORT_SYMBOL(pci_clear_mwi);
2926 * pci_intx - enables/disables PCI INTx for device dev
2927 * @pdev: the PCI device to operate on
2928 * @enable: boolean: whether to enable or disable PCI INTx
2930 * Enables/disables PCI INTx for device dev
2932 void pci_intx(struct pci_dev *pdev, int enable)
2934 u16 pci_command, new;
2936 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2939 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2941 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2943 if (new != pci_command) {
2944 struct pci_devres *dr;
2946 pci_write_config_word(pdev, PCI_COMMAND, new);
2948 dr = find_pci_dr(pdev);
2949 if (dr && !dr->restore_intx) {
2950 dr->restore_intx = 1;
2951 dr->orig_intx = !enable;
2955 EXPORT_SYMBOL_GPL(pci_intx);
2958 * pci_intx_mask_supported - probe for INTx masking support
2959 * @dev: the PCI device to operate on
2961 * Check if the device dev support INTx masking via the config space
2964 bool pci_intx_mask_supported(struct pci_dev *dev)
2966 bool mask_supported = false;
2969 if (dev->broken_intx_masking)
2972 pci_cfg_access_lock(dev);
2974 pci_read_config_word(dev, PCI_COMMAND, &orig);
2975 pci_write_config_word(dev, PCI_COMMAND,
2976 orig ^ PCI_COMMAND_INTX_DISABLE);
2977 pci_read_config_word(dev, PCI_COMMAND, &new);
2980 * There's no way to protect against hardware bugs or detect them
2981 * reliably, but as long as we know what the value should be, let's
2982 * go ahead and check it.
2984 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2985 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
2987 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2988 mask_supported = true;
2989 pci_write_config_word(dev, PCI_COMMAND, orig);
2992 pci_cfg_access_unlock(dev);
2993 return mask_supported;
2995 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2997 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2999 struct pci_bus *bus = dev->bus;
3000 bool mask_updated = true;
3001 u32 cmd_status_dword;
3002 u16 origcmd, newcmd;
3003 unsigned long flags;
3007 * We do a single dword read to retrieve both command and status.
3008 * Document assumptions that make this possible.
3010 BUILD_BUG_ON(PCI_COMMAND % 4);
3011 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3013 raw_spin_lock_irqsave(&pci_lock, flags);
3015 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3017 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3020 * Check interrupt status register to see whether our device
3021 * triggered the interrupt (when masking) or the next IRQ is
3022 * already pending (when unmasking).
3024 if (mask != irq_pending) {
3025 mask_updated = false;
3029 origcmd = cmd_status_dword;
3030 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3032 newcmd |= PCI_COMMAND_INTX_DISABLE;
3033 if (newcmd != origcmd)
3034 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3037 raw_spin_unlock_irqrestore(&pci_lock, flags);
3039 return mask_updated;
3043 * pci_check_and_mask_intx - mask INTx on pending interrupt
3044 * @dev: the PCI device to operate on
3046 * Check if the device dev has its INTx line asserted, mask it and
3047 * return true in that case. False is returned if not interrupt was
3050 bool pci_check_and_mask_intx(struct pci_dev *dev)
3052 return pci_check_and_set_intx_mask(dev, true);
3054 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3057 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3058 * @dev: the PCI device to operate on
3060 * Check if the device dev has its INTx line asserted, unmask it if not
3061 * and return true. False is returned and the mask remains active if
3062 * there was still an interrupt pending.
3064 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3066 return pci_check_and_set_intx_mask(dev, false);
3068 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3071 * pci_msi_off - disables any MSI or MSI-X capabilities
3072 * @dev: the PCI device to operate on
3074 * If you want to use MSI, see pci_enable_msi() and friends.
3075 * This is a lower-level primitive that allows us to disable
3076 * MSI operation at the device level.
3078 void pci_msi_off(struct pci_dev *dev)
3084 * This looks like it could go in msi.c, but we need it even when
3085 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3086 * dev->msi_cap or dev->msix_cap here.
3088 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3090 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3091 control &= ~PCI_MSI_FLAGS_ENABLE;
3092 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3094 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3096 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3097 control &= ~PCI_MSIX_FLAGS_ENABLE;
3098 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3101 EXPORT_SYMBOL_GPL(pci_msi_off);
3103 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3105 return dma_set_max_seg_size(&dev->dev, size);
3107 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3109 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3111 return dma_set_seg_boundary(&dev->dev, mask);
3113 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3116 * pci_wait_for_pending_transaction - waits for pending transaction
3117 * @dev: the PCI device to operate on
3119 * Return 0 if transaction is pending 1 otherwise.
3121 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3123 if (!pci_is_pcie(dev))
3126 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3127 PCI_EXP_DEVSTA_TRPND);
3129 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3131 static int pcie_flr(struct pci_dev *dev, int probe)
3135 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3136 if (!(cap & PCI_EXP_DEVCAP_FLR))
3142 if (!pci_wait_for_pending_transaction(dev))
3143 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3145 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3150 static int pci_af_flr(struct pci_dev *dev, int probe)
3155 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3159 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3160 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3167 * Wait for Transaction Pending bit to clear. A word-aligned test
3168 * is used, so we use the conrol offset rather than status and shift
3169 * the test bit to match.
3171 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3172 PCI_AF_STATUS_TP << 8))
3173 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3175 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3181 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3182 * @dev: Device to reset.
3183 * @probe: If set, only check if the device can be reset this way.
3185 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3186 * unset, it will be reinitialized internally when going from PCI_D3hot to
3187 * PCI_D0. If that's the case and the device is not in a low-power state
3188 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3190 * NOTE: This causes the caller to sleep for twice the device power transition
3191 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3192 * by default (i.e. unless the @dev's d3_delay field has a different value).
3193 * Moreover, only devices in D0 can be reset by this function.
3195 static int pci_pm_reset(struct pci_dev *dev, int probe)
3202 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3203 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3209 if (dev->current_state != PCI_D0)
3212 csr &= ~PCI_PM_CTRL_STATE_MASK;
3214 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3215 pci_dev_d3_sleep(dev);
3217 csr &= ~PCI_PM_CTRL_STATE_MASK;
3219 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3220 pci_dev_d3_sleep(dev);
3225 void pci_reset_secondary_bus(struct pci_dev *dev)
3229 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3230 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3231 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3233 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3234 * this to 2ms to ensure that we meet the minimum requirement.
3238 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3239 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3242 * Trhfa for conventional PCI is 2^25 clock cycles.
3243 * Assuming a minimum 33MHz clock this results in a 1s
3244 * delay before we can consider subordinate devices to
3245 * be re-initialized. PCIe has some ways to shorten this,
3246 * but we don't make use of them yet.
3251 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3253 pci_reset_secondary_bus(dev);
3257 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3258 * @dev: Bridge device
3260 * Use the bridge control register to assert reset on the secondary bus.
3261 * Devices on the secondary bus are left in power-on state.
3263 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3265 pcibios_reset_secondary_bus(dev);
3267 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3269 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3271 struct pci_dev *pdev;
3273 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3276 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3283 pci_reset_bridge_secondary_bus(dev->bus->self);
3288 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3292 if (!hotplug || !try_module_get(hotplug->ops->owner))
3295 if (hotplug->ops->reset_slot)
3296 rc = hotplug->ops->reset_slot(hotplug, probe);
3298 module_put(hotplug->ops->owner);
3303 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3305 struct pci_dev *pdev;
3307 if (dev->subordinate || !dev->slot)
3310 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3311 if (pdev != dev && pdev->slot == dev->slot)
3314 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3317 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3323 rc = pci_dev_specific_reset(dev, probe);
3327 rc = pcie_flr(dev, probe);
3331 rc = pci_af_flr(dev, probe);
3335 rc = pci_pm_reset(dev, probe);
3339 rc = pci_dev_reset_slot_function(dev, probe);
3343 rc = pci_parent_bus_reset(dev, probe);
3348 static void pci_dev_lock(struct pci_dev *dev)
3350 pci_cfg_access_lock(dev);
3351 /* block PM suspend, driver probe, etc. */
3352 device_lock(&dev->dev);
3355 /* Return 1 on successful lock, 0 on contention */
3356 static int pci_dev_trylock(struct pci_dev *dev)
3358 if (pci_cfg_access_trylock(dev)) {
3359 if (device_trylock(&dev->dev))
3361 pci_cfg_access_unlock(dev);
3367 static void pci_dev_unlock(struct pci_dev *dev)
3369 device_unlock(&dev->dev);
3370 pci_cfg_access_unlock(dev);
3374 * pci_reset_notify - notify device driver of reset
3375 * @dev: device to be notified of reset
3376 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3379 * Must be called prior to device access being disabled and after device
3380 * access is restored.
3382 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3384 const struct pci_error_handlers *err_handler =
3385 dev->driver ? dev->driver->err_handler : NULL;
3386 if (err_handler && err_handler->reset_notify)
3387 err_handler->reset_notify(dev, prepare);
3390 static void pci_dev_save_and_disable(struct pci_dev *dev)
3392 pci_reset_notify(dev, true);
3395 * Wake-up device prior to save. PM registers default to D0 after
3396 * reset and a simple register restore doesn't reliably return
3397 * to a non-D0 state anyway.
3399 pci_set_power_state(dev, PCI_D0);
3401 pci_save_state(dev);
3403 * Disable the device by clearing the Command register, except for
3404 * INTx-disable which is set. This not only disables MMIO and I/O port
3405 * BARs, but also prevents the device from being Bus Master, preventing
3406 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3407 * compliant devices, INTx-disable prevents legacy interrupts.
3409 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3412 static void pci_dev_restore(struct pci_dev *dev)
3414 pci_restore_state(dev);
3415 pci_reset_notify(dev, false);
3418 static int pci_dev_reset(struct pci_dev *dev, int probe)
3425 rc = __pci_dev_reset(dev, probe);
3428 pci_dev_unlock(dev);
3434 * __pci_reset_function - reset a PCI device function
3435 * @dev: PCI device to reset
3437 * Some devices allow an individual function to be reset without affecting
3438 * other functions in the same device. The PCI device must be responsive
3439 * to PCI config space in order to use this function.
3441 * The device function is presumed to be unused when this function is called.
3442 * Resetting the device will make the contents of PCI configuration space
3443 * random, so any caller of this must be prepared to reinitialise the
3444 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3447 * Returns 0 if the device function was successfully reset or negative if the
3448 * device doesn't support resetting a single function.
3450 int __pci_reset_function(struct pci_dev *dev)
3452 return pci_dev_reset(dev, 0);
3454 EXPORT_SYMBOL_GPL(__pci_reset_function);
3457 * __pci_reset_function_locked - reset a PCI device function while holding
3458 * the @dev mutex lock.
3459 * @dev: PCI device to reset
3461 * Some devices allow an individual function to be reset without affecting
3462 * other functions in the same device. The PCI device must be responsive
3463 * to PCI config space in order to use this function.
3465 * The device function is presumed to be unused and the caller is holding
3466 * the device mutex lock when this function is called.
3467 * Resetting the device will make the contents of PCI configuration space
3468 * random, so any caller of this must be prepared to reinitialise the
3469 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3472 * Returns 0 if the device function was successfully reset or negative if the
3473 * device doesn't support resetting a single function.
3475 int __pci_reset_function_locked(struct pci_dev *dev)
3477 return __pci_dev_reset(dev, 0);
3479 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3482 * pci_probe_reset_function - check whether the device can be safely reset
3483 * @dev: PCI device to reset
3485 * Some devices allow an individual function to be reset without affecting
3486 * other functions in the same device. The PCI device must be responsive
3487 * to PCI config space in order to use this function.
3489 * Returns 0 if the device function can be reset or negative if the
3490 * device doesn't support resetting a single function.
3492 int pci_probe_reset_function(struct pci_dev *dev)
3494 return pci_dev_reset(dev, 1);
3498 * pci_reset_function - quiesce and reset a PCI device function
3499 * @dev: PCI device to reset
3501 * Some devices allow an individual function to be reset without affecting
3502 * other functions in the same device. The PCI device must be responsive
3503 * to PCI config space in order to use this function.
3505 * This function does not just reset the PCI portion of a device, but
3506 * clears all the state associated with the device. This function differs
3507 * from __pci_reset_function in that it saves and restores device state
3510 * Returns 0 if the device function was successfully reset or negative if the
3511 * device doesn't support resetting a single function.
3513 int pci_reset_function(struct pci_dev *dev)
3517 rc = pci_dev_reset(dev, 1);
3521 pci_dev_save_and_disable(dev);
3523 rc = pci_dev_reset(dev, 0);
3525 pci_dev_restore(dev);
3529 EXPORT_SYMBOL_GPL(pci_reset_function);
3532 * pci_try_reset_function - quiesce and reset a PCI device function
3533 * @dev: PCI device to reset
3535 * Same as above, except return -EAGAIN if unable to lock device.
3537 int pci_try_reset_function(struct pci_dev *dev)
3541 rc = pci_dev_reset(dev, 1);
3545 pci_dev_save_and_disable(dev);
3547 if (pci_dev_trylock(dev)) {
3548 rc = __pci_dev_reset(dev, 0);
3549 pci_dev_unlock(dev);
3553 pci_dev_restore(dev);
3557 EXPORT_SYMBOL_GPL(pci_try_reset_function);
3559 /* Lock devices from the top of the tree down */
3560 static void pci_bus_lock(struct pci_bus *bus)
3562 struct pci_dev *dev;
3564 list_for_each_entry(dev, &bus->devices, bus_list) {
3566 if (dev->subordinate)
3567 pci_bus_lock(dev->subordinate);
3571 /* Unlock devices from the bottom of the tree up */
3572 static void pci_bus_unlock(struct pci_bus *bus)
3574 struct pci_dev *dev;
3576 list_for_each_entry(dev, &bus->devices, bus_list) {
3577 if (dev->subordinate)
3578 pci_bus_unlock(dev->subordinate);
3579 pci_dev_unlock(dev);
3583 /* Return 1 on successful lock, 0 on contention */
3584 static int pci_bus_trylock(struct pci_bus *bus)
3586 struct pci_dev *dev;
3588 list_for_each_entry(dev, &bus->devices, bus_list) {
3589 if (!pci_dev_trylock(dev))
3591 if (dev->subordinate) {
3592 if (!pci_bus_trylock(dev->subordinate)) {
3593 pci_dev_unlock(dev);
3601 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3602 if (dev->subordinate)
3603 pci_bus_unlock(dev->subordinate);
3604 pci_dev_unlock(dev);
3609 /* Lock devices from the top of the tree down */
3610 static void pci_slot_lock(struct pci_slot *slot)
3612 struct pci_dev *dev;
3614 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3615 if (!dev->slot || dev->slot != slot)
3618 if (dev->subordinate)
3619 pci_bus_lock(dev->subordinate);
3623 /* Unlock devices from the bottom of the tree up */
3624 static void pci_slot_unlock(struct pci_slot *slot)
3626 struct pci_dev *dev;
3628 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3629 if (!dev->slot || dev->slot != slot)
3631 if (dev->subordinate)
3632 pci_bus_unlock(dev->subordinate);
3633 pci_dev_unlock(dev);
3637 /* Return 1 on successful lock, 0 on contention */
3638 static int pci_slot_trylock(struct pci_slot *slot)
3640 struct pci_dev *dev;
3642 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3643 if (!dev->slot || dev->slot != slot)
3645 if (!pci_dev_trylock(dev))
3647 if (dev->subordinate) {
3648 if (!pci_bus_trylock(dev->subordinate)) {
3649 pci_dev_unlock(dev);
3657 list_for_each_entry_continue_reverse(dev,
3658 &slot->bus->devices, bus_list) {
3659 if (!dev->slot || dev->slot != slot)
3661 if (dev->subordinate)
3662 pci_bus_unlock(dev->subordinate);
3663 pci_dev_unlock(dev);
3668 /* Save and disable devices from the top of the tree down */
3669 static void pci_bus_save_and_disable(struct pci_bus *bus)
3671 struct pci_dev *dev;
3673 list_for_each_entry(dev, &bus->devices, bus_list) {
3674 pci_dev_save_and_disable(dev);
3675 if (dev->subordinate)
3676 pci_bus_save_and_disable(dev->subordinate);
3681 * Restore devices from top of the tree down - parent bridges need to be
3682 * restored before we can get to subordinate devices.
3684 static void pci_bus_restore(struct pci_bus *bus)
3686 struct pci_dev *dev;
3688 list_for_each_entry(dev, &bus->devices, bus_list) {
3689 pci_dev_restore(dev);
3690 if (dev->subordinate)
3691 pci_bus_restore(dev->subordinate);
3695 /* Save and disable devices from the top of the tree down */
3696 static void pci_slot_save_and_disable(struct pci_slot *slot)
3698 struct pci_dev *dev;
3700 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3701 if (!dev->slot || dev->slot != slot)
3703 pci_dev_save_and_disable(dev);
3704 if (dev->subordinate)
3705 pci_bus_save_and_disable(dev->subordinate);
3710 * Restore devices from top of the tree down - parent bridges need to be
3711 * restored before we can get to subordinate devices.
3713 static void pci_slot_restore(struct pci_slot *slot)
3715 struct pci_dev *dev;
3717 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3718 if (!dev->slot || dev->slot != slot)
3720 pci_dev_restore(dev);
3721 if (dev->subordinate)
3722 pci_bus_restore(dev->subordinate);
3726 static int pci_slot_reset(struct pci_slot *slot, int probe)
3734 pci_slot_lock(slot);
3738 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3741 pci_slot_unlock(slot);
3747 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3748 * @slot: PCI slot to probe
3750 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3752 int pci_probe_reset_slot(struct pci_slot *slot)
3754 return pci_slot_reset(slot, 1);
3756 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3759 * pci_reset_slot - reset a PCI slot
3760 * @slot: PCI slot to reset
3762 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3763 * independent of other slots. For instance, some slots may support slot power
3764 * control. In the case of a 1:1 bus to slot architecture, this function may
3765 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3766 * Generally a slot reset should be attempted before a bus reset. All of the
3767 * function of the slot and any subordinate buses behind the slot are reset
3768 * through this function. PCI config space of all devices in the slot and
3769 * behind the slot is saved before and restored after reset.
3771 * Return 0 on success, non-zero on error.
3773 int pci_reset_slot(struct pci_slot *slot)
3777 rc = pci_slot_reset(slot, 1);
3781 pci_slot_save_and_disable(slot);
3783 rc = pci_slot_reset(slot, 0);
3785 pci_slot_restore(slot);
3789 EXPORT_SYMBOL_GPL(pci_reset_slot);
3792 * pci_try_reset_slot - Try to reset a PCI slot
3793 * @slot: PCI slot to reset
3795 * Same as above except return -EAGAIN if the slot cannot be locked
3797 int pci_try_reset_slot(struct pci_slot *slot)
3801 rc = pci_slot_reset(slot, 1);
3805 pci_slot_save_and_disable(slot);
3807 if (pci_slot_trylock(slot)) {
3809 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3810 pci_slot_unlock(slot);
3814 pci_slot_restore(slot);
3818 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3820 static int pci_bus_reset(struct pci_bus *bus, int probe)
3832 pci_reset_bridge_secondary_bus(bus->self);
3834 pci_bus_unlock(bus);
3840 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3841 * @bus: PCI bus to probe
3843 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3845 int pci_probe_reset_bus(struct pci_bus *bus)
3847 return pci_bus_reset(bus, 1);
3849 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3852 * pci_reset_bus - reset a PCI bus
3853 * @bus: top level PCI bus to reset
3855 * Do a bus reset on the given bus and any subordinate buses, saving
3856 * and restoring state of all devices.
3858 * Return 0 on success, non-zero on error.
3860 int pci_reset_bus(struct pci_bus *bus)
3864 rc = pci_bus_reset(bus, 1);
3868 pci_bus_save_and_disable(bus);
3870 rc = pci_bus_reset(bus, 0);
3872 pci_bus_restore(bus);
3876 EXPORT_SYMBOL_GPL(pci_reset_bus);
3879 * pci_try_reset_bus - Try to reset a PCI bus
3880 * @bus: top level PCI bus to reset
3882 * Same as above except return -EAGAIN if the bus cannot be locked
3884 int pci_try_reset_bus(struct pci_bus *bus)
3888 rc = pci_bus_reset(bus, 1);
3892 pci_bus_save_and_disable(bus);
3894 if (pci_bus_trylock(bus)) {
3896 pci_reset_bridge_secondary_bus(bus->self);
3897 pci_bus_unlock(bus);
3901 pci_bus_restore(bus);
3905 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3908 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3909 * @dev: PCI device to query
3911 * Returns mmrbc: maximum designed memory read count in bytes
3912 * or appropriate error value.
3914 int pcix_get_max_mmrbc(struct pci_dev *dev)
3919 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3923 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3926 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3928 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3931 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3932 * @dev: PCI device to query
3934 * Returns mmrbc: maximum memory read count in bytes
3935 * or appropriate error value.
3937 int pcix_get_mmrbc(struct pci_dev *dev)
3942 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3946 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3949 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3951 EXPORT_SYMBOL(pcix_get_mmrbc);
3954 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3955 * @dev: PCI device to query
3956 * @mmrbc: maximum memory read count in bytes
3957 * valid values are 512, 1024, 2048, 4096
3959 * If possible sets maximum memory read byte count, some bridges have erratas
3960 * that prevent this.
3962 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3968 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3971 v = ffs(mmrbc) - 10;
3973 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3977 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3980 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3983 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3986 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3988 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3991 cmd &= ~PCI_X_CMD_MAX_READ;
3993 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3998 EXPORT_SYMBOL(pcix_set_mmrbc);
4001 * pcie_get_readrq - get PCI Express read request size
4002 * @dev: PCI device to query
4004 * Returns maximum memory read request in bytes
4005 * or appropriate error value.
4007 int pcie_get_readrq(struct pci_dev *dev)
4011 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4013 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4015 EXPORT_SYMBOL(pcie_get_readrq);
4018 * pcie_set_readrq - set PCI Express maximum memory read request
4019 * @dev: PCI device to query
4020 * @rq: maximum memory read count in bytes
4021 * valid values are 128, 256, 512, 1024, 2048, 4096
4023 * If possible sets maximum memory read request in bytes
4025 int pcie_set_readrq(struct pci_dev *dev, int rq)
4029 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4033 * If using the "performance" PCIe config, we clamp the
4034 * read rq size to the max packet size to prevent the
4035 * host bridge generating requests larger than we can
4038 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4039 int mps = pcie_get_mps(dev);
4045 v = (ffs(rq) - 8) << 12;
4047 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4048 PCI_EXP_DEVCTL_READRQ, v);
4050 EXPORT_SYMBOL(pcie_set_readrq);
4053 * pcie_get_mps - get PCI Express maximum payload size
4054 * @dev: PCI device to query
4056 * Returns maximum payload size in bytes
4058 int pcie_get_mps(struct pci_dev *dev)
4062 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4064 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4066 EXPORT_SYMBOL(pcie_get_mps);
4069 * pcie_set_mps - set PCI Express maximum payload size
4070 * @dev: PCI device to query
4071 * @mps: maximum payload size in bytes
4072 * valid values are 128, 256, 512, 1024, 2048, 4096
4074 * If possible sets maximum payload size
4076 int pcie_set_mps(struct pci_dev *dev, int mps)
4080 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4084 if (v > dev->pcie_mpss)
4088 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4089 PCI_EXP_DEVCTL_PAYLOAD, v);
4091 EXPORT_SYMBOL(pcie_set_mps);
4094 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4095 * @dev: PCI device to query
4096 * @speed: storage for minimum speed
4097 * @width: storage for minimum width
4099 * This function will walk up the PCI device chain and determine the minimum
4100 * link width and speed of the device.
4102 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4103 enum pcie_link_width *width)
4107 *speed = PCI_SPEED_UNKNOWN;
4108 *width = PCIE_LNK_WIDTH_UNKNOWN;
4112 enum pci_bus_speed next_speed;
4113 enum pcie_link_width next_width;
4115 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4119 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4120 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4121 PCI_EXP_LNKSTA_NLW_SHIFT;
4123 if (next_speed < *speed)
4124 *speed = next_speed;
4126 if (next_width < *width)
4127 *width = next_width;
4129 dev = dev->bus->self;
4134 EXPORT_SYMBOL(pcie_get_minimum_link);
4137 * pci_select_bars - Make BAR mask from the type of resource
4138 * @dev: the PCI device for which BAR mask is made
4139 * @flags: resource type mask to be selected
4141 * This helper routine makes bar mask from the type of resource.
4143 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4146 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4147 if (pci_resource_flags(dev, i) & flags)
4151 EXPORT_SYMBOL(pci_select_bars);
4154 * pci_resource_bar - get position of the BAR associated with a resource
4155 * @dev: the PCI device
4156 * @resno: the resource number
4157 * @type: the BAR type to be filled in
4159 * Returns BAR position in config space, or 0 if the BAR is invalid.
4161 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4165 if (resno < PCI_ROM_RESOURCE) {
4166 *type = pci_bar_unknown;
4167 return PCI_BASE_ADDRESS_0 + 4 * resno;
4168 } else if (resno == PCI_ROM_RESOURCE) {
4169 *type = pci_bar_mem32;
4170 return dev->rom_base_reg;
4171 } else if (resno < PCI_BRIDGE_RESOURCES) {
4172 /* device specific resource */
4173 *type = pci_bar_unknown;
4174 reg = pci_iov_resource_bar(dev, resno);
4179 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4183 /* Some architectures require additional programming to enable VGA */
4184 static arch_set_vga_state_t arch_set_vga_state;
4186 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4188 arch_set_vga_state = func; /* NULL disables */
4191 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4192 unsigned int command_bits, u32 flags)
4194 if (arch_set_vga_state)
4195 return arch_set_vga_state(dev, decode, command_bits,
4201 * pci_set_vga_state - set VGA decode state on device and parents if requested
4202 * @dev: the PCI device
4203 * @decode: true = enable decoding, false = disable decoding
4204 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4205 * @flags: traverse ancestors and change bridges
4206 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4208 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4209 unsigned int command_bits, u32 flags)
4211 struct pci_bus *bus;
4212 struct pci_dev *bridge;
4216 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4218 /* ARCH specific VGA enables */
4219 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4223 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4224 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4226 cmd |= command_bits;
4228 cmd &= ~command_bits;
4229 pci_write_config_word(dev, PCI_COMMAND, cmd);
4232 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4239 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4242 cmd |= PCI_BRIDGE_CTL_VGA;
4244 cmd &= ~PCI_BRIDGE_CTL_VGA;
4245 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4253 bool pci_device_is_present(struct pci_dev *pdev)
4257 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4259 EXPORT_SYMBOL_GPL(pci_device_is_present);
4261 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4262 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4263 static DEFINE_SPINLOCK(resource_alignment_lock);
4266 * pci_specified_resource_alignment - get resource alignment specified by user.
4267 * @dev: the PCI device to get
4269 * RETURNS: Resource alignment if it is specified.
4270 * Zero if it is not specified.
4272 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4274 int seg, bus, slot, func, align_order, count;
4275 resource_size_t align = 0;
4278 spin_lock(&resource_alignment_lock);
4279 p = resource_alignment_param;
4282 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4288 if (sscanf(p, "%x:%x:%x.%x%n",
4289 &seg, &bus, &slot, &func, &count) != 4) {
4291 if (sscanf(p, "%x:%x.%x%n",
4292 &bus, &slot, &func, &count) != 3) {
4293 /* Invalid format */
4294 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4300 if (seg == pci_domain_nr(dev->bus) &&
4301 bus == dev->bus->number &&
4302 slot == PCI_SLOT(dev->devfn) &&
4303 func == PCI_FUNC(dev->devfn)) {
4304 if (align_order == -1)
4307 align = 1 << align_order;
4311 if (*p != ';' && *p != ',') {
4312 /* End of param or invalid format */
4317 spin_unlock(&resource_alignment_lock);
4322 * This function disables memory decoding and releases memory resources
4323 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4324 * It also rounds up size to specified alignment.
4325 * Later on, the kernel will assign page-aligned memory resource back
4328 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4332 resource_size_t align, size;
4335 /* check if specified PCI is target device to reassign */
4336 align = pci_specified_resource_alignment(dev);
4340 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4341 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4343 "Can't reassign resources to host bridge.\n");
4348 "Disabling memory decoding and releasing memory resources.\n");
4349 pci_read_config_word(dev, PCI_COMMAND, &command);
4350 command &= ~PCI_COMMAND_MEMORY;
4351 pci_write_config_word(dev, PCI_COMMAND, command);
4353 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4354 r = &dev->resource[i];
4355 if (!(r->flags & IORESOURCE_MEM))
4357 size = resource_size(r);
4361 "Rounding up size of resource #%d to %#llx.\n",
4362 i, (unsigned long long)size);
4364 r->flags |= IORESOURCE_UNSET;
4368 /* Need to disable bridge's resource window,
4369 * to enable the kernel to reassign new resource
4372 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4373 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4374 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4375 r = &dev->resource[i];
4376 if (!(r->flags & IORESOURCE_MEM))
4378 r->flags |= IORESOURCE_UNSET;
4379 r->end = resource_size(r) - 1;
4382 pci_disable_bridge_window(dev);
4386 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4388 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4389 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4390 spin_lock(&resource_alignment_lock);
4391 strncpy(resource_alignment_param, buf, count);
4392 resource_alignment_param[count] = '\0';
4393 spin_unlock(&resource_alignment_lock);
4397 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4400 spin_lock(&resource_alignment_lock);
4401 count = snprintf(buf, size, "%s", resource_alignment_param);
4402 spin_unlock(&resource_alignment_lock);
4406 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4408 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4411 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4412 const char *buf, size_t count)
4414 return pci_set_resource_alignment_param(buf, count);
4417 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4418 pci_resource_alignment_store);
4420 static int __init pci_resource_alignment_sysfs_init(void)
4422 return bus_create_file(&pci_bus_type,
4423 &bus_attr_resource_alignment);
4425 late_initcall(pci_resource_alignment_sysfs_init);
4427 static void pci_no_domains(void)
4429 #ifdef CONFIG_PCI_DOMAINS
4430 pci_domains_supported = 0;
4434 #ifdef CONFIG_PCI_DOMAINS
4435 static atomic_t __domain_nr = ATOMIC_INIT(-1);
4437 int pci_get_new_domain_nr(void)
4439 return atomic_inc_return(&__domain_nr);
4444 * pci_ext_cfg_avail - can we access extended PCI config space?
4446 * Returns 1 if we can access PCI extended config space (offsets
4447 * greater than 0xff). This is the default implementation. Architecture
4448 * implementations can override this.
4450 int __weak pci_ext_cfg_avail(void)
4455 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4458 EXPORT_SYMBOL(pci_fixup_cardbus);
4460 static int __init pci_setup(char *str)
4463 char *k = strchr(str, ',');
4466 if (*str && (str = pcibios_setup(str)) && *str) {
4467 if (!strcmp(str, "nomsi")) {
4469 } else if (!strcmp(str, "noaer")) {
4471 } else if (!strncmp(str, "realloc=", 8)) {
4472 pci_realloc_get_opt(str + 8);
4473 } else if (!strncmp(str, "realloc", 7)) {
4474 pci_realloc_get_opt("on");
4475 } else if (!strcmp(str, "nodomains")) {
4477 } else if (!strncmp(str, "noari", 5)) {
4478 pcie_ari_disabled = true;
4479 } else if (!strncmp(str, "cbiosize=", 9)) {
4480 pci_cardbus_io_size = memparse(str + 9, &str);
4481 } else if (!strncmp(str, "cbmemsize=", 10)) {
4482 pci_cardbus_mem_size = memparse(str + 10, &str);
4483 } else if (!strncmp(str, "resource_alignment=", 19)) {
4484 pci_set_resource_alignment_param(str + 19,
4486 } else if (!strncmp(str, "ecrc=", 5)) {
4487 pcie_ecrc_get_policy(str + 5);
4488 } else if (!strncmp(str, "hpiosize=", 9)) {
4489 pci_hotplug_io_size = memparse(str + 9, &str);
4490 } else if (!strncmp(str, "hpmemsize=", 10)) {
4491 pci_hotplug_mem_size = memparse(str + 10, &str);
4492 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4493 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4494 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4495 pcie_bus_config = PCIE_BUS_SAFE;
4496 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4497 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4498 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4499 pcie_bus_config = PCIE_BUS_PEER2PEER;
4500 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4501 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4503 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4511 early_param("pci", pci_setup);