2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/pci_hotplug.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/cpumask.h>
13 #include <linux/pci-aspm.h>
14 #include <asm-generic/pci-bridge.h>
17 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
18 #define CARDBUS_RESERVE_BUSNR 3
20 static struct resource busn_resource = {
24 .flags = IORESOURCE_BUS,
27 /* Ugh. Need to stop exporting this to modules. */
28 LIST_HEAD(pci_root_buses);
29 EXPORT_SYMBOL(pci_root_buses);
31 static LIST_HEAD(pci_domain_busn_res_list);
33 struct pci_domain_busn_res {
34 struct list_head list;
39 static struct resource *get_pci_domain_busn_res(int domain_nr)
41 struct pci_domain_busn_res *r;
43 list_for_each_entry(r, &pci_domain_busn_res_list, list)
44 if (r->domain_nr == domain_nr)
47 r = kzalloc(sizeof(*r), GFP_KERNEL);
51 r->domain_nr = domain_nr;
54 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
56 list_add_tail(&r->list, &pci_domain_busn_res_list);
61 static int find_anything(struct device *dev, void *data)
67 * Some device drivers need know if pci is initiated.
68 * Basically, we think pci is not initiated when there
69 * is no device to be found on the pci_bus_type.
71 int no_pci_devices(void)
76 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
77 no_devices = (dev == NULL);
81 EXPORT_SYMBOL(no_pci_devices);
86 static void release_pcibus_dev(struct device *dev)
88 struct pci_bus *pci_bus = to_pci_bus(dev);
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 pci_release_bus_of_node(pci_bus);
97 static struct class pcibus_class = {
99 .dev_release = &release_pcibus_dev,
100 .dev_groups = pcibus_groups,
103 static int __init pcibus_class_init(void)
105 return class_register(&pcibus_class);
107 postcore_initcall(pcibus_class_init);
109 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111 u64 size = mask & maxbase; /* Find the significant bits */
115 /* Get the lowest of them to find the decode size, and
116 from that the extent. */
117 size = (size & ~(size-1)) - 1;
119 /* base == maxbase can be valid only if the BAR has
120 already been programmed with all 1s. */
121 if (base == maxbase && ((base | size) & mask) != mask)
127 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
133 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
134 flags |= IORESOURCE_IO;
138 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
139 flags |= IORESOURCE_MEM;
140 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
141 flags |= IORESOURCE_PREFETCH;
143 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
145 case PCI_BASE_ADDRESS_MEM_TYPE_32:
147 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
148 /* 1M mem BAR treated as 32-bit BAR */
150 case PCI_BASE_ADDRESS_MEM_TYPE_64:
151 flags |= IORESOURCE_MEM_64;
154 /* mem unknown type treated as 32-bit BAR */
160 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
163 * pci_read_base - read a PCI BAR
164 * @dev: the PCI device
165 * @type: type of the BAR
166 * @res: resource buffer to be filled in
167 * @pos: BAR position in the config space
169 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
171 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
172 struct resource *res, unsigned int pos)
175 u64 l64, sz64, mask64;
177 struct pci_bus_region region, inverted_region;
178 bool bar_too_big = false, bar_too_high = false, bar_invalid = false;
180 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
182 /* No printks while decoding is disabled! */
183 if (!dev->mmio_always_on) {
184 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
185 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
186 pci_write_config_word(dev, PCI_COMMAND,
187 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 res->name = pci_name(dev);
193 pci_read_config_dword(dev, pos, &l);
194 pci_write_config_dword(dev, pos, l | mask);
195 pci_read_config_dword(dev, pos, &sz);
196 pci_write_config_dword(dev, pos, l);
199 * All bits set in sz means the device isn't working properly.
200 * If the BAR isn't implemented, all bits must be 0. If it's a
201 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 if (!sz || sz == 0xffffffff)
208 * I don't know how l can have all bits set. Copied from old code.
209 * Maybe it fixes a bug on some ancient platform.
214 if (type == pci_bar_unknown) {
215 res->flags = decode_bar(dev, l);
216 res->flags |= IORESOURCE_SIZEALIGN;
217 if (res->flags & IORESOURCE_IO) {
218 l &= PCI_BASE_ADDRESS_IO_MASK;
219 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
221 l &= PCI_BASE_ADDRESS_MEM_MASK;
222 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
225 res->flags |= (l & IORESOURCE_ROM_ENABLE);
226 l &= PCI_ROM_ADDRESS_MASK;
227 mask = (u32)PCI_ROM_ADDRESS_MASK;
230 if (res->flags & IORESOURCE_MEM_64) {
233 mask64 = mask | (u64)~0 << 32;
235 pci_read_config_dword(dev, pos + 4, &l);
236 pci_write_config_dword(dev, pos + 4, ~0);
237 pci_read_config_dword(dev, pos + 4, &sz);
238 pci_write_config_dword(dev, pos + 4, l);
240 l64 |= ((u64)l << 32);
241 sz64 |= ((u64)sz << 32);
243 sz64 = pci_size(l64, sz64, mask64);
248 if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
249 sz64 > 0x100000000ULL) {
250 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
257 if ((sizeof(dma_addr_t) < 8) && l) {
258 /* Above 32-bit boundary; try to reallocate */
259 res->flags |= IORESOURCE_UNSET;
266 region.end = l64 + sz64;
269 sz = pci_size(l, sz, mask);
278 pcibios_bus_to_resource(dev->bus, res, ®ion);
279 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
282 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
283 * the corresponding resource address (the physical address used by
284 * the CPU. Converting that resource address back to a bus address
285 * should yield the original BAR value:
287 * resource_to_bus(bus_to_resource(A)) == A
289 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
290 * be claimed by the device.
292 if (inverted_region.start != region.start) {
293 res->flags |= IORESOURCE_UNSET;
295 res->end = region.end - region.start;
305 if (!dev->mmio_always_on &&
306 (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
307 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
310 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
311 pos, (unsigned long long) sz64);
313 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4G (bus address %#010llx)\n",
314 pos, (unsigned long long) l64);
316 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
317 pos, (unsigned long long) region.start);
319 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
321 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
324 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
326 unsigned int pos, reg;
328 for (pos = 0; pos < howmany; pos++) {
329 struct resource *res = &dev->resource[pos];
330 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
331 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
335 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
336 dev->rom_base_reg = rom;
337 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
338 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
339 IORESOURCE_SIZEALIGN;
340 __pci_read_base(dev, pci_bar_mem32, res, rom);
344 static void pci_read_bridge_io(struct pci_bus *child)
346 struct pci_dev *dev = child->self;
347 u8 io_base_lo, io_limit_lo;
348 unsigned long io_mask, io_granularity, base, limit;
349 struct pci_bus_region region;
350 struct resource *res;
352 io_mask = PCI_IO_RANGE_MASK;
353 io_granularity = 0x1000;
354 if (dev->io_window_1k) {
355 /* Support 1K I/O space granularity */
356 io_mask = PCI_IO_1K_RANGE_MASK;
357 io_granularity = 0x400;
360 res = child->resource[0];
361 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
362 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
363 base = (io_base_lo & io_mask) << 8;
364 limit = (io_limit_lo & io_mask) << 8;
366 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
367 u16 io_base_hi, io_limit_hi;
369 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
370 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
371 base |= ((unsigned long) io_base_hi << 16);
372 limit |= ((unsigned long) io_limit_hi << 16);
376 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
378 region.end = limit + io_granularity - 1;
379 pcibios_bus_to_resource(dev->bus, res, ®ion);
380 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
384 static void pci_read_bridge_mmio(struct pci_bus *child)
386 struct pci_dev *dev = child->self;
387 u16 mem_base_lo, mem_limit_lo;
388 unsigned long base, limit;
389 struct pci_bus_region region;
390 struct resource *res;
392 res = child->resource[1];
393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
400 region.end = limit + 0xfffff;
401 pcibios_bus_to_resource(dev->bus, res, ®ion);
402 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
406 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
408 struct pci_dev *dev = child->self;
409 u16 mem_base_lo, mem_limit_lo;
410 unsigned long base, limit;
411 struct pci_bus_region region;
412 struct resource *res;
414 res = child->resource[2];
415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
417 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
418 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
421 u32 mem_base_hi, mem_limit_hi;
423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
427 * Some bridges set the base > limit by default, and some
428 * (broken) BIOSes do not initialize them. If we find
429 * this, just assume they are not being used.
431 if (mem_base_hi <= mem_limit_hi) {
432 #if BITS_PER_LONG == 64
433 base |= ((unsigned long) mem_base_hi) << 32;
434 limit |= ((unsigned long) mem_limit_hi) << 32;
436 if (mem_base_hi || mem_limit_hi) {
437 dev_err(&dev->dev, "can't handle 64-bit address space for bridge\n");
444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
449 region.end = limit + 0xfffff;
450 pcibios_bus_to_resource(dev->bus, res, ®ion);
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
455 void pci_read_bridge_bases(struct pci_bus *child)
457 struct pci_dev *dev = child->self;
458 struct resource *res;
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
466 dev->transparent ? " (subtractive decode)" : "");
468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
476 if (dev->transparent) {
477 pci_bus_for_each_resource(child->parent, res, i) {
478 if (res && res->flags) {
479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
489 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
493 b = kzalloc(sizeof(*b), GFP_KERNEL);
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
504 #ifdef CONFIG_PCI_DOMAINS_GENERIC
506 b->domain_nr = parent->domain_nr;
511 static void pci_release_host_bridge_dev(struct device *dev)
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
515 if (bridge->release_fn)
516 bridge->release_fn(bridge);
518 pci_free_resource_list(&bridge->windows);
523 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
525 struct pci_host_bridge *bridge;
527 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
531 INIT_LIST_HEAD(&bridge->windows);
536 static const unsigned char pcix_bus_speed[] = {
537 PCI_SPEED_UNKNOWN, /* 0 */
538 PCI_SPEED_66MHz_PCIX, /* 1 */
539 PCI_SPEED_100MHz_PCIX, /* 2 */
540 PCI_SPEED_133MHz_PCIX, /* 3 */
541 PCI_SPEED_UNKNOWN, /* 4 */
542 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
543 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
544 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
545 PCI_SPEED_UNKNOWN, /* 8 */
546 PCI_SPEED_66MHz_PCIX_266, /* 9 */
547 PCI_SPEED_100MHz_PCIX_266, /* A */
548 PCI_SPEED_133MHz_PCIX_266, /* B */
549 PCI_SPEED_UNKNOWN, /* C */
550 PCI_SPEED_66MHz_PCIX_533, /* D */
551 PCI_SPEED_100MHz_PCIX_533, /* E */
552 PCI_SPEED_133MHz_PCIX_533 /* F */
555 const unsigned char pcie_link_speed[] = {
556 PCI_SPEED_UNKNOWN, /* 0 */
557 PCIE_SPEED_2_5GT, /* 1 */
558 PCIE_SPEED_5_0GT, /* 2 */
559 PCIE_SPEED_8_0GT, /* 3 */
560 PCI_SPEED_UNKNOWN, /* 4 */
561 PCI_SPEED_UNKNOWN, /* 5 */
562 PCI_SPEED_UNKNOWN, /* 6 */
563 PCI_SPEED_UNKNOWN, /* 7 */
564 PCI_SPEED_UNKNOWN, /* 8 */
565 PCI_SPEED_UNKNOWN, /* 9 */
566 PCI_SPEED_UNKNOWN, /* A */
567 PCI_SPEED_UNKNOWN, /* B */
568 PCI_SPEED_UNKNOWN, /* C */
569 PCI_SPEED_UNKNOWN, /* D */
570 PCI_SPEED_UNKNOWN, /* E */
571 PCI_SPEED_UNKNOWN /* F */
574 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
576 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
578 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
580 static unsigned char agp_speeds[] = {
588 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
594 else if (agpstat & 2)
596 else if (agpstat & 1)
608 return agp_speeds[index];
611 static void pci_set_bus_speed(struct pci_bus *bus)
613 struct pci_dev *bridge = bus->self;
616 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
618 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
622 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
623 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
625 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
626 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
629 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
632 enum pci_bus_speed max;
634 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
637 if (status & PCI_X_SSTATUS_533MHZ) {
638 max = PCI_SPEED_133MHz_PCIX_533;
639 } else if (status & PCI_X_SSTATUS_266MHZ) {
640 max = PCI_SPEED_133MHz_PCIX_266;
641 } else if (status & PCI_X_SSTATUS_133MHZ) {
642 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
643 max = PCI_SPEED_133MHz_PCIX_ECC;
645 max = PCI_SPEED_133MHz_PCIX;
647 max = PCI_SPEED_66MHz_PCIX;
650 bus->max_bus_speed = max;
651 bus->cur_bus_speed = pcix_bus_speed[
652 (status & PCI_X_SSTATUS_FREQ) >> 6];
657 if (pci_is_pcie(bridge)) {
661 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
662 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
664 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
665 pcie_update_link_speed(bus, linksta);
669 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
670 struct pci_dev *bridge, int busnr)
672 struct pci_bus *child;
677 * Allocate a new bus, and inherit stuff from the parent..
679 child = pci_alloc_bus(parent);
683 child->parent = parent;
684 child->ops = parent->ops;
685 child->msi = parent->msi;
686 child->sysdata = parent->sysdata;
687 child->bus_flags = parent->bus_flags;
689 /* initialize some portions of the bus device, but don't register it
690 * now as the parent is not properly set up yet.
692 child->dev.class = &pcibus_class;
693 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
696 * Set up the primary, secondary and subordinate
699 child->number = child->busn_res.start = busnr;
700 child->primary = parent->busn_res.start;
701 child->busn_res.end = 0xff;
704 child->dev.parent = parent->bridge;
708 child->self = bridge;
709 child->bridge = get_device(&bridge->dev);
710 child->dev.parent = child->bridge;
711 pci_set_bus_of_node(child);
712 pci_set_bus_speed(child);
714 /* Set up default resource pointers and names.. */
715 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
716 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
717 child->resource[i]->name = child->name;
719 bridge->subordinate = child;
722 ret = device_register(&child->dev);
725 pcibios_add_bus(child);
727 /* Create legacy_io and legacy_mem files for this bus */
728 pci_create_legacy_files(child);
733 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
736 struct pci_bus *child;
738 child = pci_alloc_child_bus(parent, dev, busnr);
740 down_write(&pci_bus_sem);
741 list_add_tail(&child->node, &parent->children);
742 up_write(&pci_bus_sem);
746 EXPORT_SYMBOL(pci_add_new_bus);
748 static void pci_enable_crs(struct pci_dev *pdev)
752 /* Enable CRS Software Visibility if supported */
753 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
754 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
755 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
756 PCI_EXP_RTCTL_CRSSVE);
760 * If it's a bridge, configure it and scan the bus behind it.
761 * For CardBus bridges, we don't scan behind as the devices will
762 * be handled by the bridge driver itself.
764 * We need to process bridges in two passes -- first we scan those
765 * already configured by the BIOS and after we are done with all of
766 * them, we proceed to assigning numbers to the remaining buses in
767 * order to avoid overlaps between old and new bus numbers.
769 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
771 struct pci_bus *child;
772 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
775 u8 primary, secondary, subordinate;
778 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
779 primary = buses & 0xFF;
780 secondary = (buses >> 8) & 0xFF;
781 subordinate = (buses >> 16) & 0xFF;
783 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
784 secondary, subordinate, pass);
786 if (!primary && (primary != bus->number) && secondary && subordinate) {
787 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
788 primary = bus->number;
791 /* Check if setup is sensible at all */
793 (primary != bus->number || secondary <= bus->number ||
794 secondary > subordinate)) {
795 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
796 secondary, subordinate);
800 /* Disable MasterAbortMode during probing to avoid reporting
801 of bus errors (in some architectures) */
802 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
803 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
804 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
808 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
809 !is_cardbus && !broken) {
812 * Bus already configured by firmware, process it in the first
813 * pass and just note the configuration.
819 * The bus might already exist for two reasons: Either we are
820 * rescanning the bus or the bus is reachable through more than
821 * one bridge. The second case can happen with the i450NX
824 child = pci_find_bus(pci_domain_nr(bus), secondary);
826 child = pci_add_new_bus(bus, dev, secondary);
829 child->primary = primary;
830 pci_bus_insert_busn_res(child, secondary, subordinate);
831 child->bridge_ctl = bctl;
834 cmax = pci_scan_child_bus(child);
835 if (cmax > subordinate)
836 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
838 /* subordinate should equal child->busn_res.end */
839 if (subordinate > max)
843 * We need to assign a number to this bus which we always
844 * do in the second pass.
847 if (pcibios_assign_all_busses() || broken || is_cardbus)
848 /* Temporarily disable forwarding of the
849 configuration cycles on all bridges in
850 this bus segment to avoid possible
851 conflicts in the second pass between two
852 bridges programmed with overlapping
854 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
860 pci_write_config_word(dev, PCI_STATUS, 0xffff);
862 /* Prevent assigning a bus number that already exists.
863 * This can happen when a bridge is hot-plugged, so in
864 * this case we only re-scan this bus. */
865 child = pci_find_bus(pci_domain_nr(bus), max+1);
867 child = pci_add_new_bus(bus, dev, max+1);
870 pci_bus_insert_busn_res(child, max+1, 0xff);
873 buses = (buses & 0xff000000)
874 | ((unsigned int)(child->primary) << 0)
875 | ((unsigned int)(child->busn_res.start) << 8)
876 | ((unsigned int)(child->busn_res.end) << 16);
879 * yenta.c forces a secondary latency timer of 176.
880 * Copy that behaviour here.
883 buses &= ~0xff000000;
884 buses |= CARDBUS_LATENCY_TIMER << 24;
888 * We need to blast all three values with a single write.
890 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
893 child->bridge_ctl = bctl;
894 max = pci_scan_child_bus(child);
897 * For CardBus bridges, we leave 4 bus numbers
898 * as cards with a PCI-to-PCI bridge can be
901 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
902 struct pci_bus *parent = bus;
903 if (pci_find_bus(pci_domain_nr(bus),
906 while (parent->parent) {
907 if ((!pcibios_assign_all_busses()) &&
908 (parent->busn_res.end > max) &&
909 (parent->busn_res.end <= max+i)) {
912 parent = parent->parent;
916 * Often, there are two cardbus bridges
917 * -- try to leave one valid bus number
927 * Set the subordinate bus number to its real value.
929 pci_bus_update_busn_res_end(child, max);
930 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
934 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
935 pci_domain_nr(bus), child->number);
937 /* Has only triggered on CardBus, fixup is in yenta_socket */
938 while (bus->parent) {
939 if ((child->busn_res.end > bus->busn_res.end) ||
940 (child->number > bus->busn_res.end) ||
941 (child->number < bus->number) ||
942 (child->busn_res.end < bus->number)) {
943 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
945 (bus->number > child->busn_res.end &&
946 bus->busn_res.end < child->number) ?
947 "wholly" : "partially",
948 bus->self->transparent ? " transparent" : "",
956 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
960 EXPORT_SYMBOL(pci_scan_bridge);
963 * Read interrupt line and base address registers.
964 * The architecture-dependent code can tweak these, of course.
966 static void pci_read_irq(struct pci_dev *dev)
970 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
973 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
977 void set_pcie_port_type(struct pci_dev *pdev)
982 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
985 pdev->pcie_cap = pos;
986 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
987 pdev->pcie_flags_reg = reg16;
988 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
989 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
992 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
996 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
997 if (reg32 & PCI_EXP_SLTCAP_HPC)
998 pdev->is_hotplug_bridge = 1;
1002 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1005 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1006 * when forwarding a type1 configuration request the bridge must check that
1007 * the extended register address field is zero. The bridge is not permitted
1008 * to forward the transactions and must handle it as an Unsupported Request.
1009 * Some bridges do not follow this rule and simply drop the extended register
1010 * bits, resulting in the standard config space being aliased, every 256
1011 * bytes across the entire configuration space. Test for this condition by
1012 * comparing the first dword of each potential alias to the vendor/device ID.
1014 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1015 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1017 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1019 #ifdef CONFIG_PCI_QUIRKS
1023 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1025 for (pos = PCI_CFG_SPACE_SIZE;
1026 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1027 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1039 * pci_cfg_space_size - get the configuration space size of the PCI device.
1042 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1043 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1044 * access it. Maybe we don't have a way to generate extended config space
1045 * accesses, or the device is behind a reverse Express bridge. So we try
1046 * reading the dword at 0x100 which must either be 0 or a valid extended
1047 * capability header.
1049 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1052 int pos = PCI_CFG_SPACE_SIZE;
1054 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1056 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1059 return PCI_CFG_SPACE_EXP_SIZE;
1062 return PCI_CFG_SPACE_SIZE;
1065 int pci_cfg_space_size(struct pci_dev *dev)
1071 class = dev->class >> 8;
1072 if (class == PCI_CLASS_BRIDGE_HOST)
1073 return pci_cfg_space_size_ext(dev);
1075 if (!pci_is_pcie(dev)) {
1076 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1080 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1081 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1085 return pci_cfg_space_size_ext(dev);
1088 return PCI_CFG_SPACE_SIZE;
1091 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1094 * pci_setup_device - fill in class and map information of a device
1095 * @dev: the device structure to fill
1097 * Initialize the device structure with information about the device's
1098 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1099 * Called at initialisation of the PCI subsystem and by CardBus services.
1100 * Returns 0 on success and negative if unknown type of device (not normal,
1101 * bridge or CardBus).
1103 int pci_setup_device(struct pci_dev *dev)
1107 struct pci_slot *slot;
1109 struct pci_bus_region region;
1110 struct resource *res;
1112 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1115 dev->sysdata = dev->bus->sysdata;
1116 dev->dev.parent = dev->bus->bridge;
1117 dev->dev.bus = &pci_bus_type;
1118 dev->hdr_type = hdr_type & 0x7f;
1119 dev->multifunction = !!(hdr_type & 0x80);
1120 dev->error_state = pci_channel_io_normal;
1121 set_pcie_port_type(dev);
1123 list_for_each_entry(slot, &dev->bus->slots, list)
1124 if (PCI_SLOT(dev->devfn) == slot->number)
1127 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1128 set this higher, assuming the system even supports it. */
1129 dev->dma_mask = 0xffffffff;
1131 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1132 dev->bus->number, PCI_SLOT(dev->devfn),
1133 PCI_FUNC(dev->devfn));
1135 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1136 dev->revision = class & 0xff;
1137 dev->class = class >> 8; /* upper 3 bytes */
1139 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1140 dev->vendor, dev->device, dev->hdr_type, dev->class);
1142 /* need to have dev->class ready */
1143 dev->cfg_size = pci_cfg_space_size(dev);
1145 /* "Unknown power state" */
1146 dev->current_state = PCI_UNKNOWN;
1148 /* Early fixups, before probing the BARs */
1149 pci_fixup_device(pci_fixup_early, dev);
1150 /* device class may be changed after fixup */
1151 class = dev->class >> 8;
1153 switch (dev->hdr_type) { /* header type */
1154 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1155 if (class == PCI_CLASS_BRIDGE_PCI)
1158 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1159 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1160 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1163 * Do the ugly legacy mode stuff here rather than broken chip
1164 * quirk code. Legacy mode ATA controllers have fixed
1165 * addresses. These are not always echoed in BAR0-3, and
1166 * BAR0-3 in a few cases contain junk!
1168 if (class == PCI_CLASS_STORAGE_IDE) {
1170 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1171 if ((progif & 1) == 0) {
1172 region.start = 0x1F0;
1174 res = &dev->resource[0];
1175 res->flags = LEGACY_IO_RESOURCE;
1176 pcibios_bus_to_resource(dev->bus, res, ®ion);
1177 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1179 region.start = 0x3F6;
1181 res = &dev->resource[1];
1182 res->flags = LEGACY_IO_RESOURCE;
1183 pcibios_bus_to_resource(dev->bus, res, ®ion);
1184 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1187 if ((progif & 4) == 0) {
1188 region.start = 0x170;
1190 res = &dev->resource[2];
1191 res->flags = LEGACY_IO_RESOURCE;
1192 pcibios_bus_to_resource(dev->bus, res, ®ion);
1193 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1195 region.start = 0x376;
1197 res = &dev->resource[3];
1198 res->flags = LEGACY_IO_RESOURCE;
1199 pcibios_bus_to_resource(dev->bus, res, ®ion);
1200 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1206 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1207 if (class != PCI_CLASS_BRIDGE_PCI)
1209 /* The PCI-to-PCI bridge spec requires that subtractive
1210 decoding (i.e. transparent) bridge must have programming
1211 interface code of 0x01. */
1213 dev->transparent = ((dev->class & 0xff) == 1);
1214 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1215 set_pcie_hotplug_bridge(dev);
1216 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1218 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1219 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1223 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1224 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1227 pci_read_bases(dev, 1, 0);
1228 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1229 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1232 default: /* unknown header */
1233 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1238 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1239 dev->class, dev->hdr_type);
1240 dev->class = PCI_CLASS_NOT_DEFINED;
1243 /* We found a fine healthy device, go go go... */
1247 static struct hpp_type0 pci_default_type0 = {
1249 .cache_line_size = 8,
1250 .latency_timer = 0x40,
1255 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1257 u16 pci_cmd, pci_bctl;
1260 hpp = &pci_default_type0;
1262 if (hpp->revision > 1) {
1264 "PCI settings rev %d not supported; using defaults\n",
1266 hpp = &pci_default_type0;
1269 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1270 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1271 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1272 if (hpp->enable_serr)
1273 pci_cmd |= PCI_COMMAND_SERR;
1274 if (hpp->enable_perr)
1275 pci_cmd |= PCI_COMMAND_PARITY;
1276 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1278 /* Program bridge control value */
1279 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1280 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1281 hpp->latency_timer);
1282 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1283 if (hpp->enable_serr)
1284 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1285 if (hpp->enable_perr)
1286 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1287 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1291 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1294 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1297 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1305 if (hpp->revision > 1) {
1306 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1312 * Don't allow _HPX to change MPS or MRRS settings. We manage
1313 * those to make sure they're consistent with the rest of the
1316 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1317 PCI_EXP_DEVCTL_READRQ;
1318 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1319 PCI_EXP_DEVCTL_READRQ);
1321 /* Initialize Device Control Register */
1322 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1323 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1325 /* Initialize Link Control Register */
1326 if (dev->subordinate)
1327 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1328 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1330 /* Find Advanced Error Reporting Enhanced Capability */
1331 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1335 /* Initialize Uncorrectable Error Mask Register */
1336 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1337 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1338 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1340 /* Initialize Uncorrectable Error Severity Register */
1341 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1342 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1343 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1345 /* Initialize Correctable Error Mask Register */
1346 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1347 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1348 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1350 /* Initialize Advanced Error Capabilities and Control Register */
1351 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1352 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1353 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1356 * FIXME: The following two registers are not supported yet.
1358 * o Secondary Uncorrectable Error Severity Register
1359 * o Secondary Uncorrectable Error Mask Register
1363 static void pci_configure_device(struct pci_dev *dev)
1365 struct hotplug_params hpp;
1368 memset(&hpp, 0, sizeof(hpp));
1369 ret = pci_get_hp_params(dev, &hpp);
1373 program_hpp_type2(dev, hpp.t2);
1374 program_hpp_type1(dev, hpp.t1);
1375 program_hpp_type0(dev, hpp.t0);
1378 static void pci_release_capabilities(struct pci_dev *dev)
1380 pci_vpd_release(dev);
1381 pci_iov_release(dev);
1382 pci_free_cap_save_buffers(dev);
1386 * pci_release_dev - free a pci device structure when all users of it are finished.
1387 * @dev: device that's been disconnected
1389 * Will be called only by the device core when all users of this pci device are
1392 static void pci_release_dev(struct device *dev)
1394 struct pci_dev *pci_dev;
1396 pci_dev = to_pci_dev(dev);
1397 pci_release_capabilities(pci_dev);
1398 pci_release_of_node(pci_dev);
1399 pcibios_release_device(pci_dev);
1400 pci_bus_put(pci_dev->bus);
1401 kfree(pci_dev->driver_override);
1405 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1407 struct pci_dev *dev;
1409 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1413 INIT_LIST_HEAD(&dev->bus_list);
1414 dev->dev.type = &pci_dev_type;
1415 dev->bus = pci_bus_get(bus);
1419 EXPORT_SYMBOL(pci_alloc_dev);
1421 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1426 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1429 /* some broken boards return 0 or ~0 if a slot is empty: */
1430 if (*l == 0xffffffff || *l == 0x00000000 ||
1431 *l == 0x0000ffff || *l == 0xffff0000)
1435 * Configuration Request Retry Status. Some root ports return the
1436 * actual device ID instead of the synthetic ID (0xFFFF) required
1437 * by the PCIe spec. Ignore the device ID and only check for
1440 while ((*l & 0xffff) == 0x0001) {
1446 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1448 /* Card hasn't responded in 60 seconds? Must be stuck. */
1449 if (delay > crs_timeout) {
1450 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1451 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1459 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1462 * Read the config data for a PCI device, sanity-check it
1463 * and fill in the dev structure...
1465 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1467 struct pci_dev *dev;
1470 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1473 dev = pci_alloc_dev(bus);
1478 dev->vendor = l & 0xffff;
1479 dev->device = (l >> 16) & 0xffff;
1481 pci_set_of_node(dev);
1483 if (pci_setup_device(dev)) {
1484 pci_bus_put(dev->bus);
1492 static void pci_init_capabilities(struct pci_dev *dev)
1494 /* MSI/MSI-X list */
1495 pci_msi_init_pci_dev(dev);
1497 /* Buffers for saving PCIe and PCI-X capabilities */
1498 pci_allocate_cap_save_buffers(dev);
1500 /* Power Management */
1503 /* Vital Product Data */
1504 pci_vpd_pci22_init(dev);
1506 /* Alternative Routing-ID Forwarding */
1507 pci_configure_ari(dev);
1509 /* Single Root I/O Virtualization */
1512 /* Enable ACS P2P upstream forwarding */
1513 pci_enable_acs(dev);
1516 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1520 pci_configure_device(dev);
1522 device_initialize(&dev->dev);
1523 dev->dev.release = pci_release_dev;
1525 set_dev_node(&dev->dev, pcibus_to_node(bus));
1526 dev->dev.dma_mask = &dev->dma_mask;
1527 dev->dev.dma_parms = &dev->dma_parms;
1528 dev->dev.coherent_dma_mask = 0xffffffffull;
1530 pci_set_dma_max_seg_size(dev, 65536);
1531 pci_set_dma_seg_boundary(dev, 0xffffffff);
1533 /* Fix up broken headers */
1534 pci_fixup_device(pci_fixup_header, dev);
1536 /* moved out from quirk header fixup code */
1537 pci_reassigndev_resource_alignment(dev);
1539 /* Clear the state_saved flag. */
1540 dev->state_saved = false;
1542 /* Initialize various capabilities */
1543 pci_init_capabilities(dev);
1546 * Add the device to our list of discovered devices
1547 * and the bus list for fixup functions, etc.
1549 down_write(&pci_bus_sem);
1550 list_add_tail(&dev->bus_list, &bus->devices);
1551 up_write(&pci_bus_sem);
1553 ret = pcibios_add_device(dev);
1556 /* Notifier could use PCI capabilities */
1557 dev->match_driver = false;
1558 ret = device_add(&dev->dev);
1562 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1564 struct pci_dev *dev;
1566 dev = pci_get_slot(bus, devfn);
1572 dev = pci_scan_device(bus, devfn);
1576 pci_device_add(dev, bus);
1580 EXPORT_SYMBOL(pci_scan_single_device);
1582 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1588 if (pci_ari_enabled(bus)) {
1591 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1595 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1596 next_fn = PCI_ARI_CAP_NFN(cap);
1598 return 0; /* protect against malformed list */
1603 /* dev may be NULL for non-contiguous multifunction devices */
1604 if (!dev || dev->multifunction)
1605 return (fn + 1) % 8;
1610 static int only_one_child(struct pci_bus *bus)
1612 struct pci_dev *parent = bus->self;
1614 if (!parent || !pci_is_pcie(parent))
1616 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1618 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
1619 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1625 * pci_scan_slot - scan a PCI slot on a bus for devices.
1626 * @bus: PCI bus to scan
1627 * @devfn: slot number to scan (must have zero function.)
1629 * Scan a PCI slot on the specified PCI bus for devices, adding
1630 * discovered devices to the @bus->devices list. New devices
1631 * will not have is_added set.
1633 * Returns the number of new devices found.
1635 int pci_scan_slot(struct pci_bus *bus, int devfn)
1637 unsigned fn, nr = 0;
1638 struct pci_dev *dev;
1640 if (only_one_child(bus) && (devfn > 0))
1641 return 0; /* Already scanned the entire slot */
1643 dev = pci_scan_single_device(bus, devfn);
1649 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1650 dev = pci_scan_single_device(bus, devfn + fn);
1654 dev->multifunction = 1;
1658 /* only one slot has pcie device */
1659 if (bus->self && nr)
1660 pcie_aspm_init_link_state(bus->self);
1664 EXPORT_SYMBOL(pci_scan_slot);
1666 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1670 if (!pci_is_pcie(dev))
1674 * We don't have a way to change MPS settings on devices that have
1675 * drivers attached. A hot-added device might support only the minimum
1676 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1677 * where devices may be hot-added, we limit the fabric MPS to 128 so
1678 * hot-added devices will work correctly.
1680 * However, if we hot-add a device to a slot directly below a Root
1681 * Port, it's impossible for there to be other existing devices below
1682 * the port. We don't limit the MPS in this case because we can
1683 * reconfigure MPS on both the Root Port and the hot-added device,
1684 * and there are no other devices involved.
1686 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1688 if (dev->is_hotplug_bridge &&
1689 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1692 if (*smpss > dev->pcie_mpss)
1693 *smpss = dev->pcie_mpss;
1698 static void pcie_write_mps(struct pci_dev *dev, int mps)
1702 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1703 mps = 128 << dev->pcie_mpss;
1705 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1707 /* For "Performance", the assumption is made that
1708 * downstream communication will never be larger than
1709 * the MRRS. So, the MPS only needs to be configured
1710 * for the upstream communication. This being the case,
1711 * walk from the top down and set the MPS of the child
1712 * to that of the parent bus.
1714 * Configure the device MPS with the smaller of the
1715 * device MPSS or the bridge MPS (which is assumed to be
1716 * properly configured at this point to the largest
1717 * allowable MPS based on its parent bus).
1719 mps = min(mps, pcie_get_mps(dev->bus->self));
1722 rc = pcie_set_mps(dev, mps);
1724 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1727 static void pcie_write_mrrs(struct pci_dev *dev)
1731 /* In the "safe" case, do not configure the MRRS. There appear to be
1732 * issues with setting MRRS to 0 on a number of devices.
1734 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1737 /* For Max performance, the MRRS must be set to the largest supported
1738 * value. However, it cannot be configured larger than the MPS the
1739 * device or the bus can support. This should already be properly
1740 * configured by a prior call to pcie_write_mps.
1742 mrrs = pcie_get_mps(dev);
1744 /* MRRS is a R/W register. Invalid values can be written, but a
1745 * subsequent read will verify if the value is acceptable or not.
1746 * If the MRRS value provided is not acceptable (e.g., too large),
1747 * shrink the value until it is acceptable to the HW.
1749 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1750 rc = pcie_set_readrq(dev, mrrs);
1754 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1759 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1762 static void pcie_bus_detect_mps(struct pci_dev *dev)
1764 struct pci_dev *bridge = dev->bus->self;
1770 mps = pcie_get_mps(dev);
1771 p_mps = pcie_get_mps(bridge);
1774 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1775 mps, pci_name(bridge), p_mps);
1778 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1782 if (!pci_is_pcie(dev))
1785 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1786 pcie_bus_detect_mps(dev);
1790 mps = 128 << *(u8 *)data;
1791 orig_mps = pcie_get_mps(dev);
1793 pcie_write_mps(dev, mps);
1794 pcie_write_mrrs(dev);
1796 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1797 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1798 orig_mps, pcie_get_readrq(dev));
1803 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1804 * parents then children fashion. If this changes, then this code will not
1807 void pcie_bus_configure_settings(struct pci_bus *bus)
1814 if (!pci_is_pcie(bus->self))
1817 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1818 * to be aware of the MPS of the destination. To work around this,
1819 * simply force the MPS of the entire system to the smallest possible.
1821 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1824 if (pcie_bus_config == PCIE_BUS_SAFE) {
1825 smpss = bus->self->pcie_mpss;
1827 pcie_find_smpss(bus->self, &smpss);
1828 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1831 pcie_bus_configure_set(bus->self, &smpss);
1832 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1834 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1836 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1838 unsigned int devfn, pass, max = bus->busn_res.start;
1839 struct pci_dev *dev;
1841 dev_dbg(&bus->dev, "scanning bus\n");
1843 /* Go find them, Rover! */
1844 for (devfn = 0; devfn < 0x100; devfn += 8)
1845 pci_scan_slot(bus, devfn);
1847 /* Reserve buses for SR-IOV capability. */
1848 max += pci_iov_bus_range(bus);
1851 * After performing arch-dependent fixup of the bus, look behind
1852 * all PCI-to-PCI bridges on this bus.
1854 if (!bus->is_added) {
1855 dev_dbg(&bus->dev, "fixups for bus\n");
1856 pcibios_fixup_bus(bus);
1860 for (pass = 0; pass < 2; pass++)
1861 list_for_each_entry(dev, &bus->devices, bus_list) {
1862 if (pci_is_bridge(dev))
1863 max = pci_scan_bridge(bus, dev, max, pass);
1867 * We've scanned the bus and so we know all about what's on
1868 * the other side of any bridges that may be on this bus plus
1871 * Return how far we've got finding sub-buses.
1873 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1876 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1879 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1880 * @bridge: Host bridge to set up.
1882 * Default empty implementation. Replace with an architecture-specific setup
1883 * routine, if necessary.
1885 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1890 void __weak pcibios_add_bus(struct pci_bus *bus)
1894 void __weak pcibios_remove_bus(struct pci_bus *bus)
1898 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1899 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1902 struct pci_host_bridge *bridge;
1903 struct pci_bus *b, *b2;
1904 struct pci_host_bridge_window *window, *n;
1905 struct resource *res;
1906 resource_size_t offset;
1910 b = pci_alloc_bus(NULL);
1914 b->sysdata = sysdata;
1916 b->number = b->busn_res.start = bus;
1917 pci_bus_assign_domain_nr(b, parent);
1918 b2 = pci_find_bus(pci_domain_nr(b), bus);
1920 /* If we already got to this bus through a different bridge, ignore it */
1921 dev_dbg(&b2->dev, "bus already known\n");
1925 bridge = pci_alloc_host_bridge(b);
1929 bridge->dev.parent = parent;
1930 bridge->dev.release = pci_release_host_bridge_dev;
1931 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1932 error = pcibios_root_bridge_prepare(bridge);
1938 error = device_register(&bridge->dev);
1940 put_device(&bridge->dev);
1943 b->bridge = get_device(&bridge->dev);
1944 device_enable_async_suspend(b->bridge);
1945 pci_set_bus_of_node(b);
1948 set_dev_node(b->bridge, pcibus_to_node(b));
1950 b->dev.class = &pcibus_class;
1951 b->dev.parent = b->bridge;
1952 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1953 error = device_register(&b->dev);
1955 goto class_dev_reg_err;
1959 /* Create legacy_io and legacy_mem files for this bus */
1960 pci_create_legacy_files(b);
1963 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1965 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1967 /* Add initial resources to the bus */
1968 list_for_each_entry_safe(window, n, resources, list) {
1969 list_move_tail(&window->list, &bridge->windows);
1971 offset = window->offset;
1972 if (res->flags & IORESOURCE_BUS)
1973 pci_bus_insert_busn_res(b, bus, res->end);
1975 pci_bus_add_resource(b, res, 0);
1977 if (resource_type(res) == IORESOURCE_IO)
1978 fmt = " (bus address [%#06llx-%#06llx])";
1980 fmt = " (bus address [%#010llx-%#010llx])";
1981 snprintf(bus_addr, sizeof(bus_addr), fmt,
1982 (unsigned long long) (res->start - offset),
1983 (unsigned long long) (res->end - offset));
1986 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1989 down_write(&pci_bus_sem);
1990 list_add_tail(&b->node, &pci_root_buses);
1991 up_write(&pci_bus_sem);
1996 put_device(&bridge->dev);
1997 device_unregister(&bridge->dev);
2003 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2005 struct resource *res = &b->busn_res;
2006 struct resource *parent_res, *conflict;
2010 res->flags = IORESOURCE_BUS;
2012 if (!pci_is_root_bus(b))
2013 parent_res = &b->parent->busn_res;
2015 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2016 res->flags |= IORESOURCE_PCI_FIXED;
2019 conflict = request_resource_conflict(parent_res, res);
2022 dev_printk(KERN_DEBUG, &b->dev,
2023 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2024 res, pci_is_root_bus(b) ? "domain " : "",
2025 parent_res, conflict->name, conflict);
2027 return conflict == NULL;
2030 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2032 struct resource *res = &b->busn_res;
2033 struct resource old_res = *res;
2034 resource_size_t size;
2037 if (res->start > bus_max)
2040 size = bus_max - res->start + 1;
2041 ret = adjust_resource(res, res->start, size);
2042 dev_printk(KERN_DEBUG, &b->dev,
2043 "busn_res: %pR end %s updated to %02x\n",
2044 &old_res, ret ? "can not be" : "is", bus_max);
2046 if (!ret && !res->parent)
2047 pci_bus_insert_busn_res(b, res->start, res->end);
2052 void pci_bus_release_busn_res(struct pci_bus *b)
2054 struct resource *res = &b->busn_res;
2057 if (!res->flags || !res->parent)
2060 ret = release_resource(res);
2061 dev_printk(KERN_DEBUG, &b->dev,
2062 "busn_res: %pR %s released\n",
2063 res, ret ? "can not be" : "is");
2066 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2067 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2069 struct pci_host_bridge_window *window;
2074 list_for_each_entry(window, resources, list)
2075 if (window->res->flags & IORESOURCE_BUS) {
2080 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2086 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2088 pci_bus_insert_busn_res(b, bus, 255);
2091 max = pci_scan_child_bus(b);
2094 pci_bus_update_busn_res_end(b, max);
2096 pci_bus_add_devices(b);
2099 EXPORT_SYMBOL(pci_scan_root_bus);
2101 /* Deprecated; use pci_scan_root_bus() instead */
2102 struct pci_bus *pci_scan_bus_parented(struct device *parent,
2103 int bus, struct pci_ops *ops, void *sysdata)
2105 LIST_HEAD(resources);
2108 pci_add_resource(&resources, &ioport_resource);
2109 pci_add_resource(&resources, &iomem_resource);
2110 pci_add_resource(&resources, &busn_resource);
2111 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
2113 pci_scan_child_bus(b);
2115 pci_free_resource_list(&resources);
2118 EXPORT_SYMBOL(pci_scan_bus_parented);
2120 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2123 LIST_HEAD(resources);
2126 pci_add_resource(&resources, &ioport_resource);
2127 pci_add_resource(&resources, &iomem_resource);
2128 pci_add_resource(&resources, &busn_resource);
2129 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2131 pci_scan_child_bus(b);
2132 pci_bus_add_devices(b);
2134 pci_free_resource_list(&resources);
2138 EXPORT_SYMBOL(pci_scan_bus);
2141 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2142 * @bridge: PCI bridge for the bus to scan
2144 * Scan a PCI bus and child buses for new devices, add them,
2145 * and enable them, resizing bridge mmio/io resource if necessary
2146 * and possible. The caller must ensure the child devices are already
2147 * removed for resizing to occur.
2149 * Returns the max number of subordinate bus discovered.
2151 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2154 struct pci_bus *bus = bridge->subordinate;
2156 max = pci_scan_child_bus(bus);
2158 pci_assign_unassigned_bridge_resources(bridge);
2160 pci_bus_add_devices(bus);
2166 * pci_rescan_bus - scan a PCI bus for devices.
2167 * @bus: PCI bus to scan
2169 * Scan a PCI bus and child buses for new devices, adds them,
2172 * Returns the max number of subordinate bus discovered.
2174 unsigned int pci_rescan_bus(struct pci_bus *bus)
2178 max = pci_scan_child_bus(bus);
2179 pci_assign_unassigned_bus_resources(bus);
2180 pci_bus_add_devices(bus);
2184 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2187 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2188 * routines should always be executed under this mutex.
2190 static DEFINE_MUTEX(pci_rescan_remove_lock);
2192 void pci_lock_rescan_remove(void)
2194 mutex_lock(&pci_rescan_remove_lock);
2196 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2198 void pci_unlock_rescan_remove(void)
2200 mutex_unlock(&pci_rescan_remove_lock);
2202 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2204 static int __init pci_sort_bf_cmp(const struct device *d_a,
2205 const struct device *d_b)
2207 const struct pci_dev *a = to_pci_dev(d_a);
2208 const struct pci_dev *b = to_pci_dev(d_b);
2210 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2211 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2213 if (a->bus->number < b->bus->number) return -1;
2214 else if (a->bus->number > b->bus->number) return 1;
2216 if (a->devfn < b->devfn) return -1;
2217 else if (a->devfn > b->devfn) return 1;
2222 void __init pci_sort_breadthfirst(void)
2224 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);