2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
24 static struct resource busn_resource = {
28 .flags = IORESOURCE_BUS,
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
35 static LIST_HEAD(pci_domain_busn_res_list);
37 struct pci_domain_busn_res {
38 struct list_head list;
43 static struct resource *get_pci_domain_busn_res(int domain_nr)
45 struct pci_domain_busn_res *r;
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 r->domain_nr = domain_nr;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
65 static int find_anything(struct device *dev, void *data)
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
75 int no_pci_devices(void)
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
85 EXPORT_SYMBOL(no_pci_devices);
90 static void release_pcibus_dev(struct device *dev)
92 struct pci_bus *pci_bus = to_pci_bus(dev);
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
100 static struct class pcibus_class = {
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
106 static int __init pcibus_class_init(void)
108 return class_register(&pcibus_class);
110 postcore_initcall(pcibus_class_init);
112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
114 u64 size = mask & maxbase; /* Find the significant bits */
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
157 /* mem unknown type treated as 32-bit BAR */
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
178 u64 l64, sz64, mask64;
180 struct pci_bus_region region, inverted_region;
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 res->name = pci_name(dev);
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
206 if (sz == 0xffffffff)
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
229 res->flags |= (l & IORESOURCE_ROM_ENABLE);
230 l64 = l & PCI_ROM_ADDRESS_MASK;
231 sz64 = sz & PCI_ROM_ADDRESS_MASK;
232 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
235 if (res->flags & IORESOURCE_MEM_64) {
236 pci_read_config_dword(dev, pos + 4, &l);
237 pci_write_config_dword(dev, pos + 4, ~0);
238 pci_read_config_dword(dev, pos + 4, &sz);
239 pci_write_config_dword(dev, pos + 4, l);
241 l64 |= ((u64)l << 32);
242 sz64 |= ((u64)sz << 32);
243 mask64 |= ((u64)~0 << 32);
246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252 sz64 = pci_size(l64, sz64, mask64);
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259 if (res->flags & IORESOURCE_MEM_64) {
260 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
261 && sz64 > 0x100000000ULL) {
262 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos, (unsigned long long)sz64);
270 if ((sizeof(pci_bus_addr_t) < 8) && l) {
271 /* Above 32-bit boundary; try to reallocate */
272 res->flags |= IORESOURCE_UNSET;
275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos, (unsigned long long)l64);
282 region.end = l64 + sz64;
284 pcibios_bus_to_resource(dev->bus, res, ®ion);
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
293 * resource_to_bus(bus_to_resource(A)) == A
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
298 if (inverted_region.start != region.start) {
299 res->flags |= IORESOURCE_UNSET;
301 res->end = region.end - region.start;
302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos, (unsigned long long)region.start);
313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
315 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
318 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
320 unsigned int pos, reg;
322 if (dev->non_compliant_bars)
325 for (pos = 0; pos < howmany; pos++) {
326 struct resource *res = &dev->resource[pos];
327 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
328 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
332 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
333 dev->rom_base_reg = rom;
334 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
335 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
336 __pci_read_base(dev, pci_bar_mem32, res, rom);
340 static void pci_read_bridge_io(struct pci_bus *child)
342 struct pci_dev *dev = child->self;
343 u8 io_base_lo, io_limit_lo;
344 unsigned long io_mask, io_granularity, base, limit;
345 struct pci_bus_region region;
346 struct resource *res;
348 io_mask = PCI_IO_RANGE_MASK;
349 io_granularity = 0x1000;
350 if (dev->io_window_1k) {
351 /* Support 1K I/O space granularity */
352 io_mask = PCI_IO_1K_RANGE_MASK;
353 io_granularity = 0x400;
356 res = child->resource[0];
357 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
358 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
359 base = (io_base_lo & io_mask) << 8;
360 limit = (io_limit_lo & io_mask) << 8;
362 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
363 u16 io_base_hi, io_limit_hi;
365 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
366 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
367 base |= ((unsigned long) io_base_hi << 16);
368 limit |= ((unsigned long) io_limit_hi << 16);
372 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
374 region.end = limit + io_granularity - 1;
375 pcibios_bus_to_resource(dev->bus, res, ®ion);
376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
380 static void pci_read_bridge_mmio(struct pci_bus *child)
382 struct pci_dev *dev = child->self;
383 u16 mem_base_lo, mem_limit_lo;
384 unsigned long base, limit;
385 struct pci_bus_region region;
386 struct resource *res;
388 res = child->resource[1];
389 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
390 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
391 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
392 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
396 region.end = limit + 0xfffff;
397 pcibios_bus_to_resource(dev->bus, res, ®ion);
398 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
402 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
404 struct pci_dev *dev = child->self;
405 u16 mem_base_lo, mem_limit_lo;
407 pci_bus_addr_t base, limit;
408 struct pci_bus_region region;
409 struct resource *res;
411 res = child->resource[2];
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
414 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
415 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
417 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
418 u32 mem_base_hi, mem_limit_hi;
420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
424 * Some bridges set the base > limit by default, and some
425 * (broken) BIOSes do not initialize them. If we find
426 * this, just assume they are not being used.
428 if (mem_base_hi <= mem_limit_hi) {
429 base64 |= (u64) mem_base_hi << 32;
430 limit64 |= (u64) mem_limit_hi << 32;
434 base = (pci_bus_addr_t) base64;
435 limit = (pci_bus_addr_t) limit64;
437 if (base != base64) {
438 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
439 (unsigned long long) base64);
444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
449 region.end = limit + 0xfffff;
450 pcibios_bus_to_resource(dev->bus, res, ®ion);
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
455 void pci_read_bridge_bases(struct pci_bus *child)
457 struct pci_dev *dev = child->self;
458 struct resource *res;
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
466 dev->transparent ? " (subtractive decode)" : "");
468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
476 if (dev->transparent) {
477 pci_bus_for_each_resource(child->parent, res, i) {
478 if (res && res->flags) {
479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
489 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
493 b = kzalloc(sizeof(*b), GFP_KERNEL);
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
504 #ifdef CONFIG_PCI_DOMAINS_GENERIC
506 b->domain_nr = parent->domain_nr;
511 static void pci_release_host_bridge_dev(struct device *dev)
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
515 if (bridge->release_fn)
516 bridge->release_fn(bridge);
518 pci_free_resource_list(&bridge->windows);
523 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
525 struct pci_host_bridge *bridge;
527 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
531 INIT_LIST_HEAD(&bridge->windows);
536 static const unsigned char pcix_bus_speed[] = {
537 PCI_SPEED_UNKNOWN, /* 0 */
538 PCI_SPEED_66MHz_PCIX, /* 1 */
539 PCI_SPEED_100MHz_PCIX, /* 2 */
540 PCI_SPEED_133MHz_PCIX, /* 3 */
541 PCI_SPEED_UNKNOWN, /* 4 */
542 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
543 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
544 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
545 PCI_SPEED_UNKNOWN, /* 8 */
546 PCI_SPEED_66MHz_PCIX_266, /* 9 */
547 PCI_SPEED_100MHz_PCIX_266, /* A */
548 PCI_SPEED_133MHz_PCIX_266, /* B */
549 PCI_SPEED_UNKNOWN, /* C */
550 PCI_SPEED_66MHz_PCIX_533, /* D */
551 PCI_SPEED_100MHz_PCIX_533, /* E */
552 PCI_SPEED_133MHz_PCIX_533 /* F */
555 const unsigned char pcie_link_speed[] = {
556 PCI_SPEED_UNKNOWN, /* 0 */
557 PCIE_SPEED_2_5GT, /* 1 */
558 PCIE_SPEED_5_0GT, /* 2 */
559 PCIE_SPEED_8_0GT, /* 3 */
560 PCI_SPEED_UNKNOWN, /* 4 */
561 PCI_SPEED_UNKNOWN, /* 5 */
562 PCI_SPEED_UNKNOWN, /* 6 */
563 PCI_SPEED_UNKNOWN, /* 7 */
564 PCI_SPEED_UNKNOWN, /* 8 */
565 PCI_SPEED_UNKNOWN, /* 9 */
566 PCI_SPEED_UNKNOWN, /* A */
567 PCI_SPEED_UNKNOWN, /* B */
568 PCI_SPEED_UNKNOWN, /* C */
569 PCI_SPEED_UNKNOWN, /* D */
570 PCI_SPEED_UNKNOWN, /* E */
571 PCI_SPEED_UNKNOWN /* F */
574 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
576 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
578 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
580 static unsigned char agp_speeds[] = {
588 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
594 else if (agpstat & 2)
596 else if (agpstat & 1)
608 return agp_speeds[index];
611 static void pci_set_bus_speed(struct pci_bus *bus)
613 struct pci_dev *bridge = bus->self;
616 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
618 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
622 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
623 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
625 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
626 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
629 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
632 enum pci_bus_speed max;
634 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
637 if (status & PCI_X_SSTATUS_533MHZ) {
638 max = PCI_SPEED_133MHz_PCIX_533;
639 } else if (status & PCI_X_SSTATUS_266MHZ) {
640 max = PCI_SPEED_133MHz_PCIX_266;
641 } else if (status & PCI_X_SSTATUS_133MHZ) {
642 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
643 max = PCI_SPEED_133MHz_PCIX_ECC;
645 max = PCI_SPEED_133MHz_PCIX;
647 max = PCI_SPEED_66MHz_PCIX;
650 bus->max_bus_speed = max;
651 bus->cur_bus_speed = pcix_bus_speed[
652 (status & PCI_X_SSTATUS_FREQ) >> 6];
657 if (pci_is_pcie(bridge)) {
661 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
662 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
664 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
665 pcie_update_link_speed(bus, linksta);
669 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
671 struct irq_domain *d;
674 * Any firmware interface that can resolve the msi_domain
675 * should be called from here.
677 d = pci_host_bridge_of_msi_domain(bus);
682 static void pci_set_bus_msi_domain(struct pci_bus *bus)
684 struct irq_domain *d;
688 * The bus can be a root bus, a subordinate bus, or a virtual bus
689 * created by an SR-IOV device. Walk up to the first bridge device
690 * found or derive the domain from the host bridge.
692 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
694 d = dev_get_msi_domain(&b->self->dev);
698 d = pci_host_bridge_msi_domain(b);
700 dev_set_msi_domain(&bus->dev, d);
703 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
704 struct pci_dev *bridge, int busnr)
706 struct pci_bus *child;
711 * Allocate a new bus, and inherit stuff from the parent..
713 child = pci_alloc_bus(parent);
717 child->parent = parent;
718 child->ops = parent->ops;
719 child->msi = parent->msi;
720 child->sysdata = parent->sysdata;
721 child->bus_flags = parent->bus_flags;
723 /* initialize some portions of the bus device, but don't register it
724 * now as the parent is not properly set up yet.
726 child->dev.class = &pcibus_class;
727 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
730 * Set up the primary, secondary and subordinate
733 child->number = child->busn_res.start = busnr;
734 child->primary = parent->busn_res.start;
735 child->busn_res.end = 0xff;
738 child->dev.parent = parent->bridge;
742 child->self = bridge;
743 child->bridge = get_device(&bridge->dev);
744 child->dev.parent = child->bridge;
745 pci_set_bus_of_node(child);
746 pci_set_bus_speed(child);
748 /* Set up default resource pointers and names.. */
749 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
750 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
751 child->resource[i]->name = child->name;
753 bridge->subordinate = child;
756 pci_set_bus_msi_domain(child);
757 ret = device_register(&child->dev);
760 pcibios_add_bus(child);
762 /* Create legacy_io and legacy_mem files for this bus */
763 pci_create_legacy_files(child);
768 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
771 struct pci_bus *child;
773 child = pci_alloc_child_bus(parent, dev, busnr);
775 down_write(&pci_bus_sem);
776 list_add_tail(&child->node, &parent->children);
777 up_write(&pci_bus_sem);
781 EXPORT_SYMBOL(pci_add_new_bus);
783 static void pci_enable_crs(struct pci_dev *pdev)
787 /* Enable CRS Software Visibility if supported */
788 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
789 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
790 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
791 PCI_EXP_RTCTL_CRSSVE);
795 * If it's a bridge, configure it and scan the bus behind it.
796 * For CardBus bridges, we don't scan behind as the devices will
797 * be handled by the bridge driver itself.
799 * We need to process bridges in two passes -- first we scan those
800 * already configured by the BIOS and after we are done with all of
801 * them, we proceed to assigning numbers to the remaining buses in
802 * order to avoid overlaps between old and new bus numbers.
804 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
806 struct pci_bus *child;
807 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
810 u8 primary, secondary, subordinate;
813 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
814 primary = buses & 0xFF;
815 secondary = (buses >> 8) & 0xFF;
816 subordinate = (buses >> 16) & 0xFF;
818 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
819 secondary, subordinate, pass);
821 if (!primary && (primary != bus->number) && secondary && subordinate) {
822 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
823 primary = bus->number;
826 /* Check if setup is sensible at all */
828 (primary != bus->number || secondary <= bus->number ||
829 secondary > subordinate)) {
830 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
831 secondary, subordinate);
835 /* Disable MasterAbortMode during probing to avoid reporting
836 of bus errors (in some architectures) */
837 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
838 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
839 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
843 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
844 !is_cardbus && !broken) {
847 * Bus already configured by firmware, process it in the first
848 * pass and just note the configuration.
854 * The bus might already exist for two reasons: Either we are
855 * rescanning the bus or the bus is reachable through more than
856 * one bridge. The second case can happen with the i450NX
859 child = pci_find_bus(pci_domain_nr(bus), secondary);
861 child = pci_add_new_bus(bus, dev, secondary);
864 child->primary = primary;
865 pci_bus_insert_busn_res(child, secondary, subordinate);
866 child->bridge_ctl = bctl;
869 cmax = pci_scan_child_bus(child);
870 if (cmax > subordinate)
871 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
873 /* subordinate should equal child->busn_res.end */
874 if (subordinate > max)
878 * We need to assign a number to this bus which we always
879 * do in the second pass.
882 if (pcibios_assign_all_busses() || broken || is_cardbus)
883 /* Temporarily disable forwarding of the
884 configuration cycles on all bridges in
885 this bus segment to avoid possible
886 conflicts in the second pass between two
887 bridges programmed with overlapping
889 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
895 pci_write_config_word(dev, PCI_STATUS, 0xffff);
897 /* Prevent assigning a bus number that already exists.
898 * This can happen when a bridge is hot-plugged, so in
899 * this case we only re-scan this bus. */
900 child = pci_find_bus(pci_domain_nr(bus), max+1);
902 child = pci_add_new_bus(bus, dev, max+1);
905 pci_bus_insert_busn_res(child, max+1, 0xff);
908 buses = (buses & 0xff000000)
909 | ((unsigned int)(child->primary) << 0)
910 | ((unsigned int)(child->busn_res.start) << 8)
911 | ((unsigned int)(child->busn_res.end) << 16);
914 * yenta.c forces a secondary latency timer of 176.
915 * Copy that behaviour here.
918 buses &= ~0xff000000;
919 buses |= CARDBUS_LATENCY_TIMER << 24;
923 * We need to blast all three values with a single write.
925 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
928 child->bridge_ctl = bctl;
929 max = pci_scan_child_bus(child);
932 * For CardBus bridges, we leave 4 bus numbers
933 * as cards with a PCI-to-PCI bridge can be
936 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
937 struct pci_bus *parent = bus;
938 if (pci_find_bus(pci_domain_nr(bus),
941 while (parent->parent) {
942 if ((!pcibios_assign_all_busses()) &&
943 (parent->busn_res.end > max) &&
944 (parent->busn_res.end <= max+i)) {
947 parent = parent->parent;
951 * Often, there are two cardbus bridges
952 * -- try to leave one valid bus number
962 * Set the subordinate bus number to its real value.
964 pci_bus_update_busn_res_end(child, max);
965 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
969 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
970 pci_domain_nr(bus), child->number);
972 /* Has only triggered on CardBus, fixup is in yenta_socket */
973 while (bus->parent) {
974 if ((child->busn_res.end > bus->busn_res.end) ||
975 (child->number > bus->busn_res.end) ||
976 (child->number < bus->number) ||
977 (child->busn_res.end < bus->number)) {
978 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
980 (bus->number > child->busn_res.end &&
981 bus->busn_res.end < child->number) ?
982 "wholly" : "partially",
983 bus->self->transparent ? " transparent" : "",
991 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
995 EXPORT_SYMBOL(pci_scan_bridge);
998 * Read interrupt line and base address registers.
999 * The architecture-dependent code can tweak these, of course.
1001 static void pci_read_irq(struct pci_dev *dev)
1005 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1008 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1012 void set_pcie_port_type(struct pci_dev *pdev)
1017 struct pci_dev *parent;
1019 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1022 pdev->pcie_cap = pos;
1023 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1024 pdev->pcie_flags_reg = reg16;
1025 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1026 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1029 * A Root Port is always the upstream end of a Link. No PCIe
1030 * component has two Links. Two Links are connected by a Switch
1031 * that has a Port on each Link and internal logic to connect the
1034 type = pci_pcie_type(pdev);
1035 if (type == PCI_EXP_TYPE_ROOT_PORT)
1036 pdev->has_secondary_link = 1;
1037 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1038 type == PCI_EXP_TYPE_DOWNSTREAM) {
1039 parent = pci_upstream_bridge(pdev);
1042 * Usually there's an upstream device (Root Port or Switch
1043 * Downstream Port), but we can't assume one exists.
1045 if (parent && !parent->has_secondary_link)
1046 pdev->has_secondary_link = 1;
1050 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1054 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1055 if (reg32 & PCI_EXP_SLTCAP_HPC)
1056 pdev->is_hotplug_bridge = 1;
1060 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1063 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1064 * when forwarding a type1 configuration request the bridge must check that
1065 * the extended register address field is zero. The bridge is not permitted
1066 * to forward the transactions and must handle it as an Unsupported Request.
1067 * Some bridges do not follow this rule and simply drop the extended register
1068 * bits, resulting in the standard config space being aliased, every 256
1069 * bytes across the entire configuration space. Test for this condition by
1070 * comparing the first dword of each potential alias to the vendor/device ID.
1072 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1073 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1075 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1077 #ifdef CONFIG_PCI_QUIRKS
1081 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1083 for (pos = PCI_CFG_SPACE_SIZE;
1084 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1085 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1097 * pci_cfg_space_size - get the configuration space size of the PCI device.
1100 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1101 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1102 * access it. Maybe we don't have a way to generate extended config space
1103 * accesses, or the device is behind a reverse Express bridge. So we try
1104 * reading the dword at 0x100 which must either be 0 or a valid extended
1105 * capability header.
1107 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1110 int pos = PCI_CFG_SPACE_SIZE;
1112 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1114 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1117 return PCI_CFG_SPACE_EXP_SIZE;
1120 return PCI_CFG_SPACE_SIZE;
1123 int pci_cfg_space_size(struct pci_dev *dev)
1129 class = dev->class >> 8;
1130 if (class == PCI_CLASS_BRIDGE_HOST)
1131 return pci_cfg_space_size_ext(dev);
1133 if (!pci_is_pcie(dev)) {
1134 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1138 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1139 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1143 return pci_cfg_space_size_ext(dev);
1146 return PCI_CFG_SPACE_SIZE;
1149 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1151 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1154 * Disable the MSI hardware to avoid screaming interrupts
1155 * during boot. This is the power on reset default so
1156 * usually this should be a noop.
1158 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1160 pci_msi_set_enable(dev, 0);
1162 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1164 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1168 * pci_setup_device - fill in class and map information of a device
1169 * @dev: the device structure to fill
1171 * Initialize the device structure with information about the device's
1172 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1173 * Called at initialisation of the PCI subsystem and by CardBus services.
1174 * Returns 0 on success and negative if unknown type of device (not normal,
1175 * bridge or CardBus).
1177 int pci_setup_device(struct pci_dev *dev)
1183 struct pci_bus_region region;
1184 struct resource *res;
1186 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1189 dev->sysdata = dev->bus->sysdata;
1190 dev->dev.parent = dev->bus->bridge;
1191 dev->dev.bus = &pci_bus_type;
1192 dev->hdr_type = hdr_type & 0x7f;
1193 dev->multifunction = !!(hdr_type & 0x80);
1194 dev->error_state = pci_channel_io_normal;
1195 set_pcie_port_type(dev);
1197 pci_dev_assign_slot(dev);
1198 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1199 set this higher, assuming the system even supports it. */
1200 dev->dma_mask = 0xffffffff;
1202 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1203 dev->bus->number, PCI_SLOT(dev->devfn),
1204 PCI_FUNC(dev->devfn));
1206 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1207 dev->revision = class & 0xff;
1208 dev->class = class >> 8; /* upper 3 bytes */
1210 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1211 dev->vendor, dev->device, dev->hdr_type, dev->class);
1213 /* need to have dev->class ready */
1214 dev->cfg_size = pci_cfg_space_size(dev);
1216 /* "Unknown power state" */
1217 dev->current_state = PCI_UNKNOWN;
1219 pci_msi_setup_pci_dev(dev);
1221 /* Early fixups, before probing the BARs */
1222 pci_fixup_device(pci_fixup_early, dev);
1223 /* device class may be changed after fixup */
1224 class = dev->class >> 8;
1226 if (dev->non_compliant_bars) {
1227 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1228 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1229 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1230 cmd &= ~PCI_COMMAND_IO;
1231 cmd &= ~PCI_COMMAND_MEMORY;
1232 pci_write_config_word(dev, PCI_COMMAND, cmd);
1236 switch (dev->hdr_type) { /* header type */
1237 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1238 if (class == PCI_CLASS_BRIDGE_PCI)
1241 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1242 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1243 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1246 * Do the ugly legacy mode stuff here rather than broken chip
1247 * quirk code. Legacy mode ATA controllers have fixed
1248 * addresses. These are not always echoed in BAR0-3, and
1249 * BAR0-3 in a few cases contain junk!
1251 if (class == PCI_CLASS_STORAGE_IDE) {
1253 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1254 if ((progif & 1) == 0) {
1255 region.start = 0x1F0;
1257 res = &dev->resource[0];
1258 res->flags = LEGACY_IO_RESOURCE;
1259 pcibios_bus_to_resource(dev->bus, res, ®ion);
1260 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1262 region.start = 0x3F6;
1264 res = &dev->resource[1];
1265 res->flags = LEGACY_IO_RESOURCE;
1266 pcibios_bus_to_resource(dev->bus, res, ®ion);
1267 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1270 if ((progif & 4) == 0) {
1271 region.start = 0x170;
1273 res = &dev->resource[2];
1274 res->flags = LEGACY_IO_RESOURCE;
1275 pcibios_bus_to_resource(dev->bus, res, ®ion);
1276 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1278 region.start = 0x376;
1280 res = &dev->resource[3];
1281 res->flags = LEGACY_IO_RESOURCE;
1282 pcibios_bus_to_resource(dev->bus, res, ®ion);
1283 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1289 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1290 if (class != PCI_CLASS_BRIDGE_PCI)
1292 /* The PCI-to-PCI bridge spec requires that subtractive
1293 decoding (i.e. transparent) bridge must have programming
1294 interface code of 0x01. */
1296 dev->transparent = ((dev->class & 0xff) == 1);
1297 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1298 set_pcie_hotplug_bridge(dev);
1299 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1301 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1302 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1306 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1307 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1310 pci_read_bases(dev, 1, 0);
1311 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1312 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1315 default: /* unknown header */
1316 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1321 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1322 dev->class, dev->hdr_type);
1323 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1326 /* We found a fine healthy device, go go go... */
1330 static void pci_configure_mps(struct pci_dev *dev)
1332 struct pci_dev *bridge = pci_upstream_bridge(dev);
1335 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1338 mps = pcie_get_mps(dev);
1339 p_mps = pcie_get_mps(bridge);
1344 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1345 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1346 mps, pci_name(bridge), p_mps);
1351 * Fancier MPS configuration is done later by
1352 * pcie_bus_configure_settings()
1354 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1357 rc = pcie_set_mps(dev, p_mps);
1359 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1364 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1365 p_mps, mps, 128 << dev->pcie_mpss);
1368 static struct hpp_type0 pci_default_type0 = {
1370 .cache_line_size = 8,
1371 .latency_timer = 0x40,
1376 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1378 u16 pci_cmd, pci_bctl;
1381 hpp = &pci_default_type0;
1383 if (hpp->revision > 1) {
1385 "PCI settings rev %d not supported; using defaults\n",
1387 hpp = &pci_default_type0;
1390 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1391 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1392 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1393 if (hpp->enable_serr)
1394 pci_cmd |= PCI_COMMAND_SERR;
1395 if (hpp->enable_perr)
1396 pci_cmd |= PCI_COMMAND_PARITY;
1397 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1399 /* Program bridge control value */
1400 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1401 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1402 hpp->latency_timer);
1403 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1404 if (hpp->enable_serr)
1405 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1406 if (hpp->enable_perr)
1407 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1408 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1412 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1415 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1418 static bool pcie_root_rcb_set(struct pci_dev *dev)
1420 struct pci_dev *rp = pcie_find_root_port(dev);
1426 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1427 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1433 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1441 if (hpp->revision > 1) {
1442 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1448 * Don't allow _HPX to change MPS or MRRS settings. We manage
1449 * those to make sure they're consistent with the rest of the
1452 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1453 PCI_EXP_DEVCTL_READRQ;
1454 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1455 PCI_EXP_DEVCTL_READRQ);
1457 /* Initialize Device Control Register */
1458 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1459 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1461 /* Initialize Link Control Register */
1462 if (pcie_cap_has_lnkctl(dev)) {
1465 * If the Root Port supports Read Completion Boundary of
1466 * 128, set RCB to 128. Otherwise, clear it.
1468 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1469 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1470 if (pcie_root_rcb_set(dev))
1471 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1473 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1474 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1477 /* Find Advanced Error Reporting Enhanced Capability */
1478 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1482 /* Initialize Uncorrectable Error Mask Register */
1483 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1484 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1485 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1487 /* Initialize Uncorrectable Error Severity Register */
1488 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1489 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1490 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1492 /* Initialize Correctable Error Mask Register */
1493 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1494 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1495 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1497 /* Initialize Advanced Error Capabilities and Control Register */
1498 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1499 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1500 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1503 * FIXME: The following two registers are not supported yet.
1505 * o Secondary Uncorrectable Error Severity Register
1506 * o Secondary Uncorrectable Error Mask Register
1510 static void pci_configure_device(struct pci_dev *dev)
1512 struct hotplug_params hpp;
1515 pci_configure_mps(dev);
1517 memset(&hpp, 0, sizeof(hpp));
1518 ret = pci_get_hp_params(dev, &hpp);
1522 program_hpp_type2(dev, hpp.t2);
1523 program_hpp_type1(dev, hpp.t1);
1524 program_hpp_type0(dev, hpp.t0);
1527 static void pci_release_capabilities(struct pci_dev *dev)
1529 pci_vpd_release(dev);
1530 pci_iov_release(dev);
1531 pci_free_cap_save_buffers(dev);
1535 * pci_release_dev - free a pci device structure when all users of it are finished.
1536 * @dev: device that's been disconnected
1538 * Will be called only by the device core when all users of this pci device are
1541 static void pci_release_dev(struct device *dev)
1543 struct pci_dev *pci_dev;
1545 pci_dev = to_pci_dev(dev);
1546 pci_release_capabilities(pci_dev);
1547 pci_release_of_node(pci_dev);
1548 pcibios_release_device(pci_dev);
1549 pci_bus_put(pci_dev->bus);
1550 kfree(pci_dev->driver_override);
1554 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1556 struct pci_dev *dev;
1558 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1562 INIT_LIST_HEAD(&dev->bus_list);
1563 dev->dev.type = &pci_dev_type;
1564 dev->bus = pci_bus_get(bus);
1568 EXPORT_SYMBOL(pci_alloc_dev);
1570 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1575 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1578 /* some broken boards return 0 or ~0 if a slot is empty: */
1579 if (*l == 0xffffffff || *l == 0x00000000 ||
1580 *l == 0x0000ffff || *l == 0xffff0000)
1584 * Configuration Request Retry Status. Some root ports return the
1585 * actual device ID instead of the synthetic ID (0xFFFF) required
1586 * by the PCIe spec. Ignore the device ID and only check for
1589 while ((*l & 0xffff) == 0x0001) {
1595 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1597 /* Card hasn't responded in 60 seconds? Must be stuck. */
1598 if (delay > crs_timeout) {
1599 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1600 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1608 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1611 * Read the config data for a PCI device, sanity-check it
1612 * and fill in the dev structure...
1614 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1616 struct pci_dev *dev;
1619 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1622 dev = pci_alloc_dev(bus);
1627 dev->vendor = l & 0xffff;
1628 dev->device = (l >> 16) & 0xffff;
1630 pci_set_of_node(dev);
1632 if (pci_setup_device(dev)) {
1633 pci_bus_put(dev->bus);
1641 static void pci_init_capabilities(struct pci_dev *dev)
1643 /* Enhanced Allocation */
1646 /* MSI/MSI-X list */
1647 pci_msi_init_pci_dev(dev);
1649 /* Buffers for saving PCIe and PCI-X capabilities */
1650 pci_allocate_cap_save_buffers(dev);
1652 /* Power Management */
1655 /* Vital Product Data */
1656 pci_vpd_pci22_init(dev);
1658 /* Alternative Routing-ID Forwarding */
1659 pci_configure_ari(dev);
1661 /* Single Root I/O Virtualization */
1664 /* Address Translation Services */
1667 /* Enable ACS P2P upstream forwarding */
1668 pci_enable_acs(dev);
1670 pci_cleanup_aer_error_status_regs(dev);
1674 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1675 * devices. Firmware interfaces that can select the MSI domain on a
1676 * per-device basis should be called from here.
1678 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1680 struct irq_domain *d;
1683 * If a domain has been set through the pcibios_add_device
1684 * callback, then this is the one (platform code knows best).
1686 d = dev_get_msi_domain(&dev->dev);
1691 * Let's see if we have a firmware interface able to provide
1694 d = pci_msi_get_device_domain(dev);
1701 static void pci_set_msi_domain(struct pci_dev *dev)
1703 struct irq_domain *d;
1706 * If the platform or firmware interfaces cannot supply a
1707 * device-specific MSI domain, then inherit the default domain
1708 * from the host bridge itself.
1710 d = pci_dev_msi_domain(dev);
1712 d = dev_get_msi_domain(&dev->bus->dev);
1714 dev_set_msi_domain(&dev->dev, d);
1718 * pci_dma_configure - Setup DMA configuration
1719 * @dev: ptr to pci_dev struct of the PCI device
1721 * Function to update PCI devices's DMA configuration using the same
1722 * info from the OF node or ACPI node of host bridge's parent (if any).
1724 static void pci_dma_configure(struct pci_dev *dev)
1726 struct device *bridge = pci_get_host_bridge_device(dev);
1728 if (IS_ENABLED(CONFIG_OF) &&
1729 bridge->parent && bridge->parent->of_node) {
1730 of_dma_configure(&dev->dev, bridge->parent->of_node);
1731 } else if (has_acpi_companion(bridge)) {
1732 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1733 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1735 if (attr == DEV_DMA_NOT_SUPPORTED)
1736 dev_warn(&dev->dev, "DMA not supported.\n");
1738 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1739 attr == DEV_DMA_COHERENT);
1742 pci_put_host_bridge_device(bridge);
1745 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1749 pci_configure_device(dev);
1751 device_initialize(&dev->dev);
1752 dev->dev.release = pci_release_dev;
1754 set_dev_node(&dev->dev, pcibus_to_node(bus));
1755 dev->dev.dma_mask = &dev->dma_mask;
1756 dev->dev.dma_parms = &dev->dma_parms;
1757 dev->dev.coherent_dma_mask = 0xffffffffull;
1758 pci_dma_configure(dev);
1760 pci_set_dma_max_seg_size(dev, 65536);
1761 pci_set_dma_seg_boundary(dev, 0xffffffff);
1763 /* Fix up broken headers */
1764 pci_fixup_device(pci_fixup_header, dev);
1766 /* moved out from quirk header fixup code */
1767 pci_reassigndev_resource_alignment(dev);
1769 /* Clear the state_saved flag. */
1770 dev->state_saved = false;
1772 /* Initialize various capabilities */
1773 pci_init_capabilities(dev);
1776 * Add the device to our list of discovered devices
1777 * and the bus list for fixup functions, etc.
1779 down_write(&pci_bus_sem);
1780 list_add_tail(&dev->bus_list, &bus->devices);
1781 up_write(&pci_bus_sem);
1783 ret = pcibios_add_device(dev);
1786 /* Setup MSI irq domain */
1787 pci_set_msi_domain(dev);
1789 /* Notifier could use PCI capabilities */
1790 dev->match_driver = false;
1791 ret = device_add(&dev->dev);
1795 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1797 struct pci_dev *dev;
1799 dev = pci_get_slot(bus, devfn);
1805 dev = pci_scan_device(bus, devfn);
1809 pci_device_add(dev, bus);
1813 EXPORT_SYMBOL(pci_scan_single_device);
1815 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1821 if (pci_ari_enabled(bus)) {
1824 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1828 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1829 next_fn = PCI_ARI_CAP_NFN(cap);
1831 return 0; /* protect against malformed list */
1836 /* dev may be NULL for non-contiguous multifunction devices */
1837 if (!dev || dev->multifunction)
1838 return (fn + 1) % 8;
1843 static int only_one_child(struct pci_bus *bus)
1845 struct pci_dev *parent = bus->self;
1847 if (!parent || !pci_is_pcie(parent))
1849 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1851 if (parent->has_secondary_link &&
1852 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1858 * pci_scan_slot - scan a PCI slot on a bus for devices.
1859 * @bus: PCI bus to scan
1860 * @devfn: slot number to scan (must have zero function.)
1862 * Scan a PCI slot on the specified PCI bus for devices, adding
1863 * discovered devices to the @bus->devices list. New devices
1864 * will not have is_added set.
1866 * Returns the number of new devices found.
1868 int pci_scan_slot(struct pci_bus *bus, int devfn)
1870 unsigned fn, nr = 0;
1871 struct pci_dev *dev;
1873 if (only_one_child(bus) && (devfn > 0))
1874 return 0; /* Already scanned the entire slot */
1876 dev = pci_scan_single_device(bus, devfn);
1882 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1883 dev = pci_scan_single_device(bus, devfn + fn);
1887 dev->multifunction = 1;
1891 /* only one slot has pcie device */
1892 if (bus->self && nr)
1893 pcie_aspm_init_link_state(bus->self);
1897 EXPORT_SYMBOL(pci_scan_slot);
1899 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1903 if (!pci_is_pcie(dev))
1907 * We don't have a way to change MPS settings on devices that have
1908 * drivers attached. A hot-added device might support only the minimum
1909 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1910 * where devices may be hot-added, we limit the fabric MPS to 128 so
1911 * hot-added devices will work correctly.
1913 * However, if we hot-add a device to a slot directly below a Root
1914 * Port, it's impossible for there to be other existing devices below
1915 * the port. We don't limit the MPS in this case because we can
1916 * reconfigure MPS on both the Root Port and the hot-added device,
1917 * and there are no other devices involved.
1919 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1921 if (dev->is_hotplug_bridge &&
1922 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1925 if (*smpss > dev->pcie_mpss)
1926 *smpss = dev->pcie_mpss;
1931 static void pcie_write_mps(struct pci_dev *dev, int mps)
1935 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1936 mps = 128 << dev->pcie_mpss;
1938 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1940 /* For "Performance", the assumption is made that
1941 * downstream communication will never be larger than
1942 * the MRRS. So, the MPS only needs to be configured
1943 * for the upstream communication. This being the case,
1944 * walk from the top down and set the MPS of the child
1945 * to that of the parent bus.
1947 * Configure the device MPS with the smaller of the
1948 * device MPSS or the bridge MPS (which is assumed to be
1949 * properly configured at this point to the largest
1950 * allowable MPS based on its parent bus).
1952 mps = min(mps, pcie_get_mps(dev->bus->self));
1955 rc = pcie_set_mps(dev, mps);
1957 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1960 static void pcie_write_mrrs(struct pci_dev *dev)
1964 /* In the "safe" case, do not configure the MRRS. There appear to be
1965 * issues with setting MRRS to 0 on a number of devices.
1967 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1970 /* For Max performance, the MRRS must be set to the largest supported
1971 * value. However, it cannot be configured larger than the MPS the
1972 * device or the bus can support. This should already be properly
1973 * configured by a prior call to pcie_write_mps.
1975 mrrs = pcie_get_mps(dev);
1977 /* MRRS is a R/W register. Invalid values can be written, but a
1978 * subsequent read will verify if the value is acceptable or not.
1979 * If the MRRS value provided is not acceptable (e.g., too large),
1980 * shrink the value until it is acceptable to the HW.
1982 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1983 rc = pcie_set_readrq(dev, mrrs);
1987 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1992 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1995 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1999 if (!pci_is_pcie(dev))
2002 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2003 pcie_bus_config == PCIE_BUS_DEFAULT)
2006 mps = 128 << *(u8 *)data;
2007 orig_mps = pcie_get_mps(dev);
2009 pcie_write_mps(dev, mps);
2010 pcie_write_mrrs(dev);
2012 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2013 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2014 orig_mps, pcie_get_readrq(dev));
2019 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2020 * parents then children fashion. If this changes, then this code will not
2023 void pcie_bus_configure_settings(struct pci_bus *bus)
2030 if (!pci_is_pcie(bus->self))
2033 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2034 * to be aware of the MPS of the destination. To work around this,
2035 * simply force the MPS of the entire system to the smallest possible.
2037 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2040 if (pcie_bus_config == PCIE_BUS_SAFE) {
2041 smpss = bus->self->pcie_mpss;
2043 pcie_find_smpss(bus->self, &smpss);
2044 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2047 pcie_bus_configure_set(bus->self, &smpss);
2048 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2050 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2052 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2054 unsigned int devfn, pass, max = bus->busn_res.start;
2055 struct pci_dev *dev;
2057 dev_dbg(&bus->dev, "scanning bus\n");
2059 /* Go find them, Rover! */
2060 for (devfn = 0; devfn < 0x100; devfn += 8)
2061 pci_scan_slot(bus, devfn);
2063 /* Reserve buses for SR-IOV capability. */
2064 max += pci_iov_bus_range(bus);
2067 * After performing arch-dependent fixup of the bus, look behind
2068 * all PCI-to-PCI bridges on this bus.
2070 if (!bus->is_added) {
2071 dev_dbg(&bus->dev, "fixups for bus\n");
2072 pcibios_fixup_bus(bus);
2076 for (pass = 0; pass < 2; pass++)
2077 list_for_each_entry(dev, &bus->devices, bus_list) {
2078 if (pci_is_bridge(dev))
2079 max = pci_scan_bridge(bus, dev, max, pass);
2083 * We've scanned the bus and so we know all about what's on
2084 * the other side of any bridges that may be on this bus plus
2087 * Return how far we've got finding sub-buses.
2089 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2092 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2095 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2096 * @bridge: Host bridge to set up.
2098 * Default empty implementation. Replace with an architecture-specific setup
2099 * routine, if necessary.
2101 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2106 void __weak pcibios_add_bus(struct pci_bus *bus)
2110 void __weak pcibios_remove_bus(struct pci_bus *bus)
2114 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2115 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2118 struct pci_host_bridge *bridge;
2119 struct pci_bus *b, *b2;
2120 struct resource_entry *window, *n;
2121 struct resource *res;
2122 resource_size_t offset;
2126 b = pci_alloc_bus(NULL);
2130 b->sysdata = sysdata;
2132 b->number = b->busn_res.start = bus;
2133 pci_bus_assign_domain_nr(b, parent);
2134 b2 = pci_find_bus(pci_domain_nr(b), bus);
2136 /* If we already got to this bus through a different bridge, ignore it */
2137 dev_dbg(&b2->dev, "bus already known\n");
2141 bridge = pci_alloc_host_bridge(b);
2145 bridge->dev.parent = parent;
2146 bridge->dev.release = pci_release_host_bridge_dev;
2147 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2148 error = pcibios_root_bridge_prepare(bridge);
2154 error = device_register(&bridge->dev);
2156 put_device(&bridge->dev);
2159 b->bridge = get_device(&bridge->dev);
2160 device_enable_async_suspend(b->bridge);
2161 pci_set_bus_of_node(b);
2162 pci_set_bus_msi_domain(b);
2165 set_dev_node(b->bridge, pcibus_to_node(b));
2167 b->dev.class = &pcibus_class;
2168 b->dev.parent = b->bridge;
2169 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2170 error = device_register(&b->dev);
2172 goto class_dev_reg_err;
2176 /* Create legacy_io and legacy_mem files for this bus */
2177 pci_create_legacy_files(b);
2180 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2182 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2184 /* Add initial resources to the bus */
2185 resource_list_for_each_entry_safe(window, n, resources) {
2186 list_move_tail(&window->node, &bridge->windows);
2188 offset = window->offset;
2189 if (res->flags & IORESOURCE_BUS)
2190 pci_bus_insert_busn_res(b, bus, res->end);
2192 pci_bus_add_resource(b, res, 0);
2194 if (resource_type(res) == IORESOURCE_IO)
2195 fmt = " (bus address [%#06llx-%#06llx])";
2197 fmt = " (bus address [%#010llx-%#010llx])";
2198 snprintf(bus_addr, sizeof(bus_addr), fmt,
2199 (unsigned long long) (res->start - offset),
2200 (unsigned long long) (res->end - offset));
2203 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2206 down_write(&pci_bus_sem);
2207 list_add_tail(&b->node, &pci_root_buses);
2208 up_write(&pci_bus_sem);
2213 put_device(&bridge->dev);
2214 device_unregister(&bridge->dev);
2219 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2221 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2223 struct resource *res = &b->busn_res;
2224 struct resource *parent_res, *conflict;
2228 res->flags = IORESOURCE_BUS;
2230 if (!pci_is_root_bus(b))
2231 parent_res = &b->parent->busn_res;
2233 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2234 res->flags |= IORESOURCE_PCI_FIXED;
2237 conflict = request_resource_conflict(parent_res, res);
2240 dev_printk(KERN_DEBUG, &b->dev,
2241 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2242 res, pci_is_root_bus(b) ? "domain " : "",
2243 parent_res, conflict->name, conflict);
2245 return conflict == NULL;
2248 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2250 struct resource *res = &b->busn_res;
2251 struct resource old_res = *res;
2252 resource_size_t size;
2255 if (res->start > bus_max)
2258 size = bus_max - res->start + 1;
2259 ret = adjust_resource(res, res->start, size);
2260 dev_printk(KERN_DEBUG, &b->dev,
2261 "busn_res: %pR end %s updated to %02x\n",
2262 &old_res, ret ? "can not be" : "is", bus_max);
2264 if (!ret && !res->parent)
2265 pci_bus_insert_busn_res(b, res->start, res->end);
2270 void pci_bus_release_busn_res(struct pci_bus *b)
2272 struct resource *res = &b->busn_res;
2275 if (!res->flags || !res->parent)
2278 ret = release_resource(res);
2279 dev_printk(KERN_DEBUG, &b->dev,
2280 "busn_res: %pR %s released\n",
2281 res, ret ? "can not be" : "is");
2284 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2285 struct pci_ops *ops, void *sysdata,
2286 struct list_head *resources, struct msi_controller *msi)
2288 struct resource_entry *window;
2293 resource_list_for_each_entry(window, resources)
2294 if (window->res->flags & IORESOURCE_BUS) {
2299 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2307 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2309 pci_bus_insert_busn_res(b, bus, 255);
2312 max = pci_scan_child_bus(b);
2315 pci_bus_update_busn_res_end(b, max);
2320 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2321 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2323 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2326 EXPORT_SYMBOL(pci_scan_root_bus);
2328 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2331 LIST_HEAD(resources);
2334 pci_add_resource(&resources, &ioport_resource);
2335 pci_add_resource(&resources, &iomem_resource);
2336 pci_add_resource(&resources, &busn_resource);
2337 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2339 pci_scan_child_bus(b);
2341 pci_free_resource_list(&resources);
2345 EXPORT_SYMBOL(pci_scan_bus);
2348 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2349 * @bridge: PCI bridge for the bus to scan
2351 * Scan a PCI bus and child buses for new devices, add them,
2352 * and enable them, resizing bridge mmio/io resource if necessary
2353 * and possible. The caller must ensure the child devices are already
2354 * removed for resizing to occur.
2356 * Returns the max number of subordinate bus discovered.
2358 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2361 struct pci_bus *bus = bridge->subordinate;
2363 max = pci_scan_child_bus(bus);
2365 pci_assign_unassigned_bridge_resources(bridge);
2367 pci_bus_add_devices(bus);
2373 * pci_rescan_bus - scan a PCI bus for devices.
2374 * @bus: PCI bus to scan
2376 * Scan a PCI bus and child buses for new devices, adds them,
2379 * Returns the max number of subordinate bus discovered.
2381 unsigned int pci_rescan_bus(struct pci_bus *bus)
2385 max = pci_scan_child_bus(bus);
2386 pci_assign_unassigned_bus_resources(bus);
2387 pci_bus_add_devices(bus);
2391 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2394 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2395 * routines should always be executed under this mutex.
2397 static DEFINE_MUTEX(pci_rescan_remove_lock);
2399 void pci_lock_rescan_remove(void)
2401 mutex_lock(&pci_rescan_remove_lock);
2403 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2405 void pci_unlock_rescan_remove(void)
2407 mutex_unlock(&pci_rescan_remove_lock);
2409 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2411 static int __init pci_sort_bf_cmp(const struct device *d_a,
2412 const struct device *d_b)
2414 const struct pci_dev *a = to_pci_dev(d_a);
2415 const struct pci_dev *b = to_pci_dev(d_b);
2417 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2418 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2420 if (a->bus->number < b->bus->number) return -1;
2421 else if (a->bus->number > b->bus->number) return 1;
2423 if (a->devfn < b->devfn) return -1;
2424 else if (a->devfn > b->devfn) return 1;
2429 void __init pci_sort_breadthfirst(void)
2431 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);